Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-06-19 04:24:17 +08:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

note

Browse Source
This commit is contained in:
WBI\nxf44444
2020-10-26 14:58:46 +08:00
parent 6bc3301e08 877921f10b
commit 102976e89f
4798 changed files with 2741394 additions and 281772 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.gitee/ISSUE_TEMPLATE.en.md
+9
View File
@@ -0,0 +1,9 @@
### How is this problem caused?
### Steps to reproduce
### Error message
.gitee/ISSUE_TEMPLATE.zh-CN.md
+9
View File
@@ -0,0 +1,9 @@
### 该问题是怎么引起的？
### 重现步骤
### 报错信息
.gitee/ISSUE_TEMPLATE.zh-TW.md
+9
View File
@@ -0,0 +1,9 @@
### 該問題是怎麽引起的？
### 重現步驟
### 報錯信息
.gitee/PULL_REQUEST_TEMPLATE.en.md
+29
View File
@@ -0,0 +1,29 @@
## PR description
[
The content in this square bracket must be filled in and replaced, otherwise PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
And confirm in which case or board have been tested.
]
The following content must not be changed in submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use web browser to visit PR, and check items one by one, and ticked them if no problem.
### Intent for your PR
Choose one (Mandatory):
- [ ] This PR is for a code-review and is intended to get feedback
- [ ] This PR is mature, and ready to be integrated into the repo
### Code Quality：
As part of this pull request, I've considered the following:
- [ ] Already check the difference between PR and old code
- [ ] Style guide is adhered to, including spacing, naming and other style
- [ ] All redundant code is removed and cleaned up
- [ ] BSP All modifications are justified and not affect other components or BSP
- [ ] I've commented appropriately where code is tricky
- [ ] Code in this PR is of high quality
.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md
+29
View File
@@ -0,0 +1,29 @@
## 拉取/合并请求描述：
[
这段方括号里的内容是您**必须填写并替换掉**的，否则PR不可能被合并。**方括号外面的内容不需要修改，但请仔细阅读。**
请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
并确认并列出已经在什么情况或板卡上进行了测试。
]
以下的内容不应该在提交PR时的message修改，修改下述message，PR会被直接关闭。请在提交PR后，浏览器查看PR并对以下检查项逐项check，没问题后逐条在页面上打钩。
### 当前拉取/合并请求的状态：
必须选择一项:
- [ ] 本拉取/合并请求是一个草稿版本
- [ ] 本拉取/合并请求是一个成熟版本
### 代码质量：
我在这个拉取/合并请求中已经考虑了:
- [ ] 已经仔细查看过代码改动的对比
- [ ] 代码风格正确，包括缩进空格，命名及其他风格
- [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码
- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或
- [ ] 对难懂代码均提供对应的注释
- [ ] 本拉取/合并请求代码是高质量的
.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md
+29
View File
@@ -0,0 +1,29 @@
## 拉取/合並請求描述：
[
這段方括號裏的內容是您**必須填寫並替換掉**的，否則PR不可能被合並。**方括號外面的內容不需要修改，但請仔細閱讀。**
請在這裏填寫您的PR描述，可以包括以下之壹的內容：為什麽提交這份PR；解決的問題是什麽，妳的解決方案是什麽；
並確認並列出已經在什麽情況或板卡上進行了測試。
]
以下的內容不應該在提交PR時的message修改，修改下述message，PR會被直接關閉。請在提交PR後，瀏覽器查看PR並對以下檢查項逐項check，沒問題後逐條在頁面上打鉤。
### 當前拉取/合並請求的狀態：
必須選擇壹項:
- [ ] 本拉取/合並請求是壹個草稿版本
- [ ] 本拉取/合並請求是壹個成熟版本
### 代碼質量：
我在這個拉取/合並請求中已經考慮了:
- [ ] 已經仔細查看過代碼改動的對比
- [ ] 代碼風格正確，包括縮進空格，命名及其他風格
- [ ] 沒有垃圾代碼，代碼盡量精簡，不包含`#if 0`代碼，不包含已經被註釋了的代碼
- [ ] 所有變更均有原因及合理的，並且不會影響到其他軟件組件代碼或
- [ ] 對難懂代碼均提供對應的註釋
- [ ] 本拉取/合並請求代碼是高質量的
.github/PULL_REQUEST_TEMPLATE.md
+4 -4
View File
@@ -2,17 +2,17 @@
[
这段方括号里的内容是您**必须填写并替换掉**的，否则PR不可能被合并。**方括号外面的内容不需要修改，但请仔细阅读。**
The content in this square bracket must be filled in and replaced, otherwise PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
The content in this square bracket must be filled in and replaced, otherwise, PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
并确认并列出已经在什么情况或板卡上进行了测试。
And confirm in which case or board have been tested.
And confirm in which case or board has been tested.
]
以下的内容不应该在提交PR时的message修改，修改下述message，PR会被直接关闭。请在提交PR后，浏览器查看PR并对以下检查项逐项check，没问题后逐条在页面上打钩。
The following content must not be changed in submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use web browser to visit PR, and check items one by one, and ticked them if no problem.
The following content must not be changed in the submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use a web browser to visit PR, and check items one by one, and ticked them if no problem.
### 当前拉取/合并请求的状态 Intent for your PR
@@ -26,7 +26,7 @@ The following content must not be changed in submitted PR message. Otherwise, th
我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
- [ ] 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
- [ ] 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other style
- [ ] 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
- [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up
- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
- [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
.travis.yml
+20 -3
View File
@@ -41,6 +41,7 @@ env:
- RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='tm4c123bsp' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
@@ -65,8 +66,8 @@ env:
# - RTT_BSP='mini4020' # no scons
# - RTT_BSP='mm32l07x' # not support gcc
# - RTT_BSP='nios_ii' # no scons
- RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='pic32ethernet' # no scons
- RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
@@ -81,13 +82,18 @@ env:
- RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-onenet-nbiot' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f103-yf-ufun' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f410-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f411-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f411-weact-MiniF4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f413-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f427-robomaster-a' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
@@ -99,19 +105,28 @@ env:
- RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32g070-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32g431-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32h747-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l412-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l433-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l496-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32mp157a-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32mp157a-st-ev1' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32wb55-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
# - RTT_BSP='upd70f3454' # iar
# - RTT_BSP='x86' # x86
@@ -119,8 +134,10 @@ env:
- RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
# - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f403a-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f407-start' RTT_TOOL_CHAIN='sourcery-arm'
stage: compile
script:
ChangeLog.md
+156 -487
View File
File diff suppressed because it is too large Load Diff
Jenkinsfile
Vendored
+158
View File
@@ -0,0 +1,158 @@
pipeline {
agent {
docker {
image 'ubuntu_ci:latest'
}
}
stages {
stage('build') {
steps {
sh '''
uname -a
cat /etc/issue
apt-get update
apt-get install -y -qq lib32ncurses5 lib32z1 > /dev/null
curl -s http://download.isrc.rt-thread.com/download/gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2 | sudo tar xjf - -C /opt
/opt/gcc-arm-none-eabi-5_4-2016q3/bin/arm-none-eabi-gcc --version
'''
script {
def bsp_array = [
['CME_M7', 'sourcery-arm'],
// ['apollo2', 'sourcery-arm'], /* CI compile not support */
['asm9260t', 'sourcery-arm'],
['at91sam9260', 'sourcery-arm'],
['allwinner_tina', 'sourcery-arm'],
['efm32', 'sourcery-arm'],
// ['gd32e230k-start', 'sourcery-arm'], /* CI compile not support */
['gd32303e-eval', 'sourcery-arm'],
// ['gd32450z-eval', 'sourcery-arm'], /* CI link not support */
['gkipc', 'sourcery-arm'],
['imx6sx/cortex-a9', 'sourcery-arm'],
// ['imxrt/imxrt1052-atk-commander', 'sourcery-arm'], /* CI compile not support */
// ['imxrt/imxrt1052-fire-pro', 'sourcery-arm'], /* CI compile not support */
// ['imxrt/imxrt1052-nxp-evk', 'sourcery-arm'], /* CI compile not support */
['lm3s8962', 'sourcery-arm'],
['lm3s9b9x', 'sourcery-arm'],
['lm4f232', 'sourcery-arm'],
['tm4c129x', 'sourcery-arm'],
// ['lpc43xx/M4', 'sourcery-arm'], /* CI compile not support */
['lpc176x', 'sourcery-arm'],
['lpc178x', 'sourcery-arm'],
['lpc408x', 'sourcery-arm'],
['lpc1114', 'sourcery-arm'],
['lpc2148', 'sourcery-arm'],
['lpc2478', 'sourcery-arm'],
['lpc5410x', 'sourcery-arm'],
// ['lpc54114-lite', 'sourcery-arm'], /* CI link not support */
['mb9bf500r', 'sourcery-arm'],
['mb9bf506r', 'sourcery-arm'],
['mb9bf618s', 'sourcery-arm'],
['mb9bf568r', 'sourcery-arm'],
['mini2440', 'sourcery-arm'],
['nuvoton_nuc472', 'sourcery-arm'],
['nuvoton_m05x', 'sourcery-arm'],
['qemu-vexpress-a9', 'sourcery-arm'],
['qemu-vexpress-gemini', 'sourcery-arm'],
['sam7x', 'sourcery-arm'],
// ['stm32/stm32f072-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f091-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-atk-nano', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-atk-warshipv3', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-dofly-lyc8', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-dofly-M3S', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-fire-arbitrary', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-hw100k-ibox', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-mini-system', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-onenet-nbiot', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f103-yf-ufun', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f107-uc-eval', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f401-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f405-smdz-breadfruit', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f407-atk-explorer', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f407-st-discovery', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f410-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f411-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f411-weact-MiniF4', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f413-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f427-robomaster-a', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f429-armfly-v6', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f429-atk-apollo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f429-fire-challenger', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f429-st-disco', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f446-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f469-st-disco', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32f746-st-disco', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32f767-atk-apollo', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32f767-fire-challenger', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32f767-st-nucleo', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32g071-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32g431-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32h743-atk-apollo', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32h743-st-nucleo', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32h747-st-discovery', 'sourcery-arm'], /* CI compile -mcpu= not support */
// ['stm32/stm32l4r9-st-eval', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l010-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l053-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l412-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l432-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l433-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l475-atk-pandora', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l475-st-discovery', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l476-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l496-ali-developer', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l496-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
['stm32f20x', 'sourcery-arm'],
['swm320-lq100', 'sourcery-arm'],
['beaglebone', 'sourcery-arm'],
['zynq7000', 'sourcery-arm'],
['frdm-k64f', 'sourcery-arm'],
['fh8620', 'sourcery-arm'],
['xplorer4330/M4', 'sourcery-arm'],
// ['at32/at32f403a-start', 'sourcery-arm'],/* CI link not support */
// ['at32/at32f407-start', 'sourcery-arm']/* CI compile C99 not support */
]
for (int i in bsp_array) {
sh """
export RTT_BSP=${i.getAt(0)}
export RTT_TOOL_CHAIN=${i.getAt(1)}
export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/
export RTT_CC='gcc'
export RTT_ROOT=`pwd`
echo \$RTT_EXEC_PATH
export CPUS=\$(cat /proc/cpuinfo | grep "processor" | sort | uniq | wc -l)
scons -j\${CPUS} -C bsp/\$RTT_BSP
"""
}
}
}
}
}
post {
failure {
addGiteeMRComment(comment: """:x: Jenkins CI 构建失败。\n\n \
查看更多日志详细信息： \
<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a> \
<hr /> \
:x: The Jenkins CI build failed.\n\n \
Results available at: \
<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a>""")
}
success {
addGiteeMRComment(comment: """:white_check_mark: Jenkins CI 构建通过。\n\n \
查看更多日志详细信息： \
<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a> \
<hr /> \
:white_check_mark: The Jenkins CI build passed.\n\n \
Results available at: \
<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a>""")
}
}
}
README.md
+113 -46
View File
@@ -9,76 +9,143 @@
[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
RT-Thread is an open source IoT operating system from China, which has strong scalability: from a tiny kernel running on a tiny core, for example ARM Cortex-M0, or Cortex-M3/4/7, to a rich feature system running on MIPS32, ARM Cortex-A8, ARM Cortex-A9 DualCore etc.
# Introduction
## Overview ##
RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS).
RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue, signal etc. However, it has three different things:
RT-Thread is mainly written in C language, easy to understand and easy to port(can be quickly port to a wide range of mainstream MCUs and module chips). It applies object-oriented programming methods to real-time system design, making the code elegant, structured, modular, and very tailorable.
* Device Driver;
* Component;
* Dynamic Module
RT-Thread has Standard version and Nano version. For resource-constrained microcontroller (MCU) systems, the NANO kernel version that requires only 3KB Flash and 1.2KB RAM memory resources can be tailored with easy-to-use tools; And for resource-rich IoT devices, RT-Thread can use the on-line software package management tool, together with system configuration tools, to achieve intuitive and rapid modular cutting, seamlessly import rich software packages, thus achieving complex functions like Android's graphical interface and touch sliding effects, smart voice interaction effects, and so on.
The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features.
## RT-Thread Architecture
The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
RT-Thread has not only a real-time kernel, but also rich components. Its architecture is as follows:
The Dynamic Module, formerly named as User Applicaion (UA) is a dynamic loaded module or library, it can be compiled standalone without Kernel. Each Dynamic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
## Board Support Package ##
![architecture](./documentation/figures/architecture.png)
RT-Thread RTOS can support many architectures:
* ARM Cortex-M0
* ARM Cortex-M3/M4/7
* ARM Cortex-R4
* ARM Cortex-A8/A9
* ARM920T/ARM926 etc
* MIPS32
* x86
* Andes
* C-Sky
* RISC-V
* PowerPC
It includes:
## License ##
- Kernel layer: RT-Thread kernel, the core part of RT-Thread, includes the implementation of objects in the kernel system, such as multi-threading and its scheduling, semaphore, mailbox, message queue, memory management, timer, etc.; libcpu/BSP (Chip Migration Related Files/Board Support Package) is closely related to hardware and consists of peripheral drivers and CPU porting.
RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v3.1.1. License and copyright information can be found within the code.
- Components and Service Layer: Components are based on upper-level software on top of the RT-Thread kernel, such as virtual file systems, FinSH command-line interfaces, network frameworks, device frameworks, and more. Its modular design allows for high internal cohesion inside the components and low coupling between components.
- RT-Thread software package: A general-purpose software component running on the RT-Thread IoT operating system platform for different application areas, consisting of description information, source code or library files. RT-Thread provides an open package platform with officially available or developer-supplied packages that provide developers with a choice of reusable packages that are an important part of the RT-Thread ecosystem. The package ecosystem is critical to the choice of an operating system because these packages are highly reusable and modular, making it easy for application developers to build the system they want in the shortest amount of time. RT-Thread supports more than 180 software packages.
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
## RT-Thread Features
Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA).
- Designed for resource-constrained devices, the minimum kernel requires only 1.2KB of RAM and 3 KB of Flash.
## Usage ##
- Has rich components and a prosperous and fast growing package ecosystem.
RT-Thread RTOS uses [scons](http://www.scons.org) as building system. Therefore, please install scons and Python 2.7 firstly.
So far, the RT-Thread scons building system support the command line compile or generate some IDE's project. There are some option varaibles in the scons building script (rtconfig.py):
- Elegant code style, easy to use, read and master.
* ```CROSS_TOOL``` the compiler which you want to use, gcc/keil/iar.
* ```EXEC_PATH``` the path of compiler.
- High Scalability. RT-Thread has high-quality scalable software architecture, loose coupling, modularity, is easy to tailor and expand.
In SConstruct file:
- Supports high-performance applications.
```RTT_ROOT``` This variable is the root directory of RT-Thread RTOS. If you build the porting in the bsp directory, you can use the default setting. Also, you can set the root directory in ```RTT_ROOT``` environment variable and not modify SConstruct files.
- Supports cross-platform and a wide range of chips.
When you set these variables correctly, you can use command:
## Code Catalogue
scons
RT-Thread source code catalog is shown as follow:
under BSP directory to simplely compile RT-Thread RTOS.
| Name | Description |
| ------------- | ------------------------------------------------------- |
| BSP | Board Support Package based on the porting of various development boards |
| components | Components, such as finsh shell, file system, protocol stack etc. |
| documentation | Related documents, like coding style, doxygen etc. |
| examples | Related sample code |
| include | Head files of RT-Thread kernel |
| libcpu | CPU porting code such as ARM/MIPS/RISC-V etc. |
| src | The source files for the RT-Thread kernel. |
| tools | The script files for the RT-Thread command build tool. |
If you want to generate the IDE's project file, you can use command:
RT-Thread has now been ported for nearly 90 development boards, most BSPs support MDK, IAR development environment and GCC compiler, and have provided default MDK and IAR project, which allows users to add their own application code directly based on the project. Each BSP has a similar directory structure, and most BSPs provide a README.md file, which is a markdown-format file that contains the basic introduction of BSP, and introduces how to simply start using BSP.
scons --target=mdk/mdk4/mdk5/iar/cb -s
Env is a development tool developed by RT-Thread which provides a build environment, text graphical system configuration, and package management capabilities for project based on the RT-Thread operating system. Its built-in `menuconfig` provides an easy-to-use configuration tool. It can tailor the kernels, components and software packages freely, so that the system can be constructed by building blocks.
to generate the project file.
- [Download Env Tool](https://www.rt-thread.io/download.html?download=Env)
- [User manual of Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files.
# Resources
## Contribution ##
## Supported Architectures
Please refer the contributors in the github. Thank all of RT-Thread Developers.
RT-Thread supports many architectures, and has covered the major architectures in current applications. Architecture and chip manufacturer involved:
- **ARM Cortex-M0/M0+**：manufacturers like ST
- **ARM Cortex-M3**：manufacturers like ST、Winner Micro、MindMotion, ect.
- **ARM Cortex-M4**：manufacturers like ST、Nuvton、NXP、GigaDevice、Realtek、Ambiq Micro, ect.
- **ARM Cortex-M7**：manufacturers like ST、NXP
- **ARM Cortex-M23**：manufacturers like GigaDevice
- **ARM Cortex-R4**
- **ARM Cortex-A8/A9**：manufacturers like NXP
- **ARM7**：manufacturers like Samsung
- **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
- **ARM11**：manufacturers like Fullhan
- **MIPS32**：manufacturers like loongson、Ingenic
- **RISC-V**：manufacturers like Hifive、Kendryte、[Nuclei](https://nucleisys.com/)
- **ARC**：manufacturers like SYNOPSYS
- **DSP**：manufacturers like TI
- **C-Sky**
- **x86**
## Supported IDE and Compiler
The main IDE/compilers supported by RT-Thread are:
- MDK KEIL
- IAR
- GCC
- RT-Thread Studio
Use Python-based [scons](http://www.scons.org/) for command-line builds.
RT-Thread Studio Demonstration:
![studio](./documentation/figures/studio.gif)
## Getting Started
RT-Thread BSP can be compiled directly and downloaded to the corresponding development board for use. In addition, RT-Thread also provides qemu-vexpress-a9 BSP, which can be used without hardware platform. See the getting started guide below for details.
- [Getting Started of QEMU (Windows)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu.md)
- [Getting Started of QEMU (Ubuntu)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu_linux.md)
## Documentation
[RT-Thread Programming Guide](https://github.com/RT-Thread/rtthread-manual-doc) | [RT-Thread Supported Chips & Boards](https://www.rt-thread.io/board.html) |
[RT-Thread Software Package](https://github.com/RT-Thread/packages) | [RT-Thread Studio](https://www.rt-thread.io/studio.html)
## Sample
[Kernel Sample](https://github.com/RT-Thread-packages/kernel-sample) | [Device Sample Code](https://github.com/RT-Thread-packages/peripheral-sample) | [File System Sample Code](https://github.com/RT-Thread-packages/filesystem-sample ) | [Network Sample Code](https://github.com/RT-Thread-packages/network-sample ) |
[Based on the STM32L475 IoT Board SDK](https://github.com/RT-Thread/IoT_Board) | [Based on the W601 IoT Board SDK](https://github.com/RT-Thread/W601_IoT_Board)
# License
RT-Thread is an open source software and has been licensed under Apache License Version 2.0 since v3.1.1. License information and copyright information can generally be seen at the beginning of the code:
```c
/* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
* ...
*/
```
To avoid possible future license conflicts, developers need to sign a Contributor License Agreement (CLA) when submitting PR to RT-Thread.
# Community
RT-Thread is very grateful for the support from all community developers, and if you have any ideas, suggestions or questions in the process of using RT-Thread, RT-Thread can be reached by the following means, and we are also updating RT-Thread in real time on these channels. At the same time, Any questions can be asked in the [issue section of rtthread-manual-doc](https://github.com/RT-Thread/rtthread-manual-doc/issues). By creating a new issue to describe your questions, community members will answer them.
[Website](https://www.rt-thread.io) | [Twitter](https://twitter.com/rt_thread) | [Youtube]( https://www.youtube.com/channel/UCdDHtIfSYPq4002r27ffqPw?view_as=subscriber) | [Gitter]( https://gitter.im/RT-Thread) | [Facebook](https://www.facebook.com/RT-Thread-IoT-OS-110395723808463/?modal=admin_todo_tour) | [Medium](https://medium.com/@rt_thread)
# Contribution
If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/contribution_guide/contribution_guide.md).
README_zh.md
+143 -62
View File
@@ -1,97 +1,178 @@
# RT-Thread #
## 简介
[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
RT-Thread诞生于2006年，是一款以开源、中立、社区化发展起来的物联网操作系统。
RT-Thread主要采用 C 语言编写，浅显易懂，且具有方便移植的特性（可快速移植到多种主流 MCU 及模组芯片上）。RT-Thread把面向对象的设计方法应用到实时系统设计中，使得代码风格优雅、架构清晰、系统模块化并且可裁剪性非常好。
RT-Thread是一个来自中国的开源物联网操作系统，它提供了非常强的可伸缩能力：从一个可以运行在ARM Cortex-M0芯片上的极小内核，到中等的ARM Cortex-M3/4/7系统，甚至是运行于MIPS32、ARM Cortex-A系列处理器上功能丰富系统。
RT-Thread有完整版和Nano版，对于资源受限的微控制器（MCU）系统，可通过简单易用的工具，裁剪出仅需要 3KB Flash、1.2KB RAM 内存资源的 NANO 内核版本；而相对资源丰富的物联网设备，可使用RT-Thread完整版，通过在线的软件包管理工具，配合系统配置工具实现直观快速的模块化裁剪，并且可以无缝地导入丰富的软件功能包，实现类似 Android 的图形界面及触摸滑动效果、智能语音交互效果等复杂功能。
## 简介 ##
## **RT-Thread架构**
RT-Thread包含了一个自有的、传统的硬实时内核：可抢占的多任务实时调度器，信号量，互斥量，邮箱，消息队列，信号等。当然，它和传统的实时操作系统还存在着三种不同：
RT-Thread是一个集实时操作系统（RTOS）内核、中间件组件的物联网操作系统，架构如下：
* 设备驱动框架；
* 软件组件；
* 应用模块
![architecturezh](./documentation/figures/architecturezh.png)
设备驱动框架更类似一套驱动框架，涉及到UART，IIC，SPI，SDIO，USB从设备/主设备，EMAC，NAND闪存设备等。它会把这些设备驱动中的共性抽象/抽取出来，而驱动工程师只需要按照固定的模式实现少量的底层硬件操作及板级配置。通过这样的方式，让一个硬件外设更容易地对接到RT-Thread系统中，并获得RT-Thread平台上的完整软件栈功能。
软件组件是位于RT-Thread内核上的软件单元，例如命令行（finsh/msh shell），虚拟文件系统（FAT，YAFFS，UFFS，ROM/RAM文件系统等），TCP/IP网络协议栈（lwIP），Libc/POSIX标准层等。一般的，一个软件组件放置于一个目录下，例如RT-Thread/components目录下的文件夹，并且每个软件组件通过一个 SConscript文件来描述并被添加到RT-Thread的构建系统中。当系统配置中开启了这一软件组件时，这个组件将被编译并链接到最终的RT-Thread固件中。
注：随着RT-Thread 3.0中的包管理器开启，越来越多的软件组件将以package方式出现在RT-Thread平台中。而RT-Thread平台更多的是指：
- 内核层：RT-Thread内核，是 RT-Thread的核心部分，包括了内核系统中对象的实现，例如多线程及其调度、信号量、邮箱、消息队列、内存管理、定时器等；libcpu/BSP（芯片移植相关文件 / 板级支持包）与硬件密切相关，由外设驱动和 CPU 移植构成。
* RT-Thread内核；
* shell命令行；
* 虚拟文件系统；
* TCP/IP网络协议栈；
* 设备驱动框架；
* Libc/POSIX标准层。
- 组件与服务层：组件是基于 RT-Thread内核之上的上层软件，例如虚拟文件系统、FinSH命令行界面、网络框架、设备框架等。采用模块化设计，做到组件内部高内聚，组件之间低耦合。
更多的IoT软件包则以package方式被添加到RT-Thread系统中。
应用模块，或者说用户应用（User Application，UA）是一个可动态加载的模块：它可以独立于RT-Thread固件而单独编译。一般的，每个UA都包含一个main函数入口；一个它自己的对象链表，用于管理这个应用的任务/信号量/消息队列等内核对象，创建、初始化、销毁等。更多关于UA的信息，请访问另外一个 [git 仓库](https://github.com/RT-Thread/rtthread-apps) 了解。
- RT-Thread软件包：运行于 RT-Thread物联网操作系统平台上，面向不同应用领域的通用软件组件，由描述信息、源代码或库文件组成。RT-Thread提供了开放的软件包平台，这里存放了官方提供或开发者提供的软件包，该平台为开发者提供了众多可重用软件包的选择，这也是 RT-Thread生态的重要组成部分。软件包生态对于一个操作系统的选择至关重要，因为这些软件包具有很强的可重用性，模块化程度很高，极大的方便应用开发者在最短时间内，打造出自己想要的系统。RT-Thread已经支持的软件包数量已经达到 180+。
## 支持的芯片架构 ##
RT-Thread支持数种芯片体系架构，已经覆盖当前应用中的主流体系架构：
## RT-Thread的特点
* ARM Cortex-M0
* ARM Cortex-M3/M4/7
* ARM Cortex-R4
* ARM Cortex-A8/A9
* ARM920T/ARM926 etc
* MIPS32
* x86
* Andes
* C-Sky
* RISC-V
* PowerPC
- 资源占用极低，超低功耗设计，最小内核（Nano版本）仅需1.2KB RAM，3KB Flash。
## 许可证 ##
- 组件丰富，繁荣发展的软件包生态 。
RT-Thread从v3.1.1版本开始，是一个以Apache许可证2.0版本授权的开源软件，许可证信息以及版权信息一般的可以在代码首部看到：
- 简单易用 ，优雅的代码风格，易于阅读、掌握。
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
- 高度可伸缩，优质的可伸缩的软件架构，松耦合，模块化，易于裁剪和扩展。
从2018/09/09开始，开发者提交PR需要签署贡献者许可协议（CLA）。
- 强大，支持高性能应用。
注意：
- 跨平台、芯片支持广泛。
以Apache许可协议v2.0版本授权仅在RT-Thread v3.1.1正式版发布之后才正式实施，当前依然在准备阶段（准备所有原有开发者签署CLA协议）。
## 编译 ##
## **代码目录**
RT-Thread使用了[scons](http://www.scons.org)做为自身的编译构建系统，并进行一定的定制以满足自身的需求（可以通过scons --help查看RT-Thread中额外添加的命令）。在编译RT-Thread前，请先安装Python 2.7.x及scons。
RT-Thread源代码目录结构如下图所示：
截至目前，RT-Thread scons构建系统可以使用命令行方式编译代码，或者使用scons来生成不同IDE的工程文件。在使用scons时，需要对构建配置文件（rtconfig.py）中如下的变量进行配置：
| 名称 | 描述 |
| ------------- | ------------------------------------------------------- |
| BSP | Board Support Package（板级支持包）基于各种开发板的移植 |
| components | RT-Thread 的各个组件代码，例如 finsh，gui 等。 |
| documentation | 相关文档，如编码规范等 |
| examples | 相关示例代码 |
| include | RT-Thread 内核的头文件。 |
| libcpu | 各类芯片的移植代码。 |
| src | RT-Thread 内核的源文件。 |
| tools | RT-Thread 命令构建工具的脚本文件。 |
* ```CROSS_TOOL``` 指定希望使用的工具链，例如gcc/keil/iar.
* ```EXEC_PATH``` 工具链的路径.
目前RT-Thread已经针对将近90种开发板做好了移植，大部分 BSP 都支持 MDK﹑IAR开发环境和GCC编译器，并且已经提供了默认的 MDK 和 IAR 工程，用户可以直接基于这个工程添加自己的应用代码。 每个 BSP 的目录结构高度统一，且都提供一个 README.md 文件，包含了对这个 BSP 的基本介绍，以及相应的说明，方便用户快速上手。
注：在SConstruct文件中：
Env 是RT-Thread推出的开发辅助工具，针对基于RT-Thread操作系统的项目工程，提供编译构建环境、图形化系统配置及软件包管理功能。其内置的 menuconfig 提供了简单易用的配置剪裁工具，可对内核、组件和软件包进行自由裁剪，使系统以搭积木的方式进行构建。
```RTT_ROOT``` 这个变量指向了RT-Thread的发布源代码根目录。如果你仅计划编译bsp目录下的target，这个`RTT_ROOT`可以使用默认配置。另外，你也可以设置同名的环境变量来指向不同的RT-Thread源代码根目录。
[下载 Env 工具](https://www.rt-thread.org/page/download.html)
当你把相关的配置都配置正确后，你可以在具有目标目录下（这个目录应包括rtconfig.py、SContruct文件）执行以下命令：
[Env 用户手册](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
scons
从而简单地就编译好RT-Thread。
# 资源文档
如果你希望使用IDE来编译RT-Thread，你也可以使用命令行：
## **硬件支持**
scons --target=mdk/mdk4/mdk5/iar/cb -s
RT-Thread RTOS 支持许多架构，并且已经涵盖了当前应用中的主要架构。涉及的架构和芯片制造商有：
来生成mdk/iar等的工程文件。而后在IDE中打开project前缀的工程文件来编译RT-Thread。
- ARM Cortex-M0/M0+：如芯片制造商 ST
注意：RT-Thread的scons构建系统会根据配置头文件rtconfig.h来裁剪系统。例如，如果你关闭了rtconfig.h中的lwIP定义（通过注释掉```#define RT_USING_LWIP```的方式），则scons生成的IDE工程文件中将自动不包括lwIP相关的文件。而在RT-Thread 3.0版本中，可以通过menuconfig的方式来配置整个系统，而不需要再手工更改rtconfig.h配置头文件。
- ARM Cortex-M3：如芯片制造商 ST、全志、灵动等.
## 贡献者 ##
- ARM Cortex-M4：如芯片制造商 ST、Nuvton、NXP、GigaDevice、Realtek、Ambiq Micro等
- ARM Cortex-M7：如芯片制造商 ST、NXP
- ARM Cortex-M23：如芯片制造商 GigaDevice
- ARM Cortex-R4
- ARM Cortex-A8/A9：如芯片制造商 NXP
- ARM7：如芯片制造商Samsung
- ARM9：如芯片制造商Allwinner、Xilinx 、GOKE
- ARM11：如芯片制造商Fullhan
- MIPS32：如芯片制造商loongson、Ingenic
- RISC-V：如芯片制造商Hifive、Kendryte、[芯来Nuclei](https://nucleisys.com/)
- ARC：如芯片制造商SYNOPSYS
- DSP：如芯片制造商 TI
- C-Sky
- x86
## **支持的 IDE 和编译器**
RT-Thread主要支持的IDE/编译器包括：
- MDK KEIL
- IAR
- Gcc
- RT-Thread Studio
使用基于 Python 的 [scons](http://www.scons.org/) 进行命令行生成。
RT-Thread Studio演示：
![studiozh](./documentation/figures/studiozh.gif)
## **快速上手**
RT-Thread BSP可以直接编译并下载到相应的开发板使用。此外，RT-Thread还提供 qemu-vexpress-a9 BSP，无需硬件平台即可使用。有关详细信息，请参阅下面的入门指南。
[QEMU 入门指南(Windows)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu.md)
[QEMU 入门指南(Ubuntu)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu_linux.md)
## 文档
[文档中心](https://www.rt-thread.org/document/site/ ) | [编程指南](https://www.rt-thread.org/document/site/programming-manual/basic/basic/ )
[应用 RT-Thread 实现蜂鸣器播放器教程](https://www.rt-thread.org/document/site/tutorial/beep-player/) | [分布式温度监控系统教程](https://www.rt-thread.org/document/site/tutorial/temperature-system/ ) | [智能车连载教程](https://www.rt-thread.org/document/site/tutorial/smart-car/ )
## 例程
[内核示例](https://github.com/RT-Thread-packages/kernel-sample) | [设备示例代码](https://github.com/RT-Thread-packages/peripheral-sample ) | [文件系统示例代码](https://github.com/RT-Thread-packages/filesystem-sample ) | [网络示例代码](https://github.com/RT-Thread-packages/network-sample ) | [RT-Thread API参考手册](https://www.rt-thread.org/document/api/ )
[基于STM32L475 IoT Board 开发板SDK](https://github.com/RT-Thread/IoT_Board) | [基于W601 IoT Board 开发板SDK](https://github.com/RT-Thread/W601_IoT_Board)
## 视频
RT-Thread视频中心提供了一系列RT-Thread相关教程及分享内容。
如：内核入门系列 | Env系列 | 网络系列 | Nano移植系列 | RT-Thread Studio系列 | 柿饼UI系列 | 答疑直播系列 | 社区作品系列
更多详情，请前往 [视频中心](https://www.rt-thread.org/page/video.html)
# **许可协议**
RT-Thread系统完全开源，3.1.0 及以前的版本遵循 GPL V2 + 开源许可协议。从 3.1.0 以后的版本遵循Apache License 2.0开源许可协议，可以免费在商业产品中使用，并且不需要公开私有代码。
```
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
```
# 社区支持
RT-Thread非常感谢所有社区小伙伴的支持，在使用RT-Thread的过程中若您有任何的想法，建议或疑问都可通过以下方式联系到 RT-Thread，我们也实时在这些频道更新RT-Thread的最新讯息。同时，任何问题都可以在 [issue section](https://github.com/RT-Thread/rtthread-manual-doc/issues) 中提出。通过创建一个issue来描述您的问题，社区成员将回答这些问题。
[官网]( https://www.rt-thread.org) | [论坛]( https://www.rt-thread.org/qa/forum.php) | [哔哩哔哩官方账号](https://space.bilibili.com/423462075?spm_id_from=333.788.b_765f7570696e666f.2) | [微博官方账号](https://weibo.com/rtthread?is_hot=1) | [知乎官方账号](https://www.zhihu.com/topic/19964581/hot)
RT-Thread微信公众号：
![qrcode](./documentation/figures/qrcode.png)
# 贡献代码
如果您对RT-Thread感兴趣，并希望参与RT-Thread的开发并成为代码贡献者，请参阅[代码贡献指南](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/contribution_guide/contribution_guide.md)。
请访问github上RT-Thread项目上的contributors了解已经为RT-Thread提交过代码，PR的贡献者。感谢所有为RT-Thread付出的开发者们！
bsp/allwinner_tina/drivers/drv_gpio.c
+1
View File
@@ -538,6 +538,7 @@ static const struct rt_pin_ops ops =
pin_attach_irq,
pin_detach_irq,
pin_irq_enable,
RT_NULL,
};
#endif
bsp/amebaz/libraries/Kconfig
+1 -1
View File
@@ -1,7 +1,7 @@
menu "External Libraries"
config RT_USING_SMARTCONFIG_LIB
bool "Using RT-Thrad SmartConfig Library"
bool "Using RT-Thread SmartConfig Library"
default n
endmenu
bsp/apollo2/board/gpio.c
+1
View File
@@ -212,6 +212,7 @@ const static struct rt_pin_ops am_pin_ops =
am_pin_attach_irq,
am_pin_dettach_irq,
am_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_acc.h
+95
View File
@@ -0,0 +1,95 @@
/**
**************************************************************************
* File Name : at32f4xx_acc.h
* Description : at32f4xx ACC header file
* Date : 2018-10-08
* Version : V1.0.5
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32f4xx_ACC_H
#define __AT32f4xx_ACC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup ACC
* @{
*/
/** @defgroup ACC_Exported_Constants
* @{
*/
#define ACC_CAL_Enable ((uint16_t)0x0001)
#define ACC_CAL_ON ((uint16_t)0x0001)
#define ACC_TRIM_ON ((uint16_t)0x0003)
#define ACC_CAL_HSICAL ((uint16_t)0x0000)
#define ACC_CAL_HSITRIM ((uint16_t)0x0002)
#define ACC_FLAG_RSLOST ((uint16_t)0x0002)
#define ACC_FLAG_CALRDY ((uint16_t)0x0001)
#define ACC_IT_CALRDYIEN ((uint16_t)0x0020)
#define ACC_IT_EIEN ((uint16_t)0x0010)
/**
* @}
*/
/** @defgroup ACC_Exported_Functions
* @{
*/
void ACC_EnterCALMode(uint16_t ACC_ON, FunctionalState NewState);
void ACC_ExitCALMode(void);
void ACC_SetStep(uint8_t StepValue);
void ACC_CAL_Choose(uint16_t ACC_Calibration_Choose);
void ACC_ITConfig(uint16_t ACC_IT, FunctionalState NewState);
uint8_t ACC_GetHSITRIM(void);
uint8_t ACC_GetHSICAL(void);
void ACC_WriteC1(uint16_t ACC_C1_Value);
void ACC_WriteC2(uint16_t ACC_C2_Value);
void ACC_WriteC3(uint16_t ACC_C3_Value);
uint16_t ACC_ReadC1(void);
uint16_t ACC_ReadC2(void);
uint16_t ACC_ReadC3(void);
FlagStatus ACC_GetFlagStatus(uint16_t ACC_FLAG);
void ACC_ClearFlag(uint16_t ACC_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_ACC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_adc.h
+526
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_bkp.h
+198
View File
@@ -0,0 +1,198 @@
/**
**************************************************************************
* File Name : at32f4xx_bkp.h
* Description : at32f4xx BKP header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_BKP_H
#define __AT32F4xx_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup BKP
* @{
*/
/** @defgroup BKP_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Constants
* @{
*/
/** @defgroup Tamper_Pin_active_level
* @{
*/
#define BKP_TamperPinLv_H ((uint16_t)0x0000)
#define BKP_TamperPinLv_L ((uint16_t)0x0001)
#define IS_BKP_TAMPER_PIN_LV(LV) (((LV) == BKP_TamperPinLv_H) || \
((LV) == BKP_TamperPinLv_L))
/**
* @}
*/
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
* @{
*/
#define BKP_RTCOutput_None ((uint16_t)0x0000)
#define BKP_RTCOutput_CalClk ((uint16_t)0x0080)
#define BKP_RTCOutput_Alarm_Pulse ((uint16_t)0x0100)
#define BKP_RTCOutput_Second_Pulse ((uint16_t)0x0300)
#if defined (AT32F403Axx) || defined (AT32F407xx)
#define BKP_RTCOutput_Alarm_Toggle ((uint16_t)0x0900)
#define BKP_RTCOutput_Second_Toggle ((uint16_t)0x0B00)
#endif
#if defined (AT32F403Axx) || defined (AT32F407xx)
#define IS_BKP_RTC_OUTPUT_SEL(SEL) (((SEL) == BKP_RTCOutput_None) || \
((SEL) == BKP_RTCOutput_CalClk) || \
((SEL) == BKP_RTCOutput_Alarm_Pulse) || \
((SEL) == BKP_RTCOutput_Second_Pulse) || \
((SEL) == BKP_RTCOutput_Alarm_Toggle) || \
((SEL) == BKP_RTCOutput_Second_Toggle))
#elif defined (AT32F403xx) || defined (AT32F413xx)
#define IS_BKP_RTC_OUTPUT_SEL(SEL) (((SEL) == BKP_RTCOutput_None) || \
((SEL) == BKP_RTCOutput_CalClk) || \
((SEL) == BKP_RTCOutput_Alarm_Pulse) || \
((SEL) == BKP_RTCOutput_Second_Pulse))
#endif
/**
* @}
*/
/** @defgroup Data_Backup_Register
* @{
*/
#define BKP_DT1 ((uint16_t)0x0004)
#define BKP_DT2 ((uint16_t)0x0008)
#define BKP_DT3 ((uint16_t)0x000C)
#define BKP_DT4 ((uint16_t)0x0010)
#define BKP_DT5 ((uint16_t)0x0014)
#define BKP_DT6 ((uint16_t)0x0018)
#define BKP_DT7 ((uint16_t)0x001C)
#define BKP_DT8 ((uint16_t)0x0020)
#define BKP_DT9 ((uint16_t)0x0024)
#define BKP_DT10 ((uint16_t)0x0028)
#define BKP_DT11 ((uint16_t)0x0040)
#define BKP_DT12 ((uint16_t)0x0044)
#define BKP_DT13 ((uint16_t)0x0048)
#define BKP_DT14 ((uint16_t)0x004C)
#define BKP_DT15 ((uint16_t)0x0050)
#define BKP_DT16 ((uint16_t)0x0054)
#define BKP_DT17 ((uint16_t)0x0058)
#define BKP_DT18 ((uint16_t)0x005C)
#define BKP_DT19 ((uint16_t)0x0060)
#define BKP_DT20 ((uint16_t)0x0064)
#define BKP_DT21 ((uint16_t)0x0068)
#define BKP_DT22 ((uint16_t)0x006C)
#define BKP_DT23 ((uint16_t)0x0070)
#define BKP_DT24 ((uint16_t)0x0074)
#define BKP_DT25 ((uint16_t)0x0078)
#define BKP_DT26 ((uint16_t)0x007C)
#define BKP_DT27 ((uint16_t)0x0080)
#define BKP_DT28 ((uint16_t)0x0084)
#define BKP_DT29 ((uint16_t)0x0088)
#define BKP_DT30 ((uint16_t)0x008C)
#define BKP_DT31 ((uint16_t)0x0090)
#define BKP_DT32 ((uint16_t)0x0094)
#define BKP_DT33 ((uint16_t)0x0098)
#define BKP_DT34 ((uint16_t)0x009C)
#define BKP_DT35 ((uint16_t)0x00A0)
#define BKP_DT36 ((uint16_t)0x00A4)
#define BKP_DT37 ((uint16_t)0x00A8)
#define BKP_DT38 ((uint16_t)0x00AC)
#define BKP_DT39 ((uint16_t)0x00B0)
#define BKP_DT40 ((uint16_t)0x00B4)
#define BKP_DT41 ((uint16_t)0x00B8)
#define BKP_DT42 ((uint16_t)0x00BC)
#define IS_BKP_DT(DT) (((DT) == BKP_DT1) || ((DT) == BKP_DT2) || ((DT) == BKP_DT3) || \
((DT) == BKP_DT4) || ((DT) == BKP_DT5) || ((DT) == BKP_DT6) || \
((DT) == BKP_DT7) || ((DT) == BKP_DT8) || ((DT) == BKP_DT9) || \
((DT) == BKP_DT10) || ((DT) == BKP_DT11) || ((DT) == BKP_DT12) || \
((DT) == BKP_DT13) || ((DT) == BKP_DT14) || ((DT) == BKP_DT15) || \
((DT) == BKP_DT16) || ((DT) == BKP_DT17) || ((DT) == BKP_DT18) || \
((DT) == BKP_DT19) || ((DT) == BKP_DT20) || ((DT) == BKP_DT21) || \
((DT) == BKP_DT22) || ((DT) == BKP_DT23) || ((DT) == BKP_DT24) || \
((DT) == BKP_DT25) || ((DT) == BKP_DT26) || ((DT) == BKP_DT27) || \
((DT) == BKP_DT28) || ((DT) == BKP_DT29) || ((DT) == BKP_DT30) || \
((DT) == BKP_DT31) || ((DT) == BKP_DT32) || ((DT) == BKP_DT33) || \
((DT) == BKP_DT34) || ((DT) == BKP_DT35) || ((DT) == BKP_DT36) || \
((DT) == BKP_DT37) || ((DT) == BKP_DT38) || ((DT) == BKP_DT39) || \
((DT) == BKP_DT40) || ((DT) == BKP_DT41) || ((DT) == BKP_DT42))
#define IS_BKP_CAL_VAL(VAL) ((VAL) <= 0x7F)
/**
* @}
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Functions
* @{
*/
void BKP_Reset(void);
void BKP_TamperPinLvConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_IntConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalValue(uint8_t CalibrationValue);
void BKP_WriteBackupReg(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupReg(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetIntStatus(void);
void BKP_ClearIntPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_BKP_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_can.h
+689
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_comp.h
+271
View File
@@ -0,0 +1,271 @@
/**
******************************************************************************
* @file at32f4xx_comp.h
* @author Artery
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the COMP firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 Artery</center></h2>
*
* Licensed under Artery Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4XX_COMP_H
#define __AT32F4XX_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup AT32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t COMP_INMInput; /*!< Selects the inverting input of the comparator.
This parameter can be a value of @ref COMP_INMInput */
uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
This parameter can be a value of @ref COMP_Output */
uint32_t COMP_OutPolarity; /*!< Selects the output polarity of the comparator.
This parameter can be a value of @ref COMP_OutputPolarity */
uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
This parameter can be a value of @ref COMP_Hysteresis */
uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
and allows to adjust the speed/consumption.
This parameter can be a value of @ref COMP_Mode */
}COMP_InitType;
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants
* @{
*/
/** @defgroup COMP_Selection
* @{
*/
#define COMP1_Selection ((uint32_t)0x00000000) /*!< COMP1 Selection */
#define COMP2_Selection ((uint32_t)0x00000010) /*!< COMP2 Selection */
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP1_Selection) || \
((PERIPH) == COMP2_Selection))
/**
* @}
*/
/** @defgroup COMP_NonInvertingInput
* @{
*/
#define COMP_INPInput_00 ((uint32_t)0x00000000) /*!< PA5/PA7 connected to comparator1/2 non-inverting input */
#define COMP_INPInput_01 ((uint32_t)0x00000001) /*!< PA1/PA3 connected to comparator1/2 non-inverting input */
#define COMP_INPInput_10 ((uint32_t)0x00000002) /*!< PA0/PA2 connected to comparator1/2 non-inverting input */
#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_INPInput_00) || \
((INPUT) == COMP_INPInput_01) || \
((INPUT) == COMP_INPInput_10))
/** @defgroup COMP_InvertingInput
* @{
*/
#define COMP_INMInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
#define COMP_INMInput_1_2VREFINT ((uint32_t)0x00000010) /*!< 1/2 VREFINT connected to comparator inverting input */
#define COMP_INMInput_3_4VREFINT ((uint32_t)0x00000020) /*!< 3/4 VREFINT connected to comparator inverting input */
#define COMP_INMInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
#define COMP_INMInput_IN1 ((uint32_t)0x00000040) /*!< I/O (PA4 for COMP1 and PA3 for COMP2) connected to comparator inverting input */
#define COMP_INMInput_IN2 ((uint32_t)0x00000050) /*!< I/O (PA5 for COMP1 and PA7 for COMP2) connected to comparator inverting input */
#define COMP_INMInput_IN3 ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_INMInput_1_4VREFINT) || \
((INPUT) == COMP_INMInput_1_2VREFINT) || \
((INPUT) == COMP_INMInput_3_4VREFINT) || \
((INPUT) == COMP_INMInput_VREFINT) || \
((INPUT) == COMP_INMInput_IN1) || \
((INPUT) == COMP_INMInput_1_4VREFINT) || \
((INPUT) == COMP_INMInput_IN3))
/**
* @}
*/
/** @defgroup COMP_Output
* @{
*/
#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
#define COMP_Output_TMR1BKIN ((uint32_t)0x00000100) /*!< COMP output connected to TIM1 Break Input (BKIN) */
#define COMP_Output_TMR1IC1 ((uint32_t)0x00000200) /*!< COMP output connected to TIM1 Input Capture 1 */
#define COMP_Output_TMR1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */
#define COMP_Output_TMR2IC4 ((uint32_t)0x00000400) /*!< COMP output connected to TIM2 Input Capture 4 */
#define COMP_Output_TMR2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */
#define COMP_Output_TMR3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */
#define COMP_Output_TMR3OCREFCLR ((uint32_t)0x00000700) /*!< COMP output connected to TIM3 OCREF Clear */
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
((OUTPUT) == COMP_Output_TMR1BKIN) || \
((OUTPUT) == COMP_Output_TMR1IC1) || \
((OUTPUT) == COMP_Output_TMR1OCREFCLR) || \
((OUTPUT) == COMP_Output_TMR2IC4) || \
((OUTPUT) == COMP_Output_TMR2OCREFCLR) || \
((OUTPUT) == COMP_Output_TMR3IC1) || \
((OUTPUT) == COMP_Output_TMR3OCREFCLR))
/**
* @}
*/
/** @defgroup COMP_OutputPolarity
* @{
*/
#define COMP_OutPolarity_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
#define COMP_OutPolarity_Inverted COMP_CTRLSTS_COMP1POL /*!< COMP output on GPIO is inverted */
#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutPolarity_NonInverted) || \
((POL) == COMP_OutPolarity_Inverted))
/**
* @}
*/
/** @defgroup COMP_Hysteresis
* @{
*/
/* Please refer to the electrical characteristics in the device datasheet for
the hysteresis level */
#define COMP_Hysteresis_No ((uint32_t)0x00000000) /*!< No hysteresis */
#define COMP_Hysteresis_Low COMP_CTRLSTS_COMP1HYST_0 /*!< Hysteresis level low */
#define COMP_Hysteresis_Medium COMP_CTRLSTS_COMP1HYST_1 /*!< Hysteresis level medium */
#define COMP_Hysteresis_High COMP_CTRLSTS_COMP1HYST /*!< Hysteresis level high */
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
((HYSTERESIS) == COMP_Hysteresis_Low) || \
((HYSTERESIS) == COMP_Hysteresis_Medium) || \
((HYSTERESIS) == COMP_Hysteresis_High))
/**
* @}
*/
/** @defgroup COMP_Mode
* @{
*/
/* Please refer to the electrical characteristics in the device datasheet for
the power consumption values */
#define COMP_Mode_Fast ((uint32_t)0x00000000) /*!< High Speed */
#define COMP_Mode_Slow COMP_CTRLSTS_COMP1MDE_0 /*!< Low power mode */
#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_Slow) || \
((MODE) == COMP_Mode_Fast))
/**
* @}
*/
/** @defgroup COMP_OutputLevel
* @{
*/
/* When output polarity is not inverted, comparator output is high when
the non-inverting input is at a higher voltage than the inverting input */
#define COMP_OutputState_High COMP_CTRLSTS_COMP1OUT
/* When output polarity is not inverted, comparator output is low when
the non-inverting input is at a lower voltage than the inverting input*/
#define COMP_OutputState_Low ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup COMP_High_Pulse_Filter
* @{
*/
#define IS_COMP_HighPulseCnt(HighPulse) ((HighPulse) <= 0x3F)
/**
* @}
*/
/** @defgroup COMP_Low_Pulse_Filter
* @{
*/
#define IS_COMP_LowPulseCnt(LowPulse) ((LowPulse) <= 0x3F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the COMP configuration to the default reset state ****/
void COMP_Reset(void);
/* Initialization and Configuration functions *********************************/
void COMP_Init(uint32_t COMP_Selection, COMP_InitType* COMP_InitStruct);
void COMP_SelectINPInput(uint32_t COMP_Selection, uint32_t COMP_INPInput);
void COMP_StructInit(COMP_InitType* COMP_InitStruct);
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
void COMP_SwitchCmd(FunctionalState NewState);
uint32_t COMP_GetOutputState(uint32_t COMP_Selection);
/* Window mode control function ***********************************************/
void COMP_WindowCmd(FunctionalState NewState);
/* COMP configuration locking function ****************************************/
void COMP_LockConfig(uint32_t COMP_Selection);
/* COMP configuration glitch filter ****************************************/
void COMP_FilterConfig(uint16_t COMP_HighPulseCnt, uint16_t COMP_LowPulseCnt, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /*__AT32F4xx_COMP_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT Artery *****END OF FILE****/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_crc.h
+82
View File
@@ -0,0 +1,82 @@
/**
**************************************************************************
* File Name : at32f4xx_crc.h
* Description : at32f4xx CRC header file
* Date : 2018-10-08
* Version : V1.0.5
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_CRC_H
#define __AT32F4xx_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Functions
* @{
*/
void CRC_ResetDT(void);
uint32_t CRC_CalculateCRC(uint32_t Data);
uint32_t CRC_CalculateBlkCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDTReg(uint8_t IDValue);
uint8_t CRC_GetIDTReg(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_CRC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_dac.h
+269
View File
@@ -0,0 +1,269 @@
/**
**************************************************************************
* File Name : at32f4xx_dac.h
* Description : at32f4xx DAC header file
* Date : 2018-10-08
* Version : V1.0.5
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_DAC_H
#define __AT32F4xx_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
} DAC_InitType;
/**
* @}
*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_TMR6_TRGO ((uint32_t)0x00000004) /*!< TMR6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_TMR8_TRGO ((uint32_t)0x0000000C) /*!< TMR8 TRGO selected as external conversion trigger for DAC channel
only in High-density devices*/
#define DAC_Trigger_TMR7_TRGO ((uint32_t)0x00000014) /*!< TMR7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_TMR5_TRGO ((uint32_t)0x0000001C) /*!< TMR5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_TMR2_TRGO ((uint32_t)0x00000024) /*!< TMR2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_TMR4_TRGO ((uint32_t)0x0000002C) /*!< TMR4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_INT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_TMR6_TRGO) || \
((TRIGGER) == DAC_Trigger_TMR8_TRGO) || \
((TRIGGER) == DAC_Trigger_TMR7_TRGO) || \
((TRIGGER) == DAC_Trigger_TMR5_TRGO) || \
((TRIGGER) == DAC_Trigger_TMR2_TRGO) || \
((TRIGGER) == DAC_Trigger_TMR4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_INT9) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_LFSRUnmsk_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmsk_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmsk_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmp_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmp_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmp_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmp_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmp_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmp_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmp_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmp_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmp_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmp_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmp_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmp_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmsk_Bit0) || \
((VALUE) == DAC_LFSRUnmsk_Bits1_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits2_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits3_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits4_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits5_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits6_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits7_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits8_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits9_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits10_0) || \
((VALUE) == DAC_LFSRUnmsk_Bits11_0) || \
((VALUE) == DAC_TriangleAmp_1) || \
((VALUE) == DAC_TriangleAmp_3) || \
((VALUE) == DAC_TriangleAmp_7) || \
((VALUE) == DAC_TriangleAmp_15) || \
((VALUE) == DAC_TriangleAmp_31) || \
((VALUE) == DAC_TriangleAmp_63) || \
((VALUE) == DAC_TriangleAmp_127) || \
((VALUE) == DAC_TriangleAmp_255) || \
((VALUE) == DAC_TriangleAmp_511) || \
((VALUE) == DAC_TriangleAmp_1023) || \
((VALUE) == DAC_TriangleAmp_2047) || \
((VALUE) == DAC_TriangleAmp_4095))
/**
* @}
*/
/** @defgroup DAC_output_buffer
* @{
*/
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_data_alignment
* @{
*/
#define DAC_Align_12b_Right ((uint32_t)0x00000000)
#define DAC_Align_12b_Left ((uint32_t)0x00000004)
#define DAC_Align_8b_Right ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_Right) || \
((ALIGN) == DAC_Align_12b_Left) || \
((ALIGN) == DAC_Align_8b_Right))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Functions
* @{
*/
void DAC_Reset(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct);
void DAC_StructInit(DAC_InitType* DAC_InitStruct);
void DAC_Ctrl(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DMACtrl(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCtrl(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCtrl(FunctionalState NewState);
void DAC_WaveGenerationCtrl(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#ifdef __cplusplus
}
#endif
#endif /*__AT32F4xx_DAC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_dbgmcu.h
+105
View File
@@ -0,0 +1,105 @@
/**
**************************************************************************
* File Name : at32f4xx_dbgmcu.h
* Description : at32f4xx MCUDBG header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_MCUDBG_H
#define __AT32F4xx_MCUDBG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DBGMCU
* @{
*/
/** @defgroup DBGMCU_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Constants
* @{
*/
#define MCUDBG_SLEEP ((uint32_t)0x00000001)
#define MCUDBG_STOP ((uint32_t)0x00000002)
#define MCUDBG_STANDBY ((uint32_t)0x00000004)
#define MCUDBG_IWDG_STOP ((uint32_t)0x00000100)
#define MCUDBG_WWDG_STOP ((uint32_t)0x00000200)
#define MCUDBG_TMR1_STOP ((uint32_t)0x00000400)
#define MCUDBG_TMR2_STOP ((uint32_t)0x00000800)
#define MCUDBG_TMR3_STOP ((uint32_t)0x00001000)
#define MCUDBG_TMR4_STOP ((uint32_t)0x00002000)
#define MCUDBG_CAN1_STOP ((uint32_t)0x00004000)
#define MCUDBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define MCUDBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define MCUDBG_TMR8_STOP ((uint32_t)0x00020000)
#define MCUDBG_TMR5_STOP ((uint32_t)0x00040000)
#define MCUDBG_TMR6_STOP ((uint32_t)0x00080000)
#define MCUDBG_TMR7_STOP ((uint32_t)0x00100000)
#define MCUDBG_TMR15_STOP ((uint32_t)0x00400000)
#define MCUDBG_TMR12_STOP ((uint32_t)0x02000000)
#define MCUDBG_TMR13_STOP ((uint32_t)0x04000000)
#define MCUDBG_TMR14_STOP ((uint32_t)0x08000000)
#define MCUDBG_TMR9_STOP ((uint32_t)0x10000000)
#define MCUDBG_TMR10_STOP ((uint32_t)0x20000000)
#define MCUDBG_TMR11_STOP ((uint32_t)0x40000000)
#define MCUDBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x80000000)
#define IS_MCUDBG_PERIPH(PERIPH) ((((PERIPH) & 0x008000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Functions
* @{
*/
uint32_t MCUDBG_GetRevID(void);
uint32_t MCUDBG_GetDevID(void);
void MCUDBG_PeriphDebugModeConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_MCUDBG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_dma.h
+574
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_ertc.h
+864
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_eth.h
+1735
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_exti.h
+191
View File
@@ -0,0 +1,191 @@
/**
**************************************************************************
* File Name : at32f4xx_exti.h
* Description : at32f4xx EXTI header file
* Date : 2019-06-04
* Version : V1.0.5
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_EXTI_H
#define __AT32F4xx_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @defgroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTIMode_Type;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTITrigger_Type;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_Type EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_Type */
EXTITrigger_Type EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_Type */
FunctionalState EXTI_LineEnable; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitType;
/**
* @}
*/
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_Lines
* @{
*/
#define EXTI_Line0 ((uint32_t)0x000001) /*!< External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x000002) /*!< External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x000004) /*!< External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x000008) /*!< External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x000010) /*!< External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x000020) /*!< External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x000040) /*!< External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x000080) /*!< External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x000100) /*!< External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x000200) /*!< External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x000400) /*!< External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x000800) /*!< External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x001000) /*!< External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x002000) /*!< External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x004000) /*!< External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x008000) /*!< External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x010000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x040000) /*!< External interrupt line 18 Connected to the USB Device FS
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x080000) /*!< External interrupt line 19 Connected to the COMP1*/
#ifdef AT32F415xx
#define EXTI_Line20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the COMP2*/
#define EXTI_Line21 ((uint32_t)0x200000) /*!< External interrupt line 20 Connected to the RTC Temper_Pin and Temper_Stamp*/
#define EXTI_Line22 ((uint32_t)0x400000) /*!< External interrupt line 20 Connected to the RTC Wakeup*/
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
((LINE) == EXTI_Line22))
#else
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
#endif
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_Reset(void);
void EXTI_Init(EXTI_InitType* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitType* EXTI_InitStruct);
void EXTI_GenerateSWInt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetIntStatus(uint32_t EXTI_Line);
void EXTI_ClearIntPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_flash.h
+428
View File
@@ -0,0 +1,428 @@
/**
**************************************************************************
* File Name : at32f4xx_flash.h
* Description : at32f4xx FMC header file
* Date : 2018-10-08
* Version : V1.0.5
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_FLASH_H
#define __AT32F4xx_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_Exported_Types
* @{
*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BSY = 1,
FLASH_PGRM_FLR,
FLASH_WRPRT_FLR,
FLASH_PRC_DONE,
FLASH_TIMEOUT
} FLASH_Status;
/**
* @brief BANK3 SEL
*/
typedef enum
{
E_BANK3_SEL_ESMT_SP=0,
E_BANK3_SEL_GENERAL_CFGQE,
E_BANK3_SEL_GENERAL,
}T_BANK3_SEL;
/**
* @}
*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
/* Values to be used with AT32F4xx Medium-density devices */
#define FLASH_WRPRT_PAGE_0to3 ((uint32_t)0x00000001) /*!< AT32F4xx Medium-density devices: Write protection of page 0 to 3 */
#define FLASH_WRPRT_PAGE_4to7 ((uint32_t)0x00000002) /*!< AT32F4xx Medium-density devices: Write protection of page 4 to 7 */
#define FLASH_WRPRT_PAGE_8to11 ((uint32_t)0x00000004) /*!< AT32F4xx Medium-density devices: Write protection of page 8 to 11 */
#define FLASH_WRPRT_PAGE_12to15 ((uint32_t)0x00000008) /*!< AT32F4xx Medium-density devices: Write protection of page 12 to 15 */
#define FLASH_WRPRT_PAGE_16to19 ((uint32_t)0x00000010) /*!< AT32F4xx Medium-density devices: Write protection of page 16 to 19 */
#define FLASH_WRPRT_PAGE_20to23 ((uint32_t)0x00000020) /*!< AT32F4xx Medium-density devices: Write protection of page 20 to 23 */
#define FLASH_WRPRT_PAGE_24to27 ((uint32_t)0x00000040) /*!< AT32F4xx Medium-density devices: Write protection of page 24 to 27 */
#define FLASH_WRPRT_PAGE_28to31 ((uint32_t)0x00000080) /*!< AT32F4xx Medium-density devices: Write protection of page 28 to 31 */
#define FLASH_WRPRT_PAGE_32to35 ((uint32_t)0x00000100) /*!< AT32F4xx Medium-density devices: Write protection of page 32 to 35 */
#define FLASH_WRPRT_PAGE_36to39 ((uint32_t)0x00000200) /*!< AT32F4xx Medium-density devices: Write protection of page 36 to 39 */
#define FLASH_WRPRT_PAGE_40to43 ((uint32_t)0x00000400) /*!< AT32F4xx Medium-density devices: Write protection of page 40 to 43 */
#define FLASH_WRPRT_PAGE_44to47 ((uint32_t)0x00000800) /*!< AT32F4xx Medium-density devices: Write protection of page 44 to 47 */
#define FLASH_WRPRT_PAGE_48to51 ((uint32_t)0x00001000) /*!< AT32F4xx Medium-density devices: Write protection of page 48 to 51 */
#define FLASH_WRPRT_PAGE_52to55 ((uint32_t)0x00002000) /*!< AT32F4xx Medium-density devices: Write protection of page 52 to 55 */
#define FLASH_WRPRT_PAGE_56to59 ((uint32_t)0x00004000) /*!< AT32F4xx Medium-density devices: Write protection of page 56 to 59 */
#define FLASH_WRPRT_PAGE_60to63 ((uint32_t)0x00008000) /*!< AT32F4xx Medium-density devices: Write protection of page 60 to 63 */
#define FLASH_WRPRT_PAGE_64to67 ((uint32_t)0x00010000) /*!< AT32F4xx Medium-density devices: Write protection of page 64 to 67 */
#define FLASH_WRPRT_PAGE_68to71 ((uint32_t)0x00020000) /*!< AT32F4xx Medium-density devices: Write protection of page 68 to 71 */
#define FLASH_WRPRT_PAGE_72to75 ((uint32_t)0x00040000) /*!< AT32F4xx Medium-density devices: Write protection of page 72 to 75 */
#define FLASH_WRPRT_PAGE_76to79 ((uint32_t)0x00080000) /*!< AT32F4xx Medium-density devices: Write protection of page 76 to 79 */
#define FLASH_WRPRT_PAGE_80to83 ((uint32_t)0x00100000) /*!< AT32F4xx Medium-density devices: Write protection of page 80 to 83 */
#define FLASH_WRPRT_PAGE_84to87 ((uint32_t)0x00200000) /*!< AT32F4xx Medium-density devices: Write protection of page 84 to 87 */
#define FLASH_WRPRT_PAGE_88to91 ((uint32_t)0x00400000) /*!< AT32F4xx Medium-density devices: Write protection of page 88 to 91 */
#define FLASH_WRPRT_PAGE_92to95 ((uint32_t)0x00800000) /*!< AT32F4xx Medium-density devices: Write protection of page 92 to 95 */
#define FLASH_WRPRT_PAGE_96to99 ((uint32_t)0x01000000) /*!< AT32F4xx Medium-density devices: Write protection of page 96 to 99 */
#define FLASH_WRPRT_PAGE_100to103 ((uint32_t)0x02000000) /*!< AT32F4xx Medium-density devices: Write protection of page 100 to 103 */
#define FLASH_WRPRT_PAGE_104to107 ((uint32_t)0x04000000) /*!< AT32F4xx Medium-density devices: Write protection of page 104 to 107 */
#define FLASH_WRPRT_PAGE_108to111 ((uint32_t)0x08000000) /*!< AT32F4xx Medium-density devices: Write protection of page 108 to 111 */
#define FLASH_WRPRT_PAGE_112to115 ((uint32_t)0x10000000) /*!< AT32F4xx Medium-density devices: Write protection of page 112 to 115 */
#define FLASH_WRPRT_PAGE_116to119 ((uint32_t)0x20000000) /*!< AT32F4xx Medium-density devices: Write protection of page 115 to 119 */
#define FLASH_WRPRT_PAGE_120to123 ((uint32_t)0x40000000) /*!< AT32F4xx Medium-density devices: Write protection of page 120 to 123 */
#define FLASH_WRPRT_PAGE_124to127 ((uint32_t)0x80000000) /*!< AT32F4xx Medium-density devices: Write protection of page 124 to 127 */
/* Values to be used with AT32F4xx High-density, XL-density and AT32F415xx devices */
#define FLASH_WRPRT_PAGE_0to1 ((uint32_t)0x00000001) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 0 to 1 */
#define FLASH_WRPRT_PAGE_2to3 ((uint32_t)0x00000002) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 2 to 3 */
#define FLASH_WRPRT_PAGE_4to5 ((uint32_t)0x00000004) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 4 to 5 */
#define FLASH_WRPRT_PAGE_6to7 ((uint32_t)0x00000008) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 6 to 7 */
#define FLASH_WRPRT_PAGE_8to9 ((uint32_t)0x00000010) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 8 to 9 */
#define FLASH_WRPRT_PAGE_10to11 ((uint32_t)0x00000020) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 10 to 11 */
#define FLASH_WRPRT_PAGE_12to13 ((uint32_t)0x00000040) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 12 to 13 */
#define FLASH_WRPRT_PAGE_14to15 ((uint32_t)0x00000080) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 14 to 15 */
#define FLASH_WRPRT_PAGE_16to17 ((uint32_t)0x00000100) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 16 to 17 */
#define FLASH_WRPRT_PAGE_18to19 ((uint32_t)0x00000200) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 18 to 19 */
#define FLASH_WRPRT_PAGE_20to21 ((uint32_t)0x00000400) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 20 to 21 */
#define FLASH_WRPRT_PAGE_22to23 ((uint32_t)0x00000800) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 22 to 23 */
#define FLASH_WRPRT_PAGE_24to25 ((uint32_t)0x00001000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 24 to 25 */
#define FLASH_WRPRT_PAGE_26to27 ((uint32_t)0x00002000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 26 to 27 */
#define FLASH_WRPRT_PAGE_28to29 ((uint32_t)0x00004000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 28 to 29 */
#define FLASH_WRPRT_PAGE_30to31 ((uint32_t)0x00008000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 30 to 31 */
#define FLASH_WRPRT_PAGE_32to33 ((uint32_t)0x00010000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 32 to 33 */
#define FLASH_WRPRT_PAGE_34to35 ((uint32_t)0x00020000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 34 to 35 */
#define FLASH_WRPRT_PAGE_36to37 ((uint32_t)0x00040000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 36 to 37 */
#define FLASH_WRPRT_PAGE_38to39 ((uint32_t)0x00080000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 38 to 39 */
#define FLASH_WRPRT_PAGE_40to41 ((uint32_t)0x00100000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 40 to 41 */
#define FLASH_WRPRT_PAGE_42to43 ((uint32_t)0x00200000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 42 to 43 */
#define FLASH_WRPRT_PAGE_44to45 ((uint32_t)0x00400000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 44 to 45 */
#define FLASH_WRPRT_PAGE_46to47 ((uint32_t)0x00800000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 46 to 47 */
#define FLASH_WRPRT_PAGE_48to49 ((uint32_t)0x01000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 48 to 49 */
#define FLASH_WRPRT_PAGE_50to51 ((uint32_t)0x02000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 50 to 51 */
#define FLASH_WRPRT_PAGE_52to53 ((uint32_t)0x04000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 52 to 53 */
#define FLASH_WRPRT_PAGE_54to55 ((uint32_t)0x08000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 54 to 55 */
#define FLASH_WRPRT_PAGE_56to57 ((uint32_t)0x10000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 56 to 57 */
#define FLASH_WRPRT_PAGE_58to59 ((uint32_t)0x20000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 58 to 59 */
#define FLASH_WRPRT_PAGE_60to61 ((uint32_t)0x40000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
Write protection of page 60 to 61 */
#define FLASH_WRPRT_PAGE_62to63 ((uint32_t)0x80000000) /*!< AT32F415xx Medium-density devices: Write protection of page 62 to 63 */
#define FLASH_WRPRT_PAGE_62to127 ((uint32_t)0x80000000) /*!< AT32F4xx High-density, AT32F415xx Medium-density, High-density devices:
Write protection of page 62 to 127 */
#define FLASH_WRPRT_PAGE_62to255 ((uint32_t)0x80000000) /*!< AT32F4xx High-density devices: Write protection of page 62 to 255 */
#define FLASH_WRPRT_PAGE_62to511 ((uint32_t)0x80000000) /*!< AT32F4xx XL-density devices: Write protection of page 62 to 511 */
#define FLASH_WRPRT_AllPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
#define IS_FLASH_WRPRT_PAGES(PAGES) (((PAGES) != 0x00000000))
#define IS_FLASH_ADDR(ADDR) (((ADDR) >= 0x08000000) && ((ADDR) <= FLASH_BANK3_ADDR_MAX))
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define UOB_SW_IWDG ((uint16_t)0x0001) /*!< Software IWDG selected */
#define UOB_HW_IWDG ((uint16_t)0x0000) /*!< Hardware IWDG selected */
#define IS_UOB_IWDG_CFG(CFG) (((CFG) == UOB_SW_IWDG) || ((CFG) == UOB_HW_IWDG))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define UOB_NO_RST_STP ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
#define UOB_RST_STP ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
#define IS_UOB_STOP_CFG(CFG) (((CFG) == UOB_NO_RST_STP) || ((CFG) == UOB_RST_STP))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define UOB_NO_RST_STDBY ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
#define UOB_RST_STDBY ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
#define IS_UOB_STDBY_CFG(CFG) (((CFG) == UOB_NO_RST_STDBY) || ((CFG) == UOB_RST_STDBY))
#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
defined(AT32F407RGT7) || defined(AT32F407VGT7)
/**
* @}
*/
/** @defgroup FLASH_Boot
* @{
*/
#define FLASH_BOOT_FROM_BANK1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank1(Default) */
#define FLASH_BOOT_FROM_BANK2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2 or Bank 1,
depending on the activation of the bank */
#define IS_FLASH_BOOT_CFG(CFG) (((CFG) == FLASH_BOOT_FROM_BANK1) || ((CFG) == FLASH_BOOT_FROM_BANK2))
#endif
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_INT_FLR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
#define FLASH_INT_PRCDN ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define FLASH_INT_BANK1_FLR FLASH_INT_FLR /*!< FPEC BANK1 error interrupt source */
#define FLASH_INT_BANK1_PRCDN FLASH_INT_PRCDN /*!< End of FLASH BANK1 Operation Interrupt source */
#define FLASH_INT_BANK3 ((uint32_t)0x40000000)
#define FLASH_INT_BANK3_MASK (~FLASH_INT_BANK3)
#define FLASH_INT_BANK3_FLR ((uint32_t)0x40000400) /*!< FPEC BANK1 error interrupt source */
#define FLASH_INT_BANK3_PRCDN ((uint32_t)0x40001000) /*!< End of FLASH BANK1 Operation Interrupt source */
#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
defined(AT32F407RGT7) || defined(AT32F407VGT7)
#define FLASH_INT_BANK2 ((uint32_t)0x80000000)
#define FLASH_INT_BANK2_MASK (~FLASH_INT_BANK2)
#define FLASH_INT_BANK2_FLR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
#define FLASH_INT_BANK2_PRCDN ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
#define IS_FLASH_INT(INT) ((((INT) & (uint32_t)0x3FFFEBFF) == 0x00000000) && (((INT) != 0x00000000)))
#else
#define IS_FLASH_INT(INT) ((((INT) & (uint32_t)0xBFFFEBFF) == 0x00000000) && (((INT) != 0x00000000)))
#endif
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_PRCDN ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PRGMFLR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTFLR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_UOBFLR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define FLASH_FLAG_BNK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BNK1_PRCDN FLASH_FLAG_PRCDN /*!< FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BNK1_PRGMFLR FLASH_FLAG_PRGMFLR /*!< FLASH BANK1 Program error flag */
#define FLASH_FLAG_BNK1_WRPRTFLR FLASH_FLAG_WRPRTFLR /*!< FLASH BANK1 Write protected error flag */
#define FLASH_FLAG_BANK3 ((uint32_t)0x40000000)
#define FLASH_FLAG_BNK3_BSY ((uint32_t)0x40000001) /*!< FLASH BANK3 Busy flag*/
#define FLASH_FLAG_BNK3_PRCDN ((uint32_t)0x40000020) /*!< FLASH BANK3 End of Operation flag */
#define FLASH_FLAG_BNK3_PRGMFLR ((uint32_t)0x40000004) /*!< FLASH BANK3 Program error flag */
#define FLASH_FLAG_BNK3_WRPRTFLR ((uint32_t)0x40000010) /*!< FLASH BANK3 Write protected error flag */
#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
defined(AT32F407RGT7) || defined(AT32F407VGT7)
#define FLASH_FLAG_BANK2 ((uint32_t)0x80000000)
#define FLASH_FLAG_BNK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
#define FLASH_FLAG_BNK2_PRCDN ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
#define FLASH_FLAG_BNK2_PRGMFLR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
#define FLASH_FLAG_BNK2_WRPRTFLR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x3FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PRCDN) || \
((FLAG) == FLASH_FLAG_PRGMFLR) || ((FLAG) == FLASH_FLAG_WRPRTFLR) || \
((FLAG) == FLASH_FLAG_UOBFLR)|| \
((FLAG) == FLASH_FLAG_BNK1_BSY) || ((FLAG) == FLASH_FLAG_BNK1_PRCDN) || \
((FLAG) == FLASH_FLAG_BNK1_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK1_WRPRTFLR) || \
((FLAG) == FLASH_FLAG_BNK2_BSY) || ((FLAG) == FLASH_FLAG_BNK2_PRCDN) || \
((FLAG) == FLASH_FLAG_BNK2_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK2_WRPRTFLR) || \
((FLAG) == FLASH_FLAG_BNK3_BSY) || ((FLAG) == FLASH_FLAG_BNK3_PRCDN) || \
((FLAG) == FLASH_FLAG_BNK3_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK3_WRPRTFLR))
#else
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xBFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PRCDN) || \
((FLAG) == FLASH_FLAG_PRGMFLR) || ((FLAG) == FLASH_FLAG_WRPRTFLR) || \
((FLAG) == FLASH_FLAG_BNK1_BSY) || ((FLAG) == FLASH_FLAG_BNK1_PRCDN) || \
((FLAG) == FLASH_FLAG_BNK1_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK1_WRPRTFLR) || \
((FLAG) == FLASH_FLAG_UOBFLR) || \
((FLAG) == FLASH_FLAG_BNK3_BSY) || ((FLAG) == FLASH_FLAG_BNK3_PRCDN) || \
((FLAG) == FLASH_FLAG_BNK3_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK3_WRPRTFLR))
#endif
#define FLASH_BANK3_ADDR_MAX ((uint32_t)0x1FFEFFFF)
#define IS_IN_FLASH_BANK3_RANGE(ADDR) (((ADDR) >=EXT_FLASH_BASE) && ((ADDR) <= FLASH_BANK3_ADDR_MAX))
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions
* @{
*/
/*------------ Functions used for all at32f4xx devices -----*/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseUserOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_ProgramUserOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtect(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadProtectConfig(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t UOB_IWDG, uint16_t UOB_STOP, uint16_t UOB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectStatus(void);
FlagStatus FLASH_GetReadProtectStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForProcess(uint32_t Timeout);
#if defined (AT32F415xx)
/*------------ Functions used only for at32f415 devices -----*/
FLASH_Status FLASH_SYS_AP(void);
FLASH_Status FLASH_SlibSysEnable(uint32_t Psw,uint8_t data_start_page);
FlagStatus FLASH_GetOptionByteProtectStatus(void);
FLASH_Status FLASH_RDPandOptionByteProtectEnable(void);
void FLASH_OptionByteProtectDisable(void);
#endif /* AT32F415xx */
/*------------ New function used for all at32f4xx devices -----*/
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseBank1AllPages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForBank1Process(uint32_t Timeout);
#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
defined(AT32F407RGT7) || defined(AT32F407VGT7)
/*---- New Functions used only with at32f403_XL density devices -----*/
void FLASH_UnlockBank2(void);
void FLASH_LockBank2(void);
FLASH_Status FLASH_EraseBank2AllPages(void);
FLASH_Status FLASH_GetBank2Status(void);
FLASH_Status FLASH_WaitForBank2Process(uint32_t Timeout);
FLASH_Status FLASH_BootOptConfig(uint16_t FLASH_BOOT);
#endif
#if !defined (AT32F415xx)
/*---- New Functions for extrenal flash -----*/
void FLASH_UnlockBank3(void);
void FLASH_LockBank3(void);
FLASH_Status FLASH_EraseBank3AllPages(void);
FLASH_Status FLASH_GetBank3Status(void);
FLASH_Status FLASH_WaitForBank3Process(uint32_t Timeout);
void FLASH_Bank3EncEndAddrConfig(uint32_t EndAddress);
#endif
/*---- New Functions for SLIB -----*/
FLASH_Status FLASH_SlibMainEnable(uint32_t Psw, uint16_t StartPage, uint16_t DataPage, uint16_t EndPage);
uint32_t FLASH_SlibDisable(uint32_t dwPsw);
#if !defined (AT32F415xx)
uint32_t FLASH_GetSlibCurCnt(void);
#endif
uint8_t FLASH_GetSlibState(void);
uint16_t FLASH_GetSlibStartPage(void);
uint16_t FLASH_GetSlibDataStartPage(void);
uint16_t FLASH_GetSlibEndPage(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_gpio.h
+677
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_i2c.h
+682
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_iwdg.h
+128
View File
@@ -0,0 +1,128 @@
/**
**************************************************************************
* File Name : at32f4xx_iwdg.h
* Description : at32f4xx IWDG header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_IWDG_H
#define __AT32F4xx_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/** @defgroup IWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_KeyRegWrite_Enable ((uint16_t)0x5555)
#define IWDG_KeyRegWrite_Disable ((uint16_t)0x0000)
#define IS_IWDG_KEY_REG_WRITE(WRITE) (((WRITE) == IWDG_KeyRegWrite_Enable) || \
((WRITE) == IWDG_KeyRegWrite_Disable))
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_Psc_4 ((uint8_t)0x00)
#define IWDG_Psc_8 ((uint8_t)0x01)
#define IWDG_Psc_16 ((uint8_t)0x02)
#define IWDG_Psc_32 ((uint8_t)0x03)
#define IWDG_Psc_64 ((uint8_t)0x04)
#define IWDG_Psc_128 ((uint8_t)0x05)
#define IWDG_Psc_256 ((uint8_t)0x06)
#define IS_IWDG_PSC(PSC) (((PSC) == IWDG_Psc_4) || \
((PSC) == IWDG_Psc_8) || \
((PSC) == IWDG_Psc_16) || \
((PSC) == IWDG_Psc_32) || \
((PSC) == IWDG_Psc_64) || \
((PSC) == IWDG_Psc_128)|| \
((PSC) == IWDG_Psc_256))
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_FLAG_PSCF ((uint16_t)0x0001)
#define IWDG_FLAG_RLDF ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PSCF) || ((FLAG) == IWDG_FLAG_RLDF))
#define IS_IWDG_RLD(RLD) ((RLD) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions
* @{
*/
void IWDG_KeyRegWrite(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_IWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_pwr.h
+156
View File
@@ -0,0 +1,156 @@
/**
**************************************************************************
* File Name : at32f4xx_pwr.h
* Description : at32f4xx PWR header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_PWR_H
#define __AT32F4xx_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @defgroup PWR_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PVD_detection_level
* @{
*/
#define PWR_PVDS_2V2 ((uint32_t)0x00000000)
#define PWR_PVDS_2V3 ((uint32_t)0x00000020)
#define PWR_PVDS_2V4 ((uint32_t)0x00000040)
#define PWR_PVDS_2V5 ((uint32_t)0x00000060)
#define PWR_PVDS_2V6 ((uint32_t)0x00000080)
#define PWR_PVDS_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDS_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDS_2V9 ((uint32_t)0x000000E0)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDS_2V2) || ((LEVEL) == PWR_PVDS_2V3)|| \
((LEVEL) == PWR_PVDS_2V4) || ((LEVEL) == PWR_PVDS_2V5)|| \
((LEVEL) == PWR_PVDS_2V6) || ((LEVEL) == PWR_PVDS_2V7)|| \
((LEVEL) == PWR_PVDS_2V8) || ((LEVEL) == PWR_PVDS_2V9))
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry
* @{
*/
#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
/** @defgroup Regulator_state_is_STOP_mode
* @{
*/
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
/** @defgroup STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WUF ((uint32_t)0x00000001)
#define PWR_FLAG_SBF ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WUF) || ((FLAG) == PWR_FLAG_SBF) || \
((FLAG) == PWR_FLAG_PVDO))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WUF) || ((FLAG) == PWR_FLAG_SBF))
/**
* @}
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_Reset(void);
void PWR_BackupAccessCtrl(FunctionalState NewState);
void PWR_PVDCtrl(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCtrl(FunctionalState NewState);
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
#if defined (AT32F403xx) || defined (AT32F413xx)
void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry);
#else
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
#endif
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_PWR_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_rcc.h
+784
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_rtc.h
+123
View File
@@ -0,0 +1,123 @@
/**
**************************************************************************
* File Name : at32f4xx_rtc.h
* Description : at32f4xx RTC header file
* Date : 2018-10-08
* Version : V1.0.5
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_RTC_H
#define __AT32F4xx_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/** @defgroup RTC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Constants
* @{
*/
/** @defgroup RTC_interrupts_define
* @{
*/
#define RTC_INT_OV ((uint16_t)0x0004) /*!< Overflow interrupt */
#define RTC_INT_ALA ((uint16_t)0x0002) /*!< Alarm interrupt */
#define RTC_INT_PACE ((uint16_t)0x0001) /*!< Second interrupt */
#define IS_RTC_INT(INT) ((((INT) & (uint16_t)0xFFF8) == 0x00) && ((INT) != 0x00))
#define IS_RTC_GET_INT(INT) (((INT) == RTC_INT_OV) || ((INT) == RTC_INT_ALA) || \
((INT) == RTC_INT_PACE))
/**
* @}
*/
/** @defgroup RTC_interrupts_flags
* @{
*/
#define RTC_FLAG_RTF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
#define RTC_FLAG_RSYNF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
#define RTC_FLAG_OV ((uint16_t)0x0004) /*!< Overflow flag */
#define RTC_FLAG_ALA ((uint16_t)0x0002) /*!< Alarm flag */
#define RTC_FLAG_PACE ((uint16_t)0x0001) /*!< Second flag */
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTF) || ((FLAG) == RTC_FLAG_RSYNF) || \
((FLAG) == RTC_FLAG_OV) || ((FLAG) == RTC_FLAG_ALA) || \
((FLAG) == RTC_FLAG_PACE))
#define IS_RTC_DIV(DIV) ((DIV) <= 0xFFFFF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions
* @{
*/
void RTC_INTConfig(uint16_t RTC_INT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetDIV(uint32_t PrescalerValue);
void RTC_SetAlarmValue(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetINTStatus(uint16_t RTC_INT);
void RTC_ClearINTPendingBit(uint16_t RTC_INT);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_RTC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_sdio.h
+526
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_spi.h
+513
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_tim.h
+1402
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_usart.h
+400
View File
@@ -0,0 +1,400 @@
/**
**************************************************************************
* File Name : at32f4xx_usart.h
* Description : at32f4xx USART header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_USART_H
#define __AT32F4xx_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_Exported_Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitType;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitType;
/**
* @}
*/
/** @defgroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4) || \
((PERIPH) == UART5))
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3))
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4))
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
* @{
*/
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_0_5) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
*/
/** @defgroup USART_Mode
* @{
*/
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @defgroup USART_Clock
* @{
*/
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/** @defgroup USART_Interrupt_definition
* @{
*/
#define USART_INT_PERR ((uint16_t)0x0028)
#define USART_INT_TDE ((uint16_t)0x0727)
#define USART_INT_TRAC ((uint16_t)0x0626)
#define USART_INT_RDNE ((uint16_t)0x0525)
#define USART_INT_IDLEF ((uint16_t)0x0424)
#define USART_INT_LBDF ((uint16_t)0x0846)
#define USART_INT_CTSF ((uint16_t)0x096A)
#define USART_INT_ERR ((uint16_t)0x0060)
#define USART_INT_ORERR ((uint16_t)0x0360)
#define USART_INT_NERR ((uint16_t)0x0260)
#define USART_INT_FERR ((uint16_t)0x0160)
#define IS_USART_CONFIG_INT(INT) (((INT) == USART_INT_PERR) || ((INT) == USART_INT_TDE) || \
((INT) == USART_INT_TRAC) || ((INT) == USART_INT_RDNE) || \
((INT) == USART_INT_IDLEF) || ((INT) == USART_INT_LBDF) || \
((INT) == USART_INT_CTSF) || ((INT) == USART_INT_ERR))
#define IS_USART_GET_INT(INT) (((INT) == USART_INT_PERR) || ((INT) == USART_INT_TDE) || \
((INT) == USART_INT_TRAC) || ((INT) == USART_INT_RDNE) || \
((INT) == USART_INT_IDLEF) || ((INT) == USART_INT_LBDF) || \
((INT) == USART_INT_CTSF) || ((INT) == USART_INT_ORERR) || \
((INT) == USART_INT_NERR) || ((INT) == USART_INT_FERR))
#define IS_USART_CLEAR_INT(INT) (((INT) == USART_INT_TRAC) || ((INT) == USART_INT_RDNE) || \
((INT) == USART_INT_LBDF) || ((INT) == USART_INT_CTSF))
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_WakeUp_methods
* @{
*/
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/**
* @}
*/
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/**
* @}
*/
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/**
* @}
*/
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_CTSF ((uint16_t)0x0200)
#define USART_FLAG_LBDF ((uint16_t)0x0100)
#define USART_FLAG_TDE ((uint16_t)0x0080)
#define USART_FLAG_TRAC ((uint16_t)0x0040)
#define USART_FLAG_RDNE ((uint16_t)0x0020)
#define USART_FLAG_IDLEF ((uint16_t)0x0010)
#define USART_FLAG_ORERR ((uint16_t)0x0008)
#define USART_FLAG_NERR ((uint16_t)0x0004)
#define USART_FLAG_FERR ((uint16_t)0x0002)
#define USART_FLAG_PERR ((uint16_t)0x0001)
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PERR) || ((FLAG) == USART_FLAG_TDE) || \
((FLAG) == USART_FLAG_TRAC) || ((FLAG) == USART_FLAG_RDNE) || \
((FLAG) == USART_FLAG_IDLEF)|| ((FLAG) == USART_FLAG_LBDF) || \
((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_ORERR) || \
((FLAG) == USART_FLAG_NERR) || ((FLAG) == USART_FLAG_FERR))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_FLAG) != USART_FLAG_CTSF))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup USART_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USART_Exported_Functions
* @{
*/
void USART_Reset(USART_Type* USARTx);
void USART_Init(USART_Type* USARTx, USART_InitType* USART_InitStruct);
void USART_StructInit(USART_InitType* USART_InitStruct);
void USART_ClockInit(USART_Type* USARTx, USART_ClockInitType* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
void USART_Cmd(USART_Type* USARTx, FunctionalState NewState);
void USART_INTConfig(USART_Type* USARTx, uint16_t USART_INT, FunctionalState NewState);
void USART_DMACmd(USART_Type* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_Type* USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_Type* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_Type* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_Type* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_Type* USARTx, FunctionalState NewState);
void USART_SendData(USART_Type* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_Type* USARTx);
void USART_SendBreak(USART_Type* USARTx);
void USART_SetGuardTime(USART_Type* USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_Type* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_Type* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_Type* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_Type* USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_Type* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_Type* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_Type* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_Type* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_Type* USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_Type* USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_Type* USARTx, uint16_t USART_INT);
void USART_ClearITPendingBit(USART_Type* USARTx, uint16_t USART_INT);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_USART_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_wwdg.h
+103
View File
@@ -0,0 +1,103 @@
/**
**************************************************************************
* File Name : at32f4xx_wwdg.h
* Description : at32f4xx WWDG header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F4xx_WWDG_H
#define __AT32F4xx_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/** @defgroup WWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_Prescaler
* @{
*/
#define WWDG_Psc_1 ((uint32_t)0x00000000)
#define WWDG_Psc_2 ((uint32_t)0x00000080)
#define WWDG_Psc_4 ((uint32_t)0x00000100)
#define WWDG_Psc_8 ((uint32_t)0x00000180)
#define IS_WWDG_PSC(PSC) (((PSC) == WWDG_Psc_1) || \
((PSC) == WWDG_Psc_2) || \
((PSC) == WWDG_Psc_4) || \
((PSC) == WWDG_Psc_8))
#define IS_WWDG_WCNTR(WCNTR) ((WCNTR) <= 0x7F)
#define IS_WWDG_CNTR(CNTR) (((CNTR) >= 0x40) && ((CNTR) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions
* @{
*/
void WWDG_Reset(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowCounter(uint8_t WindowValue);
void WWDG_EnableINT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F4xx_WWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_xmc.h
+739
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/misc.h
+219
View File
@@ -0,0 +1,219 @@
/*
**************************************************************************
* Copyright (C) 2016 by ARTERY Technology Co., Ltd. All Rights Reserved.
**************************************************************************
* THIS SOURCE FILE IS DISTRIBUTED IN THE HOPE THAT CAN REDUCE EFFORTS AND
* TIME, BUT WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
**************************************************************************
* File Name : misc.h
* Description : at32f4xx MISC header file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete AT32 Devices IRQ Channels list, please
refer to at32f4xx.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitType;
/**
* @}
*/
/** @defgroup NVIC_Priority_Table
* @{
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
*/
/** @defgroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_acc.c
+238
View File
@@ -0,0 +1,238 @@
/**
**************************************************************************
* File Name : at32f4xx_acc.c
* Description : at32f4xx ACC source file
* Date : 2018-10-08
* Version : V1.0.5
**************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx_acc.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @defgroup ACC
* @brief ACC driver modules
* @{
*/
#if defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F403Axx) || \
defined (AT32F407xx)
/** @defgroup ACC_Private_Functions
* @{
*/
/**
* @brief Stores Calibration Step data in ACC's CTRL1 register.
* @param StepValue: value to be stored in the ACC's CTRL1 register
* @retval None
*/
void ACC_SetStep(uint8_t StepValue)
{
ACC->CTRL1 |= StepValue<<8;
}
/**
* @brief Enables the specified ACC Calibration.
* @param ACC_CAL: specifies the ACC CAL sources.
* This parameter can be one of the following values:
* @arg ACC_CAL_HSICAL: Calibration HSICAL
* @arg ACC_CAL_HSITRIM: Calibration HSITRIM
* @retval None
*/
void ACC_CAL_Choose(uint16_t ACC_CAL)
{
ACC->CTRL1 &= ~0x2;
ACC->CTRL1 |= ACC_CAL;
}
/**
* @brief Enables or disables the specified ACC interrupts.
* @param ACC_IT: specifies the ACC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ACC_IT_CALRDYIEN: CALRDY interrupt enable
* @arg ACC_IT_EIEN: RSLOST error interrupt enable
* @param NewState: new state of the specified ACC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ACC_ITConfig(uint16_t ACC_IT, FunctionalState NewState)
{
if (NewState != DISABLE)
{
/* Enable the Interrupt sources */
ACC->CTRL1 |= ACC_IT;
}
else
{
/* Disable the Interrupt sources */
ACC->CTRL1 &= (uint16_t)~ACC_IT;
}
}
/**
* @brief Enters the ACC Calibration mode.
* @param ACC_IT: specifies the ACC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ACC_CAL_ON: CALRDY interrupt enable
* @arg ACC_TRIM_ON: RSLOST error interrupt enable
* @param NewState: new state of the specified ACC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ACC_EnterCALMode(uint16_t ACC_ON, FunctionalState NewState)
{
ACC->CTRL1 |= ACC_ON;
}
/**
* @brief Exits from the ACC Calibration mode.
* @param None
* @retval None
*/
void ACC_ExitCALMode(void)
{
ACC->CTRL1 &= ~ACC_CAL_Enable;
}
/**
* @brief Checks whether the specified ACC flag is set or not.
* @param ACC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg ACC_FLAG_RSLOST: Reference Signal Lost
* @arg ACC_FLAG_CALRDY: Internal high-speed clock calibration ready
* @retval The new state of ACC_FLAG (SET or RESET).
*/
FlagStatus ACC_GetFlagStatus(uint16_t ACC_FLAG)
{
FlagStatus bitstatus = RESET;
if ((ACC->STS & ACC_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Wtire the value to ACC C1 register.
* @param ACC_C1_Value
* @retval none.
*/
void ACC_WriteC1(uint16_t ACC_C1_Value)
{
ACC->C1 = ACC_C1_Value;
}
/**
* @brief Wtire the value to ACC C2 register.
* @param ACC_C2_Value
* @retval none.
*/
void ACC_WriteC2(uint16_t ACC_C2_Value)
{
ACC->C2 = ACC_C2_Value;
}
/**
* @brief Wtire the value to ACC C3 register.
* @param ACC_C3_Value
* @retval none.
*/
void ACC_WriteC3(uint16_t ACC_C3_Value)
{
ACC->C3 = ACC_C3_Value;
}
/**
* @brief Returns the current ACC HSITRIM value.
* @param None
* @retval 8-bit HSITRIM value.
*/
uint8_t ACC_GetHSITRIM(void)
{
return ((uint8_t)((ACC->CTRL2)>>8));
}
/**
* @brief Returns the current ACC HSICAL value.
* @param None
* @retval 8-bit HSITRIM value.
*/
uint8_t ACC_GetHSICAL(void)
{
return ((uint8_t)(ACC->CTRL2));
}
/**
* @brief Returns the current ACC C1 value.
* @param None
* @retval 16-bit C1 value.
*/
uint16_t ACC_ReadC1(void)
{
return ((uint16_t)(ACC->C1));
}
/**
* @brief Returns the current ACC C2 value.
* @param None
* @retval 16-bit C2 value.
*/
uint16_t ACC_ReadC2(void)
{
return ((uint16_t)(ACC->C2));
}
/**
* @brief Returns the current ACC C3 value.
* @param None
* @retval 16-bit C3 value.
*/
uint16_t ACC_ReadC3(void)
{
return ((uint16_t)(ACC->C3));
}
/**
* @brief Checks whether the specified ACC flag is set or not.
* @param ACC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg ACC_FLAG_RSLOST: Reference Signal Lost
* @arg ACC_FLAG_CALRDY: Internal high-speed clock calibration ready
* @retval None.
*/
void ACC_ClearFlag(uint16_t ACC_FLAG)
{
if(ACC_FLAG == ACC_FLAG_CALRDY)
{
ACC->STS &= ~1;
}
if(ACC_FLAG == ACC_FLAG_RSLOST)
{
ACC->STS &= ~2;
}
}
/**
* @}
*/
#endif /* AT32F413xx || AT32F415xx || AT32F403Axx || AT32F407xx */
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_adc.c
+1331
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_bkp.c
+302
View File
@@ -0,0 +1,302 @@
/**
**************************************************************************
* File Name : at32f4xx_bkp.c
* Description : at32f4xx BKP source file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx_bkp.h"
#include "at32f4xx_rcc.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @defgroup BKP
* @brief BKP driver modules
* @{
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F403Axx) || \
defined (AT32F407xx)
/** @defgroup BKP_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Defines
* @{
*/
/* ------------ BKP registers bit address in the alias region --------------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- CTRL Register ----*/
/* Alias word address of TPAL bit */
#define CTRL_OFFSET (BKP_OFFSET + 0x30)
#define TPALV_BitPos 0x01
#define CTRL_TPALV_BBMAP (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TPALV_BitPos * 4))
/* Alias word address of TPE bit */
#define TPEN_BitPos 0x00
#define CTRL_TPEN_BBMAP (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TPEN_BitPos * 4))
/* --- CTRLSTS Register ---*/
/* Alias word address of TPIE bit */
#define CTRLSTS_OFFSET (BKP_OFFSET + 0x34)
#define TPIEN_BitPos 0x02
#define CTRLSTS_TPIEN_BBMAP (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPIEN_BitPos * 4))
/* Alias word address of TIF bit */
#define TPIF_BitPos 0x09
#define CTRLSTS_TPIF_BBMAP (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPIF_BitPos * 4))
/* Alias word address of TEF bit */
#define TPEF_BitPos 0x08
#define CTRLSTS_TPEF_BBMAP (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPEF_BitPos * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCAL_CAL_MASK ((uint16_t)0xFF80)
#define RTCCAL_MASK ((uint16_t)0xFC7F)
/**
* @}
*/
/** @defgroup BKP_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Functions
* @{
*/
/**
* @brief Deinitializes the BKP peripheral registers to their default reset values.
* @param None
* @retval None
*/
void BKP_Reset(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/**
* @brief Configures the Tamper Pin active level.
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
* This parameter can be one of the following values:
* @arg BKP_TamperPinLv_H: Tamper pin active on high level
* @arg BKP_TamperPinLv_L: Tamper pin active on low level
* @retval None
*/
void BKP_TamperPinLvConfig(uint16_t BKP_TamperPinLevel)
{
/* Check the parameters */
assert_param(IS_BKP_TAMPER_PIN_LV(BKP_TamperPinLevel));
*(__IO uint32_t *) CTRL_TPALV_BBMAP = BKP_TamperPinLevel;
}
/**
* @brief Enables or disables the Tamper Pin activation.
* @param NewState: new state of the Tamper Pin activation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_TamperPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CTRL_TPEN_BBMAP = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Tamper Pin Interrupt.
* @param NewState: new state of the Tamper Pin Interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_IntConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CTRLSTS_TPIEN_BBMAP = (uint32_t)NewState;
}
/**
* @brief Select the RTC output source to output on the Tamper pin.
* @param BKP_RTCOutputSource: specifies the RTC output source.
* This parameter can be one of the following values:
* @arg BKP_RTCOutput_None: no RTC output on the Tamper pin.
* @arg BKP_RTCOutput_CalClk: output the RTC clock with frequency
* divided by 64 on the Tamper pin.
* @arg BKP_RTCOutput_Alarm: output the RTC Alarm pulse signal on
* the Tamper pin.
* @arg BKP_RTCOutput_Second: output the RTC Second pulse signal on
* the Tamper pin.
* @retval None
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_RTC_OUTPUT_SEL(BKP_RTCOutputSource));
tmpreg = BKP->RTCCAL;
/* Clear CCO, ASOE and ASOS bits */
tmpreg &= RTCCAL_MASK;
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
tmpreg |= BKP_RTCOutputSource;
/* Store the new value */
BKP->RTCCAL = tmpreg;
}
/**
* @brief Sets RTC Clock Calibration value.
* @param CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* @retval None
*/
void BKP_SetRTCCalValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_CAL_VAL(CalibrationValue));
tmpreg = BKP->RTCCAL;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCAL_CAL_MASK;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
BKP->RTCCAL = tmpreg;
}
/**
* @brief Writes user data to the specified Data Backup Register.
* @param BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* @param Data: data to write
* @retval None
*/
void BKP_WriteBackupReg(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_BKP_DT(BKP_DR));
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Reads data from the specified Data Backup Register.
* @param BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* @retval The content of the specified Data Backup Register
*/
uint16_t BKP_ReadBackupReg(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_BKP_DT(BKP_DR));
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *) tmp);
}
/**
* @brief Checks whether the Tamper Pin Event flag is set or not.
* @param None
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
*/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(__IO uint32_t *) CTRLSTS_TPEF_BBMAP);
}
/**
* @brief Clears Tamper Pin Event pending flag.
* @param None
* @retval None
*/
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CTRLSTS |= BKP_CTRLSTS_CTPEF;
}
/**
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
* @param None
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
*/
ITStatus BKP_GetIntStatus(void)
{
return (ITStatus)(*(__IO uint32_t *) CTRLSTS_TPIF_BBMAP);
}
/**
* @brief Clears Tamper Pin Interrupt pending bit.
* @param None
* @retval None
*/
void BKP_ClearIntPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CTRLSTS |= BKP_CTRLSTS_CTPIF;
}
/**
* @}
*/
#endif /* AT32F403xx || AT32F413xx || AT32F403Axx || AT32F407xx */
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_can.c
+1480
View File
File diff suppressed because it is too large Load Diff
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_comp.c
+449
View File
@@ -0,0 +1,449 @@
/**
******************************************************************************
* @file at32f4xx_comp.c
* @author Artery
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the comparators (COMP1 and COMP2) peripheral:
* + Comparators configuration
* + Window mode control
*
* @verbatim
*
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The device integrates two analog comparators COMP1 and COMP2:
(+) The non inverting input is set to PA1 for COMP1 and to PA3
for COMP2.
(+) The inverting input can be selected among: DAC_OUT1,
1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
I/O (PA0 for COMP1 and PA2 for COMP2)
(+) The COMP output is internally is available using COMP_GetOutputState()
and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
and PA2, PA7, PA12 for COMP2
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2
and TIM3)
(+) The two comparators COMP1 and COMP2 can be combined in window
mode and only COMP1 non inverting (PA1) can be used as non-
inverting input.
(+) The two comparators COMP1 and COMP2 have interrupt capability
with wake-up from Sleep and Stop modes (through the EXTI controller).
COMP1 and COMP2 outputs are internally connected to EXTI Line 21
and EXTI Line 22 respectively.
##### How to configure the comparator #####
===============================================================================
[..]
This driver provides functions to configure and program the Comparators
of all AT32F4xx devices.
[..] To use the comparator, perform the following steps:
(#) Enable the SYSCFG APB clock to get write access to comparator
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
(#) Configure the comparator input in analog mode using GPIO_Init()
(#) Configure the comparator output in alternate function mode
using GPIO_Init() and use GPIO_PinAFConfig() function to map the
comparator output to the GPIO pin
(#) Configure the comparator using COMP_Init() function:
(++) Select the inverting input
(++) Select the output polarity
(++) Select the output redirection
(++) Select the hysteresis level
(++) Select the power mode
(#) Enable the comparator using COMP_Cmd() function
(#) If required enable the COMP interrupt by configuring and enabling
EXTI line in Interrupt mode and selecting the desired sensitivity
level using EXTI_Init() function. After that enable the comparator
interrupt vector using NVIC_Init() function.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 Artery</center></h2>
*
* Licensed under Artery Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx_comp.h"
/** @addtogroup AT32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup COMP
* @brief COMP driver modules
* @{
*/
#if defined (AT32F415xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CTRLSTS1 register Mask */
#define COMP_CTRLSTS1_CLEAR_MASK ((uint32_t)0x00003FFE)
#define COMP_CTRLSTS2_CLEAR_MASK ((uint32_t)0x00000003)
#define COMP_HIGH_PULSE_CLEAR_MASK ((uint16_t)0x003F)
#define COMP_LOW_PULSE_CLEAR_MASK ((uint16_t)0x003F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup COMP_Private_Functions
* @{
*/
/**
* @brief Deinitializes COMP peripheral registers to their default reset values.
* @note Deinitialization can't be performed if the COMP configuration is locked.
* To unlock the configuration, perform a system reset.
* @param None
* @retval None
*/
void COMP_Reset(void)
{
COMP->CTRLSTS1 = ((uint32_t)0x00000000); /*!< Set COMP_CTRLSTS register to reset value */
}
/**
* @brief Initializes the COMP peripheral according to the specified parameters
* in COMP_InitStruct
* @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @note By default, PA1 is selected as COMP1 non inverting input.
* To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
* @param COMP_Selection: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP1_Selection: COMP1 selected
* @arg COMP2_Selection: COMP2 selected
* @param COMP_InitStruct: pointer to an COMP_InitType structure that contains
* the configuration information for the specified COMP peripheral.
* @retval None
*/
void COMP_Init(uint32_t COMP_Selection, COMP_InitType* COMP_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_INMInput));
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutPolarity));
assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
/*!< Get the COMP_CTRLSTS register value */
tmpreg = COMP->CTRLSTS1;
/*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */
tmpreg &= (uint32_t) ~(COMP_CTRLSTS1_CLEAR_MASK<<COMP_Selection);
/*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
/*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
/*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
/*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
/*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
/*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
tmpreg |= (uint32_t)((COMP_InitStruct->COMP_INMInput | COMP_InitStruct->COMP_Output |
COMP_InitStruct->COMP_OutPolarity | COMP_InitStruct->COMP_Hysteresis |
COMP_InitStruct->COMP_Mode)<<COMP_Selection);
/*!< Write to COMP_CTRLSTS1 register */
COMP->CTRLSTS1 = tmpreg;
}
/**
* @brief Select the non-inverting input for COMP1/COMP2.
* @param COMP_Selection: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP1_Selection: COMP1 selected
* @arg COMP2_Selection: COMP2 selected
* @param COMP_INPInput: the selected COMP non-inverting input.
* This parameter can be one of the following values:
* @arg COMP_INPInput_00: PA5/PA7 connected to comparator1/2 non-inverting input
* @arg COMP_INPInput_01: PA1/PA3 connected to comparator1/2 non-inverting input
* @arg COMP_INPInput_10: PA0/PA2 connected to comparator1/2 non-inverting input
* @retval None
*/
void COMP_SelectINPInput(uint32_t COMP_Selection, uint32_t COMP_INPInput)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_COMP_NONINVERTING_INPUT(COMP_INPInput));
/*!< Get the COMP_CTRLSTS register value */
tmpreg = COMP->CTRLSTS2;
/*!< Clear the COMPxINPSEL bits */
tmpreg &= (uint32_t) ~(COMP_CTRLSTS2_CLEAR_MASK<<COMP_Selection);
/*!< Set COMPxINPSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
tmpreg |= (uint32_t)(COMP_INPInput<<COMP_Selection);
/*!< Write to COMP_CTRLSTS2 register */
COMP->CTRLSTS2 = tmpreg;
}
/**
* @brief Fills each COMP_InitStruct member with its default value.
* @param COMP_InitStruct: pointer to an COMP_InitType structure which will
* be initialized.
* @retval None
*/
void COMP_StructInit(COMP_InitType* COMP_InitStruct)
{
COMP_InitStruct->COMP_INMInput = COMP_INMInput_1_4VREFINT;
COMP_InitStruct->COMP_Output = COMP_Output_None;
COMP_InitStruct->COMP_OutPolarity = COMP_OutPolarity_NonInverted;
COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
COMP_InitStruct->COMP_Mode = COMP_Mode_Slow;
}
/**
* @brief Enable or disable the COMP peripheral.
* @note If the selected comparator is locked, enable/disable can't be performed.
* To unlock the configuration, perform a system reset.
* @param COMP_Selection: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP1_Selection: COMP1 selected
* @arg COMP2_Selection: COMP2 selected
* @param NewState: new state of the COMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, the comparator compares the non inverting input with
* the inverting input and the comparison result is available on comparator output.
* @note When disabled, the comparator doesn't perform comparison and the
* output level is low.
* @retval None
*/
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected COMP peripheral */
COMP->CTRLSTS1 |= (uint32_t) (1<<COMP_Selection);
}
else
{
/* Disable the selected COMP peripheral */
COMP->CTRLSTS1 &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
}
}
/**
* @brief Close or Open the SW1 switch.
* @note This switch is solely intended to redirect signals onto high
* impedance input, such as COMP1 non-inverting input (highly resistive switch)
* @param NewState: New state of the analog switch.
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, the SW1 is closed; PA1 is connected to PA4
* @note When disabled, the SW1 switch is open; PA1 is disconnected from PA4
* @retval None
*/
void COMP_SwitchCmd(FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Close SW1 switch */
COMP->CTRLSTS1 |= (uint32_t) (COMP_CTRLSTS_COMP1SW1);
}
else
{
/* Open SW1 switch */
COMP->CTRLSTS1 &= (uint32_t)(~COMP_CTRLSTS_COMP1SW1);
}
}
/**
* @brief Return the output level (high or low) of the selected comparator.
* @note The output level depends on the selected polarity.
* @note If the polarity is not inverted:
* - Comparator output is low when the non-inverting input is at a lower
* voltage than the inverting input
* - Comparator output is high when the non-inverting input is at a higher
* voltage than the inverting input
* @note If the polarity is inverted:
* - Comparator output is high when the non-inverting input is at a lower
* voltage than the inverting input
* - Comparator output is low when the non-inverting input is at a higher
* voltage than the inverting input
* @param COMP_Selection: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP1_Selection: COMP1 selected
* @arg COMP2_Selection: COMP2 selected
* @retval Returns the selected comparator output level: low or high.
*
*/
uint32_t COMP_GetOutputState(uint32_t COMP_Selection)
{
uint32_t compout = 0x0;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Check if selected comparator output is high */
if ((COMP->CTRLSTS1 & (COMP_CTRLSTS_COMP1OUT<<COMP_Selection)) != 0)
{
compout = COMP_OutputState_High;
}
else
{
compout = COMP_OutputState_Low;
}
/* Return the comparator output level */
return (uint32_t)(compout);
}
/**
* @brief Enables or disables the window mode.
* @note In window mode, COMP1 and COMP2 non inverting inputs are connected
* together and only COMP1 non inverting input (PA1) can be used.
* @param NewState: new state of the window mode.
* This parameter can be :
* @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
* @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
* @retval None
*/
void COMP_WindowCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the window mode */
COMP->CTRLSTS1 |= (uint32_t)COMP_CTRLSTS_WNDWEN;
}
else
{
/* Disable the window mode */
COMP->CTRLSTS1 &= (uint32_t)(~COMP_CTRLSTS_WNDWEN);
}
}
/**
* @brief Lock the selected comparator (COMP1/COMP2) configuration.
* @note Locking the configuration means that all control bits are read-only.
* To unlock the comparator configuration, perform a system reset.
* @param COMP_Selection: selects the comparator to be locked
* This parameter can be a value of the following values:
* @arg COMP1_Selection: COMP1 configuration is locked.
* @arg COMP2_Selection: COMP2 configuration is locked.
* @retval None
*/
void COMP_LockConfig(uint32_t COMP_Selection)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Set the lock bit corresponding to selected comparator */
COMP->CTRLSTS1 |= (uint32_t) (COMP_CTRLSTS_COMP1LOCK<<COMP_Selection);
}
/**
* @brief Configure COMP Glitch Filter.
* @note G_FILTER_EN, HIGH_PULSE and LOW_PULSE registers will
* act on both COMP1 and COMP2.
* @param COMP_HighPulseCnt: COMP High Pulse Count.
* This parameter must be a value between 0x00 and 0x3F
* @param COMP_LowPulseCnt: COMP Low Pulse Count.
* This parameter must be a value between 0x00 and 0x3F
* @param NewState: new state of the Glitch Filter.
* This parameter can be :
* @arg ENABLE: COMP1 and COMP2 turn on glitch filter.
* @arg DISABLE: COMP1 and COMP2 turn off glitch filter.
* @retval None
*/
void COMP_FilterConfig(uint16_t COMP_HighPulseCnt, uint16_t COMP_LowPulseCnt, FunctionalState NewState)
{
uint16_t tmphp = 0;
uint16_t tmplp = 0;
/* Check the parameters */
assert_param(IS_COMP_HighPulseCnt(COMP_HighPulseCnt));
assert_param(IS_COMP_LowPulseCnt(COMP_LowPulseCnt));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the glitch filter */
COMP->G_FILTER_EN |= (uint16_t)COMP_G_FILTER_EN_GFE;
tmphp = COMP->HIGH_PULSE;
tmplp = COMP->LOW_PULSE;
/* Reset the H_PULSE_CNT and L_PULSE_CNT Bits */
tmphp &= ~COMP_HIGH_PULSE_CLEAR_MASK;
tmplp &= ~COMP_LOW_PULSE_CLEAR_MASK;
/* Set the H_PULSE_CNT and L_PULSE_CNT Bits */
tmphp |= COMP_HighPulseCnt;
tmplp |= COMP_LowPulseCnt;
/* Write to COMP HIGH_PULSE and LOW_PULSE */
COMP->HIGH_PULSE = tmphp;
COMP->LOW_PULSE = tmplp;
}
else
{
/* Disable the glitch filter */
COMP->G_FILTER_EN &= (uint16_t)(~COMP_G_FILTER_EN_GFE);
/* Reset the H_PULSE_CNT and L_PULSE_CNT Bits */
COMP->HIGH_PULSE &= ~COMP_HIGH_PULSE_CLEAR_MASK;
COMP->LOW_PULSE &= ~COMP_LOW_PULSE_CLEAR_MASK;
}
}
/**
* @}
*/
#endif /* AT32F415xx */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT Artery *****END OF FILE****/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_crc.c
+150
View File
@@ -0,0 +1,150 @@
/**
**************************************************************************
* File Name : at32f4xx_crc.c
* Description : at32f4xx CRC source file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx_crc.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/** @defgroup CRC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Resets the CRC Data register (DR).
* @param None
* @retval None
*/
void CRC_ResetDT(void)
{
/* Reset CRC generator */
CRC->CTRL = CRC_CTRL_RST;
}
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param Data: data word(32-bit) to compute its CRC
* @retval 32-bit CRC
*/
uint32_t CRC_CalculateCRC(uint32_t Data)
{
CRC->DT = Data;
return (CRC->DT);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
*/
uint32_t CRC_CalculateBlkCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DT = pBuffer[index];
}
return (CRC->DT);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DT);
}
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param IDValue: 8-bit value to be stored in the ID register
* @retval None
*/
void CRC_SetIDTReg(uint8_t IDValue)
{
CRC->IDT = IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
* @param None
* @retval 8-bit value of the ID register
*/
uint8_t CRC_GetIDTReg(void)
{
return (CRC->IDT);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_dac.c
+420
View File
@@ -0,0 +1,420 @@
/**
**************************************************************************
* File Name : at32f4xx_dac.c
* Description : at32f4xx DAC source file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx_dac.h"
#include "at32f4xx_rcc.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
/** @defgroup DAC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Defines
* @{
*/
/* CTRL register Mask */
#define CTRL_CLEAR_MSK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
#define DUAL_SWTRIG_RST ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define ODT_OFFSET ((uint32_t)0x0000002C)
/**
* @}
*/
/** @defgroup DAC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_Reset(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_DAC, DISABLE);
}
/**
* @brief Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitType structure that
* contains the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CTRL Configuration --------------------------*/
/* Get the DAC CTRL value */
tmpreg1 = DAC->CTRL;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CTRL_CLEAR_MSK << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
mask/amplitude for wave generation */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CTRL register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CTRL */
DAC->CTRL = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct : pointer to a DAC_InitType structure which will
* be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitType* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmsk_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_Ctrl(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CTRL |= (DAC_CTRL_EN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel */
DAC->CTRL &= ~(DAC_CTRL_EN1 << DAC_Channel);
}
}
/**
* @brief Enables or disables the specified DAC channel DMA request.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DMACtrl(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CTRL |= (DAC_CTRL_DMAEN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CTRL &= ~(DAC_CTRL_DMAEN1 << DAC_Channel);
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTriggerCtrl(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRG |= (uint32_t)DAC_SWTRG_SWTRG1 << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRG &= ~((uint32_t)DAC_SWTRG_SWTRG1 << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTriggerCtrl(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRG |= DUAL_SWTRIG_SET ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRG &= DUAL_SWTRIG_RST;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_WaveGenerationCtrl(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CTRL |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CTRL &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_Right: 8bit right data alignment selected
* @arg DAC_Align_12b_Left: 12bit left data alignment selected
* @arg DAC_Align_12b_Right: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_Right: 8bit right data alignment selected
* @arg DAC_Align_12b_Left: 12bit left data alignment selected
* @arg DAC_Align_12b_Right: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
}
/**
* @brief Set the specified data holding register value for dual channel
* DAC.
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_Right: 8bit right data alignment selected
* @arg DAC_Align_12b_Left: 12bit left data alignment selected
* @arg DAC_Align_12b_Right: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @retval None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_Right)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DAC_BASE ;
tmp += ODT_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**
* @}
*/
#endif /* AT32F403xx || AT32F403Axx || AT32F407xx */
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_dbgmcu.c
+149
View File
@@ -0,0 +1,149 @@
/**
**************************************************************************
* File Name : at32f4xx_dbgmcu.c
* Description : at32f4xx MCUDBG source file
* Date : 2018-02-26
* Version : V1.0.4
**************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx_dbgmcu.h"
/** @addtogroup at32f4xx_StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/** @defgroup DBGMCU_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Defines
* @{
*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
/** @defgroup DBGMCU_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t MCUDBG_GetRevID(void)
{
return(DBGMCU->IDCR >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t MCUDBG_GetDevID(void)
{
return(DBGMCU->IDCR & IDCODE_DEVID_MASK);
}
/**
* @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* @arg MCUDBG_SLEEP: Keep debugger connection during SLEEP mode
* @arg MCUDBG_STOP: Keep debugger connection during STOP mode
* @arg MCUDBG_STANDBY: Keep debugger connection during STANDBY mode
* @arg MCUDBG_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg MCUDBG_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg MCUDBG_TMR1_STOP: TMR1 counter stopped when Core is halted
* @arg MCUDBG_TMR2_STOP: TMR2 counter stopped when Core is halted
* @arg MCUDBG_TMR3_STOP: TMR3 counter stopped when Core is halted
* @arg MCUDBG_TMR4_STOP: TMR4 counter stopped when Core is halted
* @arg MCUDBG_CAN1_STOP: Debug CAN1 stopped when Core is halted
* @arg MCUDBG_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg MCUDBG_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg MCUDBG_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
* @arg MCUDBG_TMR5_STOP: TMR5 counter stopped when Core is halted
* @arg MCUDBG_TMR6_STOP: TMR6 counter stopped when Core is halted
* @arg MCUDBG_TMR7_STOP: TMR7 counter stopped when Core is halted
* @arg MCUDBG_TMR8_STOP: TMR8 counter stopped when Core is halted
* @arg MCUDBG_TMR15_STOP: TMR15 counter stopped when Core is halted
* @arg MCUDBG_TMR9_STOP: TMR9 counter stopped when Core is halted
* @arg MCUDBG_TMR10_STOP: TMR10 counter stopped when Core is halted
* @arg MCUDBG_TMR11_STOP: TMR11 counter stopped when Core is halted
* @arg MCUDBG_TMR12_STOP: TMR12 counter stopped when Core is halted
* @arg MCUDBG_TMR13_STOP: TMR13 counter stopped when Core is halted
* @arg MCUDBG_TMR14_STOP: TMR14 counter stopped when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void MCUDBG_PeriphDebugModeConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_MCUDBG_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CTRL |= DBGMCU_Periph;
}
else
{
DBGMCU->CTRL &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_dma.c
+755
View File
File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More