mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-01 08:27:30 +08:00
[cherryusb][fsdev] add N32H4x USBFS device support #11764
This commit is contained in:
Onlyou_tzZ
@@ -28,6 +28,8 @@ if RT_USING_CHERRYUSB
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bool "CUSTOM (Implement it yourself)"
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config RT_CHERRYUSB_DEVICE_FSDEV_ST
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bool "fsdev_st"
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config RT_CHERRYUSB_DEVICE_FSDEV_NATION
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bool "fsdev_nation"
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config RT_CHERRYUSB_DEVICE_FSDEV_CUSTOM
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bool "fsdev_custom"
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config RT_CHERRYUSB_DEVICE_DWC2_ST
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@@ -37,6 +37,9 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']):
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if GetDepend(['RT_CHERRYUSB_DEVICE_FSDEV_ST']):
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src += Glob('port/fsdev/usb_dc_fsdev.c')
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src += Glob('port/fsdev/usb_glue_st.c')
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if GetDepend(['RT_CHERRYUSB_DEVICE_FSDEV_NATION']):
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src += Glob('port/fsdev/usb_dc_fsdev.c')
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src += Glob('port/fsdev/usb_glue_nation.c')
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if GetDepend(['RT_CHERRYUSB_DEVICE_FSDEV_CUSTOM']):
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src += Glob('port/fsdev/usb_dc_fsdev.c')
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if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_ST']):
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@@ -28,3 +28,11 @@
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## CH32
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- CH32F10x、CH32V10x
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## N32
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- N32H473、N32H474、N32H475、N32H481、N32H482、N32H480、N32H487、N32H488
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- N32H49X
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@@ -5,7 +5,7 @@
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*/
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#include "usbd_core.h"
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#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG)
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#if defined(CONFIG_USB_DBG_LEVEL) && defined(USB_DBG_LOG) && (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG)
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#error "fsdev cannot enable USB_DBG_LOG"
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#endif
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@@ -60,10 +60,30 @@ __WEAK void usb_dc_low_level_deinit(void)
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{
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}
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/**
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* @brief Initialize the USB device controller.
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* @param busid USB bus index (fsdev supports a single instance, bus 0).
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* @retval 0 on success.
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*/
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int usb_dc_init(uint8_t busid)
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{
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usb_dc_low_level_init();
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#if defined(N32H4X_FSDEV)
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/* N32H4x power-on sequence: the USB_CTRL reset value is 0x0300
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* -- PD(bit9, power-down) and FRST(bit8, force-reset) are both set.
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* 1. Clear PD, wait for the internal analog voltage reference to settle.
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* 2. Clear FRST.
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* 3. Clear the STS register to drop pending interrupts. */
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USB->CNTR &= (uint32_t)~USB_CNTR_PDWN; /* exit power-down */
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/* Wait for the internal reference voltage to stabilise. */
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for (volatile uint32_t i = 0U; i < 1000U; i++) {
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}
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USB->CNTR &= (uint32_t)~USB_CNTR_FRES; /* clear force-reset flag */
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USB->ISTR = 0U; /* clear pending interrupts */
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#else
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/* Init Device */
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/* CNTR_FRES = 1 */
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USB->CNTR = (uint16_t)USB_CNTR_FRES;
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@@ -73,6 +93,7 @@ int usb_dc_init(uint8_t busid)
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/* Clear pending interrupts */
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USB->ISTR = 0U;
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#endif
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/*Set Btable Address*/
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USB->BTABLE = BTABLE_ADDRESS;
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@@ -91,8 +112,13 @@ int usb_dc_init(uint8_t busid)
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/* Set interrupt mask */
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USB->CNTR = (uint16_t)winterruptmask;
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#if defined(N32H4X_FSDEV)
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/* Enabling DP Pull-UP through USB_CTRL.PU */
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USB->CNTR |= (uint32_t)USB_CNTR_PU;
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#else
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/* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
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USB->BCDR |= (uint16_t)USB_BCDR_DPPU;
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#endif
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return 0;
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}
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@@ -325,6 +351,10 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t
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return 0;
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}
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/**
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* @brief USB FS device interrupt handler: dispatches ISTR events.
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* @param busid USB bus index (fsdev supports a single instance, bus 0).
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*/
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void USBD_IRQHandler(uint8_t busid)
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{
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uint16_t wIstr, wEPVal;
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@@ -339,7 +369,13 @@ void USBD_IRQHandler(uint8_t busid)
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wIstr = USB->ISTR;
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/* extract highest priority endpoint number */
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#if defined(N32H4X_FSDEV)
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/* EP_ID is at STS bits [11:8] */
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ep_idx = (uint8_t)((wIstr & USB_ISTR_EP_ID) >> USB_ISTR_EP_ID_Pos);
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#else
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/* ST: EP_ID is at ISTR bits [3:0] */
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ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
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#endif
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if (ep_idx == 0U) {
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if ((wIstr & USB_ISTR_DIR) == 0U) {
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,191 @@
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/*
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* Copyright (c) 2025, sakumisu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "usbd_core.h"
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/* N32H4x family detection (N32H47x_48x + N32H49x): same part-macro list as
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* the SDKs (n32h47x_48x.h typedef enum IRQn, n32h49x.h) and as
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* usb_fsdev_reg.h. Defined here locally so this file never needs to include
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* usb_fsdev_reg.h next to the SDK headers (which would re-define e.g.
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* USB_EP_SETUP). */
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#if defined(N32H473) || defined(N32H474) || defined(N32H475) || \
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defined(N32H481) || defined(N32H482) || defined(N32H480) || \
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defined(N32H487) || defined(N32H488) || defined(N32H49X)
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#define N32H4X_FSDEV 1
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#endif
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#if defined(N32H4X_FSDEV)
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#if defined(N32H473) || defined(N32H474) || defined(N32H475) || \
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defined(N32H481) || defined(N32H482) || defined(N32H480) || \
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defined(N32H487) || defined(N32H488)
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#include "n32h47x_48x_rcc.h"
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#include "n32h47x_48x_gpio.h"
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#include "misc.h"
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#define USBFS_REG_BASE 0x40004800UL
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#define USBFS_SRAM_BASE 0x40004C00UL
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#define USBFS_APB1_CLK RCC_APB1_PERIPH_USBFS
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#elif defined(N32H49X)
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#include "n32h49x_rcc.h"
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#include "n32h49x_gpio.h"
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#include "misc.h"
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#define USBFS_REG_BASE 0x40004800UL
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#define USBFS_SRAM_BASE 0x40004C00UL
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#define USBFS_APB1_CLK RCC_APB1_PERIPHEN_USBFS
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#else
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#error "unsupported N32H4x part: define a N32H47x_48x part macro (N32H473/474/475/481/482/480/487/488) or N32H49X"
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#endif /* N32H473..N32H488 (48x SDK) / N32H49X (49x SDK) */
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/*
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* N32H4x (N32H47x_48x / N32H49x) USB Full-Speed Device (USB_FS_Device).
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*
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* The USBFS core is the same Synopsys USBFS as STM32, but Nations re-arranged
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* every register/bit field. The re-map lives in usb_fsdev_reg.h; this file
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* only does the chip-level bring-up (clock, GPIO, NVIC, interrupt dispatch)
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* and mirrors the Nations USBFSD examples (HID_CDC_Composite): hw_config.c
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* (USBFS_IO_Configure / Set_USBClock / USB_Config) and n32h47x_48x_it.c /
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* n32h49x_it.c (USB_FS_LP_IRQHandler).
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*
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* USBFS:
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* - register base : 0x40004800 (USB_BASE)
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* - packet buffer : 0x40004C00 (USB_SRAM_BASE, 512 bytes)
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* - APB1 peripheral; USBFS needs a precise 48 MHz USB clock derived from
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* PLLCLK (48/96/144/192/240 MHz -> DIV1/2/3/4/5).
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* - IRQ : USB_FS_LP_IRQn (20, low priority, used here) ; USB_FS_HP_IRQn
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* (19, high priority, iso/double-buffer only)
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*/
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/**
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* @brief Configure the USBFS 48 MHz clock from the actual PLLCLK.
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*
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* The prescaler source is derived from SystemCoreClock at runtime, so the
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* divider always matches the frequency the board is actually running at
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* (no per-part compile-time table to keep in sync with the PLL setup).
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* Supported PLLCLK values: 48/96/144/192/240 MHz -> DIV1/2/3/4/5.
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* Unsupported frequencies leave the prescaler untouched and must be fixed
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* in the board clock configuration (48 MHz USB clock is then not guaranteed).
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*/
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static void Set_USBClock(void)
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{
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switch (SystemCoreClock) {
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case 48000000: /* SYSCLK_VALUE_48MHz -> DIV1 */
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RCC_ConfigUSBPLLPresClk(RCC_USBPLLCLK_SRC_PLL, RCC_USBPLLCLK_DIV1);
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RCC->CFG3 &= ~RCC_CFG3_USBFSTM;
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break;
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case 96000000: /* SYSCLK_VALUE_96MHz -> DIV2 */
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RCC_ConfigUSBPLLPresClk(RCC_USBPLLCLK_SRC_PLL, RCC_USBPLLCLK_DIV2);
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RCC->CFG3 &= ~RCC_CFG3_USBFSTM;
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break;
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case 144000000: /* SYSCLK_VALUE_144MHz -> DIV3 */
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RCC_ConfigUSBPLLPresClk(RCC_USBPLLCLK_SRC_PLL, RCC_USBPLLCLK_DIV3);
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RCC->CFG3 |= RCC_CFG3_USBFSTM;
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break;
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case 192000000: /* SYSCLK_VALUE_192MHz -> DIV4 */
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RCC_ConfigUSBPLLPresClk(RCC_USBPLLCLK_SRC_PLL, RCC_USBPLLCLK_DIV4);
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RCC->CFG3 |= RCC_CFG3_USBFSTM;
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break;
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case 240000000: /* SYSCLK_VALUE_240MHz -> DIV5 */
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RCC_ConfigUSBPLLPresClk(RCC_USBPLLCLK_SRC_PLL, RCC_USBPLLCLK_DIV5);
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RCC->CFG3 |= RCC_CFG3_USBFSTM;
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break;
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default:
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USB_LOG_ERR("Unsupported system clock %u Hz for USBFS 48 MHz clock (supported: 48/96/144/192/240 MHz)\r\n",
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(unsigned int)SystemCoreClock);
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break;
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}
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}
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/**
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* @brief Configure the USB DM/DP pins.
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*
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* Defaults to the EVAL board mapping (PA11 = DM, PA12 = DP, AF10).
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* Marked __WEAK so the board layer can override it for other pin maps.
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*/
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__WEAK void n32h4xx_usbfs_gpio_init(void)
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{
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RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA, ENABLE);
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GPIO_InitType GPIO_InitStructure;
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GPIO_InitStruct(&GPIO_InitStructure);
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GPIO_InitStructure.Pin = GPIO_PIN_11;
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GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.GPIO_Alternate = GPIO_AF10;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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GPIO_InitStructure.Pin = GPIO_PIN_12;
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GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.GPIO_Alternate = GPIO_AF10;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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}
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/**
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* @brief Low-level USBFS initialization: clock, GPIO and interrupt channel.
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*
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* Signature must match the __WEAK stub in usb_dc_fsdev.c (no parameter),
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* so the fsdev port always talks to bus 0.
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*/
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void usb_dc_low_level_init(void)
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{
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if (g_usbdev_bus[0].reg_base != USBFS_REG_BASE) {
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return;
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}
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/* 1. USBFS 48 MHz clock: source select, PLL prescaler, APB1 enable. */
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RCC_ConfigUSBFSClk(RCC_USBFS_CLKSRC_PLLPRES);
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Set_USBClock();
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RCC_EnableAPB1PeriphClk(USBFS_APB1_CLK, ENABLE);
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/* 2. USB DM/DP pins (weak hook, override in the board layer). */
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n32h4xx_usbfs_gpio_init();
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/* 3. Low-priority USB FS interrupt (all FS device events, including the
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* USB_STS.WKUP/SUSPD bits handled by usb_dc_fsdev.c). Priority-group
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* selection stays with the board/application startup code. */
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NVIC_InitType NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = USB_FS_LP_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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/**
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* @brief Low-level USBFS deinitialization: disable interrupt and APB1 clock.
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*/
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void usb_dc_low_level_deinit(void)
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{
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if (g_usbdev_bus[0].reg_base != USBFS_REG_BASE) {
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return;
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}
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NVIC_InitType NVIC_InitStructure;
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NVIC_InitStructure.NVIC_IRQChannel = USB_FS_LP_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
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NVIC_Init(&NVIC_InitStructure);
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RCC_EnableAPB1PeriphClk(USBFS_APB1_CLK, DISABLE);
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}
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/**
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* @brief Low-priority USB FS interrupt: dispatches all FS device events.
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*/
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void USB_FS_LP_IRQHandler(void)
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{
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USBD_IRQHandler(0);
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}
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#endif /* N32H4X_FSDEV */
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