[bsp][renesas] Add ra8p1-titan-board BSP.

2026-02-06 00:45:22 +08:00 · 2025-12-03 10:16:44 +08:00
parent 99e78544f4
commit 0ea9d8f3be
255 changed files with 317041 additions and 25 deletions
--- a/.github/ALL_BSP_COMPILE.json
+++ b/.github/ALL_BSP_COMPILE.json
@@ -248,7 +248,7 @@
        "nxp/mcx/mcxc/frdm-mcxc444",
        "nxp/mcx/mcxa/frdm-mcxa153",
        "nxp/mcx/mcxa/frdm-mcxa156",
-		"nxp/mcx/mcxa/frdm-mcxa346",
+        "nxp/mcx/mcxa/frdm-mcxa346",
        "nxp/mcx/mcxe/frdm-mcxe247",
        "renesas/ebf_qi_min_6m5",
        "renesas/ra6m4-cpk",
@@ -258,12 +258,13 @@
        "renesas/ra6e2-ek",
        "renesas/ra6e2-fpb",
        "renesas/ra4e2-eco",
-		"renesas/ra4m1-ek",
+        "renesas/ra4m1-ek",
        "renesas/ra4m2-eco",
        "renesas/ra2l1-cpk",
        "renesas/ra8m1-ek",
        "renesas/ra8d1-ek",
        "renesas/ra8d1-vision-board",
+        "renesas/ra8p1-titan-board",
        "renesas/rzt2m_rsk",
        "renesas/rzn2l_rsk",
        "renesas/rzn2l_etherkit",
--- a/bsp/README.md
+++ b/bsp/README.md
@@ -33,28 +33,29 @@ This document is based on the RT-Thread mainline repository and categorizes the

 #### 🟢 Renesas

-| BSP Name | GPIO | UART | ADC | CAN | CANFD | DAC | Ethernet | HWTimer | I2C | PWM | RTC | SPI | Soft SPI | Flash | SDHI | SCI | SDRAM | LCD | Other |
-|----------|------|------|-----|-----|-------|-----|----------|---------|-----|-----|-----|-----|----------|-------|------|-----|-------|-----|-------|
-| [ebf_qi_min_6m5](renesas/ebf_qi_min_6m5) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - |
-| [ra2a1-ek](renesas/ra2a1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - |
-| [ra2e2-ek](renesas/ra2e2-ek) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - |
-| [ra2l1-cpk](renesas/ra2l1-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | ✅ |
-| [ra4e2-eco](renesas/ra4e2-eco) | ✅ | ✅ | - | - | - | - | - | - | ✅ | - | - | ✅ | - | - | - | - | - | - | - |
-| [ra4e2-ek](renesas/ra4e2-ek) | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
-| [ra4m1-ek](renesas/ra4m1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - |
-| [ra4m2-eco](renesas/ra4m2-eco) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | ✅ | - | - | - | ✅ | - | - | - |
-| [ra6e2-ek](renesas/ra6e2-ek) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
-| [ra6e2-fpb](renesas/ra6e2-fpb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
-| [ra6m3-ek](renesas/ra6m3-ek) | ✅ | ✅ | - | - | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | - |
-| [ra6m3-hmi-board](renesas/ra6m3-hmi-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | ✅ |
-| [ra6m4-cpk](renesas/ra6m4-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | ✅ |
-| [ra6m4-iot](renesas/ra6m4-iot) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | - |
-| [ra8d1-ek](renesas/ra8d1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [ra8d1-vision-board](renesas/ra8d1-vision-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ |
-| [ra8m1-ek](renesas/ra8m1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | ✅ |
-| [rzn2l_etherkit](renesas/rzn2l_etherkit) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | ✅ |
-| [rzn2l_rsk](renesas/rzn2l_rsk) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | ✅ |
-| [rzt2m_rsk](renesas/rzt2m_rsk) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | ✅ |
+| BSP Name | GPIO | UART | ADC | CAN | CANFD | DAC | Ethernet | HWTimer | I2C | PWM | RTC | SPI | Soft SPI | Flash | SDHI | SCI | SDRAM | LCD | **RS485** | Other |
+|----------|------|------|-----|-----|-------|-----|----------|---------|-----|-----|-----|-----|----------|-------|------|-----|-------|-----|-------|-------|
+| [ebf_qi_min_6m5](renesas/ebf_qi_min_6m5) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - |
+| [ra2a1-ek](renesas/ra2a1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - |
+| [ra2e2-ek](renesas/ra2e2-ek) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - |
+| [ra2l1-cpk](renesas/ra2l1-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ |
+| [ra4e2-eco](renesas/ra4e2-eco) | ✅ | ✅ | - | - | - | - | - | - | ✅ | - | - | ✅ | - | - | - | - | - | - | - | - |
+| [ra4e2-ek](renesas/ra4e2-ek) | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| [ra4m1-ek](renesas/ra4m1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - |
+| [ra4m2-eco](renesas/ra4m2-eco) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | ✅ | - | - | - | ✅ | - | - | - | - |
+| [ra6e2-ek](renesas/ra6e2-ek) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| [ra6e2-fpb](renesas/ra6e2-fpb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
+| [ra6m3-ek](renesas/ra6m3-ek) | ✅ | ✅ | - | - | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | - | - |
+| [ra6m3-hmi-board](renesas/ra6m3-hmi-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | ✅ |
+| [ra6m4-cpk](renesas/ra6m4-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | - | ✅ |
+| [ra6m4-iot](renesas/ra6m4-iot) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | - | - |
+| [ra8d1-ek](renesas/ra8d1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ |
+| [ra8d1-vision-board](renesas/ra8d1-vision-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ |
+| [ra8p1-titan-board](renesas/ra8p1-titan-board) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ |
+| [ra8m1-ek](renesas/ra8m1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ |
+| [rzn2l_etherkit](renesas/rzn2l_etherkit) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ |
+| [rzn2l_rsk](renesas/rzn2l_rsk) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | - | ✅ |
+| [rzt2m_rsk](renesas/rzt2m_rsk) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | - | ✅ |

 #### 🟢 STM32

--- a/bsp/renesas/README.md
+++ b/bsp/renesas/README.md
@@ -19,7 +19,8 @@ RA 系列 BSP 目前支持情况如下表所示：
 | [ra8m1-ek](ra8m1-ek)                     | Renesas 官方 EK-RA8M1 开发板                     |
 | [ra8d1-ek](ra8d1-ek)                     | Renesas 官方 EK-RA8D1 开发板                     |
 | [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 |
-| **RZ 系列**                             |                                                  |
+| [ra8p1-titan-board](ra8p1-titan-board)   | Renesas 联合 RT-Thread RA8P1-Titan-Board 开发板  |
+| **RZ 系列**                              |                                                  |
 | [rzt2m_rsk](rzt2m_rsk)                   | Renesas 官方 RSK-RZT2M 开发板                    |
 | [rzn2l_rsk](rzn2l_rsk)                   | Renesas 官方 RSK-RZN2L 开发板                    |

--- a/bsp/renesas/libraries/HAL_Drivers/drv_common.c
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_common.c
@@ -170,6 +170,12 @@ rt_weak void rt_hw_board_init()
    rt_hw_interrupt_init();
 #endif

+#if defined(BSP_CFG_CPU_CORE) && (BSP_CFG_CPU_CORE == CPU0) && defined(SOC_SERIES_R7KA8P1) && defined(BSP_START_SECONDARY_CORE)
+    #if !defined(BSP_USING_RPMSG_LITE_MCMGR)
+        R_BSP_SecondaryCoreStart();
+    #endif
+#endif
+
    rt_hw_systick_init();

    /* Heap initialization */
--- a/bsp/renesas/libraries/Kconfig
+++ b/bsp/renesas/libraries/Kconfig
@@ -61,6 +61,12 @@ config SOC_SERIES_R7FA8M85
    select SOC_FAMILY_RENESAS_RA
    default n

+config SOC_SERIES_R7KA8P1
+    bool
+    select ARCH_ARM_CORTEX_M85
+    select SOC_FAMILY_RENESAS_RA
+    default n
+
 config SOC_SERIES_R9A07G0
    bool
    select ARCH_ARM_CORTEX_R52
--- a/bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml
+++ b/bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml
@@ -0,0 +1,40 @@
+# ------ devices CI ------
+devices.adc:
+    kconfig:
+      - CONFIG_RT_USING_ADC=y
+      - CONFIG_BSP_USING_ADC0=y
+devices.spi:
+    kconfig:
+      - CONFIG_BSP_USING_SPI=y
+      - CONFIG_BSP_USING_SPI0=y
+devices.i2c:
+    kconfig:
+      - CONFIG_BSP_USING_HW_I2C=y
+      - CONFIG_BSP_USING_HW_I2C2=y
+devices.sdhi:
+    kconfig:
+      - CONFIG_BSP_USING_SDHI=y
+      - CONFIG_BSP_USING_SDHI0=y
+      - CONFIG_SDHI_USING_1_BIT=y
+devices.timer:
+    kconfig:
+      - CONFIG_BSP_USING_TIM=y
+      - CONFIG_BSP_USING_TIM0=y
+devices.pwm:
+    kconfig:
+      - CONFIG_BSP_USING_PWM=y
+      - CONFIG_BSP_USING_PWM12=y
+devices.can:
+    kconfig:
+      - CONFIG_BSP_USING_CANFD=y
+      - CONFIG_BSP_USING_CAN_RA=y
+      - CONFIG_BSP_USING_CAN0=y
+devices.hyperram:
+    kconfig:
+      - CONFIG_BSP_USING_OSPI_RAM=y
+devices.ethernet:
+    kconfig:
+      - CONFIG_BSP_USING_ETH=y
+devices.rtc:
+    kconfig:
+      - CONFIG_BSP_USING_ONCHIP_RTC=y
--- a/bsp/renesas/ra8p1-titan-board/.config
+++ b/bsp/renesas/ra8p1-titan-board/.config
--- a/bsp/renesas/ra8p1-titan-board/.cproject
+++ b/bsp/renesas/ra8p1-titan-board/.cproject
--- a/bsp/renesas/ra8p1-titan-board/.gitignore
+++ b/bsp/renesas/ra8p1-titan-board/.gitignore
@@ -0,0 +1,26 @@
+/RTE
+/Listings
+/Objects
+/Debug
+/build
+/makefile.targets
+/rtconfig.pyc
+/libraries
+/rt-thread
+/project.custom_argvars
+/.vscode
+/__pycache
+/settings
+/rtconfig_preinc.h
+/bsp_linker_info.h
+/fsp_gen.ld
+/memory_regions.ld
+/cmake
+/.api_xml
+/.clangd
+/.secure_azone
+/.secure_rzone
+/.secure_xml
+/ra_cfg.txt
+/packages/pkgs.json
+/packages/pkgs_error.json
--- a/bsp/renesas/ra8p1-titan-board/.project
+++ b/bsp/renesas/ra8p1-titan-board/.project
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects />
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments />
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments />
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.rt-thread.studio.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>
--- a/bsp/renesas/ra8p1-titan-board/.settings/.rtmenus
+++ b/bsp/renesas/ra8p1-titan-board/.settings/.rtmenus
--- a/bsp/renesas/ra8p1-titan-board/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
+++ b/bsp/renesas/ra8p1-titan-board/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/13.3/bin
--- a/bsp/renesas/ra8p1-titan-board/.settings/language.settings.xml
+++ b/bsp/renesas/ra8p1-titan-board/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1925467032309591728" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
--- a/bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.resources.prefs
+++ b/bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+rtt-studio.preferences.renesas.configurator.root=C\:\\Renesas\\RA\\sc_v2025-04.1_fsp_v6.0.0
--- a/bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.runtime.prefs
+++ b/bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.runtime.prefs
@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1
--- a/bsp/renesas/ra8p1-titan-board/.settings/projcfg.ini
+++ b/bsp/renesas/ra8p1-titan-board/.settings/projcfg.ini
@@ -0,0 +1,20 @@
+#RT-Thread Studio Project Configuration
+#Thu Nov 27 11:45:38 CST 2025
+project_type=rt-thread
+chip_name=R7KA8P1KF
+os_branch=full
+example_name=
+os_version=latest
+selected_rtt_version=latest
+cfg_version=v3.0
+board_base_nano_proj=False
+is_use_scons_build=True
+output_project_path=C\:\\Users\\RTT\\Desktop\\PR\\sdk-bsp-ra8p1-titan-board\\project
+project_base_bsp=true
+hardware_adapter=DAP-LINK
+project_name=Titan_template
+is_base_example_project=False
+board_name=ra8p1-titan-board
+device_vendor=RENESAS
+bsp_version=1.0.2
+bsp_path=repo/Extract/Board_Support_Packages/RealThread/Titan_Board/1.0.2
--- a/bsp/renesas/ra8p1-titan-board/.settings/standalone.prefs
+++ b/bsp/renesas/ra8p1-titan-board/.settings/standalone.prefs
--- a/bsp/renesas/ra8p1-titan-board/.settings/titan_bsp.DAPLink.Debug.rttlaunch
+++ b/bsp/renesas/ra8p1-titan-board/.settings/titan_bsp.DAPLink.Debug.rttlaunch
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.adapterName" value="DAP-LINK"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.binFlashStartAddress" value=""/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="1000000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerDeviceName" value="R7KA8P1KF"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="C:\Softwares\RT-ThreadStudio\repo\Extract\Debugger_Support_Packages\RealThread\PyOCD\0.2.9\pyocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.programMode" value="HEX"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="C:\Softwares\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\ARM\GNU_Tools_for_ARM_Embedded_Processors\13.3\bin\arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="titan_bsp"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/titan_bsp"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="UTF-8"/>
+</launchConfiguration>
--- a/bsp/renesas/ra8p1-titan-board/Kconfig
+++ b/bsp/renesas/ra8p1-titan-board/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+PKGS_DIR := packages
+
+ENV_DIR := /
+
+config SOC_R7KA8P1KF
+    bool
+    select SOC_SERIES_R7KA8P1
+    select SOC_SERIES_R7KA8P1_CORE0
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+
+if !RT_USING_NANO
+rsource "$(BSP_DIR)/board/Kconfig"
+endif
--- a/bsp/renesas/ra8p1-titan-board/README.md
+++ b/bsp/renesas/ra8p1-titan-board/README.md
@@ -0,0 +1,230 @@
+# Titan Board BSP Description
+
+**English** | [**Chinese**](./README_zh.md)
+
+## Introduction
+
+This document provides the BSP (Board Support Package) description for the RT-Thread **Titan Board** development board. By following the Quick Start Guide, developers can quickly get started with this BSP and run RT-Thread on the development board.
+
+The main contents include:
+
+- Introduction to the development board
+- BSP Quick Start Guide
+
+## Development Board Introduction
+
+The Titan Board is an RT-Thread development board based on Renesas **Cortex-M85 + Cortex-M33 dual-core architecture R7KA8P1** MCU. It provides engineers a flexible and comprehensive development platform, enabling deeper exploration in embedded IoT development.
+
+Titan Board integrates the **RA8P1** chip featuring a **1GHz Arm® Cortex®-M85** core and a **250MHz Arm® Cortex®-M33** core. The RA8P1 series is Renesas’ first 32-bit AI-accelerated MCU featuring high-performance **Arm® Cortex®-M85 (CM85)** with **Helium™ vector extensions**, and an integrated **Ethos™-U55 NPU**. It delivers **256 GOPS AI performance**, over **7300 CoreMarks**, and advanced AI capabilities supporting voice, vision, and real-time analytics.
+
+The front view of the development board is shown below:
+
+![big](figures/big.png)
+
+Common **on-board resources** are as follows:
+
+![titan_board_hw_resource](figures/titan_board_hw_resource.png)
+
+## Peripheral Support
+
+The current peripheral support status in this BSP is as follows:
+
+| **On-chip Peripheral** | **Support Status** | **Component**               | **Support Status** |
+| ---------------------- | ------------------ | --------------------------- | ------------------ |
+| UART                   | Supported          | LWIP                        | Supported          |
+| GPIO                   | Supported          | TCP/UDP                     | Supported          |
+| HWTIMER                | Supported          | MQTT                        | Supported          |
+| I2C                    | Supported          | TFTP                        | Supported          |
+| WDT                    | Supported          | Telnet                      | Supported          |
+| RTC                    | Supported          | **Multicore Communication** | **Support Status** |
+| ADC                    | Supported          | RPMsg-Lite                  | Supported          |
+| DAC                    | Supported          | **Extended peripheral**     | **Support Status** |
+| SPI                    | Supported          | MIPI CSI Camera             | Supported          |
+| RS485                  | Supported          | CEU Camera                  | Supported          |
+| CANFD                  | Supported          | RGB LCD                     | Supported          |
+| SDHI                   | Supported          | CYW43438 WIFI               | Supported          |
+| USB                    | Supported          |                             |                    |
+| HyperRAM               | Supported          |                             |                    |
+| HyperFlash             | Supported          |                             |                    |
+
+> **Note:** The repository provides a minimal system by default. To enable or add additional peripherals, please refer to:
+>  Peripheral Driver Usage Guide (rt-thread.org)
+
+## User Guide
+
+The user guide is divided into the following two sections:
+
+- **Quick Start**
+
+  This section is intended for beginners who are just getting started with RT-Thread. By following simple steps, you can run the RT-Thread operating system on this development board and observe the experimental results.
+
+- **Advanced Usage**
+
+  This section is intended for developers who need to use more board resources on the RT-Thread operating system. By using the FSP and RT-Thread Settings tools to configure the project, more on-board resources can be enabled to achieve advanced functionality.
+
+### FSP Version Information
+
+This BSP uses **FSP 6.2.0**. You must download and install it for peripheral development.
+
+- Download link: [rasc-6.2.0](https://github.com/renesas/fsp/releases/download/v6.2.0/setup_fsp_v6_2_0_rasc_v2025-10.exe)
+- Note: The BSP provides minimal configuration by default. To enable other peripherals, refer to: [Peripheral Driver Usage Guide](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
+
+### Quick Start
+
+This BSP can be directly imported into **RT-Thread Studio v2.3.0**. The following steps demonstrate how to run the system using RT-Thread Studio.
+
+### **Install Toolchains**
+
+1. Install the compiler toolchain:
+
+![image-20251127164450247](figures/image-20251127164450247.png)
+
+2. Install debugging tools:
+
+Download **J-Link v8.48** and **PyOCD 0.2.9**.
+
+![image-20251127164534568](figures/image-20251127164534568.png)
+
+### **Create a Project**
+
+1. Click **File → Import**.
+
+![image-20251127164859503](figures/image-20251127164859503.png)
+
+2. Select **Import RT-Thread BSP**, then click **Next**.
+
+![image-20251127164952040](figures/image-20251127164952040.png)
+
+3. Select the BSP root directory and fill in project information, then click **Finish**.
+
+![image-20251127165319591](figures/image-20251127165319591.png)
+
+4. The project based on the BSP is created.
+
+![image-20251127165406340](figures/image-20251127165406340.png)
+
+### **Configure Debug/Download Settings**
+
+> **Note: Sometimes you may need to modify the settings twice for them to take effect.**
+
+Modify the debugger configuration in the **Debugger** tab.
+
+![image-20251127165957537](figures/image-20251127165957537.png)
+
+In the **Download** tab, change the download method to **Flash Hex File**, then click **OK**.
+
+![image-20251127170436152](figures/image-20251127170436152.png)
+
+![image-20251127171037225](figures/image-20251127171037225.png)
+
+**Hardware Connection**
+
+Use a USB cable to connect the development board to the PC, and use the DAP-Link interface to download and debug the program.
+
+**Build and Download**
+
+![image-20251127165554294](figures/image-20251127165554294.png)
+
+**View Running Results**
+
+After the program is successfully downloaded, the system will automatically run and print system information.
+
+Connect the development board’s corresponding serial port to the PC, open the corresponding serial port in a terminal tool (115200-8-1-N), and reset the device. You will then see the RT-Thread output information. Enter the `help` command to view the commands supported in the system.
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.3.0 build Nov 27 2025 13:12:46
+ 2006 - 2024 Copyright by RT-Thread team
+
+==================================================
+Hello, Titan Board!
+==================================================
+msh >help
+RT-Thread shell commands:
+backtrace        - print backtrace of a thread
+clear            - clear the terminal screen
+version          - show RT-Thread version information
+list             - list objects
+help             - RT-Thread shell help
+ps               - List threads in the system
+free             - Show the memory usage in the system
+pin              - pin [option]
+reboot           - Reboot System
+
+msh >
+
+```
+
+**Application Entry Function**
+
+The entry function of the application layer is located in **src\hal_entry.c** within `void hal_entry(void)`. User-created source files can be placed directly in the **src** directory.
+
+```c
+#include <rtthread.h>
+#include "hal_data.h"
+#include <rtdevice.h>
+#include <board.h>
+
+#define LED_PIN     BSP_IO_PORT_00_PIN_12 /* Onboard LED pins */
+
+void hal_entry(void)
+{
+    rt_kprintf("\n==================================================\n");
+    rt_kprintf("Hello, Titan Board!\n");
+    rt_kprintf("==================================================\n");
+
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(1000);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(1000);
+    }
+}
+```
+
+### Advanced Usage
+
+**Resources and Documentation**
+
+- [Development Board Official Homepage](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/hw-board/ra8p1-titan-board/ra8p1-titan-board)
+- [Development Board Datasheet](https://www.renesas.cn/zh/document/dst/25574255?r=25574019)
+- [Development Board Hardware Manual](https://www.renesas.cn/zh/document/mah/25574257?r=25574019)
+- [Dualcore Development Guide](https://www.renesas.cn/zh/document/apn/developing-ra8-dual-core-mcu?r=25574019)
+- [Renesas RA8P1 Group](https://www.renesas.cn/zh/document/fly/renesas-ra8p1-group?r=25574019)
+
+**FSP Configuration**
+
+If you need to modify the Renesas BSP peripheral configuration or add new peripheral interfaces, you will need to use the Renesas [Flexible Software Package (FSP)](https://www.renesas.cn/zh/software-tool/flexible-software-package-fsp?queryID=c20a16b5f7f3866713b62c7acb07f2fc) configuration tool. Please make sure to follow the steps below for configuration. If you encounter any issues, you may ask questions in the [RT-Thread Community Forum](https://club.rt-thread.org/).
+
+1. [Download Flexible Software Package (FSP) | Renesas](https://github.com/renesas/fsp/releases/download/v6.2.0/setup_fsp_v6_2_0_rasc_v2025-10.exe), please use **FSP version 6.2.0**
+2. Refer to the documentation: [Configuring Peripheral Drivers Using FSP for the RA Series](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动).
+
+- **Configure development by importing FSP:**
+
+Users can locate the `configuration.xml` file in the project and import it into FSP to start configuration:
+
+Select **File → Open** at the top-left corner to open the configuration file.
+
+![image-20251030163423452](figures/image-20251030163423452.png)
+
+* **Generate FSP Code:**
+
+![image-20251030163707813](figures/image-20251030163707813.png)
+
+**RT-Thread Settings**
+
+In **RT-Thread Settings**, you can configure the RT-Thread kernel, components, software packages, and Titan Board device drivers.
+
+![image-20250819173700386](figures/image-20250819173700386.png)
+
+## Contact Information
+
+If you have any thoughts or suggestions during usage, please feel free to contact us via the [RT-Thread Community Forum](https://club.rt-thread.org/).
+
+## Contribute Code
+
+If you're interested in Titan Board and have some exciting projects you'd like to share, we welcome code contributions. Please refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github).
--- a/bsp/renesas/ra8p1-titan-board/README_zh.md
+++ b/bsp/renesas/ra8p1-titan-board/README_zh.md
@@ -0,0 +1,228 @@
+# Titan Board 开发板 BSP 说明
+
+**中文** | [**English**](./README.md)
+
+## 简介
+
+本文档为 RT-Thread Titan Board 开发板提供 BSP (板级支持包) 说明。通过阅读快速上手章节，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+主要内容如下：
+
+- 开发板介绍
+- BSP 快速上手指南
+
+## 开发板介绍
+
+Titan Board 开发板是 RT-Thread 推出基于瑞萨 Cortex-M85 与 Cortex-M33 双核架构 R7KA8P1 芯片，为工程师们提供了一个灵活、全面的开发平台，助力开发者在嵌入式物联网领域获得更深层次的体验。
+
+Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 双架构核 RA8P1 芯片。RA8P1 系列是瑞萨电子首款搭载高性能 Arm® Cortex®-M85 (CM85) 及 Helium™ 矢量扩展，并集成 Ethos™-U55 NPU 的 32 位 AI 加速微控制器 (MCU)。 该系列通过单芯片实现 256 GOPS 的 AI 性能、超过 7300 CoreMarks 的突破性 CPU 性能和先进的人工智能 (AI) 功能，可支持语音、视觉和实时分析 AI 场景。
+
+开发板正面外观如下图：
+
+![big](figures/big.png)
+
+该开发板常用 **板载资源** 如下：
+
+![titan_board_hw_resource](figures/titan_board_hw_resource.png)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **组件** | **支持情况**  |
+| ------------ | ------------ | -------- | ------------ |
+| UART         | 支持         | LWIP     | 支持         |
+| GPIO         | 支持         | TCP/UDP  | 支持         |
+| HWTIMER      | 支持         | MQTT     | 支持         |
+| IIC          | 支持         | TFTP     | 支持         |
+| WDT          | 支持         | Telnet | 支持 |
+| RTC          | 支持         | **多核通信** | **支持情况** |
+| ADC          | 支持         | RPMsg-Lite | 支持 |
+| DAC          | 支持         | **拓展外设** | **支持情况** |
+| SPI          | 支持         | MIPI CSI Camera | 支持 |
+| RS485 | 支持 | CEU Camera | 支持 |
+| CANFD | 支持 | RGB LCD | 支持 |
+| SDHI | 支持 | CYW43438 WIFI | 支持 |
+| USB | 支持 | | |
+| HyperRAM | 支持 | | |
+| HyperFlash | 支持 | | |
+
+- 注意：仓库刚拉下来是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果。
+- 进阶使用
+
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 FSP 和 RT-Thread Settings 工具对项目进行配置，可以开启更多板载资源，实现更多高级功能。
+
+## FSP 版本说明
+
+本 BSP 使用的是 FSP6.2.0 版本，进行外设相关开发需要下载并安装。
+
+- 下载链接：[rasc-6.2.0](https://github.com/renesas/fsp/releases/download/v6.2.0/setup_fsp_v6_2_0_rasc_v2025-10.exe)
+- 注意：BSP默认是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
+
+### 快速上手
+
+本 BSP 目前可以直接导入到 **RT-Thread Studio v2.3.0** 中开发。下面以 RT-Thread Studio 开发环境为例，介绍如何将系统运行起来。
+
+**安装工具链**
+
+1. 安装编译工具链
+
+![image-20251127164450247](figures/image-20251127164450247.png)
+
+2. 调试工具
+
+	下载 J-Link v8.48 和 PyOCD 0.2.9。
+
+![image-20251127164534568](figures/image-20251127164534568.png)
+
+**创建工程**
+
+1. 点击左上角 文件-->导入。
+
+![image-20251127164859503](figures/image-20251127164859503.png)
+
+2. 选择导入 RT-Thread Bsp 到工作空间，点击“下一步”。
+
+![image-20251127164952040](figures/image-20251127164952040.png)
+
+3. 选择 BSP 根目录并填写好工程信息，点击“完成”。
+
+![image-20251127165319591](figures/image-20251127165319591.png)
+
+4. 基于 BSP 创建工程就完成了。
+
+![image-20251127165406340](figures/image-20251127165406340.png)
+
+**配置工程的调试下载设置**
+
+> **注意：有时需要修改两遍才生效。**
+
+在”调试器“选项卡中修改调试器的配置。
+
+![image-20251127165957537](figures/image-20251127165957537.png)
+
+在“下载”选项卡中将烧录方式改为“烧录Hex文件”，之后点击“确定“完成配置。
+
+![image-20251127170436152](figures/image-20251127170436152.png)
+
+![image-20251127171037225](figures/image-20251127171037225.png)
+
+**硬件连接**
+
+使用 USB 数据线连接开发板到 PC，使用 DAP-Link 接口下载和 DEBUG 程序。
+
+**编译下载**
+
+![image-20251127165554294](figures/image-20251127165554294.png)
+
+**查看运行结果**
+
+下载程序成功之后，系统会自动运行并打印系统信息。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.3.0 build Nov 27 2025 13:12:46
+ 2006 - 2024 Copyright by RT-Thread team
+
+==================================================
+Hello, Titan Board!
+==================================================
+msh >help
+RT-Thread shell commands:
+backtrace        - print backtrace of a thread
+clear            - clear the terminal screen
+version          - show RT-Thread version information
+list             - list objects
+help             - RT-Thread shell help
+ps               - List threads in the system
+free             - Show the memory usage in the system
+pin              - pin [option]
+reboot           - Reboot System
+
+msh >
+
+```
+
+**应用入口函数**
+
+应用层的入口函数在 **src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
+
+```c
+#include <rtthread.h>
+#include "hal_data.h"
+#include <rtdevice.h>
+#include <board.h>
+
+#define LED_PIN     BSP_IO_PORT_00_PIN_12 /* Onboard LED pins */
+
+void hal_entry(void)
+{
+    rt_kprintf("\n==================================================\n");
+    rt_kprintf("Hello, Titan Board!\n");
+    rt_kprintf("==================================================\n");
+
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(1000);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(1000);
+    }
+}
+```
+
+### 进阶使用
+
+**资料及文档**
+
+- [开发板官网主页](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/hw-board/ra8p1-titan-board/ra8p1-titan-board)
+- [开发板数据手册](https://www.renesas.cn/zh/document/dst/25574255?r=25574019)
+- [开发板硬件手册](https://www.renesas.cn/zh/document/mah/25574257?r=25574019)
+- [多核开发指南](https://www.renesas.cn/zh/document/apn/developing-ra8-dual-core-mcu?r=25574019)
+- [Renesas RA8P1 Group](https://www.renesas.cn/zh/document/fly/renesas-ra8p1-group?r=25574019)
+
+**FSP 配置**
+
+需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [RA 可扩展性强的配置软件包 (FSP)](https://www.renesas.cn/zh/software-tool/flexible-software-package-fsp?queryID=c20a16b5f7f3866713b62c7acb07f2fc) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到 [RT-Thread 社区论坛](https://club.rt-thread.org/) 中提问。
+
+1. [下载灵活配置软件包 (FSP) | Renesas](https://github.com/renesas/fsp/releases/download/v6.2.0/setup_fsp_v6_2_0_rasc_v2025-10.exe)，请使用 FSP 6.2.0 版本
+2. 请参考文档：[RA系列使用FSP配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)。
+
+* **通过导入fsp进行开发配置：**
+
+用户可通过找到工程下的configuration.xml文件，将其导入到fsp中，即可开始配置：
+
+选择左上角 file->open 打开配置文件
+
+![image-20251030163423452](figures/image-20251030163423452.png)
+
+* **生成 FSP 代码：**
+
+![image-20251030163707813](figures/image-20251030163707813.png)
+
+**RT-Thread Settings**
+
+在 RT-Thread Settings 中可以对 RT-Thread 的内核、组件、软件包以及 Titan Board 的设备驱动进行配置。
+
+![image-20250819173700386](figures/image-20250819173700386.png)
+
+## 联系人信息
+
+在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们  [RT-Thread 社区论坛](https://club.rt-thread.org/)
+
+## 贡献代码
+
+如果您对 Titan Board 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
--- a/bsp/renesas/ra8p1-titan-board/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/SConscript
@@ -0,0 +1,28 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+CPPPATH = []
+list = os.listdir(cwd)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
+    if GetOption('target') != 'mdk5':
+        CPPPATH = [cwd]
+        src = Glob('./src/*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')
--- a/bsp/renesas/ra8p1-titan-board/SConstruct
+++ b/bsp/renesas/ra8p1-titan-board/SConstruct
@@ -0,0 +1,55 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
--- a/bsp/renesas/ra8p1-titan-board/board/Kconfig
+++ b/bsp/renesas/ra8p1-titan-board/board/Kconfig
--- a/bsp/renesas/ra8p1-titan-board/board/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/board/SConscript
@@ -0,0 +1,18 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+src = Glob('*.c')
+
+CPPDEFINES = ['_RA_CORE=0']
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
--- a/bsp/renesas/ra8p1-titan-board/board/board.h
+++ b/bsp/renesas/ra8p1-titan-board/board/board.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-10      Sherman      first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_SRAM_SIZE    1872 /* The SRAM size of the chip needs to be modified */
+#define RA_SRAM_END     (0x22000000 + RA_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RAM_END$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$RAM_END$$ZI$$Base)
+#elif __ICCARM__
+#pragma section="ram_BLOCK"
+#define HEAP_BEGIN      (__segment_end("ram_BLOCK"))
+#else
+extern int __RAM_segment_used_end__;
+#define HEAP_BEGIN      (&__RAM_segment_used_end__)
+#endif
+
+#define HEAP_END        RA_SRAM_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h
+++ b/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h
@@ -0,0 +1,310 @@
+/* UNCRUSTIFY-OFF */
+#ifndef BSP_LINKER_H
+#define BSP_LINKER_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/******* Solution Definitions *************/
+#define BSP_PARTITION_RAM_CPU0_S_START (0x22000000)
+#define BSP_PARTITION_RAM_CPU0_S_SIZE (0x174000)
+#define BSP_PARTITION_SHARED_MEM_START (0x22174000)
+#define BSP_PARTITION_SHARED_MEM_SIZE (0x20000)
+#define BSP_PARTITION_RAM_CPU0_C_START (0x22174000)
+#define BSP_PARTITION_RAM_CPU0_C_SIZE (0x0)
+#define BSP_PARTITION_RAM_CPU1_S_START (0x22194000)
+#define BSP_PARTITION_RAM_CPU1_S_SIZE (0x40000)
+#define BSP_PARTITION_RAM_CPU1_C_START (0x221D4000)
+#define BSP_PARTITION_RAM_CPU1_C_SIZE (0x0)
+#define BSP_PARTITION_FLASH_CPU0_S_START (0x02000000)
+#define BSP_PARTITION_FLASH_CPU0_S_SIZE (OxCO000)
+#define BSP_PARTITION_FLASH_CPU0_C_START (0x020C0000)
+#define BSP_PARTITION_FLASH_CPU0_C_SIZE (0x0)
+#define BSP_PARTITION_FLASH_CPU1_S_START (0x020C0000)
+#define BSP_PARTITION_FLASH_CPU1_S_SIZE (0x40000)
+#define BSP_PARTITION_FLASH_CPU1_C_START (0x02100000)
+#define BSP_PARTITION_FLASH_CPU1_C_SIZE (0x0)
+#define BSP_PARTITION_DATA_FLASH_CPU0_S_START (0x27000000)
+#define BSP_PARTITION_DATA_FLASH_CPU0_S_SIZE (0x0)
+#define BSP_PARTITION_DATA_FLASH_CPU1_S_START (0x27000000)
+#define BSP_PARTITION_DATA_FLASH_CPU1_S_SIZE (0x0)
+#define BSP_PARTITION_SDRAM_CPU0_S_START (0x68000000)
+#define BSP_PARTITION_SDRAM_CPU0_S_SIZE (0x4000000)
+#define BSP_PARTITION_SDRAM_CPU1_S_START (0x6C000000)
+#define BSP_PARTITION_SDRAM_CPU1_S_SIZE (0x4000000)
+#define BSP_PARTITION_OSPI0_CS0_CPU0_S_START (0x80000000)
+#define BSP_PARTITION_OSPI0_CS0_CPU0_S_SIZE (0x8000000)
+#define BSP_PARTITION_OSPI0_CS0_CPU1_S_START (0x88000000)
+#define BSP_PARTITION_OSPI0_CS0_CPU1_S_SIZE (0x8000000)
+#define BSP_PARTITION_OSPI0_CS1_CPU0_S_START (0x90000000)
+#define BSP_PARTITION_OSPI0_CS1_CPU0_S_SIZE (0x8000000)
+#define BSP_PARTITION_OSPI0_CS1_CPU1_S_START (0x98000000)
+#define BSP_PARTITION_OSPI0_CS1_CPU1_S_SIZE (0x8000000)
+#define BSP_PARTITION_OSPI1_CS0_CPU0_S_START (0x70000000)
+#define BSP_PARTITION_OSPI1_CS0_CPU0_S_SIZE (0x4000000)
+#define BSP_PARTITION_OSPI1_CS0_CPU1_S_START (0x74000000)
+#define BSP_PARTITION_OSPI1_CS0_CPU1_S_SIZE (0x4000000)
+#define BSP_PARTITION_OSPI1_CS1_CPU0_S_START (0x78000000)
+#define BSP_PARTITION_OSPI1_CS1_CPU0_S_SIZE (0x4000000)
+#define BSP_PARTITION_OSPI1_CS1_CPU1_S_START (0x7C000000)
+#define BSP_PARTITION_OSPI1_CS1_CPU1_S_SIZE (0x4000000)
+#define BSP_PARTITION_ITCM_CPU0_S_START (0x00000000)
+#define BSP_PARTITION_ITCM_CPU0_S_SIZE (0x20000)
+#define BSP_PARTITION_DTCM_CPU0_S_START (0x20000000)
+#define BSP_PARTITION_DTCM_CPU0_S_SIZE (0x20000)
+#define BSP_PARTITION_CTCM_CPU1_S_START (0x00000000)
+#define BSP_PARTITION_CTCM_CPU1_S_SIZE (0x10000)
+#define BSP_PARTITION_STCM_CPU1_S_START (0x20000000)
+#define BSP_PARTITION_STCM_CPU1_S_SIZE (0x10000)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+/* linker generated initialization table data structures types */
+typedef enum e_bsp_init_mem
+{
+    INIT_MEM_ZERO,
+    INIT_MEM_FLASH,
+    INIT_MEM_DATA_FLASH,
+    INIT_MEM_RAM,
+    INIT_MEM_DTCM,
+    INIT_MEM_ITCM,
+    INIT_MEM_CTCM,
+    INIT_MEM_STCM,
+    INIT_MEM_OSPI0_CS0,
+    INIT_MEM_OSPI0_CS1,
+    INIT_MEM_OSPI1_CS0,
+    INIT_MEM_OSPI1_CS1,
+    INIT_MEM_QSPI_FLASH,
+    INIT_MEM_SDRAM,
+    INIT_MEM_SIP_FLASH,
+} bsp_init_mem_t;
+
+typedef struct st_bsp_init_type
+{
+    uint32_t copy_64 :8; /* if 1, must use 64 bit copy operation (to keep ecc happy) */
+    uint32_t external :8; /* =1 if either source or destination is external, else 0  */
+    uint32_t source_type :8;
+    uint32_t destination_type :8;
+} bsp_init_type_t;
+
+typedef struct st_bsp_init_zero_info
+{
+    uint32_t *const p_base;
+    uint32_t *const p_limit;
+    bsp_init_type_t type;
+} bsp_init_zero_info_t;
+
+typedef struct st_bsp_init_copy_info
+{
+    uint32_t *const p_base;
+    uint32_t *const p_limit;
+    uint32_t *const p_load;
+    bsp_init_type_t type;
+} bsp_init_copy_info_t;
+typedef struct st_bsp_init_nocache_info
+{
+    uint32_t *const p_base;
+    uint32_t *const p_limit;
+} bsp_mpu_nocache_info_t;
+
+typedef struct st_bsp_init_info
+{
+    uint32_t zero_count;
+    bsp_init_zero_info_t const *const p_zero_list;
+    uint32_t copy_count;
+    bsp_init_copy_info_t const *const p_copy_list;
+    uint32_t nocache_count;
+    bsp_mpu_nocache_info_t const *const p_nocache_list;
+} bsp_init_info_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+extern bsp_init_info_t const g_init_info;
+/* These symbols are used for sau/idau configuration in a secure project */
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+#endif   // BSP_LINKER_H
+#ifdef BSP_LINKER_C
+/***********************************************************************************************************************
+ * Objects allocated by bsp_linker.c
+ **********************************************************************************************************************/
+/* DDSC symbol definitions */
+/* Zero initialization tables */
+extern uint32_t __sdram_zero_nocache$$Base;
+extern uint32_t __sdram_zero_nocache$$Limit;
+extern uint32_t __sdram_zero$$Base;
+extern uint32_t __sdram_zero$$Limit;
+extern uint32_t __ospi0_cs0_zero_nocache$$Base;
+extern uint32_t __ospi0_cs0_zero_nocache$$Limit;
+extern uint32_t __ospi0_cs0_zero$$Base;
+extern uint32_t __ospi0_cs0_zero$$Limit;
+extern uint32_t __ospi1_cs0_zero_nocache$$Base;
+extern uint32_t __ospi1_cs0_zero_nocache$$Limit;
+extern uint32_t __ospi1_cs0_zero$$Base;
+extern uint32_t __ospi1_cs0_zero$$Limit;
+extern uint32_t __itcm_zero$$Base;
+extern uint32_t __itcm_zero$$Limit;
+extern uint32_t __dtcm_zero$$Base;
+extern uint32_t __dtcm_zero$$Limit;
+extern uint32_t __ram_zero_nocache$$Base;
+extern uint32_t __ram_zero_nocache$$Limit;
+extern uint32_t __ram_zero$$Base;
+extern uint32_t __ram_zero$$Limit;
+static const bsp_init_zero_info_t zero_list[] =
+{
+  {.p_base = &__sdram_zero_nocache$$Base, .p_limit = &__sdram_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_SDRAM}},
+  {.p_base = &__sdram_zero$$Base, .p_limit = &__sdram_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_SDRAM}},
+  {.p_base = &__ospi0_cs0_zero_nocache$$Base, .p_limit = &__ospi0_cs0_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI0_CS0}},
+  {.p_base = &__ospi0_cs0_zero$$Base, .p_limit = &__ospi0_cs0_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI0_CS0}},
+  {.p_base = &__ospi1_cs0_zero_nocache$$Base, .p_limit = &__ospi1_cs0_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI1_CS0}},
+  {.p_base = &__ospi1_cs0_zero$$Base, .p_limit = &__ospi1_cs0_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI1_CS0}},
+  {.p_base = &__itcm_zero$$Base, .p_limit = &__itcm_zero$$Limit,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_ITCM}},
+  {.p_base = &__dtcm_zero$$Base, .p_limit = &__dtcm_zero$$Limit,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_DTCM}},
+  {.p_base = &__ram_zero_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}},
+  {.p_base = &__ram_zero$$Base, .p_limit = &__ram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}}
+};
+/* Load initialization tables */
+extern uint32_t __sdram_from_ospi0_cs1$$Base;
+extern uint32_t __sdram_from_ospi0_cs1$$Limit;
+extern uint32_t __sdram_from_ospi0_cs1$$Load;
+extern uint32_t __sdram_from_ospi1_cs1$$Base;
+extern uint32_t __sdram_from_ospi1_cs1$$Limit;
+extern uint32_t __sdram_from_ospi1_cs1$$Load;
+extern uint32_t __sdram_from_data_flash$$Base;
+extern uint32_t __sdram_from_data_flash$$Limit;
+extern uint32_t __sdram_from_data_flash$$Load;
+extern uint32_t __sdram_from_flash$$Base;
+extern uint32_t __sdram_from_flash$$Limit;
+extern uint32_t __sdram_from_flash$$Load;
+extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Base;
+extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Limit;
+extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Load;
+extern uint32_t __ospi0_cs0_from_ospi1_cs1$$Base;
+extern uint32_t __ospi0_cs0_from_ospi1_cs1$$Limit;
+extern uint32_t __ospi0_cs0_from_ospi1_cs1$$Load;
+extern uint32_t __ospi0_cs0_from_data_flash$$Base;
+extern uint32_t __ospi0_cs0_from_data_flash$$Limit;
+extern uint32_t __ospi0_cs0_from_data_flash$$Load;
+extern uint32_t __ospi0_cs0_from_flash$$Base;
+extern uint32_t __ospi0_cs0_from_flash$$Limit;
+extern uint32_t __ospi0_cs0_from_flash$$Load;
+extern uint32_t __ospi1_cs0_from_ospi0_cs1$$Base;
+extern uint32_t __ospi1_cs0_from_ospi0_cs1$$Limit;
+extern uint32_t __ospi1_cs0_from_ospi0_cs1$$Load;
+extern uint32_t __ospi1_cs0_from_ospi1_cs1$$Base;
+extern uint32_t __ospi1_cs0_from_ospi1_cs1$$Limit;
+extern uint32_t __ospi1_cs0_from_ospi1_cs1$$Load;
+extern uint32_t __ospi1_cs0_from_data_flash$$Base;
+extern uint32_t __ospi1_cs0_from_data_flash$$Limit;
+extern uint32_t __ospi1_cs0_from_data_flash$$Load;
+extern uint32_t __ospi1_cs0_from_flash$$Base;
+extern uint32_t __ospi1_cs0_from_flash$$Limit;
+extern uint32_t __ospi1_cs0_from_flash$$Load;
+extern uint32_t __itcm_from_ospi0_cs1$$Base;
+extern uint32_t __itcm_from_ospi0_cs1$$Limit;
+extern uint32_t __itcm_from_ospi0_cs1$$Load;
+extern uint32_t __itcm_from_ospi1_cs1$$Base;
+extern uint32_t __itcm_from_ospi1_cs1$$Limit;
+extern uint32_t __itcm_from_ospi1_cs1$$Load;
+extern uint32_t __itcm_from_data_flash$$Base;
+extern uint32_t __itcm_from_data_flash$$Limit;
+extern uint32_t __itcm_from_data_flash$$Load;
+extern uint32_t __itcm_from_flash$$Base;
+extern uint32_t __itcm_from_flash$$Limit;
+extern uint32_t __itcm_from_flash$$Load;
+extern uint32_t __dtcm_from_ospi0_cs1$$Base;
+extern uint32_t __dtcm_from_ospi0_cs1$$Limit;
+extern uint32_t __dtcm_from_ospi0_cs1$$Load;
+extern uint32_t __dtcm_from_ospi1_cs1$$Base;
+extern uint32_t __dtcm_from_ospi1_cs1$$Limit;
+extern uint32_t __dtcm_from_ospi1_cs1$$Load;
+extern uint32_t __dtcm_from_data_flash$$Base;
+extern uint32_t __dtcm_from_data_flash$$Limit;
+extern uint32_t __dtcm_from_data_flash$$Load;
+extern uint32_t __dtcm_from_flash$$Base;
+extern uint32_t __dtcm_from_flash$$Limit;
+extern uint32_t __dtcm_from_flash$$Load;
+extern uint32_t __ram_from_ospi0_cs1$$Base;
+extern uint32_t __ram_from_ospi0_cs1$$Limit;
+extern uint32_t __ram_from_ospi0_cs1$$Load;
+extern uint32_t __ram_from_ospi1_cs1$$Base;
+extern uint32_t __ram_from_ospi1_cs1$$Limit;
+extern uint32_t __ram_from_ospi1_cs1$$Load;
+extern uint32_t __ram_from_data_flash$$Base;
+extern uint32_t __ram_from_data_flash$$Limit;
+extern uint32_t __ram_from_data_flash$$Load;
+extern uint32_t __ram_from_flash$$Base;
+extern uint32_t __ram_from_flash$$Limit;
+extern uint32_t __ram_from_flash$$Load;
+static const bsp_init_copy_info_t copy_list[] =
+{
+  {.p_base = &__sdram_from_ospi0_cs1$$Base, .p_limit = &__sdram_from_ospi0_cs1$$Limit, .p_load = &__sdram_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_SDRAM}},
+  {.p_base = &__sdram_from_ospi1_cs1$$Base, .p_limit = &__sdram_from_ospi1_cs1$$Limit, .p_load = &__sdram_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_SDRAM}},
+  {.p_base = &__sdram_from_data_flash$$Base, .p_limit = &__sdram_from_data_flash$$Limit, .p_load = &__sdram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_SDRAM}},
+  {.p_base = &__sdram_from_flash$$Base, .p_limit = &__sdram_from_flash$$Limit, .p_load = &__sdram_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_SDRAM}},
+  {.p_base = &__ospi0_cs0_from_ospi0_cs1$$Base, .p_limit = &__ospi0_cs0_from_ospi0_cs1$$Limit, .p_load = &__ospi0_cs0_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_OSPI0_CS0}},
+  {.p_base = &__ospi0_cs0_from_ospi1_cs1$$Base, .p_limit = &__ospi0_cs0_from_ospi1_cs1$$Limit, .p_load = &__ospi0_cs0_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_OSPI0_CS0}},
+  {.p_base = &__ospi0_cs0_from_data_flash$$Base, .p_limit = &__ospi0_cs0_from_data_flash$$Limit, .p_load = &__ospi0_cs0_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_OSPI0_CS0}},
+  {.p_base = &__ospi0_cs0_from_flash$$Base, .p_limit = &__ospi0_cs0_from_flash$$Limit, .p_load = &__ospi0_cs0_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_OSPI0_CS0}},
+  {.p_base = &__ospi1_cs0_from_ospi0_cs1$$Base, .p_limit = &__ospi1_cs0_from_ospi0_cs1$$Limit, .p_load = &__ospi1_cs0_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_OSPI1_CS0}},
+  {.p_base = &__ospi1_cs0_from_ospi1_cs1$$Base, .p_limit = &__ospi1_cs0_from_ospi1_cs1$$Limit, .p_load = &__ospi1_cs0_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_OSPI1_CS0}},
+  {.p_base = &__ospi1_cs0_from_data_flash$$Base, .p_limit = &__ospi1_cs0_from_data_flash$$Limit, .p_load = &__ospi1_cs0_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_OSPI1_CS0}},
+  {.p_base = &__ospi1_cs0_from_flash$$Base, .p_limit = &__ospi1_cs0_from_flash$$Limit, .p_load = &__ospi1_cs0_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_OSPI1_CS0}},
+  {.p_base = &__itcm_from_ospi0_cs1$$Base, .p_limit = &__itcm_from_ospi0_cs1$$Limit, .p_load = &__itcm_from_ospi0_cs1$$Load,.type={.copy_64 = 1, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_ITCM}},
+  {.p_base = &__itcm_from_ospi1_cs1$$Base, .p_limit = &__itcm_from_ospi1_cs1$$Limit, .p_load = &__itcm_from_ospi1_cs1$$Load,.type={.copy_64 = 1, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_ITCM}},
+  {.p_base = &__itcm_from_data_flash$$Base, .p_limit = &__itcm_from_data_flash$$Limit, .p_load = &__itcm_from_data_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_ITCM}},
+  {.p_base = &__itcm_from_flash$$Base, .p_limit = &__itcm_from_flash$$Limit, .p_load = &__itcm_from_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_ITCM}},
+  {.p_base = &__dtcm_from_ospi0_cs1$$Base, .p_limit = &__dtcm_from_ospi0_cs1$$Limit, .p_load = &__dtcm_from_ospi0_cs1$$Load,.type={.copy_64 = 1, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_DTCM}},
+  {.p_base = &__dtcm_from_ospi1_cs1$$Base, .p_limit = &__dtcm_from_ospi1_cs1$$Limit, .p_load = &__dtcm_from_ospi1_cs1$$Load,.type={.copy_64 = 1, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_DTCM}},
+  {.p_base = &__dtcm_from_data_flash$$Base, .p_limit = &__dtcm_from_data_flash$$Limit, .p_load = &__dtcm_from_data_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_DTCM}},
+  {.p_base = &__dtcm_from_flash$$Base, .p_limit = &__dtcm_from_flash$$Limit, .p_load = &__dtcm_from_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_DTCM}},
+  {.p_base = &__ram_from_ospi0_cs1$$Base, .p_limit = &__ram_from_ospi0_cs1$$Limit, .p_load = &__ram_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_RAM}},
+  {.p_base = &__ram_from_ospi1_cs1$$Base, .p_limit = &__ram_from_ospi1_cs1$$Limit, .p_load = &__ram_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_RAM}},
+  {.p_base = &__ram_from_data_flash$$Base, .p_limit = &__ram_from_data_flash$$Limit, .p_load = &__ram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_RAM}},
+  {.p_base = &__ram_from_flash$$Base, .p_limit = &__ram_from_flash$$Limit, .p_load = &__ram_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAM}}
+};
+/* nocache regions */
+extern uint32_t __sdram_noinit_nocache$$Base;
+extern uint32_t __sdram_noinit_nocache$$Limit;
+extern uint32_t __sdram_zero_nocache$$Base;
+extern uint32_t __sdram_zero_nocache$$Limit;
+extern uint32_t __ospi0_cs0_noinit_nocache$$Base;
+extern uint32_t __ospi0_cs0_noinit_nocache$$Limit;
+extern uint32_t __ospi0_cs0_zero_nocache$$Base;
+extern uint32_t __ospi0_cs0_zero_nocache$$Limit;
+extern uint32_t __ospi1_cs0_noinit_nocache$$Base;
+extern uint32_t __ospi1_cs0_noinit_nocache$$Limit;
+extern uint32_t __ospi1_cs0_zero_nocache$$Base;
+extern uint32_t __ospi1_cs0_zero_nocache$$Limit;
+extern uint32_t __ram_noinit_nocache$$Base;
+extern uint32_t __ram_noinit_nocache$$Limit;
+extern uint32_t __ram_zero_nocache$$Base;
+extern uint32_t __ram_zero_nocache$$Limit;
+static const bsp_mpu_nocache_info_t nocache_list[] =
+{
+  {.p_base = &__sdram_noinit_nocache$$Base, .p_limit = &__sdram_zero_nocache$$Limit},
+  {.p_base = &__ospi0_cs0_noinit_nocache$$Base, .p_limit = &__ospi0_cs0_zero_nocache$$Limit},
+  {.p_base = &__ospi1_cs0_noinit_nocache$$Base, .p_limit = &__ospi1_cs0_zero_nocache$$Limit},
+  {.p_base = &__ram_noinit_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit},
+};
+
+/* initialization data structure */
+const bsp_init_info_t g_init_info =
+{
+    .zero_count  = sizeof(zero_list) / sizeof(zero_list[0]),
+    .p_zero_list = zero_list,
+    .copy_count  = sizeof(copy_list) / sizeof(copy_list[0]),
+    .p_copy_list = copy_list,
+    .nocache_count  = sizeof(nocache_list) / sizeof(nocache_list[0]),
+    .p_nocache_list = nocache_list
+};
+
+#endif   // BSP_LINKER_C
+
+/* UNCRUSTIFY-ON */
--- a/bsp/renesas/ra8p1-titan-board/board/ports/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/SConscript
@@ -0,0 +1,22 @@
+import os
+from building import *
+
+objs = []
+src = []
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+if GetDepend(['BSP_USING_FILESYSTEM']):
+    src += ['drv_filesystem.c']
+
+if GetDepend(['BSP_USING_ETH']):
+    src += ['drv_rtl8211.c']
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
--- a/bsp/renesas/ra8p1-titan-board/board/ports/drv_filesystem.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/drv_filesystem.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     balanceTWK   add sdcard port file
+ * 2021-05-10     Meco Man     fix a bug that cannot use fatfs in the main thread at starting up
+ * 2021-07-28     Meco Man     implement romfs as the root filesystem
+ */
+
+#include <rtthread.h>
+
+#if defined(BSP_USING_FILESYSTEM)
+#include <dfs_romfs.h>
+#include <dfs_fs.h>
+#include <dfs_file.h>
+
+#if DFS_FILESYSTEMS_MAX < 4
+#error "Please define DFS_FILESYSTEMS_MAX more than 4"
+#endif
+#if DFS_FILESYSTEM_TYPES_MAX < 4
+#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4"
+#endif
+
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+#ifdef BSP_USING_FS_AUTO_MOUNT
+#ifdef BSP_USING_SDCARD_FATFS
+static int onboard_sdcard_mount(void)
+{
+    if (dfs_mount("sd", "/sdcard", "elm", 0, 0) == RT_EOK)
+    {
+        LOG_I("SD card mount to '/sdcard'");
+    }
+    else
+    {
+        LOG_E("SD card mount to '/sdcard' failed!");
+        rt_pin_write(0x000D, PIN_LOW);
+    }
+
+    return RT_EOK;
+}
+#endif /* BSP_USING_SDCARD_FATFS */
+#endif /* BSP_USING_FS_AUTO_MOUNT */
+
+#ifdef BSP_USING_FLASH_FS_AUTO_MOUNT
+#ifdef BSP_USING_FLASH_FATFS
+#define FS_PARTITION_NAME "filesystem"
+
+static int onboard_fal_mount(void)
+{
+    /* 初始化 fal 功能 */
+    extern int fal_init(void);
+    extern struct rt_device* fal_mtd_nor_device_create(const char *parition_name);
+    fal_init ();
+    /* 在 ospi flash 中名为 "filesystem" 的分区上创建一个块设备 */
+    struct rt_device *mtd_dev = fal_mtd_nor_device_create (FS_PARTITION_NAME);
+    if (mtd_dev == NULL)
+    {
+        LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
+        return -RT_ERROR;
+    }
+    else
+    {
+        LOG_D("Create a mtd device on the %s partition of flash successful.", FS_PARTITION_NAME);
+    }
+
+    /* 挂载 ospi flash 中名为 "filesystem" 的分区上的文件系统 */
+    if (dfs_mount (FS_PARTITION_NAME, "/fal", "lfs", 0, 0) == 0)
+    {
+        LOG_I("Filesystem initialized!");
+    }
+    else
+    {
+        dfs_mkfs ("lfs", FS_PARTITION_NAME);
+        if (dfs_mount ("filesystem", "/fal", "lfs", 0, 0) == 0)
+        {
+            LOG_I("Filesystem initialized!");
+        }
+        else
+        {
+            LOG_E("Failed to initialize filesystem!");
+            rt_pin_write(0x000D, PIN_LOW);
+        }
+    }
+
+    return RT_EOK;
+}
+#endif /*BSP_USING_FLASH_FATFS*/
+#endif /*BSP_USING_FLASH_FS_AUTO_MOUNT*/
+
+const struct romfs_dirent _romfs_root[] =
+{
+#ifdef BSP_USING_SDCARD_FATFS
+    {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0},
+#endif
+
+#ifdef BSP_USING_FLASH_FATFS
+  { ROMFS_DIRENT_DIR, "fal", RT_NULL, 0 },
+#endif
+        };
+
+const struct romfs_dirent romfs_root =
+{
+ROMFS_DIRENT_DIR, "/", (rt_uint8_t*) _romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])
+};
+
+static int filesystem_mount(void)
+{
+
+#ifdef RT_USING_DFS_ROMFS
+    if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0)
+    {
+        LOG_E("rom mount to '/' failed!");
+    }
+
+    /* 确保块设备注册成功之后再挂载文件系统 */
+    rt_thread_delay(500);
+#endif
+#ifdef BSP_USING_FS_AUTO_MOUNT
+    onboard_sdcard_mount();
+#endif /* BSP_USING_FS_AUTO_MOUNT */
+
+#ifdef BSP_USING_FLASH_FS_AUTO_MOUNT
+    onboard_fal_mount ();
+#endif
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(filesystem_mount);
+#endif /* defined(BSP_USING_FILESYSTEM)*/
--- a/bsp/renesas/ra8p1-titan-board/board/ports/drv_rtl8211.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/drv_rtl8211.c
@@ -0,0 +1,53 @@
+/*
+ * drv_ethernet.c
+ *
+ *  Created on: 2025年7月29日
+ *      Author: RTT
+ */
+#include <rtthread.h>
+#include "hal_data.h"
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef BSP_USING_ETH
+
+void rmac_phy_target_rtl8211_initialize (rmac_phy_instance_ctrl_t * phydev)
+{
+#define RTL_8211F_PAGE_SELECT 0x1F
+#define RTL_8211F_EEELCR_ADDR 0x11
+#define RTL_8211F_LED_PAGE 0xD04
+#define RTL_8211F_LCR_ADDR 0x10
+
+    uint32_t val1, val2 = 0;
+
+    /* switch to led page */
+    R_RMAC_PHY_Write(phydev, RTL_8211F_PAGE_SELECT, RTL_8211F_LED_PAGE);
+
+    /* set led1(green) Link 10/100/1000M, and set led2(yellow) Link 10/100/1000M+Active */
+    R_RMAC_PHY_Read(phydev, RTL_8211F_LCR_ADDR, &val1);
+    val1 |= (1 << 5);
+    val1 |= (1 << 8);
+    val1 &= (~(1 << 9));
+    val1 |= (1 << 10);
+    val1 |= (1 << 11);
+    R_RMAC_PHY_Write(phydev, RTL_8211F_LCR_ADDR, val1);
+
+    /* set led1(green) EEE LED function disabled so it can keep on when linked */
+    R_RMAC_PHY_Read(phydev, RTL_8211F_EEELCR_ADDR, &val2);
+    val2 &= (~(1 << 2));
+    R_RMAC_PHY_Write(phydev, RTL_8211F_EEELCR_ADDR, val2);
+
+    /* switch back to page0 */
+    R_RMAC_PHY_Write(phydev, RTL_8211F_PAGE_SELECT, 0xa42);
+}
+
+bool rmac_phy_target_rtl8211_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl,
+                                                             uint32_t                   line_speed_duplex)
+{
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+    FSP_PARAMETER_NOT_USED(line_speed_duplex);
+
+    /* This PHY-LSI supports half and full duplex mode. */
+    return true;
+}
+#endif
--- a/bsp/renesas/ra8p1-titan-board/board/ports/fal_cfg.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/fal_cfg.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Sherman      the first version
+ */
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include "hal_data.h"
+#include "rtconfig.h"
+
+#define NOR_FLASH_DEV_NAME              "ospi_flash"
+
+extern const struct fal_flash_dev _ospi_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE             \
+{                                       \
+    &_ospi_flash,                       \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/** partition table, The chip flash partition is defined in "\ra\fsp\src\bsp\mcu\ra6m4\bsp_feature.h".
+ * More details can be found in the RA6M4 Group User Manual: Hardware section 47 Flash memory.*/
+#define FAL_PART_TABLE                                                                     \
+{                                                                                          \
+    {FAL_PART_MAGIC_WORD, "whd_firmware", NOR_FLASH_DEV_NAME,         0,     512*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "whd_clm",    NOR_FLASH_DEV_NAME,    512*1024,     512*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "download",   NOR_FLASH_DEV_NAME,   1024*1024,  2*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash",  NOR_FLASH_DEV_NAME, 3*1024*1024,  1*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
+
--- a/bsp/renesas/ra8p1-titan-board/board/ports/gpio_cfg.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/gpio_cfg.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-04-07     kurisaW           first version
+ */
+
+/* Number of IRQ channels on the device */
+#define RA_IRQ_MAX  32
+
+/* PIN to IRQx table */
+#define PIN2IRQX_TABLE(pin)                 \
+{                                           \
+    switch (pin)                            \
+    {                                       \
+    case BSP_IO_PORT_01_PIN_05:             \
+    case BSP_IO_PORT_04_PIN_00:             \
+    case BSP_IO_PORT_08_PIN_06:             \
+    case BSP_IO_PORT_09_PIN_02:             \
+    case BSP_IO_PORT_11_PIN_06:             \
+    case BSP_IO_PORT_12_PIN_14:             \
+        return 0;                           \
+    case BSP_IO_PORT_01_PIN_01:             \
+    case BSP_IO_PORT_01_PIN_04:             \
+    case BSP_IO_PORT_05_PIN_08:             \
+    case BSP_IO_PORT_09_PIN_03:             \
+    case BSP_IO_PORT_11_PIN_07:             \
+    case BSP_IO_PORT_12_PIN_13:             \
+        return 1;                           \
+    case BSP_IO_PORT_01_PIN_00:             \
+    case BSP_IO_PORT_02_PIN_13:             \
+    case BSP_IO_PORT_05_PIN_09:             \
+    case BSP_IO_PORT_07_PIN_12:             \
+    case BSP_IO_PORT_09_PIN_04:             \
+    case BSP_IO_PORT_12_PIN_12:             \
+        return 2;                           \
+    case BSP_IO_PORT_02_PIN_08:             \
+    case BSP_IO_PORT_02_PIN_12:             \
+    case BSP_IO_PORT_05_PIN_10:             \
+    case BSP_IO_PORT_07_PIN_11:             \
+    case BSP_IO_PORT_09_PIN_13:             \
+    case BSP_IO_PORT_12_PIN_11:             \
+        return 3;                           \
+    case BSP_IO_PORT_02_PIN_01:             \
+    case BSP_IO_PORT_03_PIN_00:             \
+    case BSP_IO_PORT_04_PIN_11:             \
+    case BSP_IO_PORT_10_PIN_10:             \
+    case BSP_IO_PORT_12_PIN_10:             \
+        return 4;                           \
+    case BSP_IO_PORT_03_PIN_02:             \
+    case BSP_IO_PORT_04_PIN_10:             \
+    case BSP_IO_PORT_09_PIN_12:             \
+    case BSP_IO_PORT_10_PIN_09:             \
+    case BSP_IO_PORT_12_PIN_09:             \
+        return 5;                           \
+    case BSP_IO_PORT_03_PIN_01:             \
+    case BSP_IO_PORT_04_PIN_09:             \
+    case BSP_IO_PORT_05_PIN_03:             \
+    case BSP_IO_PORT_09_PIN_11:             \
+    case BSP_IO_PORT_10_PIN_08:             \
+        return 6;                           \
+    case BSP_IO_PORT_04_PIN_08:             \
+    case BSP_IO_PORT_05_PIN_04:             \
+    case BSP_IO_PORT_06_PIN_15:             \
+    case BSP_IO_PORT_07_PIN_06:             \
+    case BSP_IO_PORT_09_PIN_10:             \
+        return 7;                           \
+    case BSP_IO_PORT_03_PIN_05:             \
+    case BSP_IO_PORT_04_PIN_15:             \
+    case BSP_IO_PORT_05_PIN_05:             \
+    case BSP_IO_PORT_07_PIN_07:             \
+    case BSP_IO_PORT_09_PIN_05:             \
+    case BSP_IO_PORT_09_PIN_15:             \
+        return 8;                           \
+    case BSP_IO_PORT_03_PIN_04:             \
+    case BSP_IO_PORT_04_PIN_14:             \
+    case BSP_IO_PORT_05_PIN_06:             \
+    case BSP_IO_PORT_09_PIN_06:             \
+    case BSP_IO_PORT_09_PIN_14:             \
+    case BSP_IO_PORT_11_PIN_04:             \
+        return 9;                           \
+    case BSP_IO_PORT_05_PIN_07:             \
+    case BSP_IO_PORT_07_PIN_09:             \
+    case BSP_IO_PORT_09_PIN_07:             \
+    case BSP_IO_PORT_10_PIN_11:             \
+    case BSP_IO_PORT_11_PIN_00:             \
+        return 10;                          \
+    case BSP_IO_PORT_07_PIN_08:             \
+    case BSP_IO_PORT_08_PIN_00:             \
+    case BSP_IO_PORT_08_PIN_07:             \
+    case BSP_IO_PORT_09_PIN_08:             \
+    case BSP_IO_PORT_10_PIN_12:             \
+    case BSP_IO_PORT_11_PIN_02:             \
+        return 11;                          \
+    case BSP_IO_PORT_05_PIN_15:             \
+    case BSP_IO_PORT_07_PIN_15:             \
+    case BSP_IO_PORT_08_PIN_01:             \
+    case BSP_IO_PORT_10_PIN_13:             \
+    case BSP_IO_PORT_11_PIN_01:             \
+        return 12;                          \
+    case BSP_IO_PORT_00_PIN_15:             \
+    case BSP_IO_PORT_05_PIN_14:             \
+    case BSP_IO_PORT_07_PIN_14:             \
+    case BSP_IO_PORT_10_PIN_14:             \
+    case BSP_IO_PORT_11_PIN_03:             \
+        return 13;                          \
+    case BSP_IO_PORT_00_PIN_10:             \
+    case BSP_IO_PORT_00_PIN_13:             \
+    case BSP_IO_PORT_05_PIN_12:             \
+    case BSP_IO_PORT_07_PIN_13:             \
+    case BSP_IO_PORT_08_PIN_04:             \
+    case BSP_IO_PORT_10_PIN_15:             \
+        return 14;                          \
+    case BSP_IO_PORT_00_PIN_12:             \
+    case BSP_IO_PORT_05_PIN_11:             \
+    case BSP_IO_PORT_08_PIN_08:             \
+    case BSP_IO_PORT_08_PIN_13:             \
+    case BSP_IO_PORT_08_PIN_15:             \
+    case BSP_IO_PORT_11_PIN_05:             \
+        return 15;                          \
+    case BSP_IO_PORT_00_PIN_11:             \
+    case BSP_IO_PORT_01_PIN_03:             \
+    case BSP_IO_PORT_01_PIN_06:             \
+    case BSP_IO_PORT_06_PIN_10:             \
+    case BSP_IO_PORT_08_PIN_14:             \
+    case BSP_IO_PORT_10_PIN_07:             \
+        return 16;                          \
+    case BSP_IO_PORT_01_PIN_02:             \
+    case BSP_IO_PORT_06_PIN_11:             \
+    case BSP_IO_PORT_07_PIN_10:             \
+    case BSP_IO_PORT_10_PIN_06:             \
+    case BSP_IO_PORT_13_PIN_07:             \
+        return 17;                          \
+    case BSP_IO_PORT_04_PIN_13:             \
+    case BSP_IO_PORT_06_PIN_12:             \
+    case BSP_IO_PORT_08_PIN_02:             \
+    case BSP_IO_PORT_10_PIN_05:             \
+    case BSP_IO_PORT_13_PIN_06:             \
+        return 18;                          \
+    case BSP_IO_PORT_01_PIN_11:             \
+    case BSP_IO_PORT_06_PIN_13:             \
+    case BSP_IO_PORT_07_PIN_05:             \
+    case BSP_IO_PORT_08_PIN_03:             \
+    case BSP_IO_PORT_10_PIN_04:             \
+    case BSP_IO_PORT_13_PIN_05:             \
+        return 19;                          \
+    case BSP_IO_PORT_01_PIN_10:             \
+    case BSP_IO_PORT_02_PIN_15:             \
+    case BSP_IO_PORT_06_PIN_14:             \
+    case BSP_IO_PORT_08_PIN_09:             \
+    case BSP_IO_PORT_10_PIN_03:             \
+    case BSP_IO_PORT_13_PIN_04:             \
+        return 20;                          \
+    case BSP_IO_PORT_02_PIN_14:             \
+    case BSP_IO_PORT_08_PIN_10:             \
+    case BSP_IO_PORT_10_PIN_01:             \
+    case BSP_IO_PORT_12_PIN_07:             \
+    case BSP_IO_PORT_13_PIN_02:             \
+    case BSP_IO_PORT_13_PIN_03:             \
+        return 21;                          \
+    case BSP_IO_PORT_04_PIN_07:             \
+    case BSP_IO_PORT_06_PIN_08:             \
+    case BSP_IO_PORT_08_PIN_11:             \
+    case BSP_IO_PORT_10_PIN_00:             \
+    case BSP_IO_PORT_12_PIN_06:             \
+    case BSP_IO_PORT_13_PIN_01:             \
+        return 22;                          \
+    case BSP_IO_PORT_01_PIN_09:             \
+    case BSP_IO_PORT_02_PIN_11:             \
+    case BSP_IO_PORT_06_PIN_07:             \
+    case BSP_IO_PORT_08_PIN_12:             \
+    case BSP_IO_PORT_12_PIN_05:             \
+    case BSP_IO_PORT_13_PIN_00:             \
+        return 23;                          \
+    case BSP_IO_PORT_01_PIN_08:             \
+    case BSP_IO_PORT_02_PIN_10:             \
+    case BSP_IO_PORT_05_PIN_00:             \
+    case BSP_IO_PORT_06_PIN_06:             \
+    case BSP_IO_PORT_12_PIN_04:             \
+        return 24;                          \
+    case BSP_IO_PORT_02_PIN_07:             \
+    case BSP_IO_PORT_02_PIN_09:             \
+    case BSP_IO_PORT_05_PIN_01:             \
+    case BSP_IO_PORT_06_PIN_05:             \
+    case BSP_IO_PORT_12_PIN_03:             \
+        return 25;                          \
+    case BSP_IO_PORT_05_PIN_02:             \
+    case BSP_IO_PORT_06_PIN_04:             \
+    case BSP_IO_PORT_07_PIN_04:             \
+    case BSP_IO_PORT_12_PIN_02:             \
+        return 26;                          \
+    case BSP_IO_PORT_00_PIN_14:             \
+    case BSP_IO_PORT_01_PIN_12:             \
+    case BSP_IO_PORT_06_PIN_03:             \
+    case BSP_IO_PORT_12_PIN_01:             \
+        return 27;                          \
+    case BSP_IO_PORT_00_PIN_07:             \
+    case BSP_IO_PORT_01_PIN_13:             \
+    case BSP_IO_PORT_06_PIN_02:             \
+    case BSP_IO_PORT_12_PIN_00:             \
+        return 28;                          \
+    case BSP_IO_PORT_00_PIN_03:             \
+    case BSP_IO_PORT_06_PIN_01:             \
+    case BSP_IO_PORT_06_PIN_09:             \
+    case BSP_IO_PORT_12_PIN_08:             \
+        return 29;                          \
+    case BSP_IO_PORT_04_PIN_05:             \
+    case BSP_IO_PORT_06_PIN_00:             \
+    case BSP_IO_PORT_08_PIN_05:             \
+    case BSP_IO_PORT_12_PIN_15:             \
+        return 30;                          \
+    case BSP_IO_PORT_01_PIN_07:             \
+    case BSP_IO_PORT_04_PIN_06:             \
+    case BSP_IO_PORT_05_PIN_13:             \
+    case BSP_IO_PORT_10_PIN_02:             \
+        return 31;                          \
+    default  :                              \
+        return -1;                          \
+    }                                       \
+}
--- a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/SConscript
@@ -0,0 +1,20 @@
+from building import *
+Import('rtconfig')
+
+src   = []
+cwd   = GetCurrentDir()
+
+# add gt9147 src files.
+if GetDepend('BSP_USING_GT9147'):
+    src += Glob('src/gt9147.c')
+
+if GetDepend('BSP_USING_GT9147_SAMPLE'):
+    src += Glob('samples/gt9147_sample.c')
+
+# add gt9147 include path.
+path  = [cwd + '/inc']
+
+# add src and include to group.
+group = DefineGroup('gt9147', src, depend = ['BSP_USING_GT9147'], CPPPATH = path)
+
+Return('group')
--- a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/inc/gt9147.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/inc/gt9147.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-06-01     tyustli     the first version
+ */
+
+#ifndef __GT9147_H_
+#define __GT9147_H_
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define GTP_ADDR_LENGTH        (2)
+#define GT9147_MAX_TOUCH       (5)
+#define GT9147_POINT_INFO_NUM  (8)
+
+#define GT9147_ADDRESS_HIGH    (0x5D)
+#define GT9147_ADDRESS_LOW     (0x14)
+
+#define GT9147_COMMAND         (0x8040)
+#define GT9147_CONFIG          (0x8047)
+
+#define GT9XX_PRODUCT_ID       (0x8140)
+#define GT9147_READ_STATUS     (0x814E)
+
+#define GT9147_POINT1_REG      (0x814F)
+#define GT9147_POINT2_REG      (0X8157)
+#define GT9147_POINT3_REG      (0X815F)
+#define GT9147_POINT4_REG      (0X8167)
+#define GT9147_POINT5_REG      (0X816F)
+
+#define GT9147_CHECK_SUM       (0X80FF)
+
+int rt_hw_gt9147_init(const char *name, struct rt_touch_config *cfg);
+
+#endif
--- a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/samples/gt9147_sample.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/samples/gt9147_sample.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-06-01     tyustli     the first version
+ */
+
+#include <rtthread.h>
+#include "lcd_port.h"
+#include "gt9147.h"
+
+#define THREAD_PRIORITY   25
+#define THREAD_STACK_SIZE 1024
+#define THREAD_TIMESLICE  5
+
+#define RST_PIN   "P412"
+#define INT_PIN   "P502"
+
+static rt_thread_t  gt9147_thread = RT_NULL;
+static rt_sem_t     gt9147_sem = RT_NULL;
+static rt_device_t  touch_dev = RT_NULL;
+static struct       rt_touch_data *read_data;
+static struct       rt_touch_info info;
+
+static void gt9147_entry(void *parameter)
+{
+    rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_INFO, &info);
+
+    read_data = (struct rt_touch_data *)rt_malloc(sizeof(struct rt_touch_data) * info.point_num);
+
+    while (1)
+    {
+        rt_sem_take(gt9147_sem, RT_WAITING_FOREVER);
+
+        if (rt_device_read(touch_dev, 0, read_data, info.point_num) == info.point_num)
+        {
+            for (rt_uint8_t i = 0; i < info.point_num; i++)
+            {
+                if (read_data[i].event == RT_TOUCH_EVENT_DOWN || read_data[i].event == RT_TOUCH_EVENT_MOVE)
+                {
+                    rt_kprintf("%d %d %d %d %d\n", read_data[i].track_id,
+                               read_data[i].x_coordinate,
+                               read_data[i].y_coordinate,
+                               read_data[i].timestamp,
+                               read_data[i].width);
+                }
+            }
+        }
+        rt_device_control(touch_dev, RT_TOUCH_CTRL_ENABLE_INT, RT_NULL);
+    }
+}
+
+static rt_err_t rx_callback(rt_device_t touch_dev, rt_size_t size)
+{
+    rt_sem_release(gt9147_sem);
+    rt_device_control(touch_dev, RT_TOUCH_CTRL_DISABLE_INT, RT_NULL);
+    return 0;
+}
+
+/* Test function */
+int gt9147_sample()
+{
+    void *id;
+    int x = LCD_WIDTH;
+    int y = LCD_HEIGHT;
+
+    struct rt_touch_config cfg;
+    rt_base_t int_pin = rt_pin_get(INT_PIN);
+    rt_base_t rst_pin = rt_pin_get(RST_PIN);
+
+    cfg.dev_name = "i2c0";
+    cfg.irq_pin.pin = int_pin;
+    cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN;
+    cfg.user_data = &rst_pin;
+
+    rt_hw_gt9147_init("gt9147", &cfg);
+
+    touch_dev = rt_device_find("gt9147");
+    if (touch_dev == RT_NULL)
+    {
+        rt_kprintf("can't find gt9147 device!\n");
+        return -1;
+    }
+
+    if (rt_device_open(touch_dev, RT_DEVICE_FLAG_INT_RX) != RT_EOK)
+    {
+        rt_kprintf("open device failed!");
+        return -1;
+    }
+
+    id = rt_malloc(sizeof(struct rt_touch_info));
+    rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_ID, id);
+    rt_uint8_t * read_id = (rt_uint8_t *)id;
+    rt_kprintf("id = GT%d%d%d%d \n", read_id[0] - '0', read_id[1] - '0', read_id[2] - '0', read_id[3] - '0');
+
+    rt_device_control(touch_dev, RT_TOUCH_CTRL_SET_X_RANGE, &x);  /* if possible you can set your x y coordinate*/
+    rt_device_control(touch_dev, RT_TOUCH_CTRL_SET_Y_RANGE, &y);
+    rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_INFO, id);
+    rt_kprintf("range_x = %d \n", (*(struct rt_touch_info*)id).range_x);
+    rt_kprintf("range_y = %d \n", (*(struct rt_touch_info*)id).range_y);
+    rt_kprintf("point_num = %d \n", (*(struct rt_touch_info*)id).point_num);
+    rt_free(id);
+
+    gt9147_sem = rt_sem_create("dsem", 0, RT_IPC_FLAG_FIFO);
+    if (gt9147_sem == RT_NULL)
+    {
+        rt_kprintf("create dynamic semaphore failed.\n");
+        return -1;
+    }
+
+    rt_device_set_rx_indicate(touch_dev, rx_callback);
+
+    gt9147_thread = rt_thread_create("gt9147",
+                                     gt9147_entry,
+                                     RT_NULL,
+                                     THREAD_STACK_SIZE,
+                                     THREAD_PRIORITY,
+                                     THREAD_TIMESLICE);
+
+    if (gt9147_thread != RT_NULL)
+        rt_thread_startup(gt9147_thread);
+
+    return 0;
+}
+MSH_CMD_EXPORT(gt9147_sample, gt9147_sample);
--- a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/src/gt9147.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/src/gt9147.c
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/SConscript
@@ -0,0 +1,13 @@
+import os
+from building import *
+
+src = []
+objs = []
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+src = Glob('*.c')
+
+objs = DefineGroup('Drivers', src, depend = ['BSP_USING_OSPI_FLASH'], CPPPATH = CPPPATH)
+
+Return('objs')
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/drv_ospi_flash.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/drv_ospi_flash.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-07-09     [Your Name]  First version for Renesas RA series OSPI flash
+ */
+
+#include <rtthread.h>
+#include "hal_data.h"
+#include "ospi_b_ep.h"
+
+#ifdef BSP_USING_OSPI_FLASH
+#include "fal.h"
+
+#define LOG_TAG                "drv.ospi_flash"
+#include <drv_log.h>
+
+/* Flash device configuration */
+#define RENESAS_FLASH_START_ADDRESS    OSPI_B_CS1_START_ADDRESS
+#define RENESAS_FLASH_SIZE             (64 * 1024 * 1024) /* 64MB for W35T51NW flash */
+#define RENESAS_FLASH_SECTOR_SIZE      OSPI_B_SECTOR_SIZE_4K /* 4KB sectors */
+#define RENESAS_FLASH_END_ADDRESS      (RENESAS_FLASH_START_ADDRESS + RENESAS_FLASH_SIZE)
+
+/**
+ * @brief Read data from OSPI flash in XIP mode.
+ * @note This operation reads data directly from the memory-mapped address.
+ *
+ * @param offset Offset from the flash start address
+ * @param buf Buffer to store read data
+ * @param size Number of bytes to read
+ *
+ * @return Number of bytes read, or negative error code
+ */
+static int renesas_flash_read(long offset, rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_uint32_t addr = RENESAS_FLASH_START_ADDRESS + offset;
+
+    if ((addr + size) > RENESAS_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+#if defined(__DCACHE_PRESENT)
+    // Invalidate cache for the read region to ensure data consistency
+    SCB_InvalidateDCache_by_Addr((uint32_t *)addr, size);
+#endif
+    /* Directly read from memory-mapped address in XIP mode */
+    rt_memcpy(buf, (void *)addr, size);
+
+    return (int)size;
+}
+
+/**
+ * @brief Write data to OSPI flash using low-level API.
+ *
+ * @param offset Offset from the flash start address
+ * @param buf The write data buffer
+ * @param size Number of bytes to write
+ *
+ * @return Number of bytes written, or negative error code
+ */
+static int renesas_flash_write(long offset, const rt_uint8_t *buf, rt_uint32_t size)
+{
+    fsp_err_t err;
+    rt_uint32_t addr = RENESAS_FLASH_START_ADDRESS + offset;
+    rt_uint32_t remaining = size;
+    rt_uint8_t *p_buf = (rt_uint8_t *)buf;
+    const rt_uint32_t chunk_size = 4; // Fixed 4-byte write size
+
+    // Input validation
+    if (!buf || size == 0)
+    {
+        LOG_E("Invalid input: buf=%p, size=%u", buf, size);
+        return -RT_EINVAL;
+    }
+
+    if ((addr + size) > RENESAS_FLASH_END_ADDRESS)
+    {
+        LOG_E("Write out of range: addr=0x%08x, size=%u", addr, size);
+        return -RT_EINVAL;
+    }
+
+    // Write data in 4-byte chunks
+    while (remaining > 0)
+    {
+        // Calculate current chunk size (up to 4 bytes or remaining bytes)
+        rt_uint32_t current_size = (remaining >= chunk_size) ? chunk_size : remaining;
+
+        // Perform write operation
+        err = R_OSPI_B_Write(&g_ospi_b_ctrl, p_buf, (uint8_t *)addr, current_size);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("OSPI write failed: addr=0x%08x, size=%u, error=%d", addr, current_size, err);
+            return -RT_ERROR;
+        }
+
+#if defined(__DCACHE_PRESENT)
+        // Clean and invalidate cache for the written region
+        SCB_CleanInvalidateDCache_by_Addr((uint32_t *)addr, current_size);
+#endif
+
+        // Wait for write operation to complete
+        err = ospi_b_wait_operation(OSPI_B_TIME_WRITE);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("OSPI wait failed: addr=0x%08x, error=%d", addr, err);
+            return -RT_ERROR;
+        }
+
+        // Update address, buffer pointer, and remaining bytes
+        addr += current_size;
+        p_buf += current_size;
+        remaining -= current_size;
+    }
+
+    return (int)size;
+}
+
+/**
+ * @brief Erase data on OSPI flash using low-level API.
+ * @note Erases in 4KB sectors, using OSPI_B_APP_ADDRESS for sector alignment.
+ *
+ * @param offset Offset from the flash start address
+ * @param size Number of bytes to erase
+ *
+ * @return Number of bytes erased, or negative error code
+ */
+static int renesas_flash_erase(long offset, rt_uint32_t size)
+{
+    fsp_err_t err;
+    rt_uint32_t addr = RENESAS_FLASH_START_ADDRESS + offset;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t sector_count;
+    rt_uint32_t sector_no;
+
+    if (end_addr > RENESAS_FLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)end_addr);
+        return -RT_EINVAL;
+    }
+
+    /* Calculate starting sector and number of sectors to erase */
+    sector_no = offset / RENESAS_FLASH_SECTOR_SIZE;
+    sector_count = (size + RENESAS_FLASH_SECTOR_SIZE - 1) / RENESAS_FLASH_SECTOR_SIZE; /* Ceiling division */
+
+    for (rt_uint32_t i = 0; i < sector_count; i++)
+    {
+        rt_uint32_t sector_addr = (rt_uint32_t)OSPI_B_APP_ADDRESS(sector_no + i);
+
+        /* Perform sector erase */
+        err = R_OSPI_B_Erase(&g_ospi_b_ctrl, (uint8_t *)sector_addr, RENESAS_FLASH_SECTOR_SIZE);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("OSPI erase failed at addr 0x%08x, error code: %d", sector_addr, err);
+            return -RT_ERROR;
+        }
+
+        /* Wait for erase completion */
+        err = ospi_b_wait_operation(OSPI_B_TIME_ERASE_4K);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("OSPI wait operation failed for sector %d, error code: %d", sector_no + i, err);
+            return -RT_ERROR;
+        }
+    }
+
+    return (int)size;
+}
+
+/**
+ * @brief Initialize the OSPI flash driver for FAL.
+ * @note This function should be called during system initialization.
+ *
+ * @return RT_EOK on success, or negative error code
+ */
+int _flash_init(void)
+{
+    fsp_err_t err;
+    uint32_t flash_id = 0;
+
+    /* Initialize OSPI module and flash device */
+    err = ospi_b_init();
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("OSPI initialization failed, error code: %d", err);
+        return -RT_ERROR;
+    }
+
+    err = ospi_b_set_protocol_to_opi();
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("ospi_b_set_protocol_to_opi API FAILED: %d", err);
+        return -RT_ERROR;
+    }
+
+    err = ospi_b_read_device_id(&flash_id);
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("ospi_b_read_device_id FAILED: %d", err);
+        return -RT_ERROR;
+    }
+
+    LOG_I("Get flash id: 0x%08x", flash_id);
+
+    LOG_I("OSPI flash initialized successfully");
+
+    return RT_EOK;
+}
+
+/* FAL flash device table */
+const struct fal_flash_dev _ospi_flash =
+{
+    .name = "ospi_flash",
+    .addr = RENESAS_FLASH_START_ADDRESS,
+    .len = RENESAS_FLASH_SIZE,
+    .blk_size = RENESAS_FLASH_SECTOR_SIZE,
+    .ops = {
+        .init = _flash_init, /* Initialization handled by ospi_b_init in main application */
+        .read = renesas_flash_read,
+        .write = renesas_flash_write,
+        .erase = renesas_flash_erase
+    }
+};
+
+#endif /* BSP_USING_OSPI_FLASH */
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.c
@@ -0,0 +1,221 @@
+/***********************************************************************************************************************
+ * File Name    : ospi_b_commands.c
+ * Description  : Contains function definition.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2023 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+
+#include "ospi_b_commands.h"
+#include "ospi_b_ep.h"
+
+/*******************************************************************************************************************//**
+ * @addtogroup ospi_b_commands.c
+ * @{
+ **********************************************************************************************************************/
+
+spi_flash_direct_transfer_t g_ospi_b_direct_transfer [OSPI_B_TRANSFER_MAX] =
+{
+ /* Transfer structure for SPI mode */
+    [OSPI_B_TRANSFER_WRITE_ENABLE_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_ENABLE_SPI,
+    .address        = OSPI_B_ADDRESS_DUMMY,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_ZERO,
+    .data_length    = OSPI_B_DATA_LENGTH_ZERO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_SPI
+    },
+    [OSPI_B_TRANSFER_WRITE_CFR2V_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_REGISTER_SPI,
+    .address        = OSPI_B_ADDRESS_CFR2V_REGISTER,
+    .data           = OSPI_B_DATA_CFR2V_REGISTER,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_SPI
+    },
+    [OSPI_B_TRANSFER_WRITE_CFR3V_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_REGISTER_SPI,
+    .address        = OSPI_B_ADDRESS_CFR3V_REGISTER,
+    .data           = OSPI_B_DATA_CFR3V_REGISTER,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_SPI
+    },
+    [OSPI_B_TRANSFER_WRITE_CFR5V_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_REGISTER_SPI,
+    .address        = OSPI_B_ADDRESS_CFR5V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_SPI
+    },
+    [OSPI_B_TRANSFER_READ_STATUS_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_STATUS_SPI,
+    .address        = OSPI_B_ADDRESS_DUMMY,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_ZERO,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_STATUS_SPI
+    },
+    [OSPI_B_TRANSFER_READ_CFR2V_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_REGISTER_SPI,
+    .address        = OSPI_B_ADDRESS_CFR2V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_REGISTER_SPI
+    },
+    [OSPI_B_TRANSFER_READ_CFR3V_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_REGISTER_SPI,
+    .address        = OSPI_B_ADDRESS_CFR3V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_REGISTER_SPI
+    },
+    [OSPI_B_TRANSFER_READ_CFR5V_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_REGISTER_SPI,
+    .address        = OSPI_B_ADDRESS_CFR5V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_ONE,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_REGISTER_SPI
+    },
+    [OSPI_B_TRANSFER_READ_DEVICE_ID_SPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_DEVICE_ID_SPI,
+    .address        = OSPI_B_ADDRESS_DUMMY,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_SPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_ZERO,
+    .data_length    = OSPI_B_DATA_LENGTH_FOUR,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_STATUS_SPI
+    },
+
+    /* Transfer structure for OPI mode */
+    [OSPI_B_TRANSFER_WRITE_ENABLE_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_ENABLE_OPI,
+    .address        = OSPI_B_ADDRESS_DUMMY,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_ZERO,
+    .data_length    = OSPI_B_DATA_LENGTH_ZERO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_OPI
+    },
+    [OSPI_B_TRANSFER_WRITE_CFR2V_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_REGISTER_OPI,
+    .address        = OSPI_B_ADDRESS_CFR2V_REGISTER,
+    .data           = OSPI_B_DATA_CFR2V_REGISTER,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_OPI
+    },
+    [OSPI_B_TRANSFER_WRITE_CFR3V_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_REGISTER_OPI,
+    .address        = OSPI_B_ADDRESS_CFR3V_REGISTER,
+    .data           = OSPI_B_DATA_CFR3V_REGISTER,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_OPI
+    },
+    [OSPI_B_TRANSFER_WRITE_CFR5V_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_WRITE_REGISTER_OPI,
+    .address        = OSPI_B_ADDRESS_CFR5V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_WRITE_OPI
+    },
+    [OSPI_B_TRANSFER_READ_STATUS_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_STATUS_OPI,
+    .address        = OSPI_B_ADDRESS_DUMMY,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_STATUS_OPI
+    },
+    [OSPI_B_TRANSFER_READ_CFR2V_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_REGISTER_OPI,
+    .address        = OSPI_B_ADDRESS_CFR2V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_REGISTER_OPI
+    },
+    [OSPI_B_TRANSFER_READ_CFR3V_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_REGISTER_OPI,
+    .address        = OSPI_B_ADDRESS_CFR3V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_REGISTER_OPI
+    },
+    [OSPI_B_TRANSFER_READ_CFR5V_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_REGISTER_OPI,
+    .address        = OSPI_B_ADDRESS_CFR5V_REGISTER,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_FOUR,
+    .data_length    = OSPI_B_DATA_LENGTH_TWO,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_REGISTER_OPI
+    },
+    [OSPI_B_TRANSFER_READ_DEVICE_ID_OPI] =
+    {
+    .command        = OSPI_B_COMMAND_READ_DEVICE_ID_OPI,
+    .address        = OSPI_B_ADDRESS_DUMMY,
+    .data           = OSPI_B_DATA_DUMMY,
+    .command_length = OSPI_B_COMMAND_LENGTH_OPI,
+    .address_length = OSPI_B_ADDRESS_LENGTH_ZERO,
+    .data_length    = OSPI_B_DATA_LENGTH_FOUR,
+    .dummy_cycles   = OSPI_B_DUMMY_CYCLE_READ_STATUS_OPI
+    },
+};
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ospi_b_commands.c)
+ **********************************************************************************************************************/
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.h
@@ -0,0 +1,108 @@
+/***********************************************************************************************************************
+ * File Name    : ospi_b_commands.h
+ * Description  : Contains data structures and functions used in ospi_commands.h
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2023 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+
+#ifndef OSPI_B_COMMANDS_H_
+#define OSPI_B_COMMANDS_H_
+
+#include "hal_data.h"
+
+/* Macro for OSPI command code */
+#define OSPI_B_COMMAND_WRITE_ENABLE_SPI             (0x06)
+#define OSPI_B_COMMAND_WRITE_ENABLE_OPI             (0x0606)
+#define OSPI_B_COMMAND_WRITE_REGISTER_SPI           (0x71)
+#define OSPI_B_COMMAND_WRITE_REGISTER_OPI           (0x7171)
+#define OSPI_B_COMMAND_READ_STATUS_SPI              (0x05)
+#define OSPI_B_COMMAND_READ_STATUS_OPI              (0x0505)
+#define OSPI_B_COMMAND_READ_REGISTER_SPI            (0x65)
+#define OSPI_B_COMMAND_READ_REGISTER_OPI            (0x6565)
+#define OSPI_B_COMMAND_READ_DEVICE_ID_SPI           (0x9E)
+#define OSPI_B_COMMAND_READ_DEVICE_ID_OPI           (0x9E9E)
+
+/* Macro for OSPI command length */
+#define OSPI_B_COMMAND_LENGTH_SPI                   (1U)
+#define OSPI_B_COMMAND_LENGTH_OPI                   (2U)
+
+/* Macro for OSPI transfer address */
+#define OSPI_B_ADDRESS_DUMMY                        (0U)
+#define OSPI_B_ADDRESS_LENGTH_ZERO                  (0U)
+#define OSPI_B_ADDRESS_LENGTH_THREE                 (3U)
+#define OSPI_B_ADDRESS_LENGTH_FOUR                  (4U)
+
+/* Macro for OSPI transfer data */
+#define OSPI_B_DATA_DUMMY                           (0U)
+#define OSPI_B_DATA_LENGTH_ZERO                     (0U)
+#define OSPI_B_DATA_LENGTH_ONE                      (1U)
+#define OSPI_B_DATA_LENGTH_TWO                      (2U)
+#define OSPI_B_DATA_LENGTH_THREE                    (3U)
+#define OSPI_B_DATA_LENGTH_FOUR                     (4U)
+
+/* Macro for OSPI transfer dummy cycles */
+#define OSPI_B_DUMMY_CYCLE_WRITE_SPI                (0U)
+#define OSPI_B_DUMMY_CYCLE_WRITE_OPI                (0U)
+#define OSPI_B_DUMMY_CYCLE_READ_STATUS_SPI          (0U)
+#define OSPI_B_DUMMY_CYCLE_READ_STATUS_OPI          (8U)
+#define OSPI_B_DUMMY_CYCLE_READ_REGISTER_SPI        (0U)
+#define OSPI_B_DUMMY_CYCLE_READ_REGISTER_OPI        (8U)
+#define OSPI_B_DUMMY_CYCLE_READ_MEMORY_SPI          (8U)
+#define OSPI_B_DUMMY_CYCLE_READ_MEMORY_OPI          (16U)
+
+/* Macro for flash device register address */
+#define OSPI_B_ADDRESS_STR1V_REGISTER               (0x00800000)
+#define OSPI_B_ADDRESS_STR2V_REGISTER               (0x00800001)
+#define OSPI_B_ADDRESS_CFR1V_REGISTER               (0x00800002)
+#define OSPI_B_ADDRESS_CFR2V_REGISTER               (0x00800003)
+#define OSPI_B_ADDRESS_CFR3V_REGISTER               (0x00800004)
+#define OSPI_B_ADDRESS_CFR4V_REGISTER               (0x00800005)
+#define OSPI_B_ADDRESS_CFR5V_REGISTER               (0x00800006)
+
+/* Macros for configure flash device */
+#define OSPI_B_DATA_CFR2V_REGISTER                  (0x83)
+#define OSPI_B_DATA_CFR3V_REGISTER                  (0x40)
+#define OSPI_B_DATA_SET_SPI_CFR5V_REGISTER          (0x40)
+#define OSPI_B_DATA_SET_OPI_CFR5V_REGISTER          (0x43)
+
+typedef enum e_ospi_b_transfer
+{
+    OSPI_B_TRANSFER_WRITE_ENABLE_SPI = 0,
+    OSPI_B_TRANSFER_WRITE_CFR2V_SPI,
+    OSPI_B_TRANSFER_WRITE_CFR3V_SPI,
+    OSPI_B_TRANSFER_WRITE_CFR5V_SPI,
+    OSPI_B_TRANSFER_READ_STATUS_SPI,
+    OSPI_B_TRANSFER_READ_CFR2V_SPI,
+    OSPI_B_TRANSFER_READ_CFR3V_SPI,
+    OSPI_B_TRANSFER_READ_CFR5V_SPI,
+    OSPI_B_TRANSFER_READ_DEVICE_ID_SPI,
+
+    OSPI_B_TRANSFER_WRITE_ENABLE_OPI,
+    OSPI_B_TRANSFER_WRITE_CFR2V_OPI,
+    OSPI_B_TRANSFER_WRITE_CFR3V_OPI,
+    OSPI_B_TRANSFER_WRITE_CFR5V_OPI,
+    OSPI_B_TRANSFER_READ_STATUS_OPI,
+    OSPI_B_TRANSFER_READ_CFR2V_OPI,
+    OSPI_B_TRANSFER_READ_CFR3V_OPI,
+    OSPI_B_TRANSFER_READ_CFR5V_OPI,
+    OSPI_B_TRANSFER_READ_DEVICE_ID_OPI,
+    OSPI_B_TRANSFER_MAX
+} ospi_b_transfer_t;
+
+#endif /* OSPI_B_COMMANDS_H_ */
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.c
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.h
@@ -0,0 +1,114 @@
+/***********************************************************************************************************************
+ * File Name    : ospi_b_ep.h
+ * Description  : Contains data structures and functions used in ospi_ep.h.
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2023 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+
+#ifndef OSPI_B_EP_H_
+#define OSPI_B_EP_H_
+
+/* Macro for flash device */
+#define OSPI_B_DEVICE_ID                    (0x21A5BEF)    // For W35T51NW flash  //(0x0F1A5B34)    // For S28HS512T flash
+#define OSPI_B_DEVICE_HL_ID                 (0x21A5BEF)    // For W35T51NW flash  //(0x0F1A5A34)    // For S28HL512T flash
+#define OSPI_B_MANUFACTURER_ID              (0xEF)         // For W35T51NW flash  //(0x34)          // For S28HL512T flash
+#define OSPI_B_DEVICE_ID_TYPE               (0x5B)         // For S28HS512T flash
+#define OSPI_B_DEVICE_HL_ID_TYPE            (0x5A)         // For S28HL512T flash
+#define OSPI_B_DEVICE_ID_DENSITY            (0x1A)
+
+/* Flash device sector size */
+#define OSPI_B_SECTOR_SIZE_4K               (0x1000)
+#define OSPI_B_SECTOR_SIZE_256K             (0x40000)
+#define OSPI_B_SECTOR_SIZE_512K             (0x80000)
+#define OSPI_B_SECTOR_4K_END_ADDRESS        (0x9001FFFF)
+
+/* Flash device timing */
+#define OSPI_B_TIME_UNIT                    (BSP_DELAY_UNITS_MICROSECONDS)
+#define OSPI_B_TIME_RESET_SETUP             (2U)             //  Type 50ns
+#define OSPI_B_TIME_RESET_PULSE             (1000U)          //  Type 500us
+#define OSPI_B_TIME_ERASE_256K              (1500000U)       //  Type 256KB sector is 331 KBps -> Type 0.773s
+#define OSPI_B_TIME_ERASE_4K                (100000U)        //  Type 4KB sector is 95 KBps -> Type 0.042s
+#define OSPI_B_TIME_WRITE                   (10000U)         //  Type 256B page (4KB/256KB) is 595/533 KBps -> Type
+
+/* Flash device status bit */
+#define OSPI_B_WEN_BIT_MASK                 (0x00000002)
+#define OSPI_B_BUSY_BIT_MASK                (0x00000001)
+
+/* Flash device address space mapping */
+#define OSPI_B_CS0_START_ADDRESS            (0x80000000)
+#define OSPI_B_CS1_START_ADDRESS            (0x90000000)
+#define OSPI_B_APP_ADDRESS(sector_no)       ((uint8_t *)(OSPI_B_CS1_START_ADDRESS + ((sector_no) * OSPI_B_SECTOR_SIZE_4K)))
+#define OSPI_B_SECTOR_FIRST                 (0U)
+#define OSPI_B_SECTOR_SECOND                (1U)
+#define OSPI_B_SECTOR_THREE                 (2U)
+#define OSPI_B_SECTOR_FOUR                  (3U)
+#define OSPI_B_SECTOR_FIVE                  (4U)
+#define OSPI_B_SECTOR_SIX                   (5U)
+#define OSPI_B_SECTOR_SEVEN                 (6U)
+#define OSPI_B_SECTOR_EIGHT                 (7U)
+#define OSPI_B_APP_DATA_SIZE                (64U)
+
+/* Macro for RTT Viewer handle */
+#define RTT_SELECT_SPI_MODE_CHAR            ('1')
+#define RTT_SELECT_OPI_MODE_CHAR            ('2')
+#define RTT_SELECT_DMA_SPI_MODE_CHAR        ('3')
+#define RTT_SELECT_DMA_OPI_MODE_CHAR        ('4')
+#define RTT_SELECT_WRITE_OPERATION_CHAR     ('1')
+#define RTT_SELECT_READ_OPERATION_CHAR      ('2')
+#define RTT_SELECT_ERASE_OPERATION_CHAR     ('3')
+#define RTT_EXIT_SUB_MENU_CHAR              ('4')
+#define RTT_NULL_CHAR                       ('\0')
+#define RTT_CHECK_INDEX                     (0U)
+
+#define MAIN_MENU           "\r\nOSPI Main Menu, Protocol Mode Option:"\
+                            "\r\n1. SPI 1S-1S-1S Protocol Mode"\
+                            "\r\n2. OPI 8D-8D-8D Protocol Mode"\
+                            "\r\nProtocol Mode Select: \r\n"
+
+#define SUB_MENU            "\r\nOSPI Sub Menu, %s Operation Option:"\
+                            "\r\n1. Write Operation"\
+                            "\r\n2. Read Operation"\
+                            "\r\n3. Erase Operation"\
+                            "\r\n4. Go Back To Main menu"\
+                            "\r\nOperation Select: \r\n"
+
+#define EP_INFO             "\r\nThis example project demonstrates basic functionalities of OSPI driver\r\n"\
+                            "on Renesas RA MCUs based on Renesas FSP. Based on the User input, EP performs\r\n"\
+                            "read/write/erase operation in SPI mode (1S-1S-1S) or DOPI mode (8D-8D-8D).\r\n"\
+                            "On successful completion of each operation, success message will be printed\r\n"\
+                            "on RTT viewer. Error and info messages will be printed on JlinkRTTViewer.\r\n\n"
+
+#define RESET_VALUE         (0x00)
+
+typedef enum {
+    flash_write,
+    flash_read,
+    flash_erase
+} flash_opration_t;
+
+/* function declarations*/
+fsp_err_t ospi_b_init (void);
+fsp_err_t ospi_b_set_protocol_to_spi (void);
+fsp_err_t ospi_b_set_protocol_to_opi (void);
+//fsp_err_t ospi_b_operation (uint8_t * p_address);
+fsp_err_t ospi_b_operation (uint8_t *p_address, flash_opration_t operation);
+fsp_err_t ospi_b_read_device_id (uint32_t * const p_id);
+fsp_err_t timer_init (void);
+
+#endif /* OSPI_B_EP_H_ */
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/SConscript
@@ -0,0 +1,13 @@
+import os
+from building import *
+
+src = []
+objs = []
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+src = Glob('*.c')
+
+objs = DefineGroup('Drivers', src, depend = ['BSP_USING_OSPI_RAM'], CPPPATH = CPPPATH)
+
+Return('objs')
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.c
@@ -0,0 +1,199 @@
+#include <string.h>
+#include <inttypes.h>
+#include "hal_data.h"
+#include "hyper_ram_test.h"
+#include <rtthread.h>
+
+#define DBG_TAG "hyperram"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+#define ram_cfg  g_ospi1_cfg
+#define ram_ctrl g_ospi1_ctrl
+
+#define OSPI_OM_RESET           BSP_IO_PORT_12_PIN_07
+#define HYPER_RAM_RESET_DELAY() R_BSP_SoftwareDelay(10UL, BSP_DELAY_UNITS_MICROSECONDS)
+
+#define HYPER_RAM_CFG_REG_0_ADDRESS (0x01000000)
+#define HYPER_RAM_CFG_REG_1_ADDRESS (0x01000001)
+
+ospi_b_xspi_command_set_t g_hyper_ram_commands[] = {
+    {
+        .protocol = SPI_FLASH_PROTOCOL_8D_8D_8D,
+        .frame_format = OSPI_B_FRAME_FORMAT_XSPI_PROFILE_2_EXTENDED,
+        .latency_mode = OSPI_B_LATENCY_MODE_FIXED,
+        .command_bytes = OSPI_B_COMMAND_BYTES_1,
+        .address_bytes = SPI_FLASH_ADDRESS_BYTES_4,
+
+        .read_command = 0xA0,
+        .read_dummy_cycles = 11,
+        .program_command = 0x20,
+        .program_dummy_cycles = 11,
+
+        .address_msb_mask = 0xF0,
+        .status_needs_address = false,
+
+        .p_erase_commands = NULL,
+    }
+};
+
+uint16_t swap16(uint16_t value)
+{
+    uint16_t ret;
+    ret = value << 8;
+    ret |= value >> 8;
+    return ret;
+}
+
+static fsp_err_t hyper_ram_config_get(uint32_t address, uint16_t * const p_value_out)
+{
+    spi_flash_direct_transfer_t xfer = {
+        .address = address,
+        .address_length = 4,
+        .command_length = 2,
+        .command = 0xE000,
+        .data_length = 2,
+        .dummy_cycles = 11,
+    };
+
+    fsp_err_t err = R_OSPI_B_DirectTransfer(&ram_ctrl, &xfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("HyperRAM config get failed!");
+        return err;
+    }
+
+    *p_value_out = (uint16_t)xfer.data;
+
+    return FSP_SUCCESS;
+}
+
+static fsp_err_t hyper_ram_config_set(uint32_t address, uint16_t value)
+{
+    spi_flash_direct_transfer_t xfer = {
+        .address = address,
+        .address_length = 4,
+        .command = 0x6000,
+        .command_length = 2,
+        .data = (uint16_t)value,
+        .data_length = 2,
+        .dummy_cycles = 0,
+    };
+
+    fsp_err_t err = R_OSPI_B_DirectTransfer(&ram_ctrl, &xfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("HyperRAM config set failed!");
+        return err;
+    }
+
+    return FSP_SUCCESS;
+}
+
+
+/* Define the static array at address 0x70000000 using section attribute */
+#define TEST_SIZE 8388608 // 32MB (8M x 4 bytes)
+static uint32_t test_array[TEST_SIZE] __attribute__((section(".ospi1_cs0_noinit")));
+
+void hyper_ram_test(void)
+{
+    const uint32_t test_bytes = TEST_SIZE * 4; // Total bytes: 32MB
+    uint32_t errors = 0;
+    rt_tick_t start_time, end_time;
+    uint32_t write_speed_kbs, read_speed_kbs;
+    uint32_t write_time_ms, read_time_ms;
+
+    /* Write pattern to RAM and measure time */
+    start_time = rt_tick_get();
+    for (uint32_t i = 0; i < TEST_SIZE; i++)
+    {
+        test_array[i] = i ^ 0xA5A5A5A5; // Use XOR pattern for better error detection
+    }
+    end_time = rt_tick_get();
+
+    /* Calculate write speed in KB/s and time in ms */
+    write_time_ms = (end_time - start_time) * 1000 / RT_TICK_PER_SECOND;
+    if (write_time_ms > 0)
+    {
+        write_speed_kbs = (test_bytes / 1024) / write_time_ms * 1000; // KB/s
+    }
+    else
+    {
+        write_speed_kbs = 0; // Avoid division by zero
+    }
+
+    /* Verify written pattern while measuring read time */
+    start_time = rt_tick_get();
+    for (uint32_t i = 0; i < TEST_SIZE; i++)
+    {
+        uint32_t expected = i ^ 0xA5A5A5A5;
+        uint32_t actual = test_array[i];
+        if (actual != expected)
+        {
+            errors++;
+//            rt_kprintf("errors:%d actual:%d\n", errors, actual);
+        }
+    }
+    end_time = rt_tick_get();
+
+    /* Calculate read speed in KB/s and time in ms */
+    read_time_ms = (end_time - start_time) * 1000 / RT_TICK_PER_SECOND;
+    if (read_time_ms > 0)
+    {
+        read_speed_kbs = (test_bytes / 1024) / read_time_ms * 1000; // KB/s
+    }
+    else
+    {
+        read_speed_kbs = 0; // Avoid division by zero
+    }
+
+    /* Print test results */
+    if (errors == 0)
+    {
+        LOG_I("Hyper RAM test passed successfully!");
+    }
+    else
+    {
+        LOG_E("Hyper RAM test failed with %u errors", errors);
+    }
+
+    /* Print read and write speeds as integers */
+    LOG_I("Write speed: %u KB/s (%u ms)", write_speed_kbs, write_time_ms);
+    LOG_I("Read speed: %u KB/s (%u ms)", read_speed_kbs, read_time_ms);
+}
+MSH_CMD_EXPORT(hyper_ram_test, hyper_ram_test);
+
+int hyper_ram_init(void)
+{
+    /* Change OM_RESET back to normal IO mode. */
+    R_IOPORT_PinCfg(&g_ioport_ctrl,
+                    OSPI_OM_RESET,
+                    IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_DRIVE_HIGH | IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_HIGH);
+
+    /* Pin reset the OctaFlash */
+    R_BSP_PinWrite(OSPI_OM_RESET, BSP_IO_LEVEL_LOW);
+    HYPER_RAM_RESET_DELAY();
+    R_BSP_PinWrite(OSPI_OM_RESET, BSP_IO_LEVEL_HIGH);
+    HYPER_RAM_RESET_DELAY();
+
+    /* Open the interface and immediately transition to 8D-8D-8D mode */
+    R_OSPI_B_Open((spi_flash_ctrl_t *)&ram_ctrl, &ram_cfg);
+    R_OSPI_B_SpiProtocolSet(&ram_ctrl, SPI_FLASH_PROTOCOL_8D_8D_8D);
+
+    R_XSPI1->LIOCFGCS_b[0].WRMSKMD = 1;
+
+    uint16_t cfg_reg0 = 0;
+    hyper_ram_config_get(HYPER_RAM_CFG_REG_0_ADDRESS, &cfg_reg0);
+    LOG_D("Read CR0 value: 0x%x", swap16(cfg_reg0));
+
+    uint16_t value0 = 0x8f1d;
+    hyper_ram_config_set(HYPER_RAM_CFG_REG_0_ADDRESS, swap16(value0));
+    LOG_D("Set CR0 to 0x%x", value0);
+
+    cfg_reg0 = 0;
+    hyper_ram_config_get(HYPER_RAM_CFG_REG_0_ADDRESS, &cfg_reg0);
+    LOG_D("Read CR0 value: 0x%x", swap16(cfg_reg0));
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(hyper_ram_init);
--- a/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.h
@@ -0,0 +1,7 @@
+
+#ifndef HYPER_RAM_TEST_H_
+#define HYPER_RAM_TEST_H_
+
+void hyper_ram_test(void);
+
+#endif
--- a/bsp/renesas/ra8p1-titan-board/board/ports/lcd_port.h
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/lcd_port.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2018-07-28     liu2guang      the first version for STM32F469NI-Discovery.
+ */
+
+#ifndef __DRV_LCD_H_
+#define __DRV_LCD_H_
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+
+typedef enum
+{
+    ROTATION_ZERO = 0,
+    ROTATION_090 = 90,
+    ROTATION_180 = 180,
+    ROTATION_270 = 270,
+} bsp_rotation;
+
+#define LCD_WIDTH               DISPLAY_HSIZE_INPUT0
+#define LCD_HEIGHT              DISPLAY_VSIZE_INPUT0
+#define LCD_BITS_PER_PIXEL      DISPLAY_BITS_PER_PIXEL_INPUT1
+#define LCD_PIXEL_FORMAT        RTGRAPHIC_PIXEL_FORMAT_RGB565
+#define LCD_BUF_SIZE            (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
+
+#define LCD_XSTRIDE_PHYS        (((DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0 * LCD_BITS_PER_PIXEL + 0x1FF) & 0xFFFFFE00) / LCD_BITS_PER_PIXEL)
+#define LCD_NUM_FRAMEBUFFERS    (2)
+
+#define LCD_BL_PIN              BSP_USING_LCD_BL_PIN
+#define LCD_RST_PIN             BSP_USING_LCD_RST_PIN
+
+#endif
--- a/bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/SConscript
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/SConscript
@@ -0,0 +1,13 @@
+import os
+from building import *
+
+src = []
+objs = []
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+src = Glob('*.c')
+
+objs = DefineGroup('Drivers', src, depend = ['BSP_USING_MIPI_LCD'], CPPPATH = CPPPATH)
+
+Return('objs')
--- a/bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/mipi_config.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/mipi_config.c
@@ -0,0 +1,133 @@
+#include <rtthread.h>
+
+#if (defined(BSP_USING_LCD)) || (defined(SOC_SERIES_R7FA8M85))
+#include <lcd_port.h>
+#include "hal_data.h"
+
+#define DRV_DEBUG
+#define LOG_TAG             "mipi_cfg"
+#include <drv_log.h>
+
+#define MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG      ((mipi_dsi_cmd_id_t) 0xFE)
+#define MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE    ((mipi_dsi_cmd_id_t) 0xFD)
+
+typedef struct
+{
+    unsigned char        size;
+    unsigned char        buffer[50];
+    mipi_dsi_cmd_id_t    cmd_id;
+    mipi_dsi_cmd_flag_t flags;
+} lcd_table_setting_t;
+
+volatile static bool g_message_sent = false;
+volatile static mipi_dsi_phy_status_t g_phy_status;
+
+const lcd_table_setting_t g_lcd_init_focuslcd[] =
+{
+    // 480*800 冠显
+    {4,     {0x99, 0x71, 0x02, 0xa2},   MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {4,     {0x99, 0x71, 0x02, 0xa3},   MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {4,     {0x99, 0x71, 0x02, 0xa4},   MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+
+    {2,     {0xA4, 0x31},   MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},   // 2Lanes
+
+    {8,     {0xB0, 0x22, 0x57, 0x1E, 0x61, 0x2F, 0x57, 0x61},   MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},   // VGH_VGL  (14v)
+
+    {3,     {0xB7, 0x64, 0x64},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},  //Source  (5v)
+
+    {3,     {0xBF, 0xB4, 0xB4},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},  //VCOM  (-2v)
+
+    // Gamma----(5V)
+    {38,     {0xC8, 0x00, 0x00, 0x0F, 0x1C, 0x34, 0x00, 0x60, 0x03, 0xA0, 0x06, 0x10, 0xFE, 0x06, 0x74, 0x03, 0x21, 0xC4, 0x00, 0x08, 0x00, 0x22, 0x46, 0x0F, 0x8F, 0x0A, 0x32, 0xF2, 0x0C, 0x42, 0x0C, 0xF3, 0x80, 0x00, 0xAB, 0xC0, 0x03, 0xC4},  MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {38,     {0xC9, 0x00, 0x00, 0x0F, 0x1C, 0x34, 0x00, 0x60, 0x03, 0xA0, 0x06, 0x10, 0xFE, 0x06, 0x74, 0x03, 0x21, 0xC4, 0x00, 0x08, 0x00, 0x22, 0x46, 0x0F, 0x8F, 0x0A, 0x32, 0xF2, 0x0C, 0x42, 0x0C, 0xF3, 0x80, 0x00, 0xAB, 0xC0, 0x03, 0xC4},  MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    // Gamma----(5.5V)
+    {38,     {0xC8, 0x00, 0x00, 0x13, 0x24, 0x44, 0x00, 0x74, 0x03, 0xB8, 0x04, 0x11, 0x16, 0x08, 0x86, 0x04, 0x21, 0xD3, 0x02, 0x10, 0x0F, 0x22, 0x4D, 0x0E, 0x90, 0x09, 0x32, 0xF0, 0x0B, 0x40, 0x0E, 0xF3, 0x7D, 0x0E, 0xA9, 0xBF, 0x03, 0xC4}, MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {38,     {0xC9, 0x00, 0x00, 0x13, 0x24, 0x44, 0x00, 0x74, 0x03, 0xB8, 0x04, 0x11, 0x16, 0x08, 0x86, 0x04, 0x21, 0xD3, 0x02, 0x10, 0x0F, 0x22, 0x4D, 0x0E, 0x90, 0x09, 0x32, 0xF0, 0x0B, 0x40, 0x0E, 0xF3, 0x7D, 0x0E, 0xA9, 0xBF, 0x03, 0xC4}, MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    // GIP
+    {7,     {0xD7, 0x10, 0x2A, 0x28, 0x19, 0x90, 0x90},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},  // 800
+
+    {33,     {0xA3, 0x51, 0x03, 0x80, 0xCF, 0x44, 0x00, 0x00, 0x00, 0x00, 0x04, 0x78, 0x78, 0x00, 0x1A, 0x00, 0x45, 0x05, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x02, 0x20, 0x52, 0x00, 0x05, 0x00, 0x00, 0xFF},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {44,     {0xA6, 0x02, 0x00, 0x24, 0x55, 0x35, 0x00, 0x38, 0x00, 0x78, 0x78, 0x00, 0x24, 0x55, 0x36, 0x00, 0x37, 0x00, 0x78, 0x78, 0x02, 0xAC, 0x51, 0x3A, 0x00, 0x00, 0x00, 0x78, 0x78, 0x03, 0xAC, 0x21, 0x00, 0x04, 0x00, 0x00, 0x78, 0x78, 0x3e, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {48,     {0xA7, 0x19, 0x19, 0x00, 0x64, 0x40, 0x07, 0x16, 0x40, 0x00, 0x04, 0x03, 0x78, 0x78, 0x00, 0x64, 0x40, 0x25, 0x34, 0x00, 0x00, 0x02, 0x01, 0x78, 0x78, 0x00, 0x64, 0x40, 0x4B, 0x5A, 0x00, 0x00, 0x02, 0x01, 0x78, 0x78, 0x00, 0x24, 0x40, 0x69, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x78, 0x00, 0x44},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {37,     {0xAC, 0x08, 0x0A, 0x11, 0x00, 0x13, 0x03, 0x1B, 0x18, 0x06, 0x1A, 0x19, 0x1B, 0x1B, 0x1B, 0x18, 0x1B, 0x09, 0x0B, 0x10, 0x02, 0x12, 0x01, 0x1B, 0x18, 0x06, 0x1A, 0x19, 0x1B, 0x1B, 0x1B, 0x18, 0x1B, 0xFF, 0x67, 0xFF, 0x67, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+
+    {8,     {0xAD, 0xCC, 0x40, 0x46, 0x11, 0x04, 0x78, 0x78},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+    {15,    {0xE8, 0x30, 0x07, 0x00, 0x94, 0x94, 0x9C, 0x00, 0xE2, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEF},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+
+    {33,    {0xE7, 0x8B, 0x3C, 0x00, 0x0C, 0xF0, 0x5D, 0x00, 0x5D, 0x00, 0x5D, 0x00, 0x5D, 0x00, 0xFF, 0x00, 0x08, 0x7B, 0x00, 0x00, 0xC8, 0x6A, 0x5A, 0x08, 0x1A, 0x3C, 0x00, 0x81, 0x01, 0xCC, 0x01, 0x7F, 0xF0, 0x22},  MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
+
+    {2,     {0x11, 0x00},  MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},  //Sleep out
+    {120,    {0},                                   MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG, (mipi_dsi_cmd_flag_t)0},
+    {2,     {0x29, 0x00},  MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},  //display on
+    {2,     {0x35, 0x00},  MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},  //TE off
+
+    {0x00,  {0},                                    MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE, (mipi_dsi_cmd_flag_t)0},
+};
+
+void mipi_dsi0_callback(mipi_dsi_callback_args_t *p_args)
+{
+    switch (p_args->event)
+    {
+    case MIPI_DSI_EVENT_SEQUENCE_0:
+    {
+        if (MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED == p_args->tx_status)
+        {
+            g_message_sent = true;
+        }
+        break;
+    }
+    case MIPI_DSI_EVENT_PHY:
+    {
+        g_phy_status |= p_args->phy_status;
+        break;
+    }
+    default:
+    {
+        break;
+    }
+    }
+}
+
+static void mipi_dsi_push_table(const lcd_table_setting_t *table)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    const lcd_table_setting_t *p_entry = table;
+
+    while (MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE != p_entry->cmd_id)
+    {
+        mipi_dsi_cmd_t msg =
+        {
+            .channel = 0,
+            .cmd_id = p_entry->cmd_id,
+            .flags = p_entry->flags,
+            .tx_len = p_entry->size,
+            .p_tx_buffer = p_entry->buffer,
+        };
+
+        if (MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG == msg.cmd_id)
+        {
+            R_BSP_SoftwareDelay (table->size, BSP_DELAY_UNITS_MILLISECONDS);
+        }
+        else
+        {
+            g_message_sent = false;
+            /* Send a command to the peripheral device */
+            err = R_MIPI_DSI_Command(&g_mipi_dsi0_ctrl, &msg);
+            if (err != FSP_SUCCESS)
+            {
+                LOG_E("R_MIPI_DSI_Command error\n");
+            }
+            /* Wait */
+            while (!g_message_sent);
+        }
+        p_entry++;
+    }
+}
+
+void ra8_mipi_lcd_init(void)
+{
+    mipi_dsi_push_table(g_lcd_init_focuslcd);
+    LOG_D("initialize mipi dsi configs\n");
+}
+
+#endif
--- a/bsp/renesas/ra8p1-titan-board/board/ra8_it.c
+++ b/bsp/renesas/ra8p1-titan-board/board/ra8_it.c
@@ -0,0 +1,3 @@
+#include <rtthread.h>
+#include "hal_data.h"
+
--- a/bsp/renesas/ra8p1-titan-board/buildinfo.gpdsc
+++ b/bsp/renesas/ra8p1-titan-board/buildinfo.gpdsc
@@ -0,0 +1,157 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+  <vendor>Renesas</vendor>
+  <name>Project Content</name>
+  <description>Project content managed by the Renesas Smart Configurator</description>
+  <url/>
+  <releases>
+    <release version="1.0.0"/>
+  </releases>
+  <generators>
+    <generator id="Renesas RA Smart Configurator">
+      <project_files>
+        <file category="include" name="src/"/>
+        <file category="source" name="src/hal_entry.c"/>
+      </project_files>
+    </generator>
+  </generators>
+  <components generator="Renesas RA Smart Configurator">
+    <component Cclass="Flex Software" Cgroup="Components" Csub="ra">
+      <files>
+        <file category="include" name="ra/arm/CMSIS_6/CMSIS/Core/Include/"/>
+        <file category="include" name="ra/fsp/inc/"/>
+        <file category="include" name="ra/fsp/inc/api/"/>
+        <file category="include" name="ra/fsp/inc/instances/"/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h" path=""/>
+        <file category="other" name="ra/arm/CMSIS_6/LICENSE"/>
+        <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/fsp_common_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_exceptions.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_ipc.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_ipc.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_macl.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_macl.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mmf.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h" path=""/>
+        <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
+        <file category="source" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c"/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Build Configuration">
+      <files>
+        <file category="include" name="ra_cfg/fsp_cfg/"/>
+        <file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h" path=""/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Generated Data">
+      <files>
+        <file category="include" name="ra_gen/"/>
+        <file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
+        <file category="source" name="ra_gen/common_data.c"/>
+        <file category="header" name="ra_gen/common_data.h" path=""/>
+        <file category="source" name="ra_gen/hal_data.c"/>
+        <file category="header" name="ra_gen/hal_data.h" path=""/>
+        <file category="source" name="ra_gen/main.c"/>
+        <file category="source" name="ra_gen/pin_data.c"/>
+        <file category="source" name="ra_gen/vector_data.c"/>
+        <file category="header" name="ra_gen/vector_data.h" path=""/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Linker Script">
+      <files>
+        <file category="linkerScript" name="script/fsp.scat"/>
+      </files>
+    </component>
+  </components>
+</package>
--- a/Show More
+++ b/Show More