AT32UC3A: Implement initial BSP support for SimpleMachines' Mizar32-B (#8186)

bsp/avr32/at32uc3a0256/Kconfig

@@ -0,0 +1,136 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config ENV_DIR
+    string
+    option env="ENV_ROOT"
+    default "/"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+menu "Hardware Drivers Config"
+
+config SOC_AVR32
+    bool
+    default y
+
+choice
+    prompt "Select BSP board"
+    default BSP_BOARD_MIZAR32B
+
+    config BSP_BOARD_MIZAR32B
+        bool "Mizar32-B"
+endchoice
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_PIN
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        select RT_USING_SERIAL
+        default y
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            if BSP_USING_UART0
+                choice
+                    prompt "uart0 tx pin number (GP)"
+                    depends on BSP_USING_UART0
+                    default BSP_UART0_TX_PIN_43
+                    config BSP_UART0_TX_PIN_19
+                        bool "19"
+                    config BSP_UART0_TX_PIN_43
+                        bool "43"
+                endchoice
+                config BSP_UART0_TX_PIN
+                    int
+                    default 19 if BSP_UART0_TX_PIN_19
+                    default 43 if BSP_UART0_TX_PIN_43
+                config BSP_UART0_TX_PIN_FUNCTION
+                    int
+                    default 0 if BSP_UART0_TX_PIN_19
+                    default 2 if BSP_UART0_TX_PIN_43
+                choice
+                    prompt "uart0 rx pin number (GP)"
+                    depends on BSP_USING_UART0
+                    default BSP_UART0_RX_PIN_42
+                    config BSP_UART0_RX_PIN_18
+                        bool "18"
+                    config BSP_UART0_RX_PIN_42
+                        bool "42"
+                endchoice
+                config BSP_UART0_RX_PIN
+                    int
+                    default 18 if BSP_UART0_RX_PIN_18
+                    default 42 if BSP_UART0_RX_PIN_42
+		config BSP_UART0_RX_PIN_FUNCTION
+		    int
+		    default 0 if BSP_UART0_RX_PIN_18
+		    default 2 if BSP_UART0_RX_PIN_42
+            endif
+
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+            if BSP_USING_UART1
+                choice
+                    prompt "uart1 tx pin number (GP)"
+                    depends on BSP_USING_UART1
+                    default BSP_UART1_TX_PIN_6
+                    config BSP_UART1_TX_PIN_6
+                        bool "6"
+                    config BSP_UART1_TX_PIN_95
+                        bool "95"
+                endchoice
+                config BSP_UART1_TX_PIN
+                    int
+                    default 6 if BSP_UART1_TX_PIN_6
+                    default 95 if BSP_UART1_TX_PIN_95
+		config BSP_UART1_TX_PIN_FUNCTION
+		    int
+		    default 0 if BSP_UART1_TX_PIN_6
+		    default 1 if BSP_UART1_TX_PIN_95
+                choice
+                    prompt "uart1 rx pin number (GP)"
+                    depends on BSP_USING_UART1
+                    default BSP_UART1_RX_PIN_5
+                    config BSP_UART1_RX_PIN_5
+                        bool "5"
+                    config BSP_UART1_RX_PIN_96
+                        bool "96"
+                endchoice
+                config BSP_UART1_RX_PIN
+                    int
+                    default 5 if BSP_UART1_RX_PIN_5
+                    default 96 if BSP_UART1_RX_PIN_96
+                 config BSP_UART1_RX_PIN_FUNCTION
+                    int
+                    default 0 if BSP_UART1_RX_PIN_5
+                    default 1 if BSP_UART1_RX_PIN_96
+            endif
+        endif
+endmenu
+endmenu

bsp/avr32/at32uc3a0256/README.md

@@ -0,0 +1,171 @@
+# SimpleMachines' Mizar32 Development Board
+
+## Introduction
+
+The Mizar32 is a 32-bit computer based on the AVR32 processor. It is
+clocked at 66MHz and has 32MB of main memory. It supports mass storage
+on SD card, a USB connector, an on-board LED, two buttons, a JTAG port
+and six bus connectors.
+
+![board-snap](figures/board-snap.png)
+
+The bus connectors let you add other stackable hardware modules such
+as serial ports, ethernet, a 16x2 character LCD display and a
+VGA/keyboard/mouse/audio board based on the 8-core Parallax Propeller
+processor.
+
+The Mizar32 is designed by SimpleMachines, Italy.
+
+This board support package aims at adding RT-Thread support for the
+following Mizar32 development boards.
+
+| Model     | Flash | SRAM | SDRAM |
+| --------- | ----- | ---- | ----  |
+| Mizar32-A | 512KB | 64KB | 32MB  |
+| Mizar32-B | 256KB | 64KB | 32MB  |
+| Mizar32-C | 128KB | 64KB | 32MB  |
+
+## Specification
+
+- Main processor: AVR32 UC3A0 @ 66 MHz
+- Internal fast SRAM: 32KB or 64KB with single-cycle access time
+- On-board SDRAM: 32MB with 2-cycle access time
+- Internal Flash memory: 128/256/512KB with single-cycle access time
+- External Flash memory: up to 4GB on micro SD card.
+- Internal operating Voltage: 3.3V with 5V input tolerant I/O
+- Digital I/O Pins: 66
+- Timer/Counter: 3 channel, 16-bit.
+- Analog-to-Digital input pins: 8 with 10-bit resolution measuring 0-3.3v at up to 384,000 samples per second
+- Stereo audio bitstream Digital-to-Analog Converter with 16 bit resolution at up to 48kHz
+- Pulse Width Modulation channels (PWM): 7
+- Universal Sync/Async RX/TX (USART): 2
+- Serial Periperal Interface (SPI): 2
+- Two-Wire Interface (TWI): 1, I2C-compatible at up to 400kbit/s
+- Universal Serial Bus (USB): 1 OTG host with dedicated cable.
+- Debug Port: JTAG connector
+- Ethernet MAC 10/100: 1 (requires add-on hardware module)
+- Oscillators: 2 (12MHz and 32768Hz)
+- Buttons: Reset button, user button
+- LEDs: Power LED, User LED
+- Power supply: 5V USB or 7.5V-35V DC, 80mA (base board) to 222mA (with all add-on modules)
+- Dimensions: 96,5mm x 63,5mm
+- Weight: 42.5 grams
+- Temperature range: -45 to +85°C
+
+## Embedded Hardware Interfaces
+
+- MicroSD
+- USB
+- JTAG
+- Add-on bus connectors 1-6 interfaces on the Add-on Bus
+- 12 General Purpose I/O pins
+- 2 UARTs: one basic, one with modem control signals
+- 2 SPI
+- I2C interface with 2-way splitter
+- 8 ADC inputs
+- 3 high-resolution timers
+- Ethernet
+
+## Optional Stacked Modules
+
+![Ethernet and Real Time Clock](figures/Mizar32_Ethernet_RTC_Module.jpg)
+
+![16x2 I2C LCD Module](figures/Mizar32_I2C_LCD_Module.jpg)
+
+![RS-232/RS-485 Module](figures/Mizar32_RS_232_485_Module.jpg)
+
+![VGA Output, PS/2 Input, Audio Output](figures/Mizar32_VGA_Propeller_Module.jpg)
+
+![PHT Prototype Board](figures/Mizar32_Protoboard_PHT.jpg)
+
+![SMD Prototype Board](figures/Mizar32_Protoboard_SMD.jpg)
+
+This README is essentially a work-in-progress. I will try to further
+and documentation as and when I further the device driver base for the
+Mizar32 target.
+
+If you feel like reaching out to me for questions pertaining to the
+target development board, you can write to me: ramangopalan AT gmail
+dot com.
+
+## Supported compiler
+
+This BSP is built with the AVR32 GCC that comes with the Microchip
+Studio. I am using the Microchip Studio version 7.0.2594. Make sure
+that avr32-gcc.exe is visible on your command line. Add the binary
+directory to you PATH.
+
+![env-windows-avr32-gcc](figures/env-windows-avr32-gcc.png)
+
+I use Git Bash (Windows) for compiling the RT-Thread system. Once you
+set your path correctly, invoke Git Bash to query avr32-gcc.exe's
+version. The output should look similar to this:
+
+```bash
+$ avr32-gcc.exe --version
+avr32-gcc.exe (AVR_32_bit_GNU_Toolchain_3.4.2_435) 4.4.7
+Copyright (C) 2010 Free Software Foundation, Inc.
+This is free software; see the source for copying conditions.  There is NO
+warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+```
+
+If you see this, you're all set to compile RT-Thread for Mizar32.
+
+## Program firmware
+
+### Step 1: download the RT-Thread codebase and navigate to bsp/avr32uc3a0.
+
+```bash
+$ cd bsp/avr32uc3a0/
+```
+
+### Step 2: build
+
+```bash
+scons -c
+scons
+```
+
+### Step 3: flash
+
+If everything went well, scons should have generated an elf file:
+rtthread-uc3a0256.elf. Let us program the file. The program 'atprogram'
+comes with Microchip Studio. I didn't have to do much here. Just make sure
+`atprogram.exe' is in your PATH.
+
+```bash
+atprogram -t atmelice -i jtag -d at32uc3a0256 program -f rtthread-uc3a0256.elf
+```
+
+Note that you should already see the on-board LED (PB29) blink if your
+programming was successful. I use the Atmel ICE programmer. To access
+msh with the default menuconfig's configuration, you'll need the VGA
+shield. Connect the target board to a 12 VDC wall adapter. Also
+connect the shield to a VGA monitor and a PS/2 keyboard.
+
+## Running Result
+
+The output information on serial port for `ps' the command should look like this:
+
+```bash
+0x000003c0 tidle0    31  ready   0x00000054 0x00000100    67%   0x00000009 OK
+0x00001650 tshell    20  running 0x000000b4 0x00001000    13%   0x0000000a OK
+0x00001350 led1       5  suspend 0x0000007c 0x00000400    12%   0x00000005 EINTRPT
+```
+
+Here is a picture of the RT-Thread session on the VGA monitor:
+
+![RT-Thread VGA Session on Mizar32](figures/mizar32-vga-out.jpg)
+
+## Peripheral Support
+
+| Drive | Support | Remark  |
+| ----- | ------- | ------- |
+| UART  | Support | UART0/1 |
+| GPIO  | Support | -       |
+| I2C   | -       | -       |
+| RTC   | -       | -       |
+| SPI   | -       | -       |
+| TIMER | -       | -       |
+| WDT   | -       | -       |
+

bsp/avr32/at32uc3a0256/SConscript

@@ -0,0 +1,11 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+src_bsp = ['application.c', 'startup.c', 'board.c']
+
+src = File(src_bsp)
+CPPPATH = [RTT_ROOT + '/bsp/avr32']
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/avr32/at32uc3a0256/SConstruct

@@ -5,7 +5,7 @@ import rtconfig
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
@@ -27,7 +27,10 @@ Export('rtconfig')
 objs = PrepareBuilding(env, RTT_ROOT)
 
 # AVR32 software framework building script
-objs = objs + SConscript(RTT_ROOT + '/bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript', variant_dir='bsp/SOFTWARE_FRAMEWORK', duplicate=0)
+objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/software_framework/SConscript', variant_dir='build/software_framework', duplicate=0)
+
+# Driver abstractions
+objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/drivers/SConscript', variant_dir='build/drivers/', duplicate=0)
 
 # make a building
 DoBuilding(TARGET, objs)

bsp/avr32/at32uc3a0256/application.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author           Notes
+ * 2010-03-30     Kyle             First version
+ * 2023-10-25     Raman Gopalan    AT32UC3A: Access GPIO using RT's pin abstractions
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "compiler.h"
+#include "gpio.h"
+
+/* Mizar32's built-in LED */
+#define USER_LED_1    AVR32_PIN_PB29
+
+char thread_led1_stack[1024];
+struct rt_thread thread_led1;
+static void rt_thread_entry_led1(void* parameter)
+{
+    rt_pin_mode(USER_LED_1, PIN_MODE_OUTPUT);
+    while (1)
+    {
+        rt_pin_write(USER_LED_1, 1);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
+
+        rt_pin_write(USER_LED_1, 0);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+    }
+}
+
+int rt_application_init()
+{
+    /* create led1 thread */
+    rt_thread_init(&thread_led1,
+                   "led1",
+                   rt_thread_entry_led1,
+                   RT_NULL,
+                   &thread_led1_stack[0],
+                   sizeof(thread_led1_stack), 5, 5);
+    rt_thread_startup(&thread_led1);
+
+    return 0;
+}

bsp/avr32/at32uc3a0256/avr32elf_uc3a0256.lds

@@ -0,0 +1,211 @@
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32",
+          "elf32-avr32")
+OUTPUT_ARCH(avr32:uc)
+ENTRY(_start)
+SEARCH_DIR("/home/mingwbuild/mingwavr32/avr32/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+MEMORY
+{
+    FLASH (rxai!w) : ORIGIN = 0x80002000, LENGTH = 256K
+    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
+    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
+    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
+}
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
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+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :
+  {
+    _stack = .;
+    *(.stack)
+    . = _stack_size;
+    _estack = .;
+  } >CPUSRAM
+  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
+  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

bsp/avr32/at32uc3a0256/rtconfig.h

@@ -0,0 +1,248 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+
+/* RT-Thread Components */
+
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* Memory management */
+
+
+/* Memory protection */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers Config */
+
+#define SOC_AVR32
+#define BSP_BOARD_MIZAR32B
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_PIN
+#define BSP_USING_UART
+#define BSP_USING_UART1
+#define BSP_UART1_TX_PIN_6
+#define BSP_UART1_TX_PIN 6
+#define BSP_UART1_TX_PIN_FUNCTION 0
+#define BSP_UART1_RX_PIN_5
+#define BSP_UART1_RX_PIN 5
+#define BSP_UART1_RX_PIN_FUNCTION 0
+
+#endif

bsp/avr32/at32uc3a0256/rtconfig.py

@@ -0,0 +1,61 @@
+import os
+
+# toolchains options
+ARCH     = 'avr32'
+CPU      = 'uc3'
+PART     = 'uc3a0256'
+BOARD    = 'USERBOARD'
+ATOMICS  = ' -D__STDC_NO_ATOMICS__'
+
+CROSS_TOOL 	= 'gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'C:/Program Files (x86)/Atmel/AVR Tools/AVR Toolchain/bin'
+elif CROSS_TOOL == 'keil':
+    print('================ERROR============================')
+    print('Not support keil yet!')
+    print('=================================================')
+    exit(0)
+elif CROSS_TOOL == 'iar':
+    print('================ERROR============================')
+    print('Not support iar yet!')
+    print('=================================================')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#BUILD = 'debug'
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'avr32-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mpart=' + PART
+    CFLAGS = DEVICE + ' -DBOARD=' + BOARD + ATOMICS + ' -fmessage-length=0 -ffunction-sections -masm-addr-pseudos'
+    AFLAGS = ' -c -x assembler-with-cpp' + DEVICE
+    LFLAGS = DEVICE + ' -Wl,--gc-sections --rodata-writable -Wl,--direct-data -Lsoftware_framework/utils/libs/newlib_addons -T avr32elf_uc3a0256.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3 -Wall'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O2 -Wall'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/avr32/at32uc3b0256/.config

@@ -22,7 +22,7 @@ CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_IDLE_THREAD_STACK_SIZE=512
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
@@ -36,7 +36,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 # CONFIG_RT_KPRINTF_USING_LONGLONG is not set
 CONFIG_RT_USING_DEBUG=y
 CONFIG_RT_DEBUGING_COLOR=y
-CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_CONTEXT is not set
 # CONFIG_RT_DEBUGING_INIT is not set
 
 #
@@ -223,6 +223,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # CONFIG_RT_USING_MEMBLOCK is not set
 
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
 #
 # RT-Thread Utestcases
 #
@@ -987,6 +993,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # Uncategorized
 #
 
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_AVR32=y
+CONFIG_BSP_BOARD_MCUZONE_AVR32DEV1=y
+
 #
 # On-chip Peripheral Drivers
 #

bsp/avr32/at32uc3b0256/Kconfig

@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../.."
+    default "../../.."
 
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example : default "F:/git_repositories/rt-thread"
@@ -26,6 +26,20 @@ config ENV_DIR
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 
+menu "Hardware Drivers Config"
+
+config SOC_AVR32
+    bool
+    default y
+
+choice
+    prompt "Select BSP board"
+    default BSP_BOARD_MCUZONE_AVR32DEV1
+
+    config BSP_BOARD_MCUZONE_AVR32DEV1
+        bool "MCUZone AVR32DEV1 Kit"
+endchoice
+
 menu "On-chip Peripheral Drivers"
 
     config BSP_USING_PIN
@@ -119,3 +133,4 @@ menu "On-chip Peripheral Drivers"
             endif
         endif
 endmenu
+endmenu

bsp/avr32/at32uc3b0256/SConscript

@@ -0,0 +1,11 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+src_bsp = ['application.c', 'startup.c', 'board.c']
+
+src = File(src_bsp)
+CPPPATH = [RTT_ROOT + '/bsp/avr32']
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/avr32/at32uc3b0256/SConstruct

@@ -0,0 +1,36 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-' + rtconfig.PART + '.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+   AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+   CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+   AR = rtconfig.AR, ARFLAGS = '-rc',
+   LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# AVR32 software framework building script
+objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/software_framework/SConscript', variant_dir='build/software_framework', duplicate=0)
+
+# Driver abstractions
+objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/drivers/SConscript', variant_dir='build/drivers/', duplicate=0)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/avr32/at32uc3b0256/board.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2010-03-30     Kyle            First version
+ * 2023-10-13     Raman Gopalan   Move UART specific code sections into the drv_uart files
+ * 2023-10-20     Raman Gopalan   Initialize GPIO sub-system
+ */
+
+#include <rtthread.h>
+#include "compiler.h"
+#include "pm.h"
+#include "gpio.h"
+#include "usart.h"
+#include "intc.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+
+/**
+ * System tick interrupt handler.
+ */
+static void rt_hw_timer_handler(void)
+{
+    // Clears the interrupt request.
+    Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
+
+    rt_tick_increase();
+}
+
+/**
+ * Initialize system clock and all peripherals.
+ */
+static void peripherals_init(void)
+{
+    /*
+     * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock
+     */
+    pm_freq_param_t pm_freq_param =
+    {
+        .cpu_f = FCPU,
+        .pba_f = FPBA,
+        .osc0_f = FOSC0,
+        .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC
+    };
+    pm_configure_clocks(&pm_freq_param);
+    INTC_init_interrupts();
+}
+
+/**
+ * Initialize CPU cycle counter for system tick.
+ */
+static void cpu_counter_init(void)
+{
+    INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3);
+    Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
+    Set_system_register(AVR32_COUNT, 0);
+}
+
+void rt_hw_board_init(void)
+{
+    Disable_global_interrupt();
+
+    peripherals_init();
+    cpu_counter_init();
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef RT_USING_PIN
+    rt_hw_gpio_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}

bsp/avr32/at32uc3b0256/rtconfig.h

@@ -17,7 +17,7 @@
 #define RT_HOOK_USING_FUNC_PTR
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
+#define IDLE_THREAD_STACK_SIZE 512
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 512
@@ -26,7 +26,6 @@
 
 #define RT_USING_DEBUG
 #define RT_DEBUGING_COLOR
-#define RT_DEBUGING_CONTEXT
 
 /* Inter-Thread communication */
 
@@ -110,6 +109,9 @@
 /* Memory management */
 
 
+/* Memory protection */
+
+
 /* RT-Thread Utestcases */
 
 
@@ -226,6 +228,11 @@
 
 /* Uncategorized */
 
+/* Hardware Drivers Config */
+
+#define SOC_AVR32
+#define BSP_BOARD_MCUZONE_AVR32DEV1
+
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_PIN

bsp/avr32/at32uc3b0256/startup.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-03-30     Kyle         First version
+ */
+
+#include <rtthread.h>
+
+extern void rt_hw_board_init(void);
+extern void rt_application_init(void);
+
+#ifdef RT_USING_FINSH
+extern int finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+int main(void)
+{
+#ifdef RT_USING_HEAP
+    extern void __heap_start__;
+    extern void __heap_end__;
+#endif
+
+    rt_hw_board_init();
+    rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(&__heap_start__, &__heap_end__);
+#endif
+
+    rt_system_scheduler_init();
+    rt_application_init();
+
+#ifdef RT_USING_FINSH
+    /* init finsh */
+    finsh_system_init();
+#if !defined(RT_USING_POSIX_STDIO) && defined(RT_USING_DEVICE)
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+#endif
+
+    rt_thread_idle_init();
+    rt_system_scheduler_start();
+
+    return 0;
+}

bsp/avr32/drivers/SConscript

@@ -0,0 +1,23 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = []
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_uart_v2.c']
+    else:
+        src += ['drv_uart.c']
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/avr32/drivers/drv_gpio.c

@@ -5,19 +5,21 @@
  *
  * Change Logs:
  * Date           Author              Notes
- * 2023-10-18     Raman Gopalan       Initial version
+ * 2023-10-25     Raman Gopalan       Initial version
+ * 2023-11-06     Raman Gopalan       Abstraction for GPIO driver boilerplate
  */
 
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "gpio.h"
 #include <rtdbg.h>
+#include "drv_gpio.h"
 
 #ifdef RT_USING_PIN
 
-static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
+static void at32uc3_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
 {
-    RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
+    RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
     /* Pointer to the register set for this GPIO port */
     volatile avr32_gpio_port_t *gpio_regs = &AVR32_GPIO.port[pin >> 5];
 
@@ -36,7 +38,7 @@ static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t
         gpio_regs->puers = 1 << (pin & 0x1F);
         break;
     case PIN_MODE_INPUT_PULLDOWN:
-	LOG_W("Pull-down enable register not defined for AT32UC3B.");
+	LOG_W("Pull-down enable register not defined for this SOC.");
         break;
     case PIN_MODE_OUTPUT_OD:
 	LOG_W("The open-drain mode is not synthesized on the current AVR32 products.");
@@ -44,9 +46,9 @@ static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t
     }
 }
 
-static void at32uc3b0_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
+static void at32uc3_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
 {
-    RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
+    RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
     if (value == PIN_HIGH)
     {
         gpio_set_gpio_pin(pin);
@@ -57,17 +59,17 @@ static void at32uc3b0_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t
     }
 }
 
-static rt_int8_t at32uc3b0_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin)
 {
-    RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
+    RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
     return (gpio_get_pin_value(pin) ? PIN_HIGH : PIN_LOW);
 }
 
 static const struct rt_pin_ops ops =
 {
-    at32uc3b0_pin_mode,
-    at32uc3b0_pin_write,
-    at32uc3b0_pin_read,
+    at32uc3_pin_mode,
+    at32uc3_pin_write,
+    at32uc3_pin_read,
     RT_NULL,
     RT_NULL,
     RT_NULL,

bsp/avr32/drivers/drv_gpio.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author              Notes
+ * 2023-10-25     Raman Gopalan       Initial version
+ * 2023-11-06     Raman Gopalan       Abstraction for GPIO driver boilerplate
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtconfig.h>
+
+#ifdef RT_USING_PIN
+
+#ifndef BSP_BOARD_MIZAR32B
+#define AVR32_BSP_GPIO_PMIN AVR32_PIN_PA03
+#define AVR32_BSP_GPIO_PMAX AVR32_PIN_PB11
+#else
+#define AVR32_BSP_GPIO_PMIN AVR32_PIN_PA00
+#define AVR32_BSP_GPIO_PMAX AVR32_PIN_PX11
+#endif
+
+int rt_hw_gpio_init(void);
+
+#endif /* #ifdef RT_USING_PIN */
+
+#endif /* __DRV_GPIO_H__ */

bsp/avr32/drivers/drv_uart.c

@@ -10,7 +10,8 @@
  *                                in the buffer.
  * 2010-03-29     Bernard         cleanup code.
  * 2010-03-30     Kyle            Ported from STM32 to AVR32.
- * 2023-10-13     Raman Gopalan   UART driver for at32uc3b: Initial version
+ * 2023-10-25     Raman Gopalan   UART driver for at32uc3a: Initial version
+ * 2023-11-06     Raman Gopalan   Driver abstractions for uc3a and uc3b devices
  */
 
 #include <rthw.h>
@@ -31,19 +32,19 @@
 #endif
 
 #ifdef BSP_USING_UART0
-    void avr32uc3b_uart0_isr(void);
+    void avr32uc3_uart0_isr(void);
 #endif
 
 #ifdef BSP_USING_UART1
-    void avr32uc3b_uart1_isr(void);
+    void avr32uc3_uart1_isr(void);
 #endif
 
 #ifdef BSP_USING_UART2
-    void avr32uc3b_uart2_isr(void);
+    void avr32uc3_uart2_isr(void);
 #endif
 
 /* AVR32UC3B uart driver */
-struct avr32uc3b_uart_dev
+struct avr32uc3_uart_dev
 {
     rt_serial_t parent;
     avr32_usart_t *instance;
@@ -56,7 +57,7 @@ struct avr32uc3b_uart_dev
     void (*uart_isr)(void);
 };
 
-static struct avr32uc3b_uart_dev uart_dev[] =
+static struct avr32uc3_uart_dev uart_dev[] =
 {
 #ifdef BSP_USING_UART0
     {
@@ -67,7 +68,7 @@ static struct avr32uc3b_uart_dev uart_dev[] =
         .tx_pin_function = BSP_UART0_TX_PIN_FUNCTION,
         .rx_pin = BSP_UART0_RX_PIN,
         .rx_pin_function = BSP_UART0_RX_PIN_FUNCTION,
-        .uart_isr = avr32uc3b_uart0_isr,
+        .uart_isr = avr32uc3_uart0_isr,
     },
 #endif
 
@@ -80,7 +81,7 @@ static struct avr32uc3b_uart_dev uart_dev[] =
         .tx_pin_function = BSP_UART1_TX_PIN_FUNCTION,
         .rx_pin = BSP_UART1_RX_PIN,
         .rx_pin_function = BSP_UART1_RX_PIN_FUNCTION,
-        .uart_isr = avr32uc3b_uart1_isr,
+        .uart_isr = avr32uc3_uart1_isr,
     },
 #endif
 
@@ -93,7 +94,7 @@ static struct avr32uc3b_uart_dev uart_dev[] =
         .tx_pin_function = BSP_UART2_TX_PIN_FUNCTION,
         .rx_pin = BSP_UART2_RX_PIN,
         .rx_pin_function = BSP_UART2_RX_PIN_FUNCTION,
-        .uart_isr = avr32uc3b_uart2_isr,
+        .uart_isr = avr32uc3_uart2_isr,
     },
 #endif
 };
@@ -114,7 +115,7 @@ enum
 };
 
 #ifdef BSP_USING_UART0
-void avr32uc3b_uart0_isr(void)
+void avr32uc3_uart0_isr(void)
 {
     rt_interrupt_enter();
     /* read interrupt status and clear it */
@@ -128,7 +129,7 @@ void avr32uc3b_uart0_isr(void)
 #endif
 
 #ifdef BSP_USING_UART1
-void avr32uc3b_uart1_isr(void)
+void avr32uc3_uart1_isr(void)
 {
     rt_interrupt_enter();
     /* read interrupt status and clear it */
@@ -142,7 +143,7 @@ void avr32uc3b_uart1_isr(void)
 #endif
 
 #ifdef BSP_USING_UART2
-void avr32uc3b_uart2_isr(void)
+void avr32uc3_uart2_isr(void)
 {
     rt_interrupt_enter();
     /* read interrupt status and clear it */
@@ -160,9 +161,9 @@ void avr32uc3b_uart2_isr(void)
  */
 /*@{*/
 
-static rt_err_t avr32uc3b_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+static rt_err_t avr32uc3_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-    struct avr32uc3b_uart_dev *uart = RT_NULL;
+    struct avr32uc3_uart_dev *uart = RT_NULL;
     unsigned char l_parity;
     unsigned short l_stop;
     unsigned long l_baud;
@@ -171,7 +172,7 @@ static rt_err_t avr32uc3b_uart_configure(struct rt_serial_device *serial, struct
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
 
-    uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
+    uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
     // Set the TX and RX pins by using the function select on the GPIO
     // Set datasheet for more information on function select
     gpio_enable_module_pin(uart->tx_pin, uart->tx_pin_function);
@@ -203,16 +204,16 @@ static rt_err_t avr32uc3b_uart_configure(struct rt_serial_device *serial, struct
         .channelmode = USART_NORMAL_CHMODE
     };
 
-    usart_init_rs232(uart->instance, &usart_options, FCPU);
+    usart_init_rs232(uart->instance, &usart_options, FPBA);
 
     return RT_EOK;
 }
 
-static rt_err_t avr32uc3b_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+static rt_err_t avr32uc3_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
-    struct avr32uc3b_uart_dev *uart = RT_NULL;
+    struct avr32uc3_uart_dev *uart = RT_NULL;
     RT_ASSERT(serial != RT_NULL);
-    uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
+    uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
 
     switch (cmd)
     {
@@ -229,21 +230,21 @@ static rt_err_t avr32uc3b_uart_control(struct rt_serial_device *serial, int cmd,
     return RT_EOK;
 }
 
-static int avr32uc3b_uart_putc(struct rt_serial_device *serial, char c)
+static int avr32uc3_uart_putc(struct rt_serial_device *serial, char c)
 {
-    struct avr32uc3b_uart_dev *uart = RT_NULL;
+    struct avr32uc3_uart_dev *uart = RT_NULL;
     RT_ASSERT(serial != RT_NULL);
-    uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
+    uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
     usart_putchar(uart->instance, c);
 
     return 1;
 }
 
-static int avr32uc3b_uart_getc(struct rt_serial_device *serial)
+static int avr32uc3_uart_getc(struct rt_serial_device *serial)
 {
-    struct avr32uc3b_uart_dev *uart = RT_NULL;
+    struct avr32uc3_uart_dev *uart = RT_NULL;
     RT_ASSERT(serial != RT_NULL);
-    uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
+    uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
 
     int ch;
     if (usart_read_char(uart->instance, &ch) == USART_SUCCESS)
@@ -254,10 +255,10 @@ static int avr32uc3b_uart_getc(struct rt_serial_device *serial)
 
 const static struct rt_uart_ops _uart_ops =
 {
-    avr32uc3b_uart_configure,
-    avr32uc3b_uart_control,
-    avr32uc3b_uart_putc,
-    avr32uc3b_uart_getc,
+    avr32uc3_uart_configure,
+    avr32uc3_uart_control,
+    avr32uc3_uart_putc,
+    avr32uc3_uart_getc,
     RT_NULL,
 };
 

bsp/avr32/drivers/drv_uart.h

@@ -8,7 +8,8 @@
  * 2009-01-05     Bernard         first version
  * 2010-03-29     Bernard         remove interrupt tx and DMA rx mode.
  * 2010-03-30     Kyle            Ported from STM32 to AVR32.
- * 2023-10-13     Raman Gopalan   UART driver for at32uc3b: Initial version
+ * 2023-10-25     Raman Gopalan   UART driver for at32uc3a: Initial version
+ * 2023-11-06     Raman Gopalan   Driver abstractions for uc3a and uc3b devices
  */
 
 #ifndef __RT_HW_SERIAL_H__
@@ -20,10 +21,18 @@
 #include "usart.h"
 
 #define FOSC0   12000000
+
+#ifndef BSP_BOARD_MIZAR32B
 #define FCPU    60000000
 #define FHSB    FCPU
 #define FPBA    FCPU
 #define FPBB    FCPU
+#else
+#define FCPU    66000000
+#define FHSB    FCPU
+#define FPBA    16500000
+#define FPBB    FCPU
+#endif
 
 #define UART_RX_BUFFER_SIZE     64
 #define UART_TX_DMA_NODE_SIZE   4

bsp/avr32/software_framework/SConscript

@@ -0,0 +1,32 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Split("""
+drivers/flashc/flashc.c
+drivers/gpio/gpio.c
+drivers/intc/intc.c
+drivers/pm/pm.c
+drivers/pm/pm_conf_clocks.c
+drivers/pm/power_clocks_lib.c
+drivers/usart/usart.c
+drivers/adc/adc.c
+""")
+
+CPPPATH = [
+    cwd + '/boards',
+    cwd + '/utils',
+    cwd + '/utils/preprocessor',
+    cwd + '/drivers/flashc',
+    cwd + '/drivers/gpio',
+    cwd + '/drivers/intc',
+    cwd + '/drivers/pm',
+    cwd + '/drivers/usart',
+    cwd + '/drivers/adc',
+]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/avr32/software_framework/drivers/adc/adc.c

@@ -0,0 +1,191 @@
+/*****************************************************************************
+*
+* \file
+*
+* \brief ADC driver for AVR UC3.
+*
+* This file defines a useful set of functions for ADC on AVR UC3 devices.
+*
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+*
+* \asf_license_start
+*
+* \page License
+*
+* Subject to your compliance with these terms, you may use Microchip
+* software and any derivatives exclusively with Microchip products.
+* It is your responsibility to comply with third party license terms applicable
+* to your use of third party software (including open source software) that
+* may accompany Microchip software.
+*
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+*
+* \asf_license_stop
+*
+*****************************************************************************/
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "adc.h"
+
+/** \brief Configure ADC. Mandatory to call.
+ * If not called, ADC channels will have side effects
+ *
+ * \param *adc Base address of the ADC
+ */
+void adc_configure(volatile avr32_adc_t *adc)
+{
+	Assert( adc != NULL );
+
+#ifdef USE_ADC_8_BITS
+	adc->mr |= 1 << AVR32_ADC_LOWRES_OFFSET;
+#endif
+
+	/* Set Sample/Hold time to max so that the ADC capacitor should be
+	 * loaded entirely */
+	adc->mr |= 0xF << AVR32_ADC_SHTIM_OFFSET;
+
+	/* Set Startup to max so that the ADC capacitor should be loaded
+	 * entirely */
+	adc->mr |= 0x1F << AVR32_ADC_STARTUP_OFFSET;
+}
+
+/** \brief Start analog to digital conversion
+ * \param *adc Base address of the ADC
+ */
+void adc_start(volatile avr32_adc_t *adc)
+{
+	Assert( adc != NULL );
+
+	/* start conversion */
+	adc->cr = AVR32_ADC_START_MASK;
+}
+
+/** \brief Enable channel
+ *
+ * \param *adc Base address of the ADC
+ * \param  channel   channel to enable (0 to 7)
+ */
+void adc_enable(volatile avr32_adc_t *adc, uint16_t channel)
+{
+	Assert( adc != NULL );
+	Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
+	                                              **/
+
+	/* enable channel */
+	adc->cher = (1 << channel);
+}
+
+/** \brief Disable channel
+ *
+ * \param *adc Base address of the ADC
+ * \param  channel   channel to disable (0 to 7)
+ */
+void adc_disable(volatile avr32_adc_t *adc, uint16_t channel)
+{
+	Assert( adc != NULL );
+	Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
+	                                              **/
+
+	if (adc_get_status(adc, channel) == true) {
+		/* disable channel */
+		adc->chdr |= (1 << channel);
+	}
+}
+
+/** \brief Get channel 0 to 7 status
+ *
+ * \param *adc Base address of the ADC
+ * \param  channel   channel to handle (0 to 7)
+ * \return bool      true if channel is enabled
+ *                   false if channel is disabled
+ */
+bool adc_get_status(volatile avr32_adc_t *adc, uint16_t channel)
+{
+	Assert( adc != NULL );
+	Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
+	                                              **/
+
+	return ((adc->chsr & (1 << channel)) ? true : false);
+}
+
+/** \brief Check channel conversion status
+ *
+ * \param *adc Base address of the ADC
+ * \param  channel   channel to check (0 to 7)
+ * \return bool      true if conversion not running
+ *                   false if conversion running
+ */
+bool adc_check_eoc(volatile avr32_adc_t *adc, uint16_t channel)
+{
+	Assert( adc != NULL );
+	Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
+	                                              **/
+
+	/* get SR register : EOC bit for channel */
+	return ((adc->sr & (1 << channel)) ? true : false);
+}
+
+/** \brief Check channel conversion overrun error
+ *
+ * \param *adc Base address of the ADC
+ * \param  channel   channel to check (0 to 7)
+ * \return bool      FAIL if an error occurred
+ *                   PASS if no error occurred
+ */
+bool adc_check_ovr(volatile avr32_adc_t *adc, uint16_t channel)
+{
+	Assert( adc != NULL );
+	Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
+	                                              **/
+
+	/* get SR register : OVR bit for channel */
+	return ((adc->sr & (1 << (channel + 8))) ? FAIL : PASS);
+}
+
+/** \brief Get channel value
+ *
+ * \param *adc Base address of the ADC
+ * \param  channel   channel to handle (0 to 7)
+ * \return The value acquired (unsigned long)
+ */
+uint32_t adc_get_value(volatile avr32_adc_t *adc, uint16_t channel)
+{
+	Assert( adc != NULL );
+	Assert( channel <= AVR32_ADC_CHANNELS_MSB );
+
+	/* wait for end of conversion */
+	while (adc_check_eoc(adc, channel) != true) {
+	}
+
+	return *((uint32_t *)((&(adc->cdr0)) + channel));
+}
+
+/** \brief Wait for the next converted data and return its value
+ *
+ * \param *adc Base address of the ADC
+ * \return The latest converted value (unsigned long)
+ */
+uint32_t adc_get_latest_value(volatile avr32_adc_t *adc)
+{
+	Assert( adc != NULL );
+
+	/* Wait for the data ready flag */
+	while ((adc->sr & AVR32_ADC_DRDY_MASK) != AVR32_ADC_DRDY_MASK) {
+	}
+
+	return adc->lcdr;
+}

bsp/avr32/software_framework/drivers/adc/adc.h

@@ -0,0 +1,87 @@
+/*****************************************************************************
+*
+* \file
+*
+* \brief ADC header for AVR UC3 UC3.
+*
+* This file defines a useful set of functions for ADC on AVR UC3 devices.
+*
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+*
+* \asf_license_start
+*
+* \page License
+*
+* Subject to your compliance with these terms, you may use Microchip
+* software and any derivatives exclusively with Microchip products.
+* It is your responsibility to comply with third party license terms applicable
+* to your use of third party software (including open source software) that
+* may accompany Microchip software.
+*
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+*
+* \asf_license_stop
+*
+*****************************************************************************/
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _ADC_H_
+#define _ADC_H_
+
+/**
+ * \defgroup group_avr32_drivers_adc ADC - Analog to Digital Converter
+ *
+ * Analog to Digital Converter is able to capture analog signals and transform
+ * them
+ * into digital format with 10-bit resolution.
+ *
+ * \{
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+
+/* if using 8 bits for ADC, define this flag in your compiler options */
+/** Max value for ADC resolution */
+#ifdef USE_ADC_8_BITS
+#  define ADC_MAX_VALUE    0xFF
+#else
+#  define ADC_MAX_VALUE    0x3FF
+#endif
+
+void adc_configure(volatile avr32_adc_t *adc);
+
+void adc_start(volatile avr32_adc_t *adc);
+
+void adc_enable(volatile avr32_adc_t *adc, uint16_t channel);
+
+void adc_disable(volatile avr32_adc_t *adc, uint16_t channel);
+
+bool adc_get_status(volatile avr32_adc_t *adc, uint16_t channel);
+
+bool adc_check_eoc(volatile avr32_adc_t *adc, uint16_t channel);
+
+bool adc_check_ovr(volatile avr32_adc_t *adc, uint16_t channel);
+
+uint32_t adc_get_value(volatile avr32_adc_t *adc,
+		uint16_t channel);
+
+uint32_t adc_get_latest_value(volatile avr32_adc_t *adc);
+
+/**
+ * \}
+ */
+
+#endif  /* _ADC_H_ */

bsp/avr32/software_framework/drivers/gpio/gpio.h

@@ -0,0 +1,423 @@
+/*****************************************************************************
+*
+* \file
+*
+* \brief GPIO software driver interface for AVR UC3.
+*
+ * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
+*
+* \asf_license_start
+*
+* \page License
+*
+* Subject to your compliance with these terms, you may use Microchip
+* software and any derivatives exclusively with Microchip products.
+* It is your responsibility to comply with third party license terms applicable
+* to your use of third party software (including open source software) that
+* may accompany Microchip software.
+*
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+*
+* \asf_license_stop
+*
+*****************************************************************************/
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/**
+ * \defgroup group_avr32_drivers_gpio GPIO - General-Purpose Input/Output
+ *
+ * GPIO gives access to the MCU pins.
+ *
+ * @{
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+
+/** \name Return Values of the GPIO API
+ * @{ */
+#define GPIO_SUCCESS            0 /**< Function successfully completed. */
+#define GPIO_INVALID_ARGUMENT   1 /**< Input parameters are out of range. */
+/** @} */
+
+/** \name Interrupt Trigger Modes
+ * @{ */
+#define GPIO_PIN_CHANGE         0 /**< Interrupt triggered upon pin change. */
+#define GPIO_RISING_EDGE        1 /**< Interrupt triggered upon rising edge. */
+#define GPIO_FALLING_EDGE       2 /**< Interrupt triggered upon falling edge. */
+/** @} */
+
+/** \name Common defines for GPIO_FLAGS parameter
+ * @{ */
+#define GPIO_DIR_INPUT  (0 << 0) /**< Pin is Input */
+#define GPIO_DIR_OUTPUT (1 << 0) /**< Pin is Output */
+#define GPIO_INIT_LOW   (0 << 1) /**< Initial Output State is Low */
+#define GPIO_INIT_HIGH  (1 << 1) /**< Initial Output State is High */
+#define GPIO_PULL_UP    (1 << 2) /**< Pull-Up (when input) */
+#define GPIO_PULL_DOWN  (2 << 2) /**< Pull-Down (when input) */
+#define GPIO_BUSKEEPER  (3 << 2) /**< Bus Keeper */
+#define GPIO_DRIVE_MIN  (0 << 4) /**< Drive Min Configuration */
+#define GPIO_DRIVE_LOW  (1 << 4) /**< Drive Low Configuration */
+#define GPIO_DRIVE_HIGH (2 << 4) /**< Drive High Configuration */
+#define GPIO_DRIVE_MAX  (3 << 4) /**< Drive Max Configuration */
+#define GPIO_OPEN_DRAIN (1 << 6) /**< Open-Drain (when output) */
+#define GPIO_INTERRUPT  (1 << 7) /**< Enable Pin/Group Interrupt */
+#define GPIO_BOTHEDGES  (3 << 7) /**< Sense Both Edges */
+#define GPIO_RISING     (5 << 7) /**< Sense Rising Edge */
+#define GPIO_FALLING    (7 << 7) /**< Sense Falling Edge */
+/** @} */
+
+/** A type definition of pins and modules connectivity. */
+typedef struct {
+	uint32_t pin;      /**< Module pin. */
+	uint32_t function; /**< Module function. */
+} gpio_map_t[];
+
+/** \name Peripheral Bus Interface
+ *
+ * Low-speed interface with a non-deterministic number of clock cycles per
+ * access.
+ *
+ * This interface operates with lower clock frequencies (fPB <= fCPU), and its
+ * timing is not deterministic since it needs to access a shared bus which may
+ * be heavily loaded.
+ *
+ * \note This interface is immediately available without initialization.
+ *
+ * @{
+ */
+
+uint32_t gpio_enable_module(const gpio_map_t gpiomap, uint32_t size);
+
+uint32_t gpio_enable_module_pin(uint32_t pin, uint32_t function);
+
+void gpio_enable_gpio(const gpio_map_t gpiomap, uint32_t size);
+
+void gpio_enable_gpio_pin(uint32_t pin);
+
+void gpio_enable_pin_pull_up(uint32_t pin);
+
+void gpio_disable_pin_pull_up(uint32_t pin);
+
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) ||	\
+	defined(AVR32_GPIO_212_H_INCLUDED)
+
+void gpio_enable_pin_pull_down(uint32_t pin);
+
+void gpio_disable_pin_pull_down(uint32_t pin);
+
+void gpio_enable_pin_buskeeper(uint32_t pin);
+
+void gpio_disable_pin_buskeeper(uint32_t pin);
+
+#endif
+
+void gpio_configure_pin(uint32_t pin, uint32_t flags);
+
+void gpio_configure_group(uint32_t port, uint32_t mask, uint32_t flags);
+
+bool gpio_get_pin_value(uint32_t pin);
+
+/**
+ * \brief Check if the pin is in low logical level.
+ *
+ * \param pin The pin number.
+ * \return bool    \c true if the pin is in low logical level
+ *                 \c false if the pin is not in low logical level
+ */
+__always_inline static bool gpio_pin_is_low(uint32_t pin)
+{
+	return (gpio_get_pin_value(pin) == 0);
+}
+
+/**
+ * \brief Check if the pin is in high logical level.
+ *
+ * \param pin The pin number.
+ * \return bool    \c true  if the pin is in high logical level
+ *                 \c false if the pin is not in high logical level
+ */
+__always_inline static bool gpio_pin_is_high(uint32_t pin)
+{
+	return (gpio_get_pin_value(pin) != 0);
+}
+
+bool gpio_get_gpio_pin_output_value(uint32_t pin);
+
+bool gpio_get_gpio_open_drain_pin_output_value(uint32_t pin);
+
+void gpio_set_gpio_pin(uint32_t pin);
+
+void gpio_set_pin_high(uint32_t pin);
+
+void gpio_set_group_high(uint32_t port, uint32_t mask);
+
+void gpio_clr_gpio_pin(uint32_t pin);
+
+void gpio_set_pin_low(uint32_t pin);
+
+void gpio_set_group_low(uint32_t port, uint32_t mask);
+
+void gpio_tgl_gpio_pin(uint32_t pin);
+
+void gpio_toggle_pin(uint32_t pin);
+
+void gpio_toggle_group(uint32_t port, uint32_t mask);
+
+void gpio_set_gpio_open_drain_pin(uint32_t pin);
+
+void gpio_clr_gpio_open_drain_pin(uint32_t pin);
+
+void gpio_tgl_gpio_open_drain_pin(uint32_t pin);
+
+void gpio_enable_pin_glitch_filter(uint32_t pin);
+
+void gpio_disable_pin_glitch_filter(uint32_t pin);
+
+uint32_t gpio_enable_pin_interrupt(uint32_t pin, uint32_t mode);
+
+void gpio_disable_pin_interrupt(uint32_t pin);
+
+bool gpio_get_pin_interrupt_flag(uint32_t pin);
+
+void gpio_clear_pin_interrupt_flag(uint32_t pin);
+
+/** @} */
+
+#if (defined AVR32_GPIO_LOCAL_ADDRESS) || defined(__DOXYGEN__)
+
+/** \name Local Bus Interface
+ *
+ * High-speed interface with only one clock cycle per access.
+ *
+ * This interface operates with high clock frequency (fCPU), and its timing is
+ * deterministic since it does not need to access a shared bus which may be
+ * heavily loaded.
+ *
+ * \warning To use this interface, the clock frequency of the peripheral bus on
+ *          which the GPIO peripheral is connected must be set to the CPU clock
+ *          frequency (fPB = fCPU).
+ *
+ * \note This interface has to be initialized in order to be available.
+ *
+ * @{
+ */
+
+/** \brief Enables the local bus interface for GPIO.
+ *
+ * \note This function must have been called at least once before using other
+ *       functions in this interface.
+ */
+__always_inline static void gpio_local_init(void)
+{
+	Set_system_register(AVR32_CPUCR,
+			Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);
+}
+
+/** \brief Enables the output driver of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+__always_inline static void gpio_local_enable_pin_output_driver(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
+}
+
+/** \brief Disables the output driver of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ */
+__always_inline static void gpio_local_disable_pin_output_driver(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
+}
+
+/** \brief Returns the value of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \return The pin value.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ */
+__always_inline static bool gpio_local_get_pin_value(uint32_t pin)
+{
+	return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;
+}
+
+/** \brief Drives a GPIO pin to 1.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin nor its output
+ *       driver. \ref gpio_enable_gpio_pin and
+ *       \ref gpio_local_enable_pin_output_driver can be called for this
+ *       purpose.
+ */
+__always_inline static void gpio_local_set_gpio_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);
+}
+
+/** \brief Drives a GPIO pin to 0.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin nor its output
+ *       driver. \ref gpio_enable_gpio_pin and
+ *       \ref gpio_local_enable_pin_output_driver can be called for this
+ *       purpose.
+ */
+__always_inline static void gpio_local_clr_gpio_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
+}
+
+/** \brief Toggles a GPIO pin.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin nor its output
+ *       driver. \ref gpio_enable_gpio_pin and
+ *       \ref gpio_local_enable_pin_output_driver can be called for this
+ *       purpose.
+ */
+__always_inline static void gpio_local_tgl_gpio_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);
+}
+
+/** \brief Initializes the configuration of a GPIO pin so that it can be used
+ *         with GPIO open-drain functions.
+ *
+ * \note This function must have been called at least once before using
+ *       \ref gpio_local_set_gpio_open_drain_pin,
+ *       \ref gpio_local_clr_gpio_open_drain_pin or
+ *       \ref gpio_local_tgl_gpio_open_drain_pin.
+ */
+__always_inline static void gpio_local_init_gpio_open_drain_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
+}
+
+/** \brief Drives a GPIO pin to 1 using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
+ *       have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+__always_inline static void gpio_local_set_gpio_open_drain_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
+}
+
+/** \brief Drives a GPIO pin to 0 using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
+ *       have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+__always_inline static void gpio_local_clr_gpio_open_drain_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
+}
+
+/** \brief Toggles a GPIO pin using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
+ *       have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+__always_inline static void gpio_local_tgl_gpio_open_drain_pin(uint32_t pin)
+{
+	AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F);
+}
+
+/** @} */
+#endif /* AVR32_GPIO_LOCAL_ADDRESS */
+
+#if UC3L
+
+/** \name Peripheral Event System support
+ *
+ * The GPIO can be programmed to output peripheral events whenever an interrupt
+ * condition is detected, such as pin value change, or only when a rising or
+ * falling edge is detected.
+ *
+ * @{
+ */
+
+/** \brief Enables the peripheral event generation of a pin.
+ *
+ * \param pin The pin number.
+ *
+ */
+__always_inline static void gpio_enable_pin_periph_event(uint32_t pin)
+{
+	AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); /* The GPIO output
+	                                                      * driver is
+	                                                      * disabled for
+	                                                      * that pin. */
+	AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F);
+}
+
+/** \brief Disables the peripheral event generation of a pin.
+ *
+ * \param pin The pin number.
+ *
+ */
+__always_inline static void gpio_disable_pin_periph_event(uint32_t pin)
+{
+	AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F);
+}
+
+uint32_t gpio_configure_pin_periph_event_mode(uint32_t pin, uint32_t mode,
+		uint32_t use_igf);
+
+/** @} */
+
+#endif
+
+/** @} */
+
+#endif  /* _GPIO_H_ */

bsp/avr32/software_framework/drivers/intc/intc.c

@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief INTC software driver for AVR UC3 devices.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "preprocessor.h"
+#include "intc.h"
+
+/**
+ * \internal
+ * \brief Import the _evba symbol from exception.S
+ */
+extern void _evba;
+
+/**
+ * \internal
+ * \brief Import the symbols _int0, _int1, _int2, _int3 defined in exception.S
+ */
+extern void _int0, _int1, _int2, _int3;
+
+/**
+ * \internal
+ * \brief Values to store in the interrupt priority registers for the various
+ *  interrupt priority levels.
+ */
+#define IPR_INT0   ((AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
+			| ((int)&_int0 - (int)&_evba))
+#define IPR_INT1   ((AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
+			| ((int)&_int1 - (int)&_evba))
+#define IPR_INT2   ((AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
+			| ((int)&_int2 - (int)&_evba))
+#define IPR_INT3   ((AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
+			| ((int)&_int3 - (int)&_evba))
+
+/**
+ * \internal
+ * \brief Table of interrupt line handlers per interrupt group in order to
+ * optimize RAM space. Each line handler table contains a set of pointers to
+ * interrupt handlers.
+ */
+#if (defined __GNUC__)
+#  define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
+static volatile __int_handler \
+	_int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
+#elif (defined __ICCAVR32__)
+#  define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
+static volatile __no_init __int_handler \
+	_int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
+#endif
+MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
+#undef DECL_INT_LINE_HANDLER_TABLE
+
+/**
+ * \internal
+ * \brief Table containing for each interrupt group the number of interrupt
+ *  request lines and a pointer to the table of interrupt line handlers.
+ */
+static const struct
+{
+	unsigned int           num_irqs;
+	volatile __int_handler *_int_line_handler_table;
+} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
+{
+#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
+	{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
+	MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
+#undef INSERT_INT_LINE_HANDLER_TABLE
+};
+
+
+/**
+ * \internal
+ * \brief Default interrupt handler.
+ */
+#if (defined __GNUC__)
+__attribute__((__interrupt__))
+#elif (defined __ICCAVR32__)
+__interrupt
+#endif
+static void _unhandled_interrupt(void)
+{
+	// Catch unregistered interrupts.
+	while (true);
+}
+
+
+/**
+ * \brief Gets the interrupt handler of the current event at the \a int_level
+ *        interrupt priority level (called from exception.S).
+ *
+ * \param int_level Interrupt priority level to handle.
+ *
+ * \return Interrupt handler to execute.
+ */
+__int_handler _get_interrupt_handler(uint32_t int_level);
+__int_handler _get_interrupt_handler(uint32_t int_level)
+{
+	/* ICR3 is mapped first, ICR0 last.
+	Code in exception.S puts int_level in R12 which is used by the compiler
+	to pass a single argument to a function. */
+	uint32_t int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
+	uint32_t int_req = AVR32_INTC.irr[int_grp];
+
+	/* As an interrupt may disappear while it is being fetched by the CPU
+	(spurious interrupt caused by a delayed response from an MCU peripheral
+	to an interrupt flag clear or interrupt disable instruction), check if
+	there are remaining interrupt lines to process.
+	If a spurious interrupt occurs, the status register (SR) contains an
+	execution mode and interrupt level masks corresponding to a level 0
+	interrupt, whatever the interrupt priority level causing the spurious
+	event. This behavior has been chosen because a spurious interrupt has
+	not to be a priority one and because it may not cause any trouble to
+	other interrupts.
+	However, these spurious interrupts place the hardware in an unstable
+	state and could give problems in other/future versions of the CPU, so
+	the software has to be written so that they never occur. The only safe
+	way of achieving this is to always clear or disable peripheral
+	interrupts with the following sequence:
+	1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
+	2: Perform the bus access to the peripheral register that clears or
+	disables the interrupt.
+	3: Wait until the interrupt has actually been cleared or disabled by the
+	peripheral. This is usually performed by reading from a register in the
+	same peripheral (it DOES NOT have to be the same register that was
+	accessed in step 2, but it MUST be in the same peripheral), what takes
+	bus system latencies into account, but peripheral internal latencies
+	(generally 0 cycle) also have to be considered.
+	4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
+	Note that steps 1 and 4 are useless inside interrupt handlers as the
+	corresponding interrupt level is automatically masked by IxM (unless IxM
+	is explicitly cleared by the software).*/
+
+	/* Get the right IRQ handler.
+
+	If several interrupt lines are active in the group, the interrupt line
+	with the highest number is selected. This is to be coherent with the
+	prioritization of interrupt groups performed by the hardware interrupt
+	controller.
+
+	If no handler has been registered for the pending interrupt,
+	_unhandled_interrupt will be selected thanks to the initialization of
+	_int_line_handler_table_x by INTC_init_interrupts.
+
+	exception.S will provide the interrupt handler with a clean interrupt
+	stack frame, with nothing more pushed onto the stack. The interrupt
+	handler must manage the `rete' instruction, which can be done using
+	pure assembly, inline assembly or the `__attribute__((__interrupt__))'
+	C function attribute.*/
+	return (int_req)
+		? _int_handler_table[int_grp]._int_line_handler_table[32
+			- clz(int_req) - 1]
+		: NULL;
+}
+
+
+/**
+ * \internal
+ * \brief Init EVBA address. This operation may or may not have been done by the
+ * C startup process.
+ */
+static __inline__ void INTC_init_evba(void)
+{
+  Set_system_register(AVR32_EVBA, (int32_t)&_evba );
+}
+
+
+/**
+ * \brief Initializes the hardware interrupt controller driver.
+ *
+ */
+void INTC_init_interrupts(void)
+{
+	uint32_t int_grp, int_req;
+
+	INTC_init_evba();
+
+	// For all interrupt groups,
+	for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
+	{
+		// For all interrupt request lines of each group,
+		for (int_req = 0;
+			int_req < _int_handler_table[int_grp].num_irqs;
+			int_req++)
+		{
+			/* Assign _unhandled_interrupt as the default interrupt
+			handler. */
+			_int_handler_table[int_grp]
+				._int_line_handler_table[int_req]
+					= &_unhandled_interrupt;
+		}
+
+		/* Set the interrupt group priority register to its default
+		value.
+		By default, all interrupt groups are linked to the interrupt
+		priority level 0 and to the interrupt vector _int0. */
+		AVR32_INTC.ipr[int_grp] = IPR_INT0;
+	}
+}
+
+
+/**
+ * \brief Registers an interrupt handler.
+ *
+ * \param handler   Interrupt handler to register.
+ * \param irq       IRQ of the interrupt handler to register.
+ * \param int_level Interrupt priority level to assign to the group of this IRQ.
+ *
+ * \warning The interrupt handler must manage the `rete' instruction, which can
+ *          be done using pure assembly, inline assembly or the
+ *          `__attribute__((__interrupt__))' C function attribute.
+ *
+ * \warning If several interrupt handlers of a same group are registered with
+ *          different priority levels, only the latest priority level set will
+ *          be effective.
+ *
+ */
+void INTC_register_interrupt(__int_handler handler, uint32_t irq,
+	uint32_t int_level)
+{
+	// Determine the group of the IRQ.
+	uint32_t int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
+
+	/* Store in _int_line_handler_table_x the pointer to the interrupt
+	handler, so that _get_interrupt_handler can retrieve it when the
+	interrupt is vectored. */
+	_int_handler_table[int_grp]
+		._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP]
+			= handler;
+
+	/* Program the corresponding IPRX register to set the interrupt priority
+	level and the interrupt vector offset that will be fetched by the core
+	interrupt system.
+	NOTE: The _intx functions are intermediate assembly functions between
+	the core interrupt system and the user interrupt handler. */
+	if (int_level == AVR32_INTC_INT0) {
+		AVR32_INTC.ipr[int_grp] = IPR_INT0;
+	} else if (int_level == AVR32_INTC_INT1) {
+		AVR32_INTC.ipr[int_grp] = IPR_INT1;
+	} else if (int_level == AVR32_INTC_INT2) {
+		AVR32_INTC.ipr[int_grp] = IPR_INT2;
+	} else {
+		AVR32_INTC.ipr[int_grp] = IPR_INT3;
+	}
+}

bsp/avr32/software_framework/drivers/intc/intc.h

@@ -0,0 +1,77 @@
+/**
+ * \file
+ *
+ * \brief INTC software driver API for AVR UC3 devices.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup intc_group INTC Software Driver API for AVR UC3
+ *
+ * This is a software module to register interrupt handlers at any specified
+ * interrupt level to any interrupt line managed by the INTC module in AVR UC3
+ * devices.
+ * @{
+ */
+
+//! Maximal number of interrupt request lines per group.
+#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP      32
+
+//! Number of interrupt priority levels.
+#define AVR32_INTC_NUM_INT_LEVELS            (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)
+
+
+#ifdef __AVR32_ABI_COMPILER__
+// (Automatically defined when compiling for AVR UC3, not when assembling).
+
+extern void INTC_init_interrupts(void);
+extern void INTC_register_interrupt(__int_handler handler, uint32_t irq,
+		uint32_t int_level);
+
+#endif  // __AVR32_ABI_COMPILER__
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _INTC_H_

bsp/avr32/software_framework/drivers/pm/pm.c

@@ -1,51 +1,41 @@
-/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
-
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
+/*****************************************************************************
+ *
+ * \file
  *
  * \brief Power Manager driver.
  *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
  *
- * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
- * - Supported devices:  All AVR32 devices.
- * - AppNote:
+ * \asf_license_start
  *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
  *
  *****************************************************************************/
-
-/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an Atmel
- * AVR product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
- *
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
  */
 
+
 #include "compiler.h"
 #include "pm.h"
 
@@ -326,6 +316,21 @@ void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
 }
 
 
+void pm_cksel_get(volatile avr32_pm_t *pm, unsigned long *p_cksel)
+{
+  *p_cksel = pm->cksel;
+}
+
+
+void pm_cksel_set(volatile avr32_pm_t *pm, unsigned long cksel)
+{
+  pm->cksel = cksel;
+
+  // Wait for ckrdy bit and then clear it
+  while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
+}
+
+
 void pm_cksel(volatile avr32_pm_t *pm,
               unsigned int pbadiv,
               unsigned int pbasel,
@@ -447,6 +452,13 @@ void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
 }
 
 
+unsigned long pm_get_clock(volatile avr32_pm_t *pm)
+{
+  u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
+  return u_avr32_pm_mcctrl.MCCTRL.mcsel;
+}
+
+
 void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
 {
   // Read
@@ -474,12 +486,12 @@ void pm_bod_enable_irq(volatile avr32_pm_t *pm)
 
 void pm_bod_disable_irq(volatile avr32_pm_t *pm)
 {
-  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+  bool global_interrupt_enabled = cpu_irq_is_enabled();
 
-  if (global_interrupt_enabled) Disable_global_interrupt();
+  if (global_interrupt_enabled) cpu_irq_disable();
   pm->idr = AVR32_PM_IDR_BODDET_MASK;
   pm->isr;
-  if (global_interrupt_enabled) Enable_global_interrupt();
+  if (global_interrupt_enabled) cpu_irq_enable();
 }