Mirrors_Framework/rt-thread
1
0 Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-11-08 14:43:04 +08:00
Code Issues Packages Projects Releases Wiki Activity

nuclei: optimize rvstar support directory

Browse Source 
Signed-off-by: Huaqi Fang <578567190@qq.com>
This commit is contained in:
Huaqi Fang committed 2020-04-08 18:46:58 +08:00
1 parent 1131f6e648
commit 0e1f502edf
164 files changed
-60335
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

bsp/nuclei/gd32vf103/.config → bsp/nuclei/gd32vf103_rvstar/.config
View File
File renamed without changes.
bsp/nuclei/gd32vf103/Kconfig → bsp/nuclei/gd32vf103_rvstar/Kconfig
View File
File renamed without changes.
bsp/nuclei/gd32vf103/README.md → bsp/nuclei/gd32vf103_rvstar/README.md
View File
File renamed without changes.
bsp/nuclei/gd32vf103/SConscript → bsp/nuclei/gd32vf103_rvstar/SConscript
View File
File renamed without changes.
bsp/nuclei/gd32vf103/SConstruct → bsp/nuclei/gd32vf103_rvstar/SConstruct
View File
File renamed without changes.
bsp/nuclei/gd32vf103/applications/SConscript → bsp/nuclei/gd32vf103_rvstar/applications/SConscript
View File
File renamed without changes.
bsp/nuclei/gd32vf103/applications/main.c → bsp/nuclei/gd32vf103_rvstar/applications/main.c
View File
File renamed without changes.
bsp/nuclei/gd32vf103/board/Kconfig → bsp/nuclei/gd32vf103_rvstar/board/Kconfig
View File
File renamed without changes.
bsp/nuclei/gd32vf103/board/SConscript → bsp/nuclei/gd32vf103_rvstar/board/SConscript
View File
File renamed without changes.
bsp/nuclei/gd32vf103/board/board.c → bsp/nuclei/gd32vf103_rvstar/board/board.c
View File
File renamed without changes.
bsp/nuclei/gd32vf103/board/board.h → bsp/nuclei/gd32vf103_rvstar/board/board.h
View File
File renamed without changes.
bsp/nuclei/gd32vf103/drivers/SConscript → bsp/nuclei/gd32vf103_rvstar/drivers/SConscript
View File
File renamed without changes.
bsp/nuclei/gd32vf103/drivers/drv_usart.c → bsp/nuclei/gd32vf103_rvstar/drivers/drv_usart.c
View File
File renamed without changes.
bsp/nuclei/gd32vf103/drivers/drv_usart.h → bsp/nuclei/gd32vf103_rvstar/drivers/drv_usart.h
View File
File renamed without changes.
bsp/nuclei/gd32vf103/rtconfig.h → bsp/nuclei/gd32vf103_rvstar/rtconfig.h
View File
File renamed without changes.
bsp/nuclei/gd32vf103/rtconfig.py → bsp/nuclei/gd32vf103_rvstar/rtconfig.py
View File
File renamed without changes.
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_compatiable.h
-224
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_base.h
-1177
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_cache.h
-124
View File
@@ -1,124 +0,0 @@
/*
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CORE_FEATURE_CACHE_H__
#define __CORE_FEATURE_CACHE_H__
/*!
* @file core_feature_cache.h
* @brief Cache feature API header file for Nuclei N/NX Core
*/
/*
* Cache Feature Configuration Macro:
* 1. __ICACHE_PRESENT: Define whether I-Cache Unit is present or not.
* * 0: Not present
* * 1: Present
* 1. __DCACHE_PRESENT: Define whether D-Cache Unit is present or not.
* * 0: Not present
* * 1: Present
*/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
/* ########################## Cache functions #################################### */
/**
* \defgroup NMSIS_Core_Cache Cache Functions
* \brief Functions that configure Instruction and Data Cache.
* @{
*/
/** @} */ /* End of Doxygen Group NMSIS_Core_Cache */
/**
* \defgroup NMSIS_Core_ICache I-Cache Functions
* \ingroup NMSIS_Core_Cache
* \brief Functions that configure Instruction Cache.
* @{
*/
/**
* \brief Enable ICache
* \details
* This function enable I-Cache
* \remarks
* - This \ref CSR_MCACHE_CTL register control I Cache enable.
* \sa
* - \ref DisableICache
*/
__STATIC_FORCEINLINE void EnableICache (void)
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/**
* \brief Disable ICache
* \details
* This function Disable I-Cache
* \remarks
* - This \ref CSR_MCACHE_CTL register control I Cache enable.
* \sa
* - \ref EnableICache
*/
__STATIC_FORCEINLINE void DisableICache (void)
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
/**
* \defgroup NMSIS_Core_DCache D-Cache Functions
* \ingroup NMSIS_Core_Cache
* \brief Functions that configure Data Cache.
* @{
*/
/**
* \brief Enable DCache
* \details
* This function enable D-Cache
* \remarks
* - This \ref CSR_MCACHE_CTL register control D Cache enable.
* \sa
* - \ref DisableDCache
*/
__STATIC_FORCEINLINE void EnableDCache (void)
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/**
* \brief Disable DCache
* \details
* This function Disable D-Cache
* \remarks
* - This \ref CSR_MCACHE_CTL register control D Cache enable.
* \sa
* - \ref EnableDCache
*/
__STATIC_FORCEINLINE void DisableDCache (void)
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */
#ifdef __cplusplus
}
#endif
#endif /** __CORE_FEATURE_CACHE_H__ */
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_dsp.h
-14440
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_eclic.h
-897
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_fpu.h
-304
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_pmp.h
-260
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/core_feature_timer.h
-364
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/nmsis_compiler.h
-37
View File
@@ -1,37 +0,0 @@
/*
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __NMSIS_COMPILER_H
#define __NMSIS_COMPILER_H
#include <stdint.h>
/*!
* @file nmsis_compiler.h
* @brief NMSIS compiler generic header file
*/
#if defined ( __GNUC__ )
/** GNU GCC Compiler */
#include "nmsis_gcc.h"
#else
#error Unknown compiler.
#endif
#endif /* __NMSIS_COMPILER_H */
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/nmsis_core.h
-87
View File
@@ -1,87 +0,0 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
* -- Adaptable modifications made for Nuclei Processors. --
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __NMSIS_CORE_H__
#define __NMSIS_CORE_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#include "nmsis_version.h"
/**
* \ingroup NMSIS_Core_VersionControl
* @{
*/
/* The following enum __NUCLEI_N_REV/__NUCLEI_NX_REV definition in this file
* is only used for doxygen documentation generation,
* The <device>.h is the real file to define it by vendor
*/
#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
/**
* \brief Nuclei N class core revision number
* \details
* Reversion number format: [15:8] revision number, [7:0] patch number
* \attention
* This define is exclusive with \ref __NUCLEI_NX_REV
*/
#define __NUCLEI_N_REV (0x0104)
/**
* \brief Nuclei NX class core revision number
* \details
* Reversion number format: [15:8] revision number, [7:0] patch number
* \attention
* This define is exclusive with \ref __NUCLEI_N_REV
*/
#define __NUCLEI_NX_REV (0x0100)
#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
/** @} */ /* End of Group NMSIS_Core_VersionControl */
#include "nmsis_compiler.h" /* NMSIS compiler specific defines */
/* === Include Nuclei Core Related Headers === */
/* Include core base feature header file */
#include "core_feature_base.h"
#ifndef __NMSIS_GENERIC
/* Include core eclic feature header file */
#include "core_feature_eclic.h"
/* Include core systimer feature header file */
#include "core_feature_timer.h"
#endif
/* Include core fpu feature header file */
#include "core_feature_fpu.h"
/* Include core dsp feature header file */
#include "core_feature_dsp.h"
/* Include core pmp feature header file */
#include "core_feature_pmp.h"
/* Include core cache feature header file */
#include "core_feature_cache.h"
/* Include compatiable functions header file */
#include "core_compatiable.h"
#ifdef __cplusplus
}
#endif
#endif /* __NMSIS_CORE_H__ */
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/nmsis_gcc.h
-265
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/nmsis_version.h
-87
View File
@@ -1,87 +0,0 @@
/*
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __NMSIS_VERSION_H
#define __NMSIS_VERSION_H
/**
* \defgroup NMSIS_Core_VersionControl Version Control
* \ingroup NMSIS_Core
* \brief Version \#define symbols for NMSIS release specific C/C++ source code
* \details
*
* We followed the [semantic versioning 2.0.0](https://semver.org/) to control NMSIS version.
* The version format is **MAJOR.MINOR.PATCH**, increment the:
* 1. MAJOR version when you make incompatible API changes,
* 2. MINOR version when you add functionality in a backwards compatible manner, and
* 3. PATCH version when you make backwards compatible bug fixes.
*
* The header file `nmsis_version.h` is included by each core header so that these definitions are available.
*
* **Example Usage for NMSIS Version Check**:
* \code
* #if defined(__NMSIS_VERSION) && (__NMSIS_VERSION >= 0x00010105)
* #warning "Yes, we have NMSIS 1.1.5 or later"
* #else
* #error "We need NMSIS 1.1.5 or later!"
* #endif
* \endcode
*
* @{
*/
/*!
* \file nmsis_version.h
* \brief NMSIS Version definitions
**/
/**
* \brief Represent the NMSIS major version
* \details
* The NMSIS major version can be used to
* differentiate between NMSIS major releases.
* */
#define __NMSIS_VERSION_MAJOR (1U)
/**
* \brief Represent the NMSIS minor version
* \details
* The NMSIS minor version can be used to
* query a NMSIS release update including new features.
*
**/
#define __NMSIS_VERSION_MINOR (0U)
/**
* \brief Represent the NMSIS patch version
* \details
* The NMSIS patch version can be used to
* show bug fixes in this package.
**/
#define __NMSIS_VERSION_PATCH (0U)
/**
* \brief Represent the NMSIS Version
* \details
* NMSIS Version format: **MAJOR.MINOR.PATCH**
* * MAJOR: \ref __NMSIS_VERSION_MAJOR, stored in `bits [31:16]` of \ref __NMSIS_VERSION
* * MINOR: \ref __NMSIS_VERSION_MINOR, stored in `bits [15:8]` of \ref __NMSIS_VERSION
* * PATCH: \ref __NMSIS_VERSION_PATCH, stored in `bits [7:0]` of \ref __NMSIS_VERSION
**/
#define __NMSIS_VERSION ((__NMSIS_VERSION_MAJOR << 16U) | (__NMSIS_VERSION_MINOR << 8) | __NMSIS_VERSION_PATCH)
/** @} */ /* End of Doxygen Group NMSIS_Core_VersionControl */
#endif
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/riscv_bits.h
-92
View File
@@ -1,92 +0,0 @@
/*
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RISCV_BITS_H__
#define __RISCV_BITS_H__
#ifdef __cplusplus
extern "C" {
#endif
#if __riscv_xlen == 64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif /* __riscv_xlen */
#define REGBYTES (1 << LOG_REGBYTES)
#if __riscv_flen == 64
# define FPSTORE fsd
# define FPLOAD fld
# define LOG_FPREGBYTES 3
#else
# define FPSTORE fsw
# define FPLOAD flw
# define LOG_FPREGBYTES 2
#endif /* __riscv_flen */
#define FPREGBYTES (1 << LOG_FPREGBYTES)
#define __rv_likely(x) __builtin_expect((x), 1)
#define __rv_unlikely(x) __builtin_expect((x), 0)
#define __RV_ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define __RV_ROUNDDOWN(a, b) ((a)/(b)*(b))
#define __RV_MAX(a, b) ((a) > (b) ? (a) : (b))
#define __RV_MIN(a, b) ((a) < (b) ? (a) : (b))
#define __RV_CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define __RV_EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define __RV_INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#ifdef __ASSEMBLY__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define __AC(X,Y) (X##Y)
#define _AC(X,Y) __AC(X,Y)
#define _AT(T,X) ((T)(X))
#endif /* __ASSEMBLY__ */
#define _UL(x) (_AC(x, UL))
#define _ULL(x) (_AC(x, ULL))
#define _BITUL(x) (_UL(1) << (x))
#define _BITULL(x) (_ULL(1) << (x))
#define UL(x) (_UL(x))
#define ULL(x) (_ULL(x))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#define __STR(s) #s
#define STRINGIFY(s) __STR(s)
#ifdef __cplusplus
}
#endif
#endif /** __RISCV_BITS_H__ */
bsp/nuclei/nuclei_sdk/NMSIS/Core/Include/riscv_encoding.h
-557
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/DSP/Include/riscv_common_tables.h
-379
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/DSP/Include/riscv_const_structs.h
-67
View File
@@ -1,67 +0,0 @@
/* ----------------------------------------------------------------------
* Project: NMSIS DSP Library
* Title: riscv_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the riscv_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: RISC-V Cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _RISCV_CONST_STRUCTS_H
#define _RISCV_CONST_STRUCTS_H
#include "riscv_math.h"
#include "riscv_common_tables.h"
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len16;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len32;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len64;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len128;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len256;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len512;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len1024;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len2048;
extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len4096;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len16;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len32;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len64;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len128;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len256;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len512;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len1024;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len2048;
extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len4096;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len16;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len32;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len64;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len128;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len256;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len512;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len1024;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len2048;
extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len4096;
#endif
bsp/nuclei/nuclei_sdk/NMSIS/DSP/Include/riscv_math.h
-7169
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/NN/Include/riscv_nn_tables.h
-57
View File
@@ -1,57 +0,0 @@
/* ----------------------------------------------------------------------
* Project: NMSIS NN Library
* Title: riscv_nn_tables.h
* Description: Extern declaration for NN tables
*
* $Date: 17. January 2018
* $Revision: V.1.0.0
*
* Target Processor: RISC-V Cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _RISCV_NN_TABLES_H
#define _RISCV_NN_TABLES_H
#include "riscv_math.h"
/**
* @brief tables for various activation functions
*
*/
extern const q15_t sigmoidTable_q15[256];
extern const q7_t sigmoidTable_q7[256];
extern const q7_t tanhTable_q7[256];
extern const q15_t tanhTable_q15[256];
/**
* @brief 2-way tables for various activation functions
*
* 2-way table, H table for value larger than 1/4
* L table for value smaller than 1/4, H table for remaining
* We have this only for the q15_t version. It does not make
* sense to have it for q7_t type
*/
extern const q15_t sigmoidHTable_q15[192];
extern const q15_t sigmoidLTable_q15[128];
#endif /* RISCV_NN_TABLES_H */
bsp/nuclei/nuclei_sdk/NMSIS/NN/Include/riscv_nnfunctions.h
-1134
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/NMSIS/NN/Include/riscv_nnsupportfunctions.h
-366
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SConscript
-31
View File
@@ -1,31 +0,0 @@
# RT-Thread building script for component
Import('rtconfig')
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
SoC_Common = 'SoC/gd32vf103/Common'
SoC_Board = 'SoC/gd32vf103/Board/gd32vf103v_rvstar'
src = Glob(SoC_Common + '/Source/*.c')
src += Glob(SoC_Common + '/Source/Drivers/*.c')
src += Glob(SoC_Common + '/Source/Drivers/Usb/*.c')
src += Glob(SoC_Common + '/Source/Stubs/*.c')
src += Glob(SoC_Common + '/Source/GCC/*.S')
src += Glob(SoC_Board + '/Source/*.c')
CPPPATH = [ cwd + '/NMSIS/Core/Include',
cwd + '/NMSIS/DSP/Include',
cwd + '/NMSIS/NN/Include',
cwd + '/', SoC_Common + '/Include',
cwd + '/', SoC_Common + '/Include/Usb',
cwd + '/', SoC_Common + '/Source/Stubs/',
cwd + '/', SoC_Board + '/Include']
CPPDEFINES = ['-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP', '-DRTOS_RTTHREAD', '-DNUCLEI_BANNER=0']
group = DefineGroup('nuclei_sdk', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
Return('group')
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_eval/Include/gd32vf103v_eval.h
-168
View File
@@ -1,168 +0,0 @@
/*!
\file gd32vf103v_eval.h
\brief definitions for GD32VF103V_EVAL's leds, keys and COM ports hardware resources
\version 2019-6-5, V1.0.0, demo for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103V_EVAL_H
#define GD32VF103V_EVAL_H
#ifdef cplusplus
extern "C" {
#endif
#include "nuclei_sdk_soc.h"
/* exported types */
typedef enum
{
LED1 = 0,
LED2 = 1,
LED3 = 2,
LED4 = 3
} led_typedef_enum;
typedef enum
{
KEY_A = 0,
KEY_B = 1,
KEY_C = 2,
KEY_D = 3,
KEY_CET = 4
} key_typedef_enum;
typedef enum
{
KEY_MODE_GPIO = 0,
KEY_MODE_EXTI = 1
} keymode_typedef_enum;
/* eval board low layer led */
#define LEDn 4U
#define LED1_PIN GPIO_PIN_0
#define LED1_GPIO_PORT GPIOC
#define LED1_GPIO_CLK RCU_GPIOC
#define LED2_PIN GPIO_PIN_2
#define LED2_GPIO_PORT GPIOC
#define LED2_GPIO_CLK RCU_GPIOC
#define LED3_PIN GPIO_PIN_0
#define LED3_GPIO_PORT GPIOE
#define LED3_GPIO_CLK RCU_GPIOE
#define LED4_PIN GPIO_PIN_1
#define LED4_GPIO_PORT GPIOE
#define LED4_GPIO_CLK RCU_GPIOE
#define COMn 2U
#define GD32_COM0 USART0
#define GD32_COM0_CLK RCU_USART0
#define GD32_COM0_TX_PIN GPIO_PIN_9
#define GD32_COM0_RX_PIN GPIO_PIN_10
#define GD32_COM0_GPIO_PORT GPIOA
#define GD32_COM0_GPIO_CLK RCU_GPIOA
#define GD32_COM1 USART1
#define GD32_COM1_CLK RCU_USART1
#define GD32_COM1_TX_PIN GPIO_PIN_2
#define GD32_COM1_RX_PIN GPIO_PIN_3
#define GD32_COM1_GPIO_PORT GPIOA
#define GD32_COM1_GPIO_CLK RCU_GPIOA
#define KEYn 5U
/* wakeup push-button */
#define KEY_A_PIN GPIO_PIN_0
#define KEY_A_GPIO_PORT GPIOA
#define KEY_A_GPIO_CLK RCU_GPIOA
#define KEY_A_EXTI_LINE EXTI_0
#define KEY_A_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA
#define KEY_A_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0
#define KEY_A_EXTI_IRQn EXTI0_IRQn
/* tamper push-button */
#define KEY_B_PIN GPIO_PIN_13
#define KEY_B_GPIO_PORT GPIOC
#define KEY_B_GPIO_CLK RCU_GPIOC
#define KEY_B_EXTI_LINE EXTI_13
#define KEY_B_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
#define KEY_B_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_13
#define KEY_B_EXTI_IRQn EXTI10_15_IRQn
/* user push-button */
#define KEY_C_PIN GPIO_PIN_14
#define KEY_C_GPIO_PORT GPIOB
#define KEY_C_GPIO_CLK RCU_GPIOB
#define KEY_C_EXTI_LINE EXTI_14
#define KEY_C_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOB
#define KEY_C_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_14
#define KEY_C_EXTI_IRQn EXTI10_15_IRQn
#define KEY_D_PIN GPIO_PIN_5
#define KEY_D_GPIO_PORT GPIOC
#define KEY_D_GPIO_CLK RCU_GPIOC
#define KEY_D_EXTI_LINE EXTI_5
#define KEY_D_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
#define KEY_D_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_5
#define KEY_D_EXTI_IRQn EXTI5_9_IRQn
#define KEY_CET_PIN GPIO_PIN_4
#define KEY_CET_GPIO_PORT GPIOC
#define KEY_CET_GPIO_CLK RCU_GPIOC
#define KEY_CET_EXTI_LINE EXTI_4
#define KEY_CET_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
#define KEY_CET_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_4
#define KEY_CET_EXTI_IRQn EXTI4_IRQn
/* function declarations */
/* configure led GPIO */
void gd_eval_led_init(led_typedef_enum lednum);
/* turn on selected led */
void gd_eval_led_on(led_typedef_enum lednum);
/* turn off selected led */
void gd_eval_led_off(led_typedef_enum lednum);
/* toggle the selected led */
void gd_eval_led_toggle(led_typedef_enum lednum);
/* configure key */
void gd_eval_key_init(key_typedef_enum keynum, keymode_typedef_enum key_mode);
/* return the selected key state */
uint8_t gd_eval_key_state_get(key_typedef_enum key);
/* configure COM port */
void gd_com_init(uint32_t com);
#ifdef cplusplus
}
#endif
#endif /* GD32VF103V_EVAL_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_eval/Include/nuclei_sdk_hal.h
-18
View File
@@ -1,18 +0,0 @@
// See LICENSE for license details.
#ifndef _NUCLEI_SDK_HAL_H
#define _NUCLEI_SDK_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "gd32vf103v_eval.h"
#ifndef NUCLEI_BANNER
#define NUCLEI_BANNER 1
#endif
#ifdef __cplusplus
}
#endif
#endif
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_eval/Source/GCC/gcc_gd32vf103_flashxip.ld
-284
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_eval/Source/gd32vf103v_eval.c
-252
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_eval/openocd_gd32vf103.cfg
-47
View File
@@ -1,47 +0,0 @@
adapter_khz 1000
reset_config srst_only
adapter_nsrst_assert_width 100
interface cmsis-dap
transport select jtag
autoexit true
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6d
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0
# Work-area is a space in RAM used for flash programming
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x5000
}
# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
set _FLASH_SIZE $FLASH_SIZE
} else {
# autodetect size
set _FLASH_SIZE 0
}
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME gd32vf103 0x08000000 0 0 0 $_TARGETNAME
# Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
riscv set_reset_timeout_sec 1
init
halt
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_rvstar/Include/gd32vf103v_rvstar.h
-121
View File
@@ -1,121 +0,0 @@
/*!
\file gd32vf103c_start.h
\brief definitions for GD32VF103C_START's leds, keys and COM ports hardware resources
\version 2019-06-05, V1.0.0, demo for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103C_RVSTART_H
#define GD32VF103C_RVSTART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "nuclei_sdk_soc.h"
/* exported types */
typedef enum
{
LED1 = 0,
LED2 = 1,
LED3 = 2,
}led_typedef_enum;
typedef enum
{
KEY_WAKEUP = 0,
}key_typedef_enum;
typedef enum
{
KEY_MODE_GPIO = 0,
KEY_MODE_EXTI = 1
}keymode_typedef_enum;
/* rvstar board low layer led */
#define LEDn 3U
#define LEDG_PIN GPIO_PIN_1
#define LEDG_GPIO_PORT GPIOA
#define LEDG_GPIO_CLK RCU_GPIOA
#define LEDB_PIN GPIO_PIN_3
#define LEDB_GPIO_PORT GPIOA
#define LEDB_GPIO_CLK RCU_GPIOA
#define LEDR_PIN GPIO_PIN_2
#define LEDR_GPIO_PORT GPIOA
#define LEDR_GPIO_CLK RCU_GPIOA
/* rvstar board UART com port */
#define GD32_COM0 UART4
#define GD32_COM_CLK RCU_UART4
#define GD32_COM_TX_PIN GPIO_PIN_12
#define GD32_COM_RX_PIN GPIO_PIN_2
#define GD32_COM_TX_GPIO_PORT GPIOC
#define GD32_COM_RX_GPIO_PORT GPIOD
#define GD32_COM_TX_GPIO_CLK RCU_GPIOC
#define GD32_COM_RX_GPIO_CLK RCU_GPIOD
/* rvstar board low layer button */
#define KEYn (1U)
/* wakeup push-button */
#define WAKEUP_KEY_PIN GPIO_PIN_0
#define WAKEUP_KEY_GPIO_PORT GPIOA
#define WAKEUP_KEY_GPIO_CLK RCU_GPIOA
#define WAKEUP_KEY_EXTI_LINE EXTI_0
#define WAKEUP_KEY_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA
#define WAKEUP_KEY_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0
#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn
/* function declarations */
/* configure led GPIO */
void gd_rvstar_led_init(led_typedef_enum lednum);
/* turn on selected led */
void gd_rvstar_led_on(led_typedef_enum lednum);
/* turn off selected led */
void gd_rvstar_led_off(led_typedef_enum lednum);
/* toggle the selected led */
void gd_rvstar_led_toggle(led_typedef_enum lednum);
/* configure key */
void gd_rvstar_key_init(key_typedef_enum keynum, keymode_typedef_enum keymode);
/* return the selected key state */
uint8_t gd_rvstar_key_state_get(key_typedef_enum keynum);
/* configure COM port */
void gd_com_init(uint32_t usart_periph);
#ifdef __cplusplus
}
#endif
#endif /* GD32VF103V_RVSTART_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_rvstar/Include/nuclei_sdk_hal.h
-18
View File
@@ -1,18 +0,0 @@
// See LICENSE for license details.
#ifndef _NUCLEI_SDK_HAL_H
#define _NUCLEI_SDK_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "gd32vf103v_rvstar.h"
#ifndef NUCLEI_BANNER
#define NUCLEI_BANNER 1
#endif
#ifdef __cplusplus
}
#endif
#endif
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_rvstar/Source/GCC/gcc_gd32vf103_flashxip.ld
-284
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_rvstar/Source/gd32vf103v_rvstar.c
-191
View File
@@ -1,191 +0,0 @@
/*!
* \file gd32vf103c_start.c
* \brief firmware functions to manage leds, keys, COM ports
*
* \version 2020-02-05, V1.0.0, rvstar board functions for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103v_rvstar.h"
/* private variables */
static const uint32_t GPIO_PORT[LEDn] = {LEDG_GPIO_PORT,LEDB_GPIO_PORT,LEDR_GPIO_PORT};
static const uint32_t GPIO_PIN[LEDn] = {LEDG_PIN,LEDB_PIN,LEDR_PIN};
static const rcu_periph_enum GPIO_CLK[LEDn] = {LEDG_GPIO_CLK,LEDB_GPIO_CLK,LEDR_GPIO_CLK};
static const uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT};
static const uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN};
static const rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK};
static const exti_line_enum KEY_EXTI_LINE[KEYn] = {WAKEUP_KEY_EXTI_LINE};
static const uint8_t KEY_PORT_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PORT_SOURCE};
static const uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE};
static const uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn};
/* eval board low layer private functions */
/*!
* \brief configure led GPIO
* \param[in] lednum: specify the led to be configured
* \arg LED1
* \param[out] none
* \retval none
*/
void gd_rvstar_led_init(led_typedef_enum lednum)
{
/* enable the led clock */
rcu_periph_clock_enable(GPIO_CLK[lednum]);
/* configure led GPIO port */
gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN[lednum]);
GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
}
/*!
* \brief turn on selected led
* \param[in] lednum: specify the led to be turned on
* \arg LED1
* \param[out] none
* \retval none
*/
void gd_rvstar_led_on(led_typedef_enum lednum)
{
GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
}
/*!
* \brief turn off selected led
* \param[in] lednum: specify the led to be turned off
* \arg LED1
* \param[out] none
* \retval none
*/
void gd_rvstar_led_off(led_typedef_enum lednum)
{
GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
}
/*!
* \brief toggle selected led
* \param[in] lednum: specify the led to be toggled
* \arg LED1
* \param[out] none
* \retval none
*/
void gd_rvstar_led_toggle(led_typedef_enum lednum)
{
gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum],
(bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum])));
}
/*!
* \brief configure key
* \param[in] keynum: specify the key to be configured
* \arg KEY_WAKEUP: wakeup key
* \param[in] keymode: specify button mode
* \arg KEY_MODE_GPIO: key will be used as simple IO
* \arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt
* \param[out] none
* \retval none
*/
void gd_rvstar_key_init(key_typedef_enum keynum, keymode_typedef_enum keymode)
{
/* enable the key clock */
rcu_periph_clock_enable(KEY_CLK[keynum]);
rcu_periph_clock_enable(RCU_AF);
/* configure button pin as input */
gpio_init(KEY_PORT[keynum], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[keynum]);
if (keymode == KEY_MODE_EXTI) {
/* enable and set key EXTI interrupt to the lowest priority */
ECLIC_EnableIRQ(KEY_IRQn[keynum]);
ECLIC_SetLevelIRQ(KEY_IRQn[keynum],1);
ECLIC_SetPriorityIRQ(KEY_IRQn[keynum],1);
/* connect key EXTI line to key GPIO pin */
gpio_exti_source_select(KEY_PORT_SOURCE[keynum], KEY_PIN_SOURCE[keynum]);
/* configure key EXTI line */
exti_init(KEY_EXTI_LINE[keynum], EXTI_INTERRUPT, EXTI_TRIG_FALLING);
exti_interrupt_flag_clear(KEY_EXTI_LINE[keynum]);
}
}
/*!
* \brief return the selected key state
* \param[in] keynum: specify the key to be checked
* \arg KEY_WAKEUP: wakeup key
* \param[out] none
* \retval the key's GPIO pin value
*/
uint8_t gd_rvstar_key_state_get(key_typedef_enum keynum)
{
return gpio_input_bit_get(KEY_PORT[keynum], KEY_PIN[keynum]);
}
/*!
* \brief configure COM port
* \param[in] com: COM on the board
* \arg GD32_COM0: COM0 on the board
* \param[out] none
* \retval none
*/
void gd_com_init(uint32_t usart_periph)
{
/* enable GPIO TX and RX clock */
rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK);
rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK);
/* enable USART clock */
rcu_periph_clock_enable(GD32_COM_CLK);
/* connect port to USARTx_Tx */
gpio_init(GD32_COM_TX_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GD32_COM_TX_PIN);
/* connect port to USARTx_Rx */
gpio_init(GD32_COM_RX_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GD32_COM_RX_PIN);
/* USART configure */
usart_deinit(usart_periph);
usart_baudrate_set(usart_periph, 115200U);
usart_word_length_set(usart_periph, USART_WL_8BIT);
usart_stop_bit_set(usart_periph, USART_STB_1BIT);
usart_parity_config(usart_periph, USART_PM_NONE);
usart_hardware_flow_rts_config(usart_periph, USART_RTS_DISABLE);
usart_hardware_flow_cts_config(usart_periph, USART_CTS_DISABLE);
usart_receive_config(usart_periph, USART_RECEIVE_ENABLE);
usart_transmit_config(usart_periph, USART_TRANSMIT_ENABLE);
usart_enable(usart_periph);
}
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg
-40
View File
@@ -1,40 +0,0 @@
adapter_khz 10000
reset_config srst_only
adapter_nsrst_assert_width 100
interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
transport select jtag
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6d
# Work-area is a space in RAM used for flash programming
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x5000
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME gd32vf103 0x08000000 0 0 0 $_TARGETNAME
# Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
riscv expose_csrs 770-800,835-850,1984-2032,2064-2070
riscv set_reset_timeout_sec 1
init
halt
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h
-117
View File
@@ -1,117 +0,0 @@
/*!
\file drv_usb_core.h
\brief USB core low level driver header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __DRV_USB_CORE_H
#define __DRV_USB_CORE_H
#include "drv_usb_regs.h"
#include "usb_ch9_std.h"
#define USB_FS_EP0_MAX_LEN 64U /* maximum packet size of EndPoint0 */
#define HC_MAX_PACKET_COUNT 140U /* maximum packet count */
#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /* endpoint number */
#define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */
enum _usb_eptype {
USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */
USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */
USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */
USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */
USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */
};
typedef enum
{
USB_OTG_OK = 0, /*!< USB OTG status OK*/
USB_OTG_FAIL /*!< USB OTG status fail*/
} usb_otg_status;
typedef enum
{
USB_OK = 0, /*!< USB status OK*/
USB_FAIL /*!< USB status fail*/
} usb_status;
typedef enum
{
USB_USE_FIFO, /*!< USB use FIFO transfer mode */
USB_USE_DMA /*!< USB use DMA transfer mode */
} usb_transfer_mode;
typedef struct
{
uint8_t core_enum; /*!< USB core type */
uint8_t core_speed; /*!< USB core speed */
uint8_t num_pipe; /*!< USB host channel numbers */
uint8_t num_ep; /*!< USB device endpoint numbers */
uint8_t transfer_mode; /*!< USB transfer mode */
uint8_t phy_itf; /*!< USB core PHY interface */
uint8_t sof_enable; /*!< USB SOF output */
uint8_t low_power; /*!< USB low power */
} usb_core_basic;
/* function declarations */
/* config core capabilities */
usb_status usb_basic_init (usb_core_basic *usb_basic,
usb_core_regs *usb_regs,
usb_core_enum usb_core);
/*initializes the USB controller registers and prepares the core device mode or host mode operation*/
usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs);
/* read a packet from the Rx FIFO associated with the endpoint */
void *usb_rxfifo_read (usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count);
/* write a packet into the Tx FIFO associated with the endpoint */
usb_status usb_txfifo_write (usb_core_regs *usb_regs,
uint8_t *src_buf,
uint8_t fifo_num,
uint16_t byte_count);
/* flush a Tx FIFO or all Tx FIFOs */
usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num);
/* flush the entire Rx FIFO */
usb_status usb_rxfifo_flush (usb_core_regs *usb_regs);
/* get the global interrupts */
static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs)
{
return usb_regs->gr->GINTEN & usb_regs->gr->GINTF;
}
#endif /* __DRV_USB_CORE_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h
-217
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h
-175
View File
@@ -1,175 +0,0 @@
/*!
\file drv_usb_host.h
\brief USB host mode low level driver header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __DRV_USB_HOST_H
#define __DRV_USB_HOST_H
#include "drv_usb_regs.h"
#include "usb_ch9_std.h"
#include "drv_usb_core.h"
typedef enum _usb_pipe_status
{
PIPE_IDLE = 0U,
PIPE_XF,
PIPE_HALTED,
PIPE_NAK,
PIPE_NYET,
PIPE_STALL,
PIPE_TRACERR,
PIPE_BBERR,
PIPE_REQOVR,
PIPE_DTGERR,
} usb_pipe_staus;
typedef enum _usb_pipe_mode
{
PIPE_PERIOD = 0U,
PIPE_NON_PERIOD = 1U
} usb_pipe_mode;
typedef enum _usb_urb_state
{
URB_IDLE = 0U,
URB_DONE,
URB_NOTREADY,
URB_ERROR,
URB_STALL
} usb_urb_state;
typedef struct _usb_pipe
{
uint8_t in_used;
uint8_t dev_addr;
uint32_t dev_speed;
struct {
uint8_t num;
uint8_t dir;
uint8_t type;
uint16_t mps;
} ep;
uint8_t ping;
uint32_t DPID;
uint8_t *xfer_buf;
uint32_t xfer_len;
uint32_t xfer_count;
uint8_t data_toggle_in;
uint8_t data_toggle_out;
__IO uint32_t err_count;
__IO usb_pipe_staus pp_status;
__IO usb_urb_state urb_state;
} usb_pipe;
typedef struct _usb_host_drv
{
uint8_t rx_buf[512U];
__IO uint32_t connect_status;
__IO uint32_t port_enabled;
__IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS];
usb_pipe pipe[USBFS_MAX_TX_FIFOS];
} usb_host_drv;
typedef struct _usb_core_driver
{
usb_core_basic bp;
usb_core_regs regs;
usb_host_drv host;
} usb_core_driver;
/* initializes USB core for host mode */
usb_status usb_host_init (usb_core_driver *pudev);
/* initialize host pipe */
usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num);
/* prepare host pipe for transferring packets */
usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num);
/* halt host pipe */
usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num);
/* configure host pipe to do ping operation */
usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num);
/* reset host port */
uint32_t usb_port_reset (usb_core_driver *pudev);
/* control the VBUS to power */
void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state);
/* stop the USB host and clean up FIFO */
void usb_host_stop (usb_core_driver *pudev);
//__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev)
uint32_t usb_frame_even (usb_core_driver *pudev);
//{
// return !(pudev->regs.hr->HFINFR & 0x01U);
//}
//__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock)
void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) ;
//{
//pudev->regs.hr->HCTL &= ~HCTL_CLKSEL;
// pudev->regs.hr->HCTL |= clock;
//}
uint32_t usb_port_read (usb_core_driver *pudev);
//inline uint32_t usb_port_read (usb_core_driver *pudev)
//{
// return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
//}
uint32_t usb_curspeed_get (usb_core_driver *pudev);
//inline uint32_t usb_curspeed_get (usb_core_driver *pudev)
//{
// return *pudev->regs.HPCS & HPCS_PS;
//}
//__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *pudev)
uint32_t usb_curframe_get (usb_core_driver *pudev);
//{
// return (pudev->regs.hr->HFINFR & 0xFFFFU);
//}
#endif /* __DRV_USB_HOST_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h
-62
View File
@@ -1,62 +0,0 @@
/*!
\file drv_usb_hw.h
\brief usb hardware configuration header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __DRV_USB_HW_H
#define __DRV_USB_HW_H
#include "usb_conf.h"
/* configure USB clock */
void usb_rcu_config (void);
/* configure USB interrupt */
void usb_intr_config (void);
/* initializes delay unit using Timer2 */
void usb_timer_init (void);
/* delay in micro seconds */
void usb_udelay (const uint32_t usec);
/* delay in milli seconds */
void usb_mdelay (const uint32_t msec);
#ifdef USE_HOST_MODE
/* configure USB VBus */
void usb_vbus_config (void);
/* drive usb VBus */
void usb_vbus_drive (uint8_t State);
#endif /* USE_HOST_MODE */
#endif /* __DRV_USB_HW_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h
-666
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h
-52
View File
@@ -1,52 +0,0 @@
/*!
\file drv_usbd_int.h
\brief USB device mode interrupt header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __DRV_USBD_INT_H
#define __DRV_USBD_INT_H
#include "drv_usb_core.h"
#include "drv_usb_dev.h"
/* USB device-mode interrupts global service routine handler */
void usbd_isr (usb_core_driver *udev);
#ifdef USB_HS_DEDICATED_EP1_ENABLED
uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev);
uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev);
#endif
#endif /* __DRV_USBD_INT_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h
-49
View File
@@ -1,49 +0,0 @@
/*!
\file drv_usbh_int.h.h
\brief USB host mode interrupt management header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __DRV_USBH_INT_H
#define __DRV_USBH_INT_H
#include "drv_usb_host.h"
typedef struct _usbh_int_cb
{
uint8_t (*SOF) (usb_core_driver *pudev);
} usbh_int_cb;
extern usbh_int_cb *usbh_int_fop;
uint32_t usbh_isr (usb_core_driver *pudev);
#endif /* __DRV_USBH_INT_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h
-237
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usb_conf.h
-98
View File
@@ -1,98 +0,0 @@
#ifndef __USB_CONF_H
#define __USB_CONF_H
#include <stddef.h>
#include "gd32vf103.h"
//#ifndef USE_USB_FS
//#define USE_USB_HS
//#endif
#define USE_USB_FS
#ifdef USE_USB_FS
#define USB_FS_CORE
#endif
#ifdef USE_USB_HS
#define USB_HS_CORE
#endif
#ifdef USB_FS_CORE
#define RX_FIFO_FS_SIZE 128
#define TX0_FIFO_FS_SIZE 64
#define TX1_FIFO_FS_SIZE 128
#define TX2_FIFO_FS_SIZE 0
#define TX3_FIFO_FS_SIZE 0
#define USB_RX_FIFO_FS_SIZE 128
#define USB_HTX_NPFIFO_FS_SIZE 96
#define USB_HTX_PFIFO_FS_SIZE 96
#endif /* USB_FS_CORE */
#ifdef USB_HS_CORE
#define RX_FIFO_HS_SIZE 512
#define TX0_FIFO_HS_SIZE 128
#define TX1_FIFO_HS_SIZE 372
#define TX2_FIFO_HS_SIZE 0
#define TX3_FIFO_HS_SIZE 0
#define TX4_FIFO_HS_SIZE 0
#define TX5_FIFO_HS_SIZE 0
#ifdef USE_ULPI_PHY
#define USB_OTG_ULPI_PHY_ENABLED
#endif
#ifdef USE_EMBEDDED_PHY
#define USB_OTG_EMBEDDED_PHY_ENABLED
#endif
#define USB_OTG_HS_INTERNAL_DMA_ENABLED
#define USB_OTG_HS_DEDICATED_EP1_ENABLED
#endif /* USB_HS_CORE */
#ifndef USB_SOF_OUTPUT
#define USB_SOF_OUTPUT 0
#endif
#ifndef USB_LOW_POWER
#define USB_LOW_POWER 0
#endif
#ifndef USE_HOST_MODE
#define USE_DEVICE_MODE
#endif
//#define USE_HOST_MODE
//#define USE_DEVICE_MODE
//#define USE_OTG_MODE
#ifndef USB_FS_CORE
#ifndef USB_HS_CORE
#error "USB_HS_CORE or USB_FS_CORE should be defined"
#endif
#endif
#ifndef USE_DEVICE_MODE
#ifndef USE_HOST_MODE
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
#endif
#endif
#ifndef USE_USB_HS
#ifndef USE_USB_FS
#error "USE_USB_HS or USE_USB_FS should be defined"
#endif
#endif
/****************** C Compilers dependant keywords ****************************/
/* In HS mode and when the DMA is used, all variables and data structures dealing
with the DMA during the transaction process should be 4-bytes aligned */
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
#if defined (__GNUC__) /* GNU Compiler */
#define __ALIGN_END __attribute__ ((aligned(4)))
#define __ALIGN_BEGIN
#endif /* __GNUC__ */
#else
#define __ALIGN_BEGIN
#define __ALIGN_END
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
#endif /* __USB_CONF_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h
-10
View File
@@ -1,10 +0,0 @@
#ifndef __USBD_CONF_H
#define __USBD_CONF_H
#include "usb_conf.h"
#define USBD_CFG_MAX_NUM 1
#define USBD_ITF_MAX_NUM 1
#endif /* __USBD_CONF_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbd_core.h
-95
View File
@@ -1,95 +0,0 @@
/*!
\file usbd_core.h
\brief USB device mode core functions protype
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USBD_CORE_H
#define __USBD_CORE_H
#include "drv_usb_core.h"
#include "drv_usb_dev.h"
typedef enum
{
USBD_OK = 0, /*!< status OK */
USBD_BUSY, /*!< status busy */
USBD_FAIL, /*!< status fail */
} usbd_status;
enum _usbd_status {
USBD_DEFAULT = 1, /*!< default status */
USBD_ADDRESSED = 2, /*!< address send status */
USBD_CONFIGURED = 3, /*!< configured status */
USBD_SUSPENDED = 4 /*!< suspended status */
};
/* function declarations */
/* device connect */
void usbd_connect (usb_core_driver *udev);
/* device disconnect */
void usbd_disconnect (usb_core_driver *udev);
/* set USB device address */
void usbd_addr_set (usb_core_driver *udev, uint8_t addr);
/* initailizes the USB device-mode stack and load the class driver */
void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core);
/* endpoint initialization */
uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc);
/* configure the endpoint when it is disabled */
uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr);
/* endpoint prepare to receive data */
uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len);
/* endpoint prepare to transmit data */
uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len);
/* set an endpoint to STALL status */
uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr);
/* clear endpoint STALLed status */
uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr);
/* flush the endpoint FIFOs */
uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr);
/* get the received data length */
uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num);
#endif /* __USBD_CORE_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h
-114
View File
@@ -1,114 +0,0 @@
/*!
\file usbd_enum.h
\brief USB enumeration definitions
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USBD_ENUM_H
#define __USBD_ENUM_H
#include "usbd_core.h"
#include "usbd_conf.h"
#include <wchar.h>
#ifndef NULL
#define NULL 0U
#endif
typedef enum _usb_reqsta {
REQ_SUPP = 0x0U, /* request support */
REQ_NOTSUPP = 0x1U /* request not support */
} usb_reqsta;
/* string descriptor index */
enum _str_index
{
STR_IDX_LANGID = 0x0U, /* language ID string index */
STR_IDX_MFC = 0x1U, /* manufacturer string index */
STR_IDX_PRODUCT = 0x2U, /* product string index */
STR_IDX_SERIAL = 0x3U, /* serial string index */
STR_IDX_CONFIG = 0x4U, /* configuration string index */
STR_IDX_ITF = 0x5U, /* interface string index */
STR_IDX_MAX = 0x6U /* string maximum index */
};
typedef enum _usb_pwrsta {
USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */
USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */
} usb_pwrsta;
typedef enum _usb_feature
{
USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */
USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */
USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */
} usb_feature;
#define ENG_LANGID 0x0409U /* english language ID */
#define CHN_LANGID 0x0804U /* chinese language ID */
/* USB device exported macros */
#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U))
#define WIDE_STRING(string) _WIDE_STRING(string)
#define _WIDE_STRING(string) L##string
#define USBD_STRING_DESC(string) \
(void *)&(const struct { \
uint8_t _len; \
uint8_t _type; \
wchar_t _data[sizeof(string)]; \
}) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \
USB_DESCTYPE_STR, \
WIDE_STRING(string) \
}
/* function declarations */
/* handle USB standard device request */
usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req);
/* handle USB device class request */
usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req);
/* handle USB vendor request */
usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req);
/* handle USB enumeration error */
void usbd_enum_error (usb_core_driver *udev, usb_req *req);
/* convert hex 32bits value into unicode char */
void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len);
#endif /* __USBD_ENUM_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h
-64
View File
@@ -1,64 +0,0 @@
/*!
\file usbd_transc.h
\brief USB transaction core functions prototype
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USBD_TRANSC_H
#define __USBD_TRANSC_H
#include "usbd_core.h"
/* function declarations */
/* USB send data in the control transaction */
usbd_status usbd_ctl_send (usb_core_driver *udev);
/* USB receive data in control transaction */
usbd_status usbd_ctl_recev (usb_core_driver *udev);
/* USB send control transaction status */
usbd_status usbd_ctl_status_send (usb_core_driver *udev);
/* USB control receive status */
usbd_status usbd_ctl_status_recev (usb_core_driver *udev);
/* USB setup stage processing */
uint8_t usbd_setup_transc (usb_core_driver *udev);
/* data out stage processing */
uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0")));
/* data in stage processing */
uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0")));
#endif /* __USBD_TRANSC_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h
-9
View File
@@ -1,9 +0,0 @@
#ifndef __USBH_CONF_H
#define __USBH_CONF_H
#define USBH_MAX_EP_NUM 2
#define USBH_MAX_INTERFACES_NUM 2
#define USBH_MSC_MPS_SIZE 0x200
#endif /* __USBH_CONF_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbh_core.h
-219
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h
-78
View File
@@ -1,78 +0,0 @@
/*!
\file usbh_enum.h
\brief USB host mode USB enumeration header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USBH_ENUM_H
#define __USBH_ENUM_H
#include "usb_conf.h"
#include "usbh_core.h"
/* get the next descriptor header */
usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr);
/* configure USB control status parameters */
void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len);
/* get device descriptor from the USB device */
usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t len);
/* get configuration descriptor from the USB device */
usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len);
/* get string descriptor from the USB device */
usbh_status usbh_strdesc_get (usb_core_driver *pudev,
usbh_host *puhost,
uint8_t str_index,
uint8_t *buf,
uint16_t len);
/* set the configuration value to the connected device */
usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t config);
/* set the address to the connected device */
usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr);
/* clear or disable a specific feature */
usbh_status usbh_clrfeature (usb_core_driver *pudev,
usbh_host *puhost,
uint8_t ep_num,
uint8_t pp_num);
/* set the interface value to the connected device */
usbh_status usbh_setinterface (usb_core_driver *pudev,
usbh_host *puhost,
uint8_t ep_num,
uint8_t alter_setting);
#endif /* __USBH_ENUM_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h
-70
View File
@@ -1,70 +0,0 @@
/*!
\file usbh_pipe.h
\brief USB host mode pipe header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USBH_PIPE_H
#define __USBH_PIPE_H
#include "usbh_core.h"
#define HC_MAX 8U
#define HC_OK 0x0000U
#define HC_USED 0x8000U
#define HC_ERROR 0xFFFFU
#define HC_USED_MASK 0x7FFFU
/* allocate a new pipe */
uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr);
/* delete all USB host pipe */
uint8_t usbh_pipe_delete (usb_core_driver *pudev);
/* free a pipe */
uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num);
/* create a pipe */
uint8_t usbh_pipe_create (usb_core_driver *pudev,
usb_dev_prop *udev,
uint8_t pp_num,
uint8_t ep_type,
uint16_t ep_mpl);
/* modify a pipe */
uint8_t usbh_pipe_update (usb_core_driver *pudev,
uint8_t pp_num,
uint8_t dev_addr,
uint32_t dev_speed,
uint16_t ep_mpl);
#endif /* __USBH_PIPE_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h
-54
View File
@@ -1,54 +0,0 @@
/*!
\file usbh_transc.h
\brief USB host mode transactions header file
\version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USBH_TRANSC_H
#define __USBH_TRANSC_H
#include "usb_conf.h"
#include "usbh_core.h"
/* send the setup packet to the USB device */
usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num);
/* send a data packet to the USB device */
usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* receive a data packet from the USB device */
usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* USB control transfer handler */
usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost);
#endif /* __USBH_TRANSC_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103.h
-389
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_adc.h
-399
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h
-229
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_can.h
-720
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_crc.h
-80
View File
@@ -1,80 +0,0 @@
/*!
\file gd32vf103_crc.h
\brief definitions for the CRC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_CRC_H
#define GD32VF103_CRC_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h"
/* CRC definitions */
#define CRC CRC_BASE
/* registers definitions */
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
void crc_data_register_reset(void);
/* read the value of the data register */
uint32_t crc_data_register_read(void);
/* read the value of the free data register */
uint8_t crc_free_data_register_read(void);
/* write data to the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* calculate the CRC value of a 32-bit data */
uint32_t crc_single_data_calculate(uint32_t sdata);
/* calculate the CRC value of an array of 32-bit values */
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
#endif /* GD32VF103_CRC_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_dac.h
-244
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h
-111
View File
@@ -1,111 +0,0 @@
/*!
\file gd32vf103_dbg.h
\brief definitions for the DBG
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_DBG_H
#define GD32VF103_DBG_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
/* DBG definitions */
#define DBG DBG_BASE
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
/* DBG_CTL */
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
/* constants definitions */
/* debug hold when core is halted */
typedef enum
{
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
}dbg_periph_enum;
/* DBG low power mode configurations */
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
/* function declarations */
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/* low power behavior configuration */
/* enable low power behavior when the MCU is in debug mode */
void dbg_low_power_enable(uint32_t dbg_low_power);
/* disable low power behavior when the MCU is in debug mode */
void dbg_low_power_disable(uint32_t dbg_low_power);
/* peripheral behavior configuration */
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
#endif /* GD32VF103_DBG_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_dma.h
-285
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h
-129
View File
@@ -1,129 +0,0 @@
/*!
\file gd32vf103_exmc.h
\brief definitions for the EXMC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_EXMC_H
#define GD32VF103_EXMC_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h"
/* EXMC definitions */
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
/* registers definitions */
/* NOR/PSRAM */
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
/* bits definitions */
/* NOR/PSRAM */
/* EXMC_SNCTLx, x=0 */
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
/* EXMC_SNTCFGx, x=0 */
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
/* constants definitions */
/* EXMC NOR/SRAM timing initialize struct */
typedef struct
{
uint32_t bus_latency; /*!< configure the bus latency */
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
}exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize struct */
typedef struct
{
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */
uint32_t memory_write; /*!< enable or disable the write operation */
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
uint32_t databus_width; /*!< specifies the databus width of external memory */
uint32_t memory_type; /*!< specifies the type of external memory */
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */
}exmc_norsram_parameter_struct;
/* EXMC register address */
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
/* NOR bank memory data bus width */
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
/* NOR bank memory type */
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
/* EXMC NOR/SRAM bank region definition */
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
/* EXMC NWAIT signal polarity configuration */
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
/* function declarations */
/* deinitialize EXMC NOR/SRAM region */
void exmc_norsram_deinit(uint32_t norsram_region);
/* exmc_norsram_parameter_struct parameter initialize */
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
/* initialize EXMC NOR/SRAM region */
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
/* EXMC NOR/SRAM bank enable */
void exmc_norsram_enable(uint32_t norsram_region);
/* EXMC NOR/SRAM bank disable */
void exmc_norsram_disable(uint32_t norsram_region);
#endif /* GD32VF103_EXMC_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_exti.h
-248
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h
-314
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h
-107
View File
@@ -1,107 +0,0 @@
/*!
\file gd32vf103_fwdgt.h
\brief definitions for the FWDGT
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_FWDGT_H
#define GD32VF103_FWDGT_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
/* constants definitions */
/* psc register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
/* function declarations */
/* enable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_enable(void);
/* disable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_disable(void);
/* start the free watchdog timer counter */
void fwdgt_enable(void);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32VF103_FWDGT_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h
-423
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h
-344
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h
-59
View File
@@ -1,59 +0,0 @@
/*!
\file gd32vf103_libopt.h
\brief library optional for gd32vf103
\version 2019-6-5, V1.0.0, demo for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_LIBOPT_H
#define GD32VF103_LIBOPT_H
#include "gd32vf103.h"
#include "gd32vf103_adc.h"
#include "gd32vf103_bkp.h"
#include "gd32vf103_can.h"
#include "gd32vf103_crc.h"
#include "gd32vf103_dac.h"
#include "gd32vf103_dma.h"
#include "gd32vf103_exmc.h"
#include "gd32vf103_exti.h"
#include "gd32vf103_fmc.h"
#include "gd32vf103_gpio.h"
#include "gd32vf103_i2c.h"
#include "gd32vf103_fwdgt.h"
#include "gd32vf103_dbg.h"
#include "gd32vf103_pmu.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_rtc.h"
#include "gd32vf103_spi.h"
#include "gd32vf103_timer.h"
#include "gd32vf103_usart.h"
#include "gd32vf103_wwdgt.h"
#endif /* GD32VF103_LIBOPT_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h
-127
View File
@@ -1,127 +0,0 @@
/*!
\file gd32vf103_pmu.h
\brief definitions for the PMU
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_PMU_H
#define GD32VF103_PMU_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h"
/* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */
/* registers definitions */
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
/* bits definitions */
/* PMU_CTL */
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
/* PMU_CS */
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS_STBF BIT(1) /*!< standby flag */
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
/* PMU flag definitions */
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
/* PMU ldo definitions */
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
/* PMU flag reset definitions */
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
/* function declarations */
/* reset PMU registers */
void pmu_deinit(void);
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t lvdt_n);
/* disable PMU lvd */
void pmu_lvd_disable(void);
/* set PMU mode */
/* PMU work at sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* PMU work at deepsleep mode */
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
/* PMU work at standby mode */
void pmu_to_standbymode(uint8_t standbymodecmd);
/* enable PMU wakeup pin */
void pmu_wakeup_pin_enable(void);
/* disable PMU wakeup pin */
void pmu_wakeup_pin_disable(void);
/* backup related functions */
/* enable write access to the registers in backup domain */
void pmu_backup_write_enable(void);
/* disable write access to the registers in backup domain */
void pmu_backup_write_disable(void);
/* flag functions */
/* get flag state */
FlagStatus pmu_flag_get(uint32_t flag);
/* clear flag bit */
void pmu_flag_clear(uint32_t flag_reset);
#endif /* GD32VF103_PMU_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h
-760
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h
-150
View File
@@ -1,150 +0,0 @@
/*!
\file gd32vf103_rtc.h
\brief definitions for the RTC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_RTC_H
#define GD32VF103_RTC_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h"
/* RTC definitions */
#define RTC RTC_BASE
/* registers definitions */
#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
/* bits definitions */
/* RTC_INTEN */
#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
/* RTC_CTL */
#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
/* RTC_PSCH */
#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
/* RTC_PSCL */
#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
/* RTC_DIVH */
#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
/* RTC_DIVL */
#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
/* RTC_CNTH */
#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
/* RTC_CNTL */
#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
/* RTC_ALRMH */
#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
/* RTC_ALRML */
#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
/* constants definitions */
/* RTC interrupt enable or disable definitions */
#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
/* RTC interrupt flag definitions */
#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
/* RTC flag definitions */
#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
/* function declarations */
/* initialization functions */
/* enter RTC configuration mode */
void rtc_configuration_mode_enter(void);
/* exit RTC configuration mode */
void rtc_configuration_mode_exit(void);
/* set RTC counter value */
void rtc_counter_set(uint32_t cnt);
/* set RTC prescaler value */
void rtc_prescaler_set(uint32_t psc);
/* operation functions */
/* wait RTC last write operation finished flag set */
void rtc_lwoff_wait(void);
/* wait RTC registers synchronized flag set */
void rtc_register_sync_wait(void);
/* set RTC alarm value */
void rtc_alarm_config(uint32_t alarm);
/* get RTC counter value */
uint32_t rtc_counter_get(void);
/* get RTC divider value */
uint32_t rtc_divider_get(void);
/* flag & interrupt functions */
/* get RTC flag status */
FlagStatus rtc_flag_get(uint32_t flag);
/* clear RTC flag status */
void rtc_flag_clear(uint32_t flag);
/* get RTC interrupt flag status */
FlagStatus rtc_interrupt_flag_get(uint32_t flag);
/* clear RTC interrupt flag status */
void rtc_interrupt_flag_clear(uint32_t flag);
/* enable RTC interrupt */
void rtc_interrupt_enable(uint32_t interrupt);
/* disable RTC interrupt */
void rtc_interrupt_disable(uint32_t interrupt);
#endif /* GD32VF103_RTC_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_spi.h
-343
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_timer.h
-724
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_usart.h
-378
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h
-88
View File
@@ -1,88 +0,0 @@
/*!
\file gd32vf103_wwdgt.h
\brief definitions for the WWDGT
\version 2019-6-5, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_WWDGT_H
#define GD32VF103_WWDGT_H
#include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h"
/* WWDGT definitions */
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
/* registers definitions */
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
/* bits definitions */
/* WWDGT_CTL */
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
/* WWDGT_CFG */
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
/* WWDGT_STAT */
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
/* constants definitions */
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
/* function declarations */
/* reset the window watchdog timer configuration */
void wwdgt_deinit(void);
/* start the window watchdog timer counter */
void wwdgt_enable(void);
/* configure the window watchdog timer counter value */
void wwdgt_counter_update(uint16_t counter_value);
/* configure counter value, window value, and prescaler divider value */
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
/* enable early wakeup interrupt of WWDGT */
void wwdgt_interrupt_enable(void);
/* check early wakeup interrupt state of WWDGT */
FlagStatus wwdgt_flag_get(void);
/* clear early wakeup interrupt state of WWDGT */
void wwdgt_flag_clear(void);
#endif /* GD32VF103_WWDGT_H */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h
-16
View File
@@ -1,16 +0,0 @@
// See LICENSE for license details.
#ifndef _NUCLEI_SDK_SOC_H
#define _NUCLEI_SDK_SOC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "gd32vf103.h"
#include "gd32vf103_libopt.h"
#ifdef __cplusplus
}
#endif
#endif
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Include/system_gd32vf103.h
-80
View File
@@ -1,80 +0,0 @@
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*******************************************************************************
* @file system_gd32vf103.h
* @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for
* Device gd32vf103
* @version V1.00
* @date 7. Jan 2020
******************************************************************************/
#ifndef __SYSTEM_GD32VF103_H__
#define __SYSTEM_GD32VF103_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
* \brief Register an exception handler for exception code EXCn
*/
extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler);
/**
* \brief Get current exception handler for exception code EXCn
*/
extern unsigned long Exception_Get_EXC(uint32_t EXCn);
/**
* \brief Initialize eclic config
*/
extern void ECLIC_Init(void);
/**
* \brief Initialize a specific IRQ and register the handler
* \details
* This function set vector mode, trigger mode and polarity, interrupt level and priority,
* assign handler for specific IRQn.
*/
extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_GD32VF103_H__ */
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c
-319
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c
-749
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c
-514
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c
-595
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c
-536
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c
-265
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c
-329
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c
-696
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c
-254
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c
-441
View File
File diff suppressed because it is too large. Load diff
bsp/nuclei/nuclei_sdk/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c
-549
View File
File diff suppressed because it is too large. Load diff
Loaded 100 of 164 files, more files were not shown because too many files have changed in this diff. Show more