修改部分格式问题

[add] 增加ft2004 BSP

bsp/ft2004/Kconfig

@@ -0,0 +1,30 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+
+config FT2004
+    bool
+    select ARCH_ARM_CORTEX_A
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+
+source "./libraries/Kconfig"

bsp/ft2004/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/ft2004/SConstruct

@@ -0,0 +1,32 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'ft2004.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/ft2004/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/ft2004/applications/main.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-05     Bernard      the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "ft_cpu.h"
+#include "ft_generic_timer.h"
+
+#include <board.h>
+
+#ifdef RT_USING_SMP
+
+struct rt_thread test_core[RT_CPUS_NR];
+static char *core_thread_name[RT_CPUS_NR] = {
+    "core0_test",
+    "core1_test",
+    "core2_test",
+    "core3_test"};
+static rt_uint8_t core_stack[RT_CPUS_NR][1024];
+
+static void demo_core_thread(void *parameter)
+{
+    rt_base_t level;
+    while (1)
+    {
+        /* code */
+        level = rt_cpus_lock();
+        rt_kprintf("Hi, core%d \r\n", FCpu_IdGet());
+        rt_cpus_unlock(level);
+        rt_thread_mdelay(20000);
+    }
+}
+
+void demo_core(void)
+{
+    rt_ubase_t i;
+    rt_uint8_t cpu_id = 0;
+    for (i = 0; i < RT_CPUS_NR; i++)
+    {
+        cpu_id = i;
+        rt_thread_init(&test_core[i],
+                       core_thread_name[i],
+                       demo_core_thread,
+                       RT_NULL,
+                       &core_stack[i],
+                       1024,
+                       20,
+                       32);
+
+        rt_thread_control(&test_core[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id);
+        rt_thread_startup(&test_core[i]);
+    }
+}
+#endif
+
+int main(void)
+{
+    int count = 1;
+
+#ifdef RT_USING_SMP
+    demo_core();
+#endif
+
+    while (count++)
+    {
+        rt_thread_mdelay(2000);
+    }
+
+    return RT_EOK;
+}

bsp/ft2004/drivers/SConscript

@@ -0,0 +1,14 @@
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.S')
+src	+= Glob('*.c')
+
+
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/ft2004/drivers/board.c

@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-03-04     Carl    the first version
+ *
+ */
+
+#include <rtthread.h>
+#include "ft_printf.h"
+#include "ft_assert.h"
+#include "ft_cpu.h"
+#include "ft_psci.h"
+#include "ft_parameters.h"
+#include "board.h"
+#include "gtimer.h"
+#include "ft_generic_timer.h"
+#include <gicv3.h>
+
+#include "interrupt.h"
+#include <mmu.h>
+#include "cp15.h"
+#include "ft2004.h"
+
+#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC)
+
+struct mem_desc platform_mem_desc[] = {
+    {0x80000000,
+     0x80000000 + 0x7f000000,
+     0x80000000,
+     DDR_MEM},
+    {0, //< QSPI
+     0x1FFFFFFF,
+     0,
+     DEVICE_MEM},
+    {0x20000000, //<! LPC
+     0x27FFFFFF,
+     0x20000000,
+     DEVICE_MEM},
+    {FT_DEV_BASE_ADDR, //<! Device register
+     FT_DEV_END_ADDR,
+     FT_DEV_BASE_ADDR,
+     DEVICE_MEM},
+    {0x30000000, //<! debug
+     0x39FFFFFF,
+     0x30000000,
+     DEVICE_MEM},
+    {0x3A000000, //<! Internal register space in the on-chip network
+     0x3AFFFFFF,
+     0x3A000000,
+     DEVICE_MEM},
+    {FT_PCI_CONFIG_BASEADDR,
+     FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
+     FT_PCI_CONFIG_BASEADDR,
+     DEVICE_MEM},
+    {FT_PCI_IO_CONFIG_BASEADDR,
+     FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
+     FT_PCI_IO_CONFIG_BASEADDR,
+     DEVICE_MEM},
+    {FT_PCI_MEM32_BASEADDR,
+     FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
+     FT_PCI_MEM32_BASEADDR,
+     DEVICE_MEM},
+};
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
+
+rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return FT_GICV3_DISTRIBUTOR_BASEADDRESS;
+}
+
+static rt_uint32_t timerStep;
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    gtimer_set_load_value(timerStep);
+    rt_tick_increase();
+}
+
+int rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(30, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(30);
+    timerStep = gtimer_get_counter_frequency();
+    timerStep /= RT_TICK_PER_SECOND;
+    gtimer_set_load_value(timerStep);
+    gtimer_set_control(1);
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+static void AssertCallback(const char *File, s32 Line)
+{
+    Ft_printf("Assert Error is %s : %d \r\n", File, Line);
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
+#endif
+
+/**
+ * This function will initialize hardware board
+ */
+void rt_hw_board_init(void)
+{
+    /* bsp debug */
+    FCpu_SpinLockInit();
+    Ft_GenericTimer_Init(0, RT_NULL);
+    Ft_vsprintfRegister((vsprintf_p)rt_vsprintf);
+    Ft_assertSetCallBack((Ft_assertCallback)AssertCallback);
+
+    /* interrupt init */
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 0, 0);
+
+#if RT_CPUS_NR == 2
+    Ft_printf("arm_gic_redist_address_set is 2 \r\n");
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
+#elif RT_CPUS_NR == 3
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 2 * (2U << 16), 2);
+#elif RT_CPUS_NR == 4
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 2 * (2U << 16), 2);
+    arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 3 * (2U << 16), 3);
+#endif
+
+    rt_hw_interrupt_init();
+
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+/* 初始化内存池 */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+#ifdef RT_USING_SMP
+    /* install IPI handle */
+    rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
+    rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
+    rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
+#endif
+}
+
+static void ft_reset(void)
+{
+    FPsci_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
+
+/*@}*/

bsp/ft2004/drivers/board.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard    the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "ft_parameters.h"
+#include "ft2004.h"
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+
+#define HEAP_END (void *)(0x80000000 + 1024 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/ft2004/drivers/drv_can.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-05-11     Carl        the first version
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <board.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+#include "ft_can.h"
+
+    struct ft2004_can
+    {
+        const char *name;
+        FCan_t can_handle;
+        struct rt_semaphore recv_semaphore;
+        struct rt_can_device device; /* inherit from can device */
+    };
+
+    int rt_hw_can_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !

bsp/ft2004/drivers/drv_eth.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-03-09     Carl        the first version
+ */
+#ifndef __DRV_ETH_H__
+#define __DRV_ETH_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define FT_NETIF_LINKUP 0x1U
+#define FT_NETIF_DOWN 0x2U
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !

bsp/ft2004/drivers/drv_log.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG               "drv"
+#else
+#define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>

bsp/ft2004/drivers/drv_qspi.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-11     Carl      the first version
+ */
+
+#ifndef __DRT_QSPI_H__
+#define __DRT_QSPI_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define FT2004_QSPI_NAME "qspi"
+
+    rt_err_t ft2004_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !DRT_QSPI_H

bsp/ft2004/drivers/drv_qspi_flash.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-08     Carl        the first version
+ */
+
+#include <board.h>
+#include <drv_qspi.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <finsh.h>
+
+#ifdef BSP_USE_QSPI
+
+#include "spi_flash.h"
+#include "spi_flash_sfud.h"
+#define _QSPI_DEVICE_NAME "qspiflash"
+
+static int
+rt_hw_qspi_flash_with_sfud_init(void)
+{
+    ft2004_qspi_bus_attach_device(FT2004_QSPI_NAME, _QSPI_DEVICE_NAME, 1, RT_NULL, RT_NULL);
+
+    /* init gd */
+    rt_kprintf("start rt_sfud_flash_probe \r\n");
+    if (RT_NULL == rt_sfud_flash_probe("GD25LQ256D", _QSPI_DEVICE_NAME))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init);
+
+#endif /* BSP_USING_QSPI_FLASH */

bsp/ft2004/drivers/drv_sdcard.c

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-03-18     Carl      the first version
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_SDC
+
+#include <dfs_elm.h>
+#include <dfs_fs.h>
+#include <dfs_posix.h>
+#include "drv_sdctrl.h"
+
+#define DBG_TAG "app.card"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+static rt_err_t _sdcard_mount(void)
+{
+    rt_device_t device;
+
+    device = rt_device_find("sd0");
+    rt_kprintf("rt_device_find %x \r\n", device);
+    if (device == NULL)
+    {
+        mmcsd_wait_cd_changed(0);
+        ft2004_mmcsd_change();
+        if (mmcsd_wait_cd_changed(rt_tick_from_millisecond(5000)) == -RT_ETIMEOUT)
+        {
+            rt_kprintf("timeout \r\n");
+            return RT_ERROR;
+        }
+        device = rt_device_find("sd0");
+    }
+
+    rt_thread_mdelay(1000);
+    LOG_I("dfs_mount  \r\n");
+    if (device != RT_NULL)
+    {
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
+        {
+            LOG_I("sd card mount to '/'");
+        }
+        else
+        {
+            LOG_W("sd card mount to '/' failed!");
+            return RT_ERROR;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static void _sdcard_unmount(void)
+{
+    rt_thread_mdelay(200);
+    dfs_unmount("/");
+    LOG_I("Unmount \"/\"");
+
+    mmcsd_wait_cd_changed(0);
+    ft2004_mmcsd_change();
+    mmcsd_wait_cd_changed(rt_tick_from_millisecond(5000));
+    LOG_I("Unmount is over \r\n");
+}
+
+static void sd_mount(void *parameter)
+{
+    rt_uint8_t state = 0; /* 1. is valid card ,0 is removal */
+#ifdef BSP_SDC_IRQ_CARD_REMOVE
+    rt_uint32_t status;
+#endif
+    while (1)
+    {
+        switch (state)
+        {
+        case 0:
+            if (ft2004_card_status() == 1)
+            {
+#ifdef BSP_SDC_IRQ_CARD_REMOVE
+                ft2004_card_remove_check(0, RT_NULL); /* Clear removal flag bit */
+#endif
+                if (_sdcard_mount() == RT_EOK)
+                {
+                    state = 1;
+                }
+                else
+                {
+                    /* For the critical case of frequent plug */
+                    rt_kprintf("dfs_unmount \r\n");
+                    _sdcard_unmount();
+                    ft2004_sdctrl_reset();
+                }
+            }
+            else
+            {
+                rt_thread_mdelay(100);
+            }
+            break;
+        case 1:
+
+#ifdef BSP_SDC_IRQ_CARD_REMOVE
+            if (ft2004_card_remove_check(RT_WAITING_FOREVER, &status) == RT_EOK)
+            {
+                if (status & SDCTR_CARD_REMOVE_FLG)
+                {
+                    state = 0;
+                    _sdcard_unmount();
+                }
+            }
+#else
+            if (ft2004_card_status() == 0)
+            {
+                state = 0;
+                _sdcard_unmount();
+            }
+#endif
+            else
+            {
+                rt_thread_mdelay(100);
+            }
+            break;
+        default:
+            state = 0;
+            break;
+        }
+    }
+}
+
+int ft2004_sdcard_mount(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+                           8192, 2, 20);
+
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        LOG_E("create sd_mount thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(ft2004_sdcard_mount);
+
+#endif /* BSP_USING_SDCARD */

bsp/ft2004/drivers/drv_sdctrl.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-03-18     Carl      the first version
+ */
+
+#ifndef __DRV_SDCTRL_H__
+#define __DRV_SDCTRL_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define SDCTR_CMD_IS_COMPLETE_FLG 0x1UL /* Command is  complete */
+#define SDCTR_WRITE_IS_COMPLETE_FLG 0x2UL
+#define SDCTR_READ_IS_COMPLETE_FLG 0x4UL
+#define SDCTR_CMD_IS_ERROR_FLG 0x8UL
+#define SDCTR_CMD_CRC_IS_ERROR_FLG 0x10UL     /* Command CRC error */
+#define SDCTR_DMA_IS_ERROR_FLG 0x20UL         /*  */
+#define SDCTR_CARD_REMOVE_FLG 0x40UL          /* Card remove */
+#define SDCTR_CMD_TIMEOUT_FLG 0x70UL          /* command timeout */
+#define SDCTR_CMD_RECEIVE_IS_ERROR_FLG 0x80UL /*  CMD receive is error  */
+
+#ifndef SDCTR_BUFF_SIZE
+#define SDCTR_BUFF_SIZE (512 * 128)
+#endif
+
+#ifndef SDCTR_ALIGN_LEN
+#define SDCTR_ALIGN_LEN (32)
+#endif
+
+    void ft2004_mmcsd_change(void);
+    rt_bool_t ft2004_card_status(void);
+    rt_err_t ft2004_card_remove_check(rt_int32_t timeout, rt_uint32_t *status);
+    void ft2004_sdctrl_reset(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !

bsp/ft2004/drivers/drv_spi.h

@@ -0,0 +1,29 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-25 14:01:39
+ * @LastEditTime: 2021-04-29 09:40:13
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+#ifndef FT_DRIVERS_RTT_SPI_H
+#define FT_DRIVERS_RTT_SPI_H
+
+#include <rtthread.h>
+
+#define SPI_BUS_NAME "spi0"
+#define SPI_DEV_NAME "S25FS256"
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin);
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#endif

bsp/ft2004/drivers/drv_spi_flash.c

@@ -0,0 +1,43 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-25 14:01:16
+ * @LastEditTime: 2021-04-30 14:43:12
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include <board.h>
+#include <drv_spi.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <finsh.h>
+#include "ft_spi.h"
+
+#ifdef BSP_USE_SPI
+
+#include "spi_flash.h"
+#include "spi_flash_sfud.h"
+
+static int rt_hw_spi_flash_init(void)
+{
+    uint16_t cs_pin = 5;
+    rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_DEV_NAME, cs_pin);
+
+    rt_kprintf("attach spi flash\r\n");
+    /* lookup flah */
+    if (RT_NULL == rt_sfud_flash_probe("S25FS256S", SPI_DEV_NAME))
+    {
+        rt_kprintf("attach spi flash failed\r\n");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
+#endif

bsp/ft2004/drivers/drv_usart.c

@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-03-04     Carl      the first version
+ */
+
+#include "board.h"
+#include "drv_usart.h"
+#include "interrupt.h"
+#include "serial.h"
+#include "rtconfig.h"
+
+#ifdef RT_USING_SERIAL
+
+extern u32 FUart_GetInterruptMask(Ft_Uart *uart_ptr);
+
+static void Ft_Os_Uart_Callback(void *Args, u32 Event, u32 EventData);
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    Ft_Uart *uart_ptr = (Ft_Uart *)param;
+    FUart_InterruptHandler(uart_ptr);
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct drv_usart *uart = RT_NULL;
+    Ft_Uart *uart_ptr = RT_NULL;
+    u32 RegTemp;
+    u32 ret;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = rt_container_of(serial, struct drv_usart, serial);
+    uart_ptr = uart->handle;
+
+    RT_ASSERT(FUart_CfgInitialize(uart_ptr, FUart_LookupConfig(uart_ptr->Config.InstanceId)) == FST_SUCCESS);
+    FUart_SetHandler(uart_ptr, Ft_Os_Uart_Callback, serial);
+    rt_hw_interrupt_install(uart_ptr->Config.IsrNum, rt_hw_uart_isr, uart_ptr, "uart");
+    rt_hw_interrupt_umask(uart_ptr->Config.IsrNum);
+
+    //<! 设置波特率
+    ret = FUart_SetBaudRate(uart_ptr, cfg->baud_rate);
+    RT_ASSERT(ret == FST_SUCCESS);
+
+    //<! 打开接收中断
+    RegTemp = FUart_GetInterruptMask(uart_ptr);
+    RegTemp |= UARTMIS_RTMIS;
+    FUart_SetInterruptMask(uart_ptr, RegTemp);
+    FUart_SetOptions(uart_ptr, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN);
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct drv_usart *uart = RT_NULL;
+    Ft_Uart *uart_ptr = RT_NULL;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct drv_usart, serial);
+    uart_ptr = uart->handle;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        rt_hw_interrupt_mask(uart_ptr->Config.IsrNum);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        rt_hw_interrupt_umask(uart_ptr->Config.IsrNum);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static void Ft_Os_Uart_Callback(void *Args, u32 Event, u32 EventData)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)Args;
+
+    if (FUART_EVENT_RECV_DATA == Event || FUART_EVENT_RECV_TOUT == Event)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+    else if (FUART_EVENT_RECV_ERROR == Event)
+    {
+    }
+    else if (FUART_EVENT_SENT_DATA == Event)
+    {
+    }
+    else if (FUART_EVENT_PARE_FRAME_BRKE == Event)
+    {
+    }
+    else if (FUART_EVENT_RECV_ORERR == Event)
+    {
+    }
+
+    if (FUART_EVENT_SENT_DATA == Event)
+    {
+    }
+    else
+    {
+    }
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct drv_usart *uart = RT_NULL;
+    Ft_Uart *uart_ptr = RT_NULL;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct drv_usart, serial);
+    uart_ptr = uart->handle;
+
+    FUart_SendByte(uart_ptr->Config.BaseAddress, c);
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct drv_usart *uart = RT_NULL;
+    Ft_Uart *uart_ptr = RT_NULL;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct drv_usart, serial);
+    uart_ptr = uart->handle;
+
+    ch = FUart_GetChar(uart_ptr->Config.BaseAddress);
+    if (ch == 0xff)
+        ch = -1;
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+    {
+        uart_configure,
+        uart_control,
+        uart_putc,
+        uart_getc,
+};
+
+#ifdef RT_USING_UART0
+static Ft_Uart Ft_Uart0;
+static struct drv_usart _RtUart0;
+#endif
+
+#ifdef RT_USING_UART1
+static Ft_Uart Ft_Uart1;
+static struct drv_usart _RtUart1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    config.bufsz = RT_SERIAL_RB_BUFSZ;
+    _RtUart0.serial.ops = &_uart_ops;
+    _RtUart0.serial.config = config;
+    Ft_Uart0.Config.InstanceId = FT_UART0_ID;
+    _RtUart0.Handle = &Ft_Uart0;
+
+    rt_hw_serial_register(&_RtUart0.serial, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &_RtUart0);
+#endif
+
+#ifdef RT_USING_UART1
+    config.bufsz = RT_SERIAL_RB_BUFSZ;
+    _RtUart1.serial.ops = &_uart_ops;
+    _RtUart1.serial.config = config;
+    Ft_Uart1.Config.InstanceId = FT_UART1_ID;
+    _RtUart1.handle = &Ft_Uart1;
+    rt_hw_serial_register(&_RtUart1.serial, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &_RtUart1);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif /* RT_USING_SERIAL */

bsp/ft2004/drivers/drv_usart.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-03-04     Carl      the first version
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include "ft_uart.h"
+
+struct drv_usart
+{
+    Ft_Uart *handle;
+
+    struct rt_serial_device serial;
+};
+
+#endif // !

bsp/ft2004/drivers/ft2004.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-29     Carl    the first version
+ *
+ */
+
+#include <rtthread.h>
+#include "ft2004.h"
+#include "gicv3.h"
+
+rt_uint64_t get_main_cpu_affval(void)
+{
+    return 0;
+}
+
+rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list)
+{
+
+    if (*cpu_mask == 0)
+    {
+        return 0;
+    }
+
+    *target_list = 0;
+    *cluster_id = 0;
+
+    if (*cpu_mask & 0x3)
+    {
+        if ((*cpu_mask & 0x3) == 0x3)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x1))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0x3;
+    }
+    else if (*cpu_mask & 0xc)
+    {
+        *cluster_id = 0x100;
+        if ((*cpu_mask & 0xc) == 0xc)
+        {
+            *target_list = 3;
+        }
+        else if ((*cpu_mask & 0x4))
+        {
+            *target_list = 1;
+        }
+        else
+        {
+            *target_list = 2;
+        }
+        *cpu_mask &= ~0xc;
+    }
+    else
+    {
+        *cpu_mask = 0;
+        return 0;
+    }
+
+    return 1;
+}
+
+#ifdef RT_USING_SMP
+
+void send_core_isg(void)
+{
+    for (size_t i = 0; i <= 0xf; i++)
+    {
+        /* code */
+        rt_kprintf("i %x \r\n", i);
+        arm_gic_send_affinity_sgi(0, 0, i, 0);
+        rt_thread_mdelay(100);
+    }
+}
+MSH_CMD_EXPORT(send_core_isg, send_core_isg);
+
+#endif

bsp/ft2004/drivers/ft2004.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-29     Carl    the first version
+ *
+ */
+
+#ifndef __FT2004_H__
+#define __FT2004_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#define ARM_GIC_NR_IRQS 160
+#define ARM_GIC_MAX_NR 1
+#define MAX_HANDLERS 160
+#define GIC_IRQ_START 0
+
+rt_uint64_t get_main_cpu_affval(void);
+
+#endif // !

bsp/ft2004/drivers/ft2004_cpu.S

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-29     Carl    the first version
+ *
+ */
+
+#include "rtconfig.h"
+
+.globl rt_hw_cpu_id 
+rt_hw_cpu_id:
+    mrc p15, 0, r0, c0, c0, 5
+    ubfx r0, r0, #0, #12
+    cmp r0, #0
+    beq core0
+    cmp r0, #1
+    beq core1 
+    cmp r0, #256 
+    beq core2 
+    mov r1 ,#257
+    cmp r0, r1
+    beq core3
+    b default
+core0:
+    mov r0, #0
+    b return 
+core1: 
+    mov r0, #1
+    b return 
+core2: 
+    mov r0, #2
+    b return 
+core3: 
+    mov r0, #3
+    b return 
+default: 
+    and r0, r0, #15
+return: 
+    bx lr 
+

bsp/ft2004/drivers/secondary_cpu.c

@@ -0,0 +1,86 @@
+/*
+ * @ : Copyright (c) 2020 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-05-26 10:09:45
+ * @LastEditTime: 2021-05-26 10:31:44
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include <rtthread.h>
+#include "board.h"
+#include <gicv3.h>
+
+#ifdef RT_USING_SMP
+#include <interrupt.h>
+#include "ft_psci.h"
+#include "ft_generic_timer.h"
+
+extern int rt_hw_timer_init(void);
+extern void secondary_cpu_start(void);
+
+void rt_hw_secondary_cpu_up(void)
+{
+
+    rt_uint32_t i;
+    rt_uint32_t cpu_mask = 0;
+
+    rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n");
+    for (i = 1; i < RT_CPUS_NR; i++)
+    {
+        if (i == 1)
+        {
+            /* code */
+            FPsci_CpuOn(1 << i, (rt_uint32_t)secondary_cpu_start);
+            cpu_mask = 2;
+        }
+        else if (i == 2)
+        {
+            FPsci_CpuOn(1 << i, (rt_uint32_t)secondary_cpu_start);
+            cpu_mask = 4;
+        }
+        else if (i == 3)
+        {
+            FPsci_CpuOn(1 << i, (rt_uint32_t)secondary_cpu_start);
+            cpu_mask = 8;
+        }
+        else
+        {
+            continue;
+        }
+
+        __asm__ volatile("dsb" ::
+                             : "memory");
+        rt_hw_ipi_send(RT_SCHEDULE_IPI, cpu_mask);
+        Ft_GenericTimer_UsDelay(1000000);
+    }
+}
+
+void secondary_cpu_c_start(void)
+{
+    rt_hw_vector_init();
+    rt_hw_spin_lock(&_cpus_lock);
+
+    arm_gic_cpu_init(0);
+    arm_gic_redist_init(0);
+
+    rt_hw_timer_init();
+
+    rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
+    rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
+
+    rt_system_scheduler_start();
+}
+
+void rt_hw_secondary_cpu_idle_exec(void)
+{
+    asm volatile("wfe" ::
+                     : "memory", "cc");
+}
+
+#endif

bsp/ft2004/drivers/serial.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-29     Carl    the first version
+ *
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <board.h>
+
+int rt_hw_uart_init(void);
+
+#endif
+

bsp/ft2004/ft_aarch32.lds

@@ -0,0 +1,110 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+SECTIONS
+{
+    . = 0x80100000;
+    
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16 * 1024);
+    .l1_page_table :
+    {
+        __l1_page_table_start = .;
+        . += 16K;
+    }
+
+    . = ALIGN(8);
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(8);
+    __bss_start = .;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    .heap :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        . += 0x400;
+        __HeapLimit = .;
+        __heap_limit = .; /* Add for _sbrk */
+    }
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}

bsp/ft2004/libraries/.gitignore

@@ -0,0 +1,4 @@
+*.o
+*.elf
+*.bin
+*.map

bsp/ft2004/libraries/Kconfig

@@ -0,0 +1,146 @@
+menu "Hardware Drivers Config"
+
+menu "On-chip Peripheral Drivers"
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config RT_USING_UART1
+                bool "Enable UART1"
+                default y
+            
+            config RT_USING_UART0
+                bool "Enable UART0"
+                default n
+
+        endif
+
+    menuconfig BSP_USING_SDC
+        bool "Enable sd controller"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        default n
+
+        if BSP_USING_SDC
+
+            config BSP_SDC_DEBUG_PRINT
+                bool "Enable sd controller debug print"
+                default n
+
+
+            config BSP_SDC_USE_IRQ
+                bool "Use interrupt to handle when cmd complete, dma complete"
+                default n
+            
+            if BSP_SDC_USE_IRQ
+                config BSP_SDC_IRQ_CARD_REMOVE
+                    bool "Use interrupt to determine if the card is pulled out" 
+                    default n
+
+            endif
+
+        endif
+
+    menuconfig BSP_USING_GMAC
+        bool "Enable gmac"
+        default n
+        select RT_USING_NETDEV
+
+        
+        if BSP_USING_GMAC
+            config BSP_USING_GMAC0
+                bool "Enable GMAC0"
+                default y
+
+            config BSP_USING_GMAC1
+                bool "Enable GMAC1"
+                default n
+
+            config RT_LWIP_ETH_PAD_SIZE
+                int "set lwip ETH_PAD_SIZE"
+                range 2 256
+                default 2
+
+            config RAW_DATA_PRINT
+                bool "Enable mac raw data print"
+                default n
+
+                if RAW_DATA_PRINT
+                    config ETH_RX_DUMP
+                        bool "Enable gmac receive raw data print "
+                        default n
+
+                    config ETH_TX_DUMP
+                        bool "Enable gmac send raw data print "
+                        default n
+                endif
+
+        endif
+
+
+    # menuconfig BSP_USE_QSPI
+    #     bool "Enable Qspi"
+    #     select RT_USING_SFUD
+    #     select RT_SFUD_USING_QSPI
+    #     default n
+
+    #     if BSP_USE_QSPI
+    #         config BSP_QSPI_DEBUG
+    #             bool "Enable qspi debug print"
+    #             default n
+    #     endif
+    
+    menuconfig BSP_USE_SPI
+        bool "Enable Spi"
+        select RT_USING_SFUD
+        select RT_SFUD_USING_SPI
+        select RT_SFUD_USING_SFDP
+        select RT_SFUD_USING_FLASH_INFO_TABLE
+        select BSP_USE_GPIO
+        default n
+        if BSP_USE_SPI
+            config BSP_SPI_DEBUG
+                bool "Enable spi debug print"
+                default n
+        endif
+
+    menuconfig BSP_USE_GPIO
+        bool "Enable Gpio"
+        default n
+        if BSP_USE_GPIO
+            config BSP_GPIO_DEBUG
+                bool "Enable gpio debug print"
+                default n
+        endif
+
+    menuconfig BSP_USE_CAN
+        bool "Enable Can"
+        select RT_USING_CAN
+        default n        
+    
+        if BSP_USE_CAN
+            config BSP_USING_CAN0
+                bool "Enable can0"
+                default n
+            config BSP_USING_CAN1
+                bool "Enable can1"
+                default n
+            
+            if BSP_USING_CAN0
+                config BSP_USING_CAN0_DEBUG
+                    bool "Enable can0 work in loop back"
+                    default n
+            endif
+
+        endif
+
+    
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/ft2004/libraries/SConscript

@@ -0,0 +1,129 @@
+'''
+ : Copyright (c) 2020 Phytium Information Technology, Inc. 
+ 
+SPDX-License-Identifier: Apache-2.0.
+
+Date: 2021-05-24 14:30:13
+LastEditTime: 2021-05-26 14:58:34
+Description:  This files is for 
+
+Modify History: 
+ Ver   Who        Date         Changes
+----- ------     --------    --------------------------------------
+'''
+from building import *
+import rtconfig
+Import('RTT_ROOT')
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+bsp/standlone/ft_assert.c
+bsp/standlone/ft_generic_timer.c
+bsp/standlone/ft_printf.c
+bsp/standlone/ft_trace.c
+bsp/standlone/ft_mux.c
+bsp/standlone/inbyte.c
+bsp/standlone/outbyte.c
+bsp/standlone/ft_cache.c
+bsp/standlone/ft_cpu.c
+bsp/standlone/ft_smc.S
+bsp/standlone/ft_psci.c
+bsp/standlone/ft_debug.c
+""")
+
+
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['bsp/ft_uart/ft_uart_g.c']
+    src += ['bsp/ft_uart/ft_uart_hw.c']
+    src += ['bsp/ft_uart/ft_uart_intr.c']
+    src += ['bsp/ft_uart/ft_uart_options.c']
+    src += ['bsp/ft_uart/ft_uart_selftest.c']
+    src += ['bsp/ft_uart/ft_uart_sinit.c']
+    src += ['bsp/ft_uart/ft_uart.c']
+
+if GetDepend(['RT_USING_I2C']):
+    None
+
+if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
+    None
+
+if GetDepend(['BSP_USE_CAN']):
+    src += ['bsp/ft_can/ft_can_g.c']
+    src += ['bsp/ft_can/ft_can_hw.c']
+    src += ['bsp/ft_can/ft_can_intr.c']
+    src += ['bsp/ft_can/ft_can_sinit.c']
+    src += ['bsp/ft_can/ft_can.c']
+    src += ['bsp/ft_can/ft_can_calc.c']
+    None
+
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
+    None
+
+if GetDepend(['RT_USING_ADC']):
+    None
+
+if GetDepend(['RT_USING_RTC']):
+    None
+
+if GetDepend(['RT_USING_WDT']):
+    None
+
+if GetDepend(['RT_USING_AUDIO']):
+    None
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
+    None
+
+if GetDepend(['BSP_USING_GMAC']):
+    src += ['bsp/ft_gmac/ft_gmac_desc.c']
+    src += ['bsp/ft_gmac/ft_gmac_g.c']
+    src += ['bsp/ft_gmac/ft_gmac_hw.c']
+    src += ['bsp/ft_gmac/ft_gmac_intr.c']
+    src += ['bsp/ft_gmac/ft_gmac_sinit.c']
+    src += ['bsp/ft_gmac/ft_gmac.c']
+
+if GetDepend(['BSP_USING_SDC']):
+    src += ['bsp/ft_sd/ft_sdctrl_option.c']
+    src += ['bsp/ft_sd/ft_sdctrl_sinit.c']
+    src += ['bsp/ft_sd/ft_sdctrl_intr.c']
+    src += ['bsp/ft_sd/ft_sdctrl_g.c']
+    src += ['bsp/ft_sd/ft_sdctrl_hw.c']
+    src += ['bsp/ft_sd/ft_sdctrl.c']
+
+if GetDepend(['BSP_USE_QSPI']):
+    src += ['bsp/ft_qspi/qspi_g.c']
+    src += ['bsp/ft_qspi/qspi_hw.c']
+    src += ['bsp/ft_qspi/ft_qspi.c']
+    src += ['bsp/ft_qspi/qspi_sinit.c']
+    
+if GetDepend(['BSP_USE_SPI']):
+    src += ['bsp/ft_spi/ft_spi.c']
+    src += ['bsp/ft_spi/ft_spi_irq.c']
+
+if GetDepend(['BSP_USE_GPIO']):
+    src += ['bsp/ft_gpio/ft_gpio.c']
+
+path = [cwd + '/bsp/standlone/',
+        cwd + '/bsp/ft_gicv3',
+        cwd + '/bsp/ft_gmac',
+        cwd + '/bsp/ft_uart',
+        cwd + '/bsp/ft_sd',
+        cwd + '/bsp/ft_qspi',
+        cwd + '/bsp/ft_can',
+        cwd + '/bsp/ft_spi',
+        cwd + '/bsp/ft_gpio',
+        cwd + '/bsp/include',
+        cwd + '/include',
+        cwd + '/cpu', ]
+
+
+CPPDEFINES = ['USE_FT_DRIVER']
+group = DefineGroup('FT_DRIVER', src, depend=[
+                    ''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/ft2004/libraries/bsp/ft_can/ft_can.h

@@ -0,0 +1,142 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 15:08:44
+ * @LastEditTime: 2021-04-27 15:08:44
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_CAN_H
+#define FT_CAN_H
+
+#include "ft_types.h"
+#include "ft_error_code.h"
+
+#define FCAN_SUCCESS FST_SUCCESS                                                     /* SUCCESS */
+#define FCAN_FAILURE FT_MAKE_ERRCODE(errCan, errBspGeneral, FST_FAILURE)             /* Normal */
+#define FCAN_TIMEOUT FT_MAKE_ERRCODE(errCan, errBspGeneral, FST_TIMEOUT)             /* Timeout */
+#define FCAN_EILSEQ FT_MAKE_ERRCODE(errCan, errBspGeneral, FST_EILSEQ)               /* Illegal byte sequence. */
+#define FCAN_INVALID_PARAM FT_MAKE_ERRCODE(errCan, errBspGeneral, FST_INVALID_PARAM) /* Invalid param. */
+
+#define FCAN_HANDLER_SEND 1U  /**< Handler type for frame sending interrupt */
+#define FCAN_HANDLER_RECV 2U  /**< Handler type for frame reception interrupt*/
+#define FCAN_HANDLER_ERROR 3U /**< Handler type for error interrupt */
+#define FCAN_DATA_LENGTH 8U
+
+/* CAN payload length and DLC definitions according to ISO 11898-1 */
+#define CAN_MAX_DLC 8
+#define CAN_MAX_DLEN 8
+#define CAN_MAX_CTL 3
+#define CAN_SFF_ID_BITS 11
+#define CAN_EFF_ID_BITS 29
+
+/* special address description flags for the CAN_ID */
+#define CAN_EFF_FLAG 0x80000000U /* EFF/SFF is set in the MSB */
+#define CAN_RTR_FLAG 0x40000000U /* remote transmission request */
+#define CAN_ERR_FLAG 0x20000000U /* error message frame */
+
+/* valid bits in CAN ID for frame formats */
+#define CAN_SFF_MASK 0x000007FFU /* standard frame format (SFF) */
+#define CAN_EFF_MASK 0x1FFFFFFFU /* extended frame format (EFF) */
+#define CAN_ERR_MASK 0x1FFFFFFFU /* omit EFF, RTR, ERR flags */
+
+/* Frame type */
+#define STANDARD_FRAME 0 /* standard frame */
+#define EXTEND_FRAME 1   /* extended frame */
+
+typedef void (*FCan_irqHandler_t)(void *Args);
+
+struct FCan_Frame
+{
+    u32 CanId;
+    u8 CanDlc;
+    u8 data[FCAN_DATA_LENGTH];
+};
+
+struct FCan_Bittiming
+{
+    u32 bitrate;      /* Bit-rate in bits/second */
+    u32 sample_point; /* Sample point in one-tenth of a percent */
+    u32 tq;           /* Time quanta (TQ) in nanoseconds */
+    u32 prop_seg;     /* Propagation segment in TQs */
+    u32 phase_seg1;   /* Phase buffer segment 1 in TQs */
+    u32 phase_seg2;   /* Phase buffer segment 2 in TQs */
+    u32 sjw;          /* Synchronisation jump width in TQs */
+    u32 brp;          /* Bit-rate prescaler */
+};
+
+typedef struct
+{
+    u32 InstanceId;     /* Id of device */
+    u32 CanBaseAddress; /* Can base Address */
+    u32 IrqNum;
+    u32 BaudRate;
+    u32 TxFifoDeepth; /* The depth of the full frame , */
+} FCan_Config_t;
+
+typedef struct
+{
+    FCan_Config_t Config;
+    u32 IsReady; /* Device is initialized and ready */
+
+    volatile u32 TxFifoCnt;
+
+    FCan_irqHandler_t SendHandler;
+    void *SendRef;
+
+    FCan_irqHandler_t RecvHandler;
+    void *RecvRef;
+
+    FCan_irqHandler_t ErrorHandler;
+    void *ErrorRef;
+
+} FCan_t;
+
+FCan_Config_t *FCan_LookupConfig(u32 InstanceId);
+
+/**
+ * @name: FCan_CfgInitialize
+ * @msg:  This function initializes a Can instance/driver.
+ * @in param Can_p:    Can_p is a pointer to the FCan_t instance.
+ * @in param Config_p: Config_p points to the FCan_t device configuration structure.
+ * @return {*}
+ */
+ft_error_t FCan_CfgInitialize(FCan_t *Can_p, FCan_Config_t *Config_p);
+
+/**
+ * @name: FCan_SetHandler
+ * @msg:  This routine installs an asynchronous callback function for the given
+ * @inout param Can_p: Can_p is a pointer to the FCan_t instance.
+ * @in param HandlerType:  specifies which handler is to be attached.
+ * @in param IrqCallBackFunc: IrqCallBackFunc is the address of the callback function.
+ * @in param IrqCallBackRef: IrqCallBackRef is a user data item that will be passed to the
+ *      callback function when it is invoked.
+ * @return {*}
+ * @param {FCan_t} *Can_p
+ * @param {u32} HandlerType
+ * @param {FCan_irqHandler_t} *IrqCallBackFunc
+ * @param {void} *IrqCallBackRef
+ */
+ft_error_t FCan_SetHandler(FCan_t *Can_p, u32 HandlerType, FCan_irqHandler_t IrqCallBackFunc, void *IrqCallBackRef);
+
+ft_error_t FCan_SetTiming(FCan_t *Can_p,
+                          struct FCan_Bittiming *Bittiming_p);
+
+void FCan_IntrHandler(void *InstancePtr);
+
+ft_error_t FCan_CalcBittiming(struct FCan_Bittiming *Bt_p);
+
+u32 FCan_SendByIrq(FCan_t *Can_p,
+                   struct FCan_Frame *Frame_p,
+                   u32 FrameNumber, void (*UserIrqWait)(void));
+
+u32 FCan_RecvByIrq(FCan_t *Can_p, struct FCan_Frame *Frame_p, u32 FrameNumber);
+
+void FCan_Enable(FCan_t *Can_p);
+
+#endif // !FT_CAN_H

bsp/ft2004/libraries/bsp/ft_can/ft_can_g.c

@@ -0,0 +1,39 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 15:31:44
+ * @LastEditTime: 2021-04-27 15:31:44
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_can.h"
+#include "ft_parameters.h"
+
+FCan_Config_t FCan_Config[FT_CAN_NUM] =
+    {
+        {
+            .InstanceId = 0,                    /* Id of device */
+            .CanBaseAddress = FT_CAN0_BASEADDR, /* Can base Address */
+            .IrqNum = FT_CAN0_IRQNUM,
+            .BaudRate = 250000,
+            .TxFifoDeepth = 16,
+        },
+        {
+            .InstanceId = 1,                    /* Id of device */
+            .CanBaseAddress = FT_CAN1_BASEADDR, /* Can base Address */
+            .IrqNum = FT_CAN1_IRQNUM,
+            .BaudRate = 250000,
+            .TxFifoDeepth = 16,
+        },
+        {
+            .InstanceId = 2,                    /* Id of device */
+            .CanBaseAddress = FT_CAN2_BASEADDR, /* Can base Address */
+            .IrqNum = FT_CAN2_IRQNUM,
+            .BaudRate = 250000,
+            .TxFifoDeepth = 16,
+        }};

bsp/ft2004/libraries/bsp/ft_can/ft_can_hw.c

@@ -0,0 +1,55 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 13:52:41
+ * @LastEditTime: 2021-04-27 13:52:41
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_can_hw.h"
+#include "ft_can.h"
+#include "ft_mux.h"
+#include "ft_parameters.h"
+#include "ft_math.h"
+#include "ft_assert.h"
+#include "ft_debug.h"
+
+#define CAN_HW_DEBUG_TAG "CAN_HW"
+
+#define CAN_HW_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(CAN_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+#define CAN_HW_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(CAN_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+#define CAN_HW_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(CAN_HW_DEBUG_TAG, format, ##__VA_ARGS__)
+
+void FCan_Reset(FCan_t *Can_p)
+{
+    u32 RegValue;
+    FCan_Config_t *Config_p;
+    Ft_assertVoid(Can_p != NULL);
+    Ft_assertVoid(Can_p->IsReady == FT_COMPONENT_IS_READLY);
+    Config_p = &Can_p->Config;
+
+    RegValue = FCan_ReadReg(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET);
+
+    if (RegValue & FCAN_CTRL_XFER_MASK)
+    {
+        CAN_HW_DEBUG_E("FT can is not in configration mode\n");
+        Ft_assertVoid(0);
+        return;
+    }
+
+    FCan_WriteReg(FT_PIN_DEMUX_BASE, FT_PIN_DEMUX_REG204_OFFSET, 0x89999990); // Reuse can IO
+
+    FCan_WriteReg(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET, FCAN_CTRL_RESET_MASK);
+    FCan_SetBit(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET, FCAN_CTRL_AIME_MASK);
+    FCan_WriteReg(Config_p->CanBaseAddress, FCAN_ACC_ID0_MASK_OFFSET, FCAN_ACC_IDN_MASK);
+    FCan_WriteReg(Config_p->CanBaseAddress, FCAN_ACC_ID1_MASK_OFFSET, FCAN_ACC_IDN_MASK);
+    FCan_WriteReg(Config_p->CanBaseAddress, FCAN_ACC_ID2_MASK_OFFSET, FCAN_ACC_IDN_MASK);
+    FCan_WriteReg(Config_p->CanBaseAddress, FCAN_ACC_ID3_MASK_OFFSET, FCAN_ACC_IDN_MASK);
+    FCan_ClearBit(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET, FCAN_CTRL_RESET_MASK);
+    FCan_WriteReg(Config_p->CanBaseAddress, FCAN_INTR_OFFSET, FCAN_INTR_TEIE_MASK | FCAN_INTR_REIE_MASK);
+}

bsp/ft2004/libraries/bsp/ft_can/ft_can_hw.h

@@ -0,0 +1,161 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 13:52:47
+ * @LastEditTime: 2021-04-27 13:52:47
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_CAN_HW_H
+#define FT_CAN_HW_H
+
+#include "ft_types.h"
+#include "ft_io.h"
+#include "ft_can.h"
+
+/***ft CAN REGISTER offset*/
+#define FCAN_CTRL_OFFSET 0x00          /* Global control register */
+#define FCAN_INTR_OFFSET 0x04          /* Interrupt register */
+#define FCAN_ARB_RATE_CTRL_OFFSET 0x08 /* Arbitration rate control register */
+#define FCAN_DAT_RATE_CTRL_OFFSET 0x0C /* Data rate control register */
+#define FCAN_ACC_ID0_OFFSET 0x10       /* Acceptance identifier0 register */
+#define FCAN_ACC_ID1_OFFSET 0x14       /* Acceptance identifier1 register */
+#define FCAN_ACC_ID2_OFFSET 0x18       /* Acceptance identifier2 register */
+#define FCAN_ACC_ID3_OFFSET 0x1C       /* Acceptance identifier3 register */
+#define FCAN_ACC_ID0_MASK_OFFSET 0x20  /* Acceptance identifier0 mask register */
+#define FCAN_ACC_ID1_MASK_OFFSET 0x24  /* Acceptance identifier1 mask register */
+#define FCAN_ACC_ID2_MASK_OFFSET 0x28  /* Acceptance identifier2 mask register */
+#define FCAN_ACC_ID3_MASK_OFFSET 0x2C  /* Acceptance identifier3 mask register */
+#define FCAN_XFER_STS_OFFSET 0x30      /* Transfer status register */
+#define FCAN_ERR_CNT_OFFSET 0x34       /* Error counter register */
+#define FCAN_FIFO_CNT_OFFSET 0x38      /* FIFO counter register */
+#define FCAN_DMA_CTRL_OFFSET 0x3C      /* DMA request control register */
+#define FCAN_TX_FIFO_OFFSET 0x100      /* TX FIFO shadow register */
+#define FCAN_RX_FIFO_OFFSET 0x200      /* RX FIFO shadow register */
+
+/*----------------------------------------------------------------------------*/
+/* CAN register bit masks - FCAN_<REG>_<BIT>_MASK                            */
+/*----------------------------------------------------------------------------*/
+
+/* FCAN_CTRL mask */
+#define FCAN_CTRL_XFER_MASK (0x1 << 0) /* RW */  /*Transfer enable*/
+#define FCAN_CTRL_TXREQ_MASK (0x1 << 1) /* RW */ /*Transmit request*/
+#define FCAN_CTRL_AIME_MASK (0x1 << 2) /* RW */  /*Acceptance identifier mask enable*/
+#define FCAN_CTRL_RESET_MASK (0x1 << 6)
+
+/* FCAN_INTR mask */
+#define FCAN_INTR_STATUS_MASK (0xFF << 0) /* RO */ /*the interrupt status*/
+#define FCAN_INTR_BOIS_MASK (0x1 << 0) /* RO */    /*Bus off interrupt status*/
+#define FCAN_INTR_PWIS_MASK (0x1 << 1) /* RO */    /*Passive warning interrupt status*/
+#define FCAN_INTR_PEIS_MASK (0x1 << 2) /* RO */    /*Passive error interrupt status*/
+#define FCAN_INTR_RFIS_MASK (0x1 << 3) /* RO */    /*RX FIFO full interrupt status*/
+#define FCAN_INTR_TFIS_MASK (0x1 << 4) /* RO */    /*TX FIFO empty interrupt status*/
+#define FCAN_INTR_REIS_MASK (0x1 << 5) /* RO */    /*RX frame end interrupt status*/
+#define FCAN_INTR_TEIS_MASK (0x1 << 6) /* RO */    /*TX frame end interrupt status*/
+#define FCAN_INTR_EIS_MASK (0x1 << 7) /* RO */     /*Error interrupt status*/
+
+#define FCAN_INTR_EN_MASK (0xFF << 8) /* RO */   /*the interrupt enable*/
+#define FCAN_INTR_BOIE_MASK (0x1 << 8) /* RW */  /*Bus off interrupt enable*/
+#define FCAN_INTR_PWIE_MASK (0x1 << 9) /* RW */  /*Passive warning interrupt enable*/
+#define FCAN_INTR_PEIE_MASK (0x1 << 10) /* RW */ /*Passive error interrupt enable*/
+#define FCAN_INTR_RFIE_MASK (0x1 << 11) /* RW */ /*RX FIFO full interrupt enable*/
+#define FCAN_INTR_TFIE_MASK (0x1 << 12) /* RW */ /*TX FIFO empty interrupt enable*/
+#define FCAN_INTR_REIE_MASK (0x1 << 13) /* RW */ /*RX frame end interrupt enable*/
+#define FCAN_INTR_TEIE_MASK (0x1 << 14) /* RW */ /*TX frame end interrupt enable*/
+#define FCAN_INTR_EIE_MASK (0x1 << 15) /* RW */  /*Error interrupt enable*/
+
+#define FCAN_INTR_BOIC_MASK (0x1 << 16) /* WO */ /*Bus off interrupt clear*/
+#define FCAN_INTR_PWIC_MASK (0x1 << 17) /* WO */ /*Passive warning interrupt clear*/
+#define FCAN_INTR_PEIC_MASK (0x1 << 18) /* WO */ /*Passive error interrupt clear*/
+#define FCAN_INTR_RFIC_MASK (0x1 << 19) /* WO */ /*RX FIFO full interrupt clear*/
+#define FCAN_INTR_TFIC_MASK (0x1 << 20) /* WO */ /*TX FIFO empty interrupt clear*/
+#define FCAN_INTR_REIC_MASK (0x1 << 21) /* WO */ /*RX frame end interrupt clear*/
+#define FCAN_INTR_TEIC_MASK (0x1 << 22) /* WO */ /*TX frame end interrupt clear*/
+#define FCAN_INTR_EIC_MASK (0x1 << 23) /* WO */  /*Error interrupt clear*/
+
+/* FCAN_ACC_ID(0-3)_MASK mask */
+#define FCAN_ACC_IDN_MASK 0x1FFFFFFF /* WO */ /*don’t care the matching */
+/* FCAN_DAT_RATE_CTRL mask */
+
+/* FCAN_ERR_CNT_OFFSET mask */
+#define FCAN_ERR_CNT_RFN_MASK (0xFF << 0) /* RO */  /*Receive error counter*/
+#define FCAN_ERR_CNT_TFN_MASK (0xFF << 16) /* RO */ /*Transmit error counter*/
+
+/* FCAN_FIFO_CNT_OFFSET mask */
+#define FCAN_FIFO_CNT_RFN_MASK (0xFF << 0) /* RO */  /*Receive FIFO valid data number*/
+#define FCAN_FIFO_CNT_TFN_MASK (0xFF << 16) /* RO */ /*Transmit FIFO valid data number*/
+
+#define FCAN_ERR_CNT_TFN_SHIFT 16  /* Tx Error Count shift */
+#define FCAN_FIFO_CNT_TFN_SHIFT 16 /* Tx FIFO Count shift*/
+#define FCAN_IDR_ID1_SHIFT 21      /* Standard Messg Identifier */
+#define FCAN_IDR_ID2_SHIFT 1       /* Extended Message Identifier */
+#define FCAN_IDR_SDLC_SHIFT 14
+#define FCAN_IDR_EDLC_SHIFT 26
+#define FCAN_ACC_IDN_SHIFT 18 /*Standard ACC ID shift*/
+
+#define FCAN_IDR_ID2_MASK 0x0007FFFE  /* Extended message ident */
+#define FCAN_IDR_ID1_MASK 0xFFE00000  /* Standard msg identifier */
+#define FCAN_IDR_IDE_MASK 0x00080000  /* Identifier extension */
+#define FCAN_IDR_SRR_MASK 0x00100000  /* Substitute remote TXreq */
+#define FCAN_IDR_RTR_MASK 0x00000001  /* Extended frames remote TX request */
+#define FCAN_IDR_DLC_MASK 0x0003C000  /* Standard msg dlc */
+#define FCAN_IDR_PAD_MASK 0x00003FFF  /* Standard msg padding 1 */
+#define FCAN_IDR_EDLC_MASK 0x3C000000 /* Extended msg dlc */
+
+/* Can timming */
+#define FCAN_TSEG1_MIN 1
+#define FCAN_TSEG1_MAX 8
+#define FCAN_TSEG2_MIN 1
+#define FCAN_TSEG2_MAX 8
+#define FCAN_SJW_MAX 4
+#define FCAN_BRP_MIN 1
+#define FCAN_BRP_MAX 512
+#define FCAN_BRP_INC 1
+#define FCAN_CALC_SYNC_SEG 1
+
+/**
+*
+* This macro reads the given register.
+*
+* @param    BaseAddr is the base address of the device.
+* @param    RegOffset is the register offset to be read.
+*
+* @return   The 32-bit value of the register
+*
+* @note     None.
+*
+*****************************************************************************/
+#define FCan_ReadReg(BaseAddr, RegOffset) \
+    Ft_in32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param    BaseAddr is the base address of the device.
+* @param    RegOffset is the register offset to be written.
+* @param    Data is the 32-bit value to write to the register.
+*
+* @return   None.
+*
+* @note     None.
+*
+*****************************************************************************/
+#define FCan_WriteReg(BaseAddr, RegOffset, Data) \
+    Ft_out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+#define FCan_SetBit(BaseAddr, RegOffset, Data) \
+    Ft_setBit32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+#define FCan_ClearBit(BaseAddr, RegOffset, Data) \
+    Ft_clearBit32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+void FCan_Reset(FCan_t *Can_p);
+
+#endif // !

bsp/ft2004/libraries/bsp/ft_can/ft_can_intr.c

@@ -0,0 +1,118 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-29 10:40:47
+ * @LastEditTime: 2021-04-29 10:40:47
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_can.h"
+#include "ft_can_hw.h"
+#include "ft_assert.h"
+#include "ft_types.h"
+
+ft_error_t FCan_SetHandler(FCan_t *Can_p, u32 HandlerType, FCan_irqHandler_t IrqCallBackFunc, void *IrqCallBackRef)
+{
+    ft_error_t status = FCAN_SUCCESS;
+    Ft_assertNonvoid(Can_p != NULL);
+    Ft_assertNonvoid(Can_p->IsReady == FT_COMPONENT_IS_READLY);
+    switch (HandlerType)
+    {
+    case FCAN_HANDLER_SEND:
+        Can_p->SendHandler = IrqCallBackFunc;
+        Can_p->SendRef = IrqCallBackRef;
+        break;
+    case FCAN_HANDLER_RECV:
+        Can_p->RecvHandler = IrqCallBackFunc;
+        Can_p->RecvRef = IrqCallBackRef;
+        break;
+    case FCAN_HANDLER_ERROR:
+        Can_p->ErrorHandler = IrqCallBackFunc;
+        Can_p->ErrorRef = IrqCallBackRef;
+        break;
+    default:
+        status = FCAN_FAILURE;
+    }
+
+    return status;
+}
+
+static void FCan_TxInterrupt(FCan_t *Can_p)
+{
+    FCan_Config_t *Config_p = &Can_p->Config;
+    FCan_SetBit(Config_p->CanBaseAddress, FCAN_INTR_OFFSET, FCAN_INTR_TEIC_MASK | FCAN_INTR_REIC_MASK);
+
+    if (0 != Can_p->TxFifoCnt)
+    {
+        Can_p->TxFifoCnt--;
+        FCan_ClearBit(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
+        FCan_SetBit(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK);
+        FCan_SetBit(Config_p->CanBaseAddress, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
+    }
+    else
+    {
+        if (Can_p->SendHandler)
+        {
+            Can_p->SendHandler(Can_p->SendRef);
+        }
+    }
+}
+
+static void FCan_ErrorInterrupt(FCan_t *Can_p)
+{
+    if (Can_p->ErrorHandler)
+    {
+        Can_p->ErrorHandler(Can_p->ErrorRef);
+    }
+}
+
+static void FCan_RxInterrupt(FCan_t *Can_p)
+{
+    if (Can_p->RecvHandler)
+    {
+        Can_p->RecvHandler(Can_p->RecvRef);
+    }
+}
+
+void FCan_IntrHandler(void *InstancePtr)
+{
+    u32 Irq;
+    FCan_t *Can_p = (FCan_t *)InstancePtr;
+    FCan_Config_t *Config_p;
+    Ft_assertVoid(Can_p != NULL);
+    Ft_assertVoid(Can_p->IsReady == FT_COMPONENT_IS_READLY);
+    Config_p = &Can_p->Config;
+    Irq = FCan_ReadReg(Config_p->CanBaseAddress, FCAN_INTR_OFFSET);
+
+    if (0 == Irq)
+    {
+        return;
+    }
+
+    /* Check for the type of error interrupt and Processing it */
+    if (Irq & FCAN_INTR_TEIS_MASK)
+    {
+        Irq &= ~FCAN_INTR_REIS_MASK;
+        FCan_TxInterrupt(Can_p);
+    }
+
+    if (Irq & (FCAN_INTR_EIS_MASK | FCAN_INTR_RFIS_MASK |
+               FCAN_INTR_BOIS_MASK | FCAN_INTR_PEIS_MASK | FCAN_INTR_PWIS_MASK))
+    {
+        FCan_SetBit(Config_p->CanBaseAddress, FCAN_INTR_OFFSET, (FCAN_INTR_EIC_MASK | FCAN_INTR_RFIC_MASK | FCAN_INTR_BOIC_MASK | FCAN_INTR_PEIC_MASK | FCAN_INTR_PWIC_MASK));
+        FCan_ErrorInterrupt(Can_p);
+    }
+
+    if (Irq & FCAN_INTR_REIS_MASK)
+    {
+        FCan_SetBit(Config_p->CanBaseAddress, FCAN_INTR_OFFSET, FCAN_INTR_REIE_MASK);
+        FCan_RxInterrupt(Can_p);
+        FCan_SetBit(Config_p->CanBaseAddress, FCAN_INTR_OFFSET, FCAN_INTR_REIC_MASK);
+        FCan_SetBit(Config_p->CanBaseAddress, FCAN_INTR_OFFSET, FCAN_INTR_REIE_MASK);
+    }
+}

bsp/ft2004/libraries/bsp/ft_can/ft_can_sinit.c

@@ -0,0 +1,40 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 15:31:57
+ * @LastEditTime: 2021-04-27 15:31:57
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_can.h"
+#include "ft_parameters.h"
+
+extern FCan_Config_t FCan_Config[FT_CAN_NUM];
+
+/**
+ * @name:
+ * @msg:
+ * @in param:
+ * @return {*}
+ * @param {u32} InstanceId
+ */
+FCan_Config_t *FCan_LookupConfig(u32 InstanceId)
+{
+    FCan_Config_t *CfgPtr = NULL;
+    u32 Index;
+
+    for (Index = 0; Index < (u32)FT_CAN_NUM; Index++)
+    {
+        if (FCan_Config[Index].InstanceId == InstanceId)
+        {
+            CfgPtr = &FCan_Config[Index];
+            break;
+        }
+    }
+    return (FCan_Config_t *)CfgPtr;
+}

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac.c

@@ -0,0 +1,109 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-25 16:43:14
+ * @Description:  This files is for gmac ctrl
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_gmac.h"
+#include "ft_gmac_hw.h"
+#include "ft_assert.h"
+#include "ft_io.h"
+#include "ft_status.h"
+#include "ft_printf.h"
+#include "ft_parameters.h"
+
+static void Ft_Gmac_StubHandler(void *args)
+{
+    Ft_assertVoidAlways();
+}
+
+static void Ft_Gmac_StubErrorHandler(void *CallBackRef, u32 ErrorWord)
+{
+    // Ft_assertVoidAlways();
+}
+
+s32 Ft_Gmac_HwInitialize(Ft_Gmac_t *Gmac)
+{
+    Ft_assertNonvoid(Gmac != NULL);
+    Ft_assertNonvoid(Gmac->IsReady == FT_COMPONENT_IS_READLY);
+    return FGmac_InitializeHw(&Gmac->Config);
+}
+
+s32 Ft_GmacCfgInitialize(Ft_Gmac_t *Gmac, FGmac_Config_t *Config)
+{
+    Ft_assertNonvoid(Gmac != NULL);
+    Ft_assertNonvoid(Config != NULL);
+
+    Gmac->Config = *Config;
+    Gmac->IsReady = FT_COMPONENT_IS_READLY;
+
+    FGmac_SetHandler(Gmac, FT_GMAC_TX_COMPLETE_CB_ID, Ft_Gmac_StubHandler, Gmac);
+    FGmac_SetHandler(Gmac, FT_GMAC_RX_COMPLETE_CB_ID, Ft_Gmac_StubHandler, Gmac);
+    FGmac_SetHandler(Gmac, FT_GMAC_DMA_ERROR_CB_ID, Ft_Gmac_StubErrorHandler, Gmac);
+
+    return FST_SUCCESS;
+}
+
+s32 Ft_Gmac_Start(Ft_Gmac_t *Gmac)
+{
+    FGmac_Config_t *Config = NULL;
+    Ft_assertNonvoid(Gmac != NULL);
+    Ft_assertNonvoid(Gmac->IsReady == FT_COMPONENT_IS_READLY);
+    Config = &Gmac->Config;
+
+    FGmac_DMAReceptionTransmissionEnable(Config);
+    FGmac_ReceptionTransmissionEnable(Config);
+
+    /* Clear Tx and Rx process stopped flags */
+    Ft_out32(Gmac->Config.BaseAddress + DMA_INTR_ENA_OFFSET, DMA_INTR_ENA_RIE | DMA_INTR_ENA_AIE | DMA_INTR_ENA_NIE);
+
+    return FST_SUCCESS;
+}
+
+s32 Ft_Gmac_Stop(Ft_Gmac_t *Gmac)
+{
+    FGmac_Config_t *Config = NULL;
+    Ft_assertNonvoid(Gmac != NULL);
+    Ft_assertNonvoid(Gmac->IsReady == FT_COMPONENT_IS_READLY);
+    Config = &Gmac->Config;
+
+    FGmac_TransmissionDisable(Config);
+    FGmac_ReceptionDisable(Config);
+    FGmac_DMATransmissionDisable(Config);
+    FGmac_DMAReceptionDisable(Config);
+    return FST_SUCCESS;
+}
+
+void Ft_Gmac_Phy_Debug(Ft_Gmac_t *Gmac)
+{
+
+    Ft_printf("\r\n ****************************** \r\n");
+}
+
+
+void Ft_Gmac_UseDefaultMacAddr(Ft_Gmac_t *Gmac, u8 *MacAddr)
+{
+    u32 MacAddrLo;
+    u32 MacAddrHi;
+    FGmac_Config_t *pConfig;
+    Ft_assertNoneReturn(Gmac != NULL);
+    pConfig = &Gmac->Config;
+
+    MacAddrLo = Ft_in32(pConfig->BaseAddress + GMAC_MAC_ADDR0_LOWER16BIT_OFFSET);
+    MacAddrHi = Ft_in32(pConfig->BaseAddress + GMAC_MAC_ADDR0_UPPER16BIT_OFFSET);
+
+    MacAddr[0] = MacAddrLo & 0xFF;
+    MacAddr[1] = (MacAddrLo >> 8) & 0xFF;
+    MacAddr[2] = (MacAddrLo >> 16) & 0xFF;
+    MacAddr[3] = (MacAddrLo >> 24) & 0xFF;
+    MacAddr[4] = MacAddrHi & 0xFF;
+    MacAddr[5] = (MacAddrHi >> 8) & 0xFF;
+}

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac_desc.h

@@ -0,0 +1,20 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:24:16
+ * @Description:  This files is for gmac descrption
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef GMAC_DESC_H
+#define GMAC_DESC_H
+
+#include "ft_gmac.h"
+
+#endif // !

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac_g.c

@@ -0,0 +1,47 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:24:30
+ * @Description:  This files is for gmac config
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_gmac.h"
+#include "ft_parameters.h"
+
+FGmac_Config_t Gmac_ConfigTable[FT_GMAC_INSTANCES_NUM] = {
+    {FT_GMAC0_ID,
+     FT_GMAC_COMMON_ADDR,
+     FT_GMAC0_BASEADDR,
+     GMAC0_ISRNUM,
+     GMAC0_ISRPRIORITY,
+     0,
+     5,
+     GMAC_AUTONEGOTIATION_ENABLE,
+     GMAC_SPEED_1000M,
+     GMAC_MODE_FULLDUPLEX,
+     GMAC_RXINTERRUPT_MODE,
+     GMAC_CHECKSUM_BY_SOFTWARE,
+     GMAC_MEDIA_INTERFACE_RGMII,
+     FT_GMAC0_DEFAULT_ADDR},
+    {FT_GMAC1_ID,
+     FT_GMAC_COMMON_ADDR,
+     FT_GMAC1_BASEADDR,
+     GMAC1_ISRNUM,
+     GMAC1_ISRPRIORITY,
+     0,
+     5,
+     GMAC_AUTONEGOTIATION_ENABLE,
+     GMAC_SPEED_1000M,
+     GMAC_MODE_FULLDUPLEX,
+     GMAC_RXINTERRUPT_MODE,
+     GMAC_CHECKSUM_BY_SOFTWARE,
+     GMAC_MEDIA_INTERFACE_RGMII,
+     {0}},
+};

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac_intr.c

@@ -0,0 +1,174 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-25 16:42:56
+ * @Description:  This files is for gmac irq
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_gmac_hw.h"
+#include "ft_gmac.h"
+#include "ft_status.h"
+#include "ft_assert.h"
+#include "ft_io.h"
+
+#include "ft_debug.h"
+#define GMAC_INTR_DEBUG_TAG "GMAC_INTR"
+
+#define GMAC_INTR_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(GMAC_INTR_DEBUG_TAG, format, ##__VA_ARGS__)
+#define GMAC_INTR_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(GMAC_INTR_DEBUG_TAG, format, ##__VA_ARGS__)
+#define GMAC_INTR_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(GMAC_INTR_DEBUG_TAG, format, ##__VA_ARGS__)
+
+s32 FGmac_SetHandler(Ft_Gmac_t *Gmac, FGmac_IsrCallbackSelect_t SelectIndex, void *FuncPtr,
+                     void *Args)
+{
+    Ft_assertNonvoid(Gmac != NULL);
+    Ft_assertNonvoid(FuncPtr != NULL);
+    Ft_assertNonvoid(Gmac->IsReady == FT_COMPONENT_IS_READLY);
+
+    switch (SelectIndex)
+    {
+    case FT_GMAC_TX_COMPLETE_CB_ID:
+        /* code */
+        Gmac->SendHandler = FuncPtr;
+        Gmac->SendArgs = Args;
+        break;
+    case FT_GMAC_RX_COMPLETE_CB_ID:
+        Gmac->RecvHandler = FuncPtr;
+        Gmac->RecvArgs = Args;
+        break;
+    case FT_GMAC_DMA_ERROR_CB_ID:
+        Gmac->ErrorHandler = FuncPtr;
+        Gmac->ErrorArgs = Args;
+        break;
+    case FT_GMAC_MAC_PHY_STATUS_CB_ID:
+        Gmac->StatusHandler = FuncPtr;
+        Gmac->StatusArgs = Args;
+        break;
+    default:
+        return FST_FAILURE;
+    }
+
+    return FST_SUCCESS;
+}
+
+
+__STATIC_INLINE u32 FGmac_ErrorCheck(Ft_Gmac_t *Gmac)
+{
+    u32 RegValue = 0;
+    u32 ErrIsr_RegValue = 0;
+    u32 RetValue = 0;
+    RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET);
+    ErrIsr_RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_INTR_ENA_OFFSET);
+
+    if (((RegValue & DMA_STATUS_TPS) == DMA_STATUS_TPS) && ((ErrIsr_RegValue & DMA_INTR_ENA_TSE) == DMA_INTR_ENA_TSE))
+    {
+        RetValue |= GMAC_ERROR_TRANSMIT_PROCESS_STOPPED;
+    }
+
+    if (((RegValue & DMA_STATUS_TU) == DMA_STATUS_TU) && ((ErrIsr_RegValue & DMA_INTR_ENA_TUE) == DMA_INTR_ENA_TUE))
+    {
+        RetValue |= GMAC_ERROR_TRANSMIT_UNAVAILABLE_STATUS;
+    }
+
+    if (((RegValue & DMA_STATUS_TJT) == DMA_STATUS_TJT) && ((ErrIsr_RegValue & DMA_INTR_ENA_THE) == DMA_INTR_ENA_THE))
+    {
+        RetValue |= GMAC_ERROR_TRANSMIT_JABBER_TIMEOUT;
+    }
+
+    if (((RegValue & DMA_STATUS_OVF) == DMA_STATUS_OVF) && ((ErrIsr_RegValue & DMA_INTR_ENA_OVE) == DMA_INTR_ENA_OVE))
+    {
+        RetValue |= GMAC_ERROR_RECEIVE_FIFO_OVERFLOW;
+    }
+
+    if (((RegValue & DMA_STATUS_UNF) == DMA_STATUS_UNF) && ((ErrIsr_RegValue & DMA_INTR_ENA_UNE) == DMA_INTR_ENA_UNE))
+    {
+        RetValue |= GMAC_ERROR_TRANSMIT_UNDERFLOW;
+    }
+
+    if (((RegValue & DMA_STATUS_RU) == DMA_STATUS_RU) && ((ErrIsr_RegValue & DMA_INTR_ENA_RUE) == DMA_INTR_ENA_RUE))
+    {
+        RetValue |= GMAC_ERROR_RECEIVE_BUFFER_UNAVAILABLE;
+    }
+
+    if (((RegValue & DMA_STATUS_RPS) == DMA_STATUS_RPS) && ((ErrIsr_RegValue & DMA_INTR_ENA_RSE) == DMA_INTR_ENA_RSE))
+    {
+        RetValue |= GMAC_ERROR_RECEIVE_PROCESS_STOPPED;
+    }
+
+    if (((RegValue & DMA_STATUS_RWT) == DMA_STATUS_RWT) && ((ErrIsr_RegValue & DMA_INTR_ENA_RWE) == DMA_INTR_ENA_RWE))
+    {
+        RetValue |= GMAC_ERROR_RECEIVE_WATCHDOG_TIMEOUT;
+    }
+
+    if (((RegValue & DMA_STATUS_ETI) == DMA_STATUS_ETI) && ((ErrIsr_RegValue & DMA_INTR_ENA_ETE) == DMA_INTR_ENA_ETE))
+    {
+        RetValue |= GMAC_ERROR_EARLY_TRANSMIT_INTERRUPT;
+    }
+
+    if (((RegValue & DMA_STATUS_FBI) == DMA_STATUS_FBI) && ((ErrIsr_RegValue & DMA_INTR_ENA_FBE) == DMA_INTR_ENA_FBE))
+    {
+        RetValue |= GMAC_ERROR_FATAL_BUS_ERROR;
+    }
+
+    if (0U == RetValue)
+    {
+        RetValue |= GMAC_ERROR_UNDEFINED;
+    }
+    Ft_printf("error RetValue %x \r\n", RetValue);
+    return RetValue;
+}
+
+
+void FGmac_IntrHandler(void *Args)
+{
+    Ft_Gmac_t *Gmac;
+    u32 RegValue;
+    u32 MACRegValue;
+    Ft_assertVoid(Args != NULL);
+    Gmac = (Ft_Gmac_t *)Args;
+
+    RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET);
+    if ((RegValue)&DMA_STATUS_GLI)
+    {
+        MACRegValue = Ft_in32(Gmac->Config.BaseAddress + GMAC_MAC_MAC_PHY_STATUS);
+        if (Gmac->StatusHandler)
+        {
+            Gmac->StatusHandler(Gmac->StatusArgs, MACRegValue);
+        }
+    }
+
+    /* Frame received */
+    if ((RegValue & (DMA_STATUS_RI)) != 0)
+    {
+        if (Gmac->RecvHandler)
+        {
+            Gmac->RecvHandler(Gmac->RecvArgs);
+        }
+
+        Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_RI);
+    }
+    else if ((RegValue & DMA_STATUS_TI) == DMA_STATUS_TI)
+    {
+        Ft_printf("DMA_STATUS_TI %x \r\n", RegValue);
+        Ft_printf("ti debug %x \r\n", Ft_in32(Gmac->Config.BaseAddress + GMAC_INTERNAL_MODULE_STATUS_OFFSET));
+
+        Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_TI);
+    }
+
+    Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_NIS);
+
+    /*  DMA Error */
+    if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_AIS) == DMA_STATUS_AIS)
+    {
+        if (Gmac->ErrorHandler)
+            Gmac->ErrorHandler(Gmac->ErrorArgs, FGmac_ErrorCheck(Gmac));
+        Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET));
+    }
+}

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac_sinit.c

@@ -0,0 +1,34 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-25 16:43:06
+ * @Description:  This files is for gmac static init
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_gmac.h"
+#include "ft_parameters.h"
+
+extern FGmac_Config_t Gmac_ConfigTable[FT_GMAC_INSTANCES_NUM];
+
+FGmac_Config_t *Ft_Gmac_LookupConfig(u32 InstanceId)
+{
+    FGmac_Config_t *CfgPtr = NULL;
+    u32 Index;
+    for (Index = 0; Index < (u32)FT_GMAC_INSTANCES_NUM; Index++)
+    {
+        if (Gmac_ConfigTable[Index].InstanceId == InstanceId)
+        {
+            CfgPtr = &Gmac_ConfigTable[Index];
+            break;
+        }
+    }
+
+    return (FGmac_Config_t *)CfgPtr;
+}

bsp/ft2004/libraries/bsp/ft_gpio/ft_gpio.c

@@ -0,0 +1,107 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 17:55:31
+ * @LastEditTime: 2021-05-25 16:43:31
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_gpio.h"
+#include "ft_gpio_hw.h"
+#include "ft_assert.h"
+#include "ft_debug.h"
+
+#define GPIO_MAX_PIN 7
+#define GPIO_MAX_CTRL_ID 1
+
+void FGpio_SetGroupModeA(FT_IN u32 ctrlId, FT_IN u8 pin, FT_IN u32 mode)
+{
+    u32 RegVal;
+    Ft_assertNoneReturn(ctrlId <= GPIO_MAX_CTRL_ID);
+    Ft_assertNoneReturn(pin <= GPIO_MAX_PIN);
+
+    RegVal = FGpioA_ReadReg(ctrlId, GPIO_INTEN);
+    switch (mode)
+    {
+    case GPIO_MODE_GPIO:
+        RegVal &= ~(1 << pin);
+        break;
+    case GPIO_MODE_INT:
+        RegVal |= (1 << pin);
+        break;
+    default:
+        Ft_assertNoneReturn(0);
+        break;
+    }
+
+    FGpioA_WriteReg(ctrlId, GPIO_INTEN, RegVal);
+    return;
+}
+
+static void FGpio_SetPinInOutA(FT_IN u32 ctrlId, FT_IN u8 pin, FT_IN u8 inOut)
+{
+    u32 RegVal;
+    Ft_assertNoneReturn(ctrlId <= GPIO_MAX_CTRL_ID);
+    Ft_assertNoneReturn(pin <= GPIO_MAX_PIN);
+
+    RegVal = FGpioA_ReadReg(ctrlId, GPIO_SWPORTA_DDR);
+    if (inOut != (RegVal & (0x1 << pin)))
+    {
+        if (GPIO_INPUT == inOut)
+        {
+            RegVal &= ~(0x1 << pin);
+        }
+        else if (GPIO_OUTPUT == inOut)
+        {
+            RegVal |= (0x1 << pin);
+        }
+        else
+        {
+            Ft_assertNoneReturn(0);
+        }
+
+        FGpioA_WriteReg(ctrlId, GPIO_SWPORTA_DDR, RegVal);
+    }
+
+    return;
+}
+
+u32 FGpio_ReadPinA(FT_IN u32 ctrlId, FT_IN u8 pin)
+{
+    u32 RegVal;
+    u32 OnOff;
+    Ft_assertNoneReturn(ctrlId <= GPIO_MAX_CTRL_ID);
+    Ft_assertNoneReturn(pin <= GPIO_MAX_PIN);
+
+    FGpio_SetPinInOutA(ctrlId, pin, GPIO_INPUT);
+    RegVal = FGpioA_ReadReg(ctrlId, GPIO_EXT_PORTA);
+    OnOff = (RegVal & (0x1 << pin)) ? GPIO_ON : GPIO_OFF;
+    return OnOff;
+}
+
+void FGpio_WritePinA(FT_IN u32 ctrlId, FT_IN u8 pin, FT_IN u8 onOff)
+{
+    u32 RegVal;
+    Ft_assertNoneReturn(ctrlId <= GPIO_MAX_CTRL_ID);
+    Ft_assertNoneReturn(pin <= GPIO_MAX_PIN);
+    Ft_assertNoneReturn((onOff == GPIO_OFF) || (onOff == GPIO_ON));
+
+    FGpio_SetPinInOutA(ctrlId, pin, GPIO_OUTPUT);
+    RegVal = FGpioA_ReadReg(ctrlId, GPIO_SWPORTA_DR);
+    if (GPIO_OFF == onOff)
+    {
+        RegVal &= ~(1 << pin);
+    }
+    else
+    {
+        RegVal |= (1 << pin);
+    }
+    FGpioA_WriteReg(ctrlId, GPIO_SWPORTA_DR, RegVal);
+    return;
+}

bsp/ft2004/libraries/bsp/ft_gpio/ft_gpio.h

@@ -0,0 +1,73 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 17:55:12
+ * @LastEditTime: 2021-04-30 14:38:45
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_BSP_GPIO_H
+#define FT_BSP_GPIO_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "ft_types.h"
+#include "ft_gpio_hw.h"
+
+/* gpio mode: gpio/int */
+#define GPIO_MODE_GPIO 0
+#define GPIO_MODE_INT 1
+
+/* define debug utilities */
+#define FT_GPIO_DEBUG_TAG "FT_GPIO"
+#define FT_GPIO_ENABLE_DEBUG
+#define FT_GPIO_ERROR(format, ...) FT_DEBUG_PRINT_E(FT_GPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#ifdef FT_GPIO_ENABLE_DEBUG
+#define FT_GPIO_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FT_GPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FT_GPIO_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FT_GPIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FT_GPIO_DEBUG_I(format, ...)
+#define FT_GPIO_DEBUG_W(format, ...)
+#endif
+
+   /**
+ * @name: FGpio_SetGroupModeA
+ * @msg: set gpio mode, polling or intr
+ * @return {*}
+ * @param {FT_IN u32} ctrlId
+ * @param {FT_IN u8} pin
+ * @param {FT_IN u32} mode
+ */
+   void FGpio_SetGroupModeA(FT_IN u32 CtrlId, FT_IN u8 Pin, FT_IN u32 Mode);
+   /**
+ * @name: FGpio_ReadPinA
+ * @msg: get gpio pin status
+ * @return {*}
+ * @param {FT_IN u32} ctrlId
+ * @param {FT_IN u8} pin
+ */
+   u32 FGpio_ReadPinA(FT_IN u32 CtrlId, FT_IN u8 Pin);
+   /**
+ * @name: FGpio_WritePinA
+ * @msg: set gpio pin status
+ * @return {*}
+ * @param {FT_IN u32} ctrlId
+ * @param {FT_IN u8} pin
+ * @param {FT_IN u8} onOff
+ */
+   void FGpio_WritePinA(FT_IN u32 CtrlId, FT_IN u8 Pin, FT_IN u8 OnOff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ft2004/libraries/bsp/ft_gpio/ft_gpio_hw.h

@@ -0,0 +1,92 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-27 17:55:22
+ * @LastEditTime: 2021-04-28 08:39:20
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_BSP_GPIO_HW_H
+#define FT_BSP_GPIO_HW_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "ft_types.h"
+#include "ft_io.h"
+
+#define GPIO_CTRL_ID_0 0
+#define GPIO_CTRL_ID_1 1
+
+/* base address of gpio register */
+#define GPIO_CTRL0_PA_BASE 0x28004000
+#define GPIO_CTRL1_PA_BASE 0x28005000
+#define GPIO_GROUPA_OFFSET 0x0
+#define GPIO_GROUPB_OFFSET 0xc
+
+/* offset of register map */
+#define GPIO_SWPORTA_DR 0x00  //A 组端口输出寄存器
+#define GPIO_SWPORTA_DDR 0x04 //A 组端口方向控制寄存器
+#define GPIO_EXT_PORTA 0x08   //A 组端口输入寄存器
+
+#define GPIO_SWPORTB_DR 0x0c  //B 组端口输出寄存器
+#define GPIO_SWPORTB_DDR 0x10 //B 组端口方向控制寄存器
+#define GPIO_EXT_PORTB 0x14   //B 组端口输入寄存器
+
+#define GPIO_INTEN 0x18         //A 组端口中断使能寄存器
+#define GPIO_INTMASK 0x1c       //A 组端口中断屏蔽寄存器
+#define GPIO_INTTYPE_LEVEL 0x20 //A 组端口中断等级寄存器
+#define GPIO_INT_POLARITY 0x24  //A 组端口中断极性寄存器
+#define GPIO_INTSTATUS 0x28     //A 组端口中断状态寄存器
+#define GPIO_RAW_INTSTATUS 0x2c //A 组端口原始中断状态寄存器
+
+#define GPIO_LS_SYNC 0x30   //配置中断同步寄存器
+#define GPIO_DEBOUNCE 0x34  //防反跳配置寄存器
+#define GPIO_PORTA_EOI 0x38 //A 组端口中断清除寄存器
+
+/* misc marco */
+#define GPIO_GROUP_A 0
+#define GPIO_OFF 0
+#define GPIO_ON 1
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+    inline static u32 FGpio_GetBaseAddr(FT_IN u32 ctrlId, FT_IN u32 groupId)
+    {
+        static const u32 CtrlAddr[2] = {GPIO_CTRL0_PA_BASE, GPIO_CTRL1_PA_BASE};
+        static const u32 GroupOff[2] = {GPIO_GROUPA_OFFSET, GPIO_GROUPB_OFFSET};
+        return CtrlAddr[ctrlId] + GroupOff[groupId];
+    }
+
+/**
+ * @name: FGpio_WriteReg
+ * @msg:  write gpio register
+ * @param {u32} BaseAddress base addr of i2c
+ * @param {u32} RegOffset   addr offset of i2c register
+ * @param {u32} RegisterValue val to be write into register
+ * @return {void}
+ */
+#define FGpioA_WriteReg(ctrlId, RegOffset, RegisterValue) Ft_out32(FGpio_GetBaseAddr(ctrlId, GPIO_GROUP_A) + (u32)RegOffset, (u32)RegisterValue)
+
+/**
+ * @name: FGpio_ReadReg
+ * @msg:  read gpio register
+ * @param {u32} BaseAddress base addr of i2c
+ * @param {u32} RegOffset   addr offset of i2c register
+ * @return {u32} val read from register
+ */
+#define FGpioA_ReadReg(ctrlId, RegOffset) Ft_in32(FGpio_GetBaseAddr(ctrlId, GPIO_GROUP_A) + (u32)RegOffset)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ft2004/libraries/bsp/ft_i2c/ft_i2c.h

@@ -0,0 +1,197 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:32:20
+ * @Description:  This files is for i2c user interface
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_BSP_I2C_H
+#define FT_BSP_I2C_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "ft_types.h"
+#include "ft_debug.h"
+#include "ft_assert.h"
+#include "ft_error_code.h"
+#include "ft_i2c_hw.h"
+
+    /* I2C Ctrl instance */
+    typedef enum
+    {
+        I2C_CTRL_ID_0 = 0,
+        I2C_CTRL_ID_1,
+        I2C_CTRL_ID_2,
+        I2C_CTRL_ID_3,
+
+        MAX_I2C_CTRL_ID,
+    } FI2C_Instance_t;
+
+    static const u32 g_FI2cIrqNum[MAX_I2C_CTRL_ID] = {
+        44, 45, 46, 47};
+
+    static const u32 g_FI2cRegBaseAddr[MAX_I2C_CTRL_ID] = {
+        I2C0_BASE_ADDRESS, I2C1_BASE_ADDRESS,
+        I2C2_BASE_ADDRESS, I2C3_BASE_ADDRESS};
+
+#define I2C_DEFAULT_IRQ_PRIORITY 0
+
+    /* Type of I2C device */
+    typedef enum
+    {
+        I2C_MASTER_DEV = 0,
+        I2C_SLAVE_DEV,
+
+        MAX_I2C_DEV
+    } FI2C_DevType_t;
+
+    /* I2C work mode type */
+    typedef enum
+    {
+        I2C_POLLING_MODE = 0,
+        I2C_IRQ_MODE,
+
+        MAX_I2C_WORKMODE
+    } FI2C_WorkMode_t;
+
+    /* Type of I2C bus speed */
+    typedef enum
+    {
+        I2C_STANDARD_SPEED = 0,
+        I2C_FAST_SPEED,
+        I2C_HIGH_SPEED,
+
+        MAX_I2C_SPEED,
+    } FI2C_SpeedType_t;
+
+    /* I2C error code Submodule */
+    typedef enum
+    {
+        I2C_ERR_MODE_DEF = 0,
+
+        MAX_I2C_ERR_MODE,
+    } FI2C_Submodule_t;
+
+    /* I2C irq type */
+    typedef enum
+    {
+        I2C_IRQ_TYPE_NONE = 0,
+        I2C_IRQ_TYPE_TX_COMPLETE,
+        I2C_IRQ_TYPE_RX_COMPLETE,
+
+        MAX_I2C_IRQ_TYPE
+    } FI2C_IrqType_t;
+
+    /* I2C config info */
+    typedef struct
+    {
+        FI2C_Instance_t InstanceId; /* Id of I2C ctrl instance */
+        u32 BaseAddress;            /* base address of I2C register */
+        FI2C_DevType_t WorkMode;    /* work as master or slave */
+        FI2C_SpeedType_t BusSpeed;  /* bus speed setting */
+        u32 SclLcnt;
+        u32 SclHcnt;
+        u32 RxThres;
+        u32 TxThres;
+        bool_t Is7BitAddr; /* TRUE: use 7 bit addr, FALSE: use 10 bit addr */
+        bool_t IsPolling;  /* is polling */
+        u32 IrqNum;        /* irq num of I2C in system */
+        u32 IrqPriority;   /* irq priority */
+        u32 BlockSize;     /* block size, for eeprom */
+        bool_t WRByFifo;
+    } FI2C_Config_t;
+
+    /* I2C RX/TX buffer */
+    typedef struct
+    {
+        u8 *BytePtr;
+        u32 TotalBytes;
+        u32 DataLength;
+        u32 CurIndex;
+    } FI2C_Buffer_t;
+
+    typedef void (*FI2C_IrqCallBackHandler_t)(FT_IN u32 IrqType,
+                                              FT_INOUT void *pDev,
+                                              FT_INOUT void *pArg);
+    typedef void (*FI2C_IrqWaitHandler_t)(FT_IN u32 IrqType,
+                                          FT_INOUT void *pDev);
+    typedef int32_t (*FI2C_DelayHandler_t)(FT_IN u32);
+
+    /* I2C device info */
+    typedef struct
+    {
+        FI2C_Config_t Config; /* Configuration data structure  */
+
+        void *pRxEvent;
+        void *pTxEvent;
+        FI2C_IrqCallBackHandler_t pIrqCallBack;
+        FI2C_IrqWaitHandler_t pWaitCallBack;
+        u32 LastIrqErr;
+        FI2C_Buffer_t RxBuf;
+        FI2C_Buffer_t TxBuf;
+
+        FI2C_DelayHandler_t DelayHandle;
+        bool_t IsReady; /* Device is ininitialized and ready*/
+        u16 SlaveAddr;  /* address of I2C slave device for master */
+    } FI2C_t;
+
+    void FI2C_initMaster(FT_IN FI2C_Instance_t id,
+                         FT_IN FI2C_WorkMode_t mode,
+                         FT_IN u32 SlaveAddr,
+                         FT_IN bool_t UseWRFifo,
+                         FT_IN u32 PageSize,
+                         FT_INOUT FI2C_t *pDev);
+    u32 FI2C_writeByByte(FT_IN u32 len, FT_IN u8 *pI2cBuf, FT_IN u8 PageAddr,
+                         FT_INOUT FI2C_t *pDev);
+    u32 FI2C_readByByte(FT_IN u32 len, FT_OUT u8 *pI2cBuf, FT_IN u8 PageAddr,
+                        FT_INOUT FI2C_t *pDev);
+    u32 FI2C_setIrqHandler(FT_IN FI2C_IrqType_t IrqType, FT_IN FI2C_DelayHandler_t pHandler, FT_IN void *pArgs,
+                           FT_INOUT FI2C_t *pDev);
+    void FI2C_irqHandler(void *pArgs);
+    void FI2C_irqHandler4Fifo(void *pArgs);
+    u32 FI2C_getIrqMask(FT_IN FI2C_t *pDev);
+    void FI2C_setIrqMask(FT_IN FI2C_t *pDev, FT_IN u32 mask);
+    void FI2C_setIrq(FT_IN FI2C_t *pDev, FT_IN u32 maskBit, FT_IN bool_t enable);
+    bool_t FI2C_checkIfIntr(FT_IN FI2C_t *pDev);
+    u32 FI2C_writeByFifo(FT_IN u8 PageAddr, FT_INOUT FI2C_t *pDev);
+    u32 FI2C_readByFifo(FT_IN u8 PageAddr, FT_INOUT FI2C_t *pDev);
+    void FI2C_deInitMaster(FT_INOUT FI2C_t *pDev);
+
+#define FT_I2C_DEBUG_TAG "FT_I2C"
+//#define FT_I2C_ENABLE_DEBUG
+#define FT_I2C_ERROR(format, ...) FT_DEBUG_PRINT_E(FT_I2C_DEBUG_TAG, format, ##__VA_ARGS__)
+#ifdef FT_I2C_ENABLE_DEBUG
+#define FT_I2C_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FT_I2C_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FT_I2C_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FT_I2C_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FT_I2C_DEBUG_I(format, ...)
+#define FT_I2C_DEBUG_W(format, ...)
+#endif
+
+#define ERR_I2C_OK ERR_SUCCESS
+#define ERR_I2C_NOT_READY FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 1)
+#define ERR_I2C_WRITE_TIMEOUT FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 2)
+#define ERR_I2C_READ_TIMEOUT FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 3)
+#define ERR_I2C_SIZE_TOO_LARGE FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 4)
+#define ERR_I2C_NOT_SUPPORT FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 5)
+#define ERR_I2C_INVALID_PARAM FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 6)
+#define ERR_I2C_INVALID_HANDLER FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 7)
+#define ERR_I2C_INVALID_NO_MEM FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 8)
+#define ERR_I2C_BUS_NOT_ENABLED FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 9)
+#define ERR_I2C_EVT_TIMEOUT FT_CODE_ERR(errModeI2c, I2C_ERR_MODE_DEF, 0xA)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ft2004/libraries/bsp/ft_i2c/ft_i2c_g.c

@@ -0,0 +1,13 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-20 15:35:23
+ * @LastEditTime: 2021-04-20 15:35:24
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */

bsp/ft2004/libraries/bsp/ft_i2c/ft_i2c_irq.c

@@ -0,0 +1,182 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-20 15:35:44
+ * @LastEditTime: 2021-05-25 16:44:45
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_i2c.h"
+
+void FI2C_irqHandler(void *pArgs)
+{
+    FI2C_t *pDev;
+    u32 RegVal;
+    FI2C_IrqType_t IrqType = I2C_IRQ_TYPE_NONE;
+
+    Ft_assertNoneReturn(NULL != pArgs);
+    pDev = (FI2C_t *)pArgs;
+
+    RegVal = FI2C_GET_IRQ_STATUS(pDev);
+    if (I2C_IRQ_RX_FULL & RegVal)
+    {
+        IrqType = I2C_IRQ_TYPE_RX_COMPLETE;
+    }
+    else if (I2C_IRQ_TX_EMPTY & RegVal)
+    {
+        IrqType = I2C_IRQ_TYPE_TX_COMPLETE;
+    }
+
+    if ((NULL != pDev->pIrqCallBack) && (I2C_IRQ_TYPE_NONE != IrqType))
+    {
+        pDev->pIrqCallBack(IrqType, pDev, NULL);
+    }
+
+    if (I2C_IRQ_TYPE_RX_COMPLETE == IrqType)
+    {
+        FI2C_setIrq(pDev, I2C_IRQ_RX_FULL, FALSE);
+    }
+    else if (I2C_IRQ_TYPE_TX_COMPLETE == IrqType)
+    {
+        FI2C_setIrq(pDev, I2C_IRQ_TX_EMPTY, FALSE);
+    }
+
+    FI2C_CLR_ALL_IRQ_STATUS(pDev);
+    return;
+}
+
+void FI2C_irqHandler4Fifo(void *pArgs)
+{
+    FI2C_t *pDev;
+    u32 RegVal;
+    u32 BytesToRx;
+    FI2C_IrqType_t IrqType = I2C_IRQ_TYPE_NONE;
+
+    Ft_assertNoneReturn(NULL != pArgs);
+    pDev = (FI2C_t *)pArgs;
+
+    /* check if i2c controller is enabled */
+    if (!FI2C_IS_I2C_BUS_ENABLED(pDev))
+    {
+        pDev->LastIrqErr = ERR_I2C_BUS_NOT_ENABLED;
+        return;
+    }
+
+    /* check there is no interrupt */
+    if (!FI2C_checkIfIntr(pDev))
+    {
+        pDev->LastIrqErr = ERR_I2C_INVALID_PARAM;
+        return;
+    }
+
+    /* read interrupt status  */
+    RegVal = FI2C_GET_IRQ_STATUS(pDev);
+    if (I2C_IRQ_RX_FULL & RegVal)
+    {
+        IrqType = I2C_IRQ_TYPE_RX_COMPLETE;
+        BytesToRx = FI2C_GET_RXFLR(pDev);
+
+        while ((pDev->RxBuf.CurIndex < pDev->RxBuf.DataLength) &&
+               (0 < BytesToRx))
+        {
+            /* read one byte */
+            pDev->RxBuf.BytePtr[pDev->RxBuf.CurIndex] = FI2C_GET_RX_DATA(pDev);
+
+            pDev->RxBuf.CurIndex++;
+            BytesToRx--;
+            pDev->DelayHandle(10);
+
+            /* read next byte */
+            if (pDev->RxBuf.CurIndex != pDev->RxBuf.DataLength)
+            {
+                FI2C_SEND_RX_NEXT_CMD(pDev);
+            }
+            else
+            {
+                FI2C_SEND_RX_STOP_CMD(pDev);
+                pDev->DelayHandle(10);
+                FI2C_setIrq(pDev, I2C_IRQ_RX_FULL, FALSE);
+            }
+        }
+    }
+    else if (I2C_IRQ_TX_EMPTY & RegVal)
+    {
+        IrqType = I2C_IRQ_TYPE_TX_COMPLETE;
+
+        if (pDev->TxBuf.CurIndex == pDev->TxBuf.DataLength)
+        {
+            FI2C_SEND_TX_STOP_CMD(pDev);
+            pDev->DelayHandle(10);
+            FI2C_setIrq(pDev, I2C_IRQ_TX_EMPTY, FALSE);
+        }
+        else
+        {
+            FI2C_SET_TX_DATA(pDev, pDev->TxBuf.BytePtr[pDev->TxBuf.CurIndex]);
+            pDev->TxBuf.CurIndex++;
+        }
+    }
+
+    if ((NULL != pDev->pIrqCallBack) && (I2C_IRQ_TYPE_NONE != IrqType))
+    {
+        pDev->pIrqCallBack(IrqType, pDev, NULL);
+    }
+
+    pDev->LastIrqErr = ERR_I2C_OK;
+    return;
+}
+
+u32 FI2C_getIrqMask(FT_IN FI2C_t *pDev)
+{
+    u32 RegVal;
+    Ft_assertNoneReturn(NULL != pDev);
+
+    RegVal = FI2C_GET_IRQ_MASK(pDev);
+    return RegVal;
+}
+
+void FI2C_setIrqMask(FT_IN FI2C_t *pDev, FT_IN u32 mask)
+{
+    u32 RegVal;
+    Ft_assertNoneReturn(NULL != pDev);
+
+    RegVal = mask & I2C_IRQ_ALL_MASK;
+    FI2C_SET_IRQ_MASK(pDev, RegVal);
+    return;
+}
+
+void FI2C_setIrq(FT_IN FI2C_t *pDev, FT_IN u32 maskBit, FT_IN bool_t enable)
+{
+    Ft_assertNoneReturn(0x0 != maskBit);
+
+    if (TRUE == enable)
+    {
+        FI2C_setIrqMask(pDev, FI2C_getIrqMask(pDev) | maskBit);
+    }
+    else
+    {
+        FI2C_setIrqMask(pDev, FI2C_getIrqMask(pDev) & (~maskBit));
+    }
+    return;
+}
+
+bool_t FI2C_checkIfIntr(FT_IN FI2C_t *pDev)
+{
+    u32 RegVal;
+    Ft_assertNoneReturn(NULL != pDev);
+
+    RegVal = FI2C_ReadReg(FI2C_GET_BASE_ADDR(pDev), I2C_RAW_INTR_STAT);
+    if (0 == (RegVal & (~I2C_IRQ_ACTIVITY)))
+    {
+        return FALSE;
+    }
+    else
+    {
+        return TRUE;
+    }
+}

bsp/ft2004/libraries/bsp/ft_i2c/ft_i2c_selftest.c

@@ -0,0 +1,20 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:27:24
+ * @Description:  This files is for i2c test cases
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include <time.h>
+#include <string.h>
+#include "ft_i2c_hw.h"
+#include "ft_i2c.h"
+#include "ft_status.h"
+#include "ft_printf.h"

bsp/ft2004/libraries/bsp/ft_qspi/ft_qspi.h

@@ -0,0 +1,184 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-05 21:31:10
+ * @LastEditTime: 2021-04-05 21:31:10
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ * *   v1.0  hh       2021-04-05     init
+ */
+
+#ifndef FT_QSPI_H
+#define FT_QSPI_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "ft_types.h"
+#include "ft_error_code.h"
+
+#define FQSPI_SUCCESS FST_SUCCESS                                                      /* SUCCESS */
+#define FQSPI_FAILURE FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_FAILURE)             /* Normal */
+#define FQSPI_TIMEOUT FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_TIMEOUT)             /* Timeout */
+#define FQSPI_EILSEQ FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_EILSEQ)               /* Illegal byte sequence. */
+#define FQSPI_INVALID_PARAM FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_INVALID_PARAM) /* Invalid param. */
+
+/* qspi bsp command instruction operation  */
+#define FQSPI_CMD_NEED_ADDR_MASK 0x1U
+#define FQSPI_CMD_NEED_DUMMY_MASK 0x2U
+#define FQSPI_CMD_NEED_GET_MASK 0x4U
+#define FQSPI_CMD_NEED_SET_MASK 0x08U
+#define FQSPI_CMD_ADDRESS_3BYTE_MASK 0x10U
+#define FQSPI_CMD_ADDRESS_4BYTE_MASK 0x20U
+
+/* qspi cmd of transfer operation */
+#define FQSPI_DATA_NEED_DUMMY_MASK 0x1U
+#define FQSPI_DATA_ADDRESS_3BYTE_MASK 0x2U
+#define FQSPI_DATA_ADDRESS_4BYTE_MASK 0x4U
+
+#define FQSPI_FLASH_CMD_WRR 0x01        /* Write status register */
+#define FQSPI_FLASH_CMD_PP 0x02         /* Page program */
+#define FQSPI_FLASH_CMD_READ 0x03       /* Normal read data bytes */
+#define FQSPI_FLASH_CMD_WRDI 0x04       /* Write disable */
+#define FQSPI_FLASH_CMD_RDSR1 0x05      /* Read status register */
+#define FQSPI_FLASH_CMD_WREN 0x06       /* Write enable */
+#define FQSPI_FLASH_CMD_RDSR2 0x07      /* Read status register */
+#define FQSPI_FLASH_CMD_FAST_READ 0x0B  /* Fast read data bytes */
+#define FQSPI_FLASH_CMD_4FAST_READ 0x0C /* Fast read data bytes */
+#define FQSPI_FLASH_CMD_4PP 0x12        /* Page program */
+#define FQSPI_FLASH_CMD_4READ 0x13      /* Normal read data bytes */
+#define FQSPI_FLASH_CMD_P4E 0x20        /* Erase 4kb sector */
+#define FQSPI_FLASH_CMD_4P4E 0x21       /* Erase 4kb sector */
+#define FQSPI_FLASH_CMD_QPP 0x32        /* Quad Page program */
+#define FQSPI_FLASH_CMD_4QPP 0x34       /* Quad Page program */
+#define FQSPI_FLASH_CMD_RDCR 0x35       /* Read config register */
+#define FQSPI_FLASH_CMD_BE 0x60         /* Bulk erase */
+#define FQSPI_FLASH_CMD_RDAR 0x65       /* Read Any Register  */
+#define FQSPI_FLASH_CMD_QOR 0x6B        /* Quad read data bytes */
+#define FQSPI_FLASH_CMD_4QOR 0x6C       /* Quad read data bytes */
+#define FQSPI_FLASH_CMD_WRAR 0x71       /* Write Any Register  */
+#define FQSPI_FLASH_CMD_RDID 0x9F       /* Read JEDEC ID */
+#define FQSPI_FLASH_CMD_4BAM 0xB7       /* Enter 4 Bytes Mode */
+#define FQSPI_FLASH_CMD_4BE 0xC7        /* Bulk erase */
+#define FQSPI_FLASH_CMD_SE 0xD8         /* Sector erase */
+#define FQSPI_FLASH_CMD_4SE 0xDC        /* Sector erase */
+#define FQSPI_FLASH_CMD_4BEX 0xE9       /* Exit 4 Bytes Mode */
+#define FQSPI_FLASH_CMD_QIOR 0xEB       /* Quad read data bytes */
+#define FQSPI_FLASH_CMD_4QIOR 0xEC      /* Quad read data bytes */
+#define FQSPI_FLASH_DISCOVERABLE_PARAMETER 0x5a
+#define FQSPI_CMD_ENABLE_RESET 0x66
+#define FQSPI_CMD_RESET 0x99
+
+    struct FQSpi_DataPack
+    {
+        u32 flags;      /* Follow qspi cmd of transfer operation */
+        u32 cmd;        /* Command instruction */
+        u32 addr;       /* Flash address */
+        u32 dummyCycle; /* dummy Cycle */
+        const u8 *txBuf;
+        u8 *rxBuf;  /* Need send or read buffer */
+        u32 length; /*  Buffer length */
+    };
+
+    struct FQSpi_CmdPack
+    {
+        u32 flags;      /* Follow qspi bsp command instruction operation */
+        u32 cmd;        /* Command instruction */
+        u32 addr;       /* Command address */
+        u32 dummyCycle; /* dummy Cycle */
+        const u8 *txBuf;
+        u8 *rxBuf;  /* Need send or read buffer */
+        u32 length; /*  Buffer length */
+    };
+
+    typedef struct
+    {
+        u32 instanceId;        /* Id of device */
+        uintptr_t baseAddress; /* Base address of qspi */
+        u32 transMode;         /* Transfer mode */
+        u32 capacity;          /* Flash capacity */
+        u32 addrMode;          /**/
+        u32 clkDiv;
+        u32 qspiDevNum; /*Qspi device number */
+        u32 channel;    /* Cs number */
+        u32 bitWidth;   /* Transfer unit width */
+    } FQSpi_Config_t;
+
+    typedef struct
+    {
+        FQSpi_Config_t config;
+        u32 isReady; /**< Device is initialized and ready */
+
+    } FQSpi_t;
+
+    /**
+     * @name: FQSpi_LookupConfig
+     * @msg:  FQSpi_LookupConfig returns a reference FQSpi_Config_t structure based on the
+     *          unique device id.
+     * @in param {u32} instanceId : unique device
+     * @return {FQSpi_Config_t} FQSpi_Config_t is a reference to a config record in the configuration
+     *        table (in qspi_g.c) corresponding to <i>instanceId</i>, or NULL if no match is found.
+     */
+    FQSpi_Config_t *FQSpi_LookupConfig(u32 instanceId);
+
+    /**
+     * @name: FQSpi_CfgInitialize
+     * @msg:  This function intializes the configuration for the qspi instance
+     * @in param {FQSpi_t *} pQspi:  A pointer to the qspi instance
+     * @in param {FQSpi_Config_t *} pConfig:  A pointer to the qspi instance config record
+     * @return {ft_error_t}
+     */
+    ft_error_t FQSpi_CfgInitialize(FQSpi_t *pQspi, FQSpi_Config_t *pConfig);
+
+    /**
+     * @name: FQSpi_CmdOperation
+     * @msg:  This function send command instruction  by the struct FQSpi_CmdPack
+     * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance
+     * @in param {struct FQSpi_CmdPack *} pCmdPack:  Need to send command instruction package
+     * @return {ft_error_t}
+     */
+    ft_error_t FQSpi_CmdOperation(FQSpi_t *pQspi, struct FQSpi_CmdPack *pCmdPack);
+
+    /**
+     * @name: FQSpi_Read
+     * @msg:  This function reads flash data from a specific address by {struct FQSpi_DataPack}
+     * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance
+     * @in param {struct FQSpi_DataPack *} pDataPack: Need to read data package
+     * @return {ft_error_t}
+     */
+    ft_error_t FQSpi_Read(FQSpi_t *pQspi, struct FQSpi_DataPack *pDataPack);
+
+    /**
+     * @name: FQSpi_Write
+     * @msg:  This function writes data  from a specific address by {struct FQSpi_DataPack}
+     * @in param {FQSpi_t *} pQspi:  A pointer to the qspi instance
+     * @in param {struct FQSpi_DataPack *} pDataPack: Need to read data package
+     * @return {ft_error_t}
+     */
+    ft_error_t FQSpi_Write(FQSpi_t *pQspi, struct FQSpi_DataPack *pDataPack);
+
+    /**
+     * @name: FQSpi_FlashRegSet
+     * @msg:  This function sends command instruction with specific parameters
+     * @in param {FQSpi_t *} pQspi:  A pointer to the qspi instance
+     * @in param {FT_IN u8} cmd:   Command instruction
+     * @in param {FT_IN u8 *} writebuf: Data that needs to be sent through command instruction registers
+     * @in param {u32} length: Data length
+     * @return {ft_error_t}
+     */
+    ft_error_t FQSpi_FlashRegSet(FQSpi_t *pQspi,
+                                 FT_IN u8 cmd,
+                                 FT_IN u8 *writebuf,
+                                 u32 length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ft2004/libraries/bsp/ft_qspi/qspi_g.c

@@ -0,0 +1,26 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 11:31:12
+ * @LastEditTime: 2021-04-07 11:31:13
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ * *   v1.0   hh       2021-04-07    init
+ */
+#include "ft_qspi.h"
+#include "ft_parameters.h"
+
+FQSpi_Config_t FqSpi_ConfigTable[FT_QSPI_NUM] = {
+    {.instanceId = FT_QSPI_INSTANCE,      /* Id of device */
+     .baseAddress = FT_QSPI_BASEADDR,     /* Base address of qspi */
+     .transMode = FT_QSPI_TRANSFER_1_1_1, /* Transfer mode */
+     .capacity = FT_QSPI_FLASH_CAP_32MB,  /* Flash capacity */
+     .addrMode = FT_QSPI_ADDR_SEL_3,      /**/
+     .clkDiv = FT_QSPI_SCK_DIV_128,
+     .qspiDevNum = 1,
+     .channel = 0,
+     .bitWidth = 8}};

bsp/ft2004/libraries/bsp/ft_qspi/qspi_hw.c

@@ -0,0 +1,25 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-02 18:32:42
+ * @LastEditTime: 2021-04-02 18:32:43
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+#include "qspi_hw.h"
+#include "ft_qspi.h"
+#include "ft_assert.h"
+#include "ft_io.h"
+
+void FQSpi_Reset(FQSpi_t *pQspi)
+{
+    FQSpi_Config_t *pConfig = NULL;
+    Ft_assertVoid(pQspi != NULL);
+    pConfig = &pQspi->config;
+    Ft_out32(pConfig->baseAddress + FT_REG_QSPI_CAP_OFFSET,
+             FT_REG_QSPI_CAP_FLASH_NUM(pConfig->qspiDevNum) | FT_REG_QSPI_CAP_FLASH_CAP(pConfig->capacity));
+}

bsp/ft2004/libraries/bsp/ft_qspi/qspi_hw.h

@@ -0,0 +1,199 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-02 18:32:54
+ * @LastEditTime: 2021-05-24 14:33:45
+ * @Description:  Description of file
+ *
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef QSPI_HW_H
+#define QSPI_HW_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "ft_qspi.h"
+#include "ft_types.h"
+
+/* register definition */
+#define FT_REG_QSPI_CAP_OFFSET (0x00)       /* Flash capacity setting register */
+#define FT_REG_QSPI_RD_CFG_OFFSET (0x04)    /* Address access reads configuration registers */
+#define FT_REG_QSPI_WR_CFG_OFFSET (0x08)    /* Write buffer flush register */
+#define FT_REG_QSPI_FLUSH_OFFSET (0x0C)     /* Write buffer flush register */
+#define FT_REG_QSPI_CMD_PORT_OFFSET (0x10)  /* Command port register */
+#define FT_REG_QSPI_ADDR_PORT_OFFSET (0x14) /* Address port register */
+#define FT_REG_QSPI_HD_PORT_OFFSET (0x18)   /* Upper bit port register */
+#define FT_REG_QSPI_LD_PORT_OFFSET (0x1C)   /* low bit port register */
+#define FT_REG_QSPI_FUN_SET_OFFSET (0x20)   /* CS setting register  */
+#define FT_REG_QSPI_WIP_RD_OFFSET (0x24)    /* WIP reads the Settings register */
+#define FT_REG_QSPI_WP_OFFSET (0x28)        /* WP register */
+#define FT_REG_QSPI_MODE_OFFSET (0x2C)      /* Mode setting register */
+
+/*QSPI_CAP*/
+#define FT_REG_QSPI_CAP_FLASH_NUM(data) ((data) << 3) /* Flash number */
+#define FT_REG_QSPI_CAP_FLASH_CAP(data) ((data) << 0) /*  The flash capacity */
+
+/* RD_CFG */
+#define FT_RD_CFG_CMD(data) ((data) << 24)       /* Read Command */
+#define FT_RD_CFG_THROUGH(data) ((data) << 23)   /*  The programming flag in the status register */
+#define FT_RD_CFG_TRANSFER(data) ((data) << 20)  /*  */
+#define FT_RD_CFG_ADDR_SEL(data) ((data) << 19)  /*  */
+#define FT_RD_CFG_LATENCY(data) ((data) << 18)   /*  */
+#define FT_RD_CFG_MODE_BYTE(data) ((data) << 17) /*  */
+#define FT_RD_CFG_CMD_SIGN(data) ((data) << 9)   /*  */
+#define FT_RD_CFG_DUMMY(data) ((data) << 4)      /*  */
+#define FT_RD_CFG_D_BUFFER(data) ((data) << 3)   /*  */
+#define FT_RD_CFG_SCK_SEL(data) ((data) << 0)    /*  */
+
+/*QSPI_WR_CFG*/
+#define FT_WR_CFG_CMD(data) ((data) << 24)
+#define FT_WR_CFG_WAIT(data) ((data) << 9)
+#define FT_WR_CFG_THROUGH(data) ((data) << 8)
+#define FT_WR_CFG_TRANSFER(data) ((data) << 5)
+#define FT_WR_CFG_ADDRSEL(data) ((data) << 4)
+#define FT_WR_CFG_MODE(data) ((data) << 3)
+#define FT_WR_CFG_SCK_SEL(data) ((data) << 0)
+
+/*QSPI_CMD_PORT*/
+#define FT_CMD_PORT_CMD(data) ((data) << 24)
+#define FT_CMD_PORT_WAIT(data) ((data) << 22)
+#define FT_CMD_PORT_THROUGH(data) ((data) << 21)
+#define FT_CMD_PORT_CS(data) ((data) << 19)
+#define FT_CMD_PORT_TRANSFER(data) ((data) << 16)
+#define FT_CMD_PORT_ADDR(data) ((data) << 15)
+#define FT_CMD_PORT_LATENCY(data) ((data) << 14)
+#define FT_CMD_PORT_DATA_TRANS(data) ((data) << 13)
+#define FT_CMD_PORT_ADDR_SEL(data) ((data) << 12)
+#define FT_CMD_PORT_DUMMY(data) ((data) << 7)
+#define FT_CMD_PORT_P_BUFFER(data) ((data) << 6)
+#define FT_CMD_PORT_RW_NUM(data) ((data) << 3)
+#define FT_CMD_PORT_CLK_SEL(data) ((data) << 0)
+
+/*QSPI_FUN_SET*/
+#define FT_FUN_SET_CS_HOLD(data) ((data) << 24)
+#define FT_FUN_SET_CS_SETUP(data) ((data) << 16)
+#define FT_FUN_SET_CS_DELAY(data) ((data) << 0)
+
+/*QSPI_WIP_RD*/
+#define FT_WIP_RD_CMD(data) ((data) << 24)
+#define FT_WIP_RD_TRANSFER(data) ((data) << 3)
+#define FT_WIP_RD_SCK_SEL(data) ((data) << 0)
+
+/*QSPI_WP*/
+#define FT_WP_EN(data) ((data) << 17)
+#define FT_WP_WP(data) ((data) << 16)
+#define FT_WP_HOLD(data) ((data) << 8)
+#define FT_WP_SETUP(data) ((data) << 0)
+
+/*QSPI_MODE*/
+#define FT_MODE_VALID(data) ((data) << 8)
+#define FT_MODE_MODE(data) ((data) << 0)
+
+#define FT_QSPI_FLASH_CAP_4MB 0
+#define FT_QSPI_FLASH_CAP_8MB 1
+#define FT_QSPI_FLASH_CAP_16MB 2
+#define FT_QSPI_FLASH_CAP_32MB 3
+#define FT_QSPI_FLASH_CAP_64MB 4
+#define FT_QSPI_FLASH_CAP_128MB 5
+#define FT_QSPI_FLASH_CAP_256MB 6
+
+#define FT_QSPI_ADDR_SEL_3 0
+#define FT_QSPI_ADDR_SEL_4 1
+
+#define FT_QSPI_SCK_DIV_128 0
+#define FT_QSPI_SCK_DIV_2 1
+#define FT_QSPI_SCK_DIV_4 2
+#define FT_QSPI_SCK_DIV_8 3
+#define FT_QSPI_SCK_DIV_16 4
+#define FT_QSPI_SCK_DIV_32 5
+#define FT_QSPI_SCK_DIV_64 6
+
+#define FT_QSPI_TRANSFER_1_1_1 0
+#define FT_QSPI_TRANSFER_1_1_2 1
+#define FT_QSPI_TRANSFER_1_1_4 2
+#define FT_QSPI_TRANSFER_1_2_2 3
+#define FT_QSPI_TRANSFER_1_4_4 4
+#define FT_QSPI_TRANSFER_2_2_2 5
+#define FT_QSPI_TRANSFER_4_4_4 6
+
+    /* typedefs */
+    /*QSPI_RD_CFG*/
+    typedef union
+    {
+        u32 data;
+        struct
+        {
+            u32 rdSckSel : 3;   /* 2:0   */
+            u32 dBuffer : 1;    /* 3     */
+            u32 dummy : 5;      /* 8:4   */
+            u32 cmdSign : 8;    /* 16:9  */
+            u32 modeByte : 1;   /* 17    */
+            u32 rdLatency : 1;  /* 18    */
+            u32 rdAddrSel : 1;  /* 19    */
+            u32 rdTransfer : 3; /* 22:20 */
+            u32 rdThrough : 1;  /* 23    */
+            u32 rdCmd : 8;      /* 31:24 */
+        } val;
+    } FQSpi_RdCfgReg_t;
+
+    /*QSPI_WR_CFG*/
+    typedef union
+    {
+        u32 data;
+        struct
+        {
+            u32 wrSckSel : 3;   /* 2:0   */
+            u32 wrMode : 1;     /* 3     */
+            u32 wrAddrsel : 1;  /* 4     */
+            u32 wrTransfer : 3; /* 7:5   */
+            u32 wrThrough : 1;  /* 8     */
+            u32 wrWait : 1;     /* 9     */
+            u32 wrRes : 14;     /* 23:10 */
+            u32 wrCmd : 8;      /* 31:24 */
+        } val;
+    } FQSpi_WrCfgReg_t;
+
+    /*QSPI_CMD_PORT*/
+    typedef union
+    {
+        u32 data;
+        struct
+        {
+            u32 sckSel : 3;       /* 2:0   */
+            u32 rwMum : 3;        /* 5:3   */
+            u32 pBuffer : 1;      /* 6     */
+            u32 dummy : 5;        /* 11:7  */
+            u32 addrSel : 1;      /* 12    */
+            u32 dataTransfer : 1; /* 13    */
+            u32 latency : 1;      /* 14    */
+            u32 cmdAddr : 1;      /* 15    */
+            u32 transfer : 3;     /* 18:16 */
+            u32 cs : 2;           /* 20:19 */
+            u32 through : 1;      /* 21    */
+            u32 wait : 1;         /* 22    */
+            u32 res : 1;          /* 23    */
+            u32 cmd : 8;          /* 31:24 */
+        } val;
+    } FQSpi_CmdPortReg_t;
+
+    /**
+ * @name: FQSpi_Reset
+ * @msg:  This routine performs the QSPI controller initialization.
+ * @in param: pQspi
+ * @return {*}
+ */
+    void FQSpi_Reset(FQSpi_t *pQspi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !

bsp/ft2004/libraries/bsp/ft_qspi/qspi_sinit.c

@@ -0,0 +1,34 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 13:22:01
+ * @LastEditTime: 2021-04-07 13:22:01
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_qspi.h"
+#include "ft_parameters.h"
+
+extern FQSpi_Config_t FqSpi_ConfigTable[FT_QSPI_NUM];
+
+FQSpi_Config_t *FQSpi_LookupConfig(u32 instanceId)
+{
+    FQSpi_Config_t *pFQSpi_Config_t = NULL;
+
+    u32 Index;
+    for (Index = 0; Index < (u32)FT_GMAC_INSTANCES_NUM; Index++)
+    {
+        if (FqSpi_ConfigTable[Index].instanceId == instanceId)
+        {
+            pFQSpi_Config_t = &FqSpi_ConfigTable[Index];
+            break;
+        }
+    }
+
+    return pFQSpi_Config_t;
+}

bsp/ft2004/libraries/bsp/ft_sd/ft_sdctrl_g.c

@@ -0,0 +1,31 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-03-31 14:59:20
+ * @LastEditTime: 2021-05-24 14:34:13
+ * @Description:  This files is for sd ctrl config definition
+ *
+ * @Modify History: * * Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_sdctrl.h"
+#include "ft_parameters.h"
+
+/* configs of sd ctrl */
+FSdCtrl_Config_t FSdCtrl_Config[FT_SDC_NUM] =
+    {
+        {
+            .instanceId = FT_SDC_INSTANCE,
+            .baseAddress = FT_SDC_BASEADDR,
+            .inputClockHz = FT_SDC_FREQ,
+            .cardDetect = 1,
+            .writeProtect = 0,
+            .busWidth = 1,
+            .dmaIrqNum = 52,
+            .normalIrqNum = 53,
+            .errIrqNum = 54,
+            .workMode = 0 /*FTSDCTRL_CMD_IRQ_MASK | FTSDCTRL_DATA_WRITE_IRQ_MASK | FTSDCTRL_DATA_READ_IRQ_MASK*/
+        }};

bsp/ft2004/libraries/bsp/ft_sd/ft_sdctrl_hw.c

@@ -0,0 +1,41 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-03-31 14:59:20
+ * @LastEditTime: 2021-05-25 16:46:46
+ * @Description:  This files is for sd ctrl register-related implementations
+ *
+ * @Modify History: * * Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_sdctrl_hw.h"
+#include "ft_sdctrl.h"
+
+#include "ft_io.h"
+#include "ft_types.h"
+#include "ft_assert.h"
+#include "ft_generic_timer.h"
+
+void FSdCtrl_Reset(FT_INOUT FtsdCtrl_t *pFtsdCtrl, pFtsdCtrl_delayTimer_t fDelayTimer)
+{
+    FSdCtrl_Config_t *pConfig;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+
+    pConfig = &pFtsdCtrl->config;
+    /* trigger software reset for 1us */
+    Ft_setBit32(pConfig->baseAddress + SOFTWARE_RESET_REG_OFFSET, SOFTWARE_RESET_SRST);
+    /* Wait for reset is ok */
+    Ft_GenericTimer_UsDelay(1);
+    Ft_clearBit32(pConfig->baseAddress + SOFTWARE_RESET_REG_OFFSET, SOFTWARE_RESET_SRST);
+
+    /* wait dat[0] to be high-lev */
+    while ((!(Ft_in32(pConfig->baseAddress + STATUS_REG) & STATUS_REG_DLSL(1))))
+    {
+        fDelayTimer(1);
+    }
+
+    return;
+}

bsp/ft2004/libraries/bsp/ft_sd/ft_sdctrl_intr.c

@@ -0,0 +1,110 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-03-31 14:59:20
+ * @LastEditTime: 2021-05-25 16:46:54
+ * @Description:  This files is for sd ctrl irq handling
+ *
+ * @Modify History: * * Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_sdctrl.h"
+#include "ft_sdctrl_hw.h"
+#include "ft_assert.h"
+#include "ft_types.h"
+#include "ft_io.h"
+#include "ft_printf.h"
+#include "ft_debug.h"
+
+#ifndef LOG_LOCAL_LEVEL
+#define LOG_LOCAL_LEVEL FT_LOG_NONE
+#endif
+#define FT_SD_CTRL_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FT_SD_CTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FT_SD_CTRL_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FT_SD_CTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FT_SD_CTRL_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FT_SD_CTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+
+void FSdCtrl_NormalIrq(FT_INOUT FtsdCtrl_t *pFtsdCtrl)
+{
+    FSdCtrl_Config_t *pConfig;
+    FSdCtrl_IrqConfig_t *irqConfig;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+    pConfig = &pFtsdCtrl->config;
+    irqConfig = &pFtsdCtrl->irqConfig;
+
+    //FT_SD_CTRL_DEBUG_I("enter cmd irq procedure\r\n");
+    if (irqConfig->pCmdCallback)
+    {
+        irqConfig->pCmdCallback(irqConfig->pCmdArgs);
+    }
+
+    /* clear interrupts */
+    Ft_out32(pConfig->baseAddress + NORMAL_INT_STATUS_REG, NORMAL_INT_STATUS_ALL_MASK);
+    Ft_out32(pConfig->baseAddress + NORMAL_INT_STATUS_REG, 0);
+}
+
+void FSdCtrl_DmaIrq(FT_INOUT FtsdCtrl_t *pFtsdCtrl)
+{
+    FSdCtrl_Config_t *pConfig;
+    FSdCtrl_IrqConfig_t *irqConfig;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+    pConfig = &pFtsdCtrl->config;
+    irqConfig = &pFtsdCtrl->irqConfig;
+
+    if (irqConfig->pDmaDataCallback)
+    {
+        irqConfig->pDmaDataCallback(irqConfig->pDmaDataArgs);
+    }
+
+    /* clear interrupts */
+    Ft_out32(pConfig->baseAddress + BD_ISR_REG, BD_ISR_ALL_MASK);
+    Ft_out32(pConfig->baseAddress + BD_ISR_REG, 0);
+}
+
+void FSdCtrl_ErrIrq(FT_INOUT FtsdCtrl_t *pFtsdCtrl)
+{
+    FSdCtrl_Config_t *pConfig;
+    FSdCtrl_IrqConfig_t *irqConfig;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+    pConfig = &pFtsdCtrl->config;
+    irqConfig = &pFtsdCtrl->irqConfig;
+
+    if (irqConfig->pErrorCallback)
+    {
+        irqConfig->pErrorCallback(irqConfig->pErrorArgs);
+    }
+
+    /* clear interrupts */
+    Ft_out32(pConfig->baseAddress + ERROR_INT_STATUS_REG, ERROR_INT_STATUS_ALL_MASK);
+    Ft_out32(pConfig->baseAddress + ERROR_INT_STATUS_REG, 0);
+}
+
+ft_error_t FSdCtrl_SetHandler(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_IrqCallbackSelect_t selectIndex,
+                              void *FuncPtr, void *Args)
+{
+    Ft_assertNonvoid(pFtsdCtrl != NULL);
+    Ft_assertNonvoid(FuncPtr != NULL);
+    Ft_assertNonvoid(pFtsdCtrl->isReady == FT_COMPONENT_IS_READLY);
+
+    switch (selectIndex)
+    {
+    case FTSDCTRL_DMADATAIRQID:
+        pFtsdCtrl->irqConfig.pDmaDataCallback = FuncPtr;
+        pFtsdCtrl->irqConfig.pDmaDataArgs = Args;
+        break;
+    case FTSDCTRL_CMDIRQID:
+        pFtsdCtrl->irqConfig.pCmdCallback = FuncPtr;
+        pFtsdCtrl->irqConfig.pCmdArgs = Args;
+        break;
+    case FTSDCTRL_ERRORIRQID:
+        pFtsdCtrl->irqConfig.pErrorCallback = FuncPtr;
+        pFtsdCtrl->irqConfig.pErrorArgs = Args;
+        break;
+    default:
+        return FTSDC_FAILURE;
+    }
+
+    return FTSDC_SUCCESS;
+}

bsp/ft2004/libraries/bsp/ft_sd/ft_sdctrl_option.c

@@ -0,0 +1,61 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-03-31 14:59:20
+ * @LastEditTime: 2021-05-25 16:47:05
+ * @Description:  This files is for sd ctrl option setting
+ *
+ * @Modify History: * * Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_sdctrl.h"
+#include "ft_sdctrl_hw.h"
+#include "ft_types.h"
+#include "ft_io.h"
+#include "ft_printf.h"
+#include "ft_assert.h"
+
+void FSdCtrl_NormalIrqSet(FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_NormalIrqSelect_t flgs)
+{
+    FSdCtrl_Config_t *pConfig;
+    u32 regValue;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+    pConfig = &pFtsdCtrl->config;
+
+    /*  */
+    regValue = ((flgs & NORMAL_IRQ_CC) ? NORMAL_INT_EN_ECC : 0) | ((flgs & NORMAL_IRQ_CR) ? NORMAL_INT_EN_ECCRCE : 0) |
+               ((flgs & NORMAL_IRQ_EI) ? NORMAL_INT_EN_ECIE : 0);
+
+    Ft_out32(pConfig->baseAddress + NORMAL_INT_EN_REG_OFFSET, regValue);
+}
+
+void FsdCtrl_errorIrqSet(FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_ErrorIrqSelect_t flgs)
+{
+    FSdCtrl_Config_t *pConfig;
+    u32 regValue;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+    pConfig = &pFtsdCtrl->config;
+
+    regValue = ((flgs & ERROR_IRQ_CTE) ? ERROR_INT_EN_CTE : 0) | ((flgs & ERROR_IRQ_CCRCE) ? ERROR_INT_EN_CCRCE : 0) |
+               ((flgs & ERROR_IRQ_CIR) ? ERROR_INT_EN_CIR : 0) | ((flgs & ERROR_IRQ_CNR) ? ERROR_INT_EN_CNR : 0);
+
+    Ft_out32(pConfig->baseAddress + ERROR_INT_EN_REG_OFFSET, regValue);
+}
+
+void FSdCtrl_BdIrqSet(FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_BdIrqSelect flgs)
+{
+    FSdCtrl_Config_t *pConfig;
+    u32 regValue;
+    Ft_assertVoid(FT_NULL != pFtsdCtrl);
+    pConfig = &pFtsdCtrl->config;
+
+    regValue = ((flgs & BD_IRQ_TRS) ? BD_ISR_EN_ETRS : 0) | ((flgs & BD_IRQ_DTE) ? BD_ISR_EN_EDTE : 0) |
+               ((flgs & BD_IRQ_CMDE) ? BD_ISR_EN_ECMDE : 0) | ((flgs & BD_IRQ_TRE) ? BD_ISR_EN_ETRE : 0) |
+               ((flgs & BD_IRQ_NRCRC) ? BD_ISR_EN_ENRCRCE : 0) | ((flgs & BD_IRQ_DATFRAX) ? BD_ISR_EN_EDATFRAXE : 0) |
+               ((flgs & BD_IRQ_RESPE) ? BD_ISR_EN_RESPE : 0) | ((flgs & BD_IRQ_DAIS) ? BD_ISR_EN_EDAISE : 0);
+
+    Ft_out32(pConfig->baseAddress + BD_ISR_EN_REG_OFFSET, regValue);
+}

bsp/ft2004/libraries/bsp/ft_sd/ft_sdctrl_sinit.c

@@ -0,0 +1,33 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-03-31 14:59:20
+ * @LastEditTime: 2021-05-25 16:47:14
+ * @Description:  This files is for sd ctrl static initialization
+ *
+ * @Modify History: * * Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_sdctrl.h"
+#include "ft_parameters.h"
+
+extern FSdCtrl_Config_t FSdCtrl_Config[FT_SDC_NUM];
+
+FSdCtrl_Config_t *FSdCtrl_LookupConfig(u32 instanceId)
+{
+    FSdCtrl_Config_t *CfgPtr = NULL;
+    u32 Index;
+    for (Index = 0; Index < (u32)FT_GMAC_INSTANCES_NUM; Index++)
+    {
+        if (FSdCtrl_Config[Index].instanceId == instanceId)
+        {
+            CfgPtr = &FSdCtrl_Config[Index];
+            break;
+        }
+    }
+
+    return (FSdCtrl_Config_t *)CfgPtr;
+}

bsp/ft2004/libraries/bsp/ft_spi/ft_spi.c

@@ -0,0 +1,192 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-25 14:00:25
+ * @LastEditTime: 2021-05-24 14:34:28
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_assert.h"
+#include "ft_spi.h"
+#include "ft_spi_hw.h"
+#include "ft_generic_timer.h"
+#include "ft_gpio.h"
+
+void FSpi_DumpAllStatus(FT_IN FSpi_Ctrl_t *pCtrl, FT_IN char *tag)
+{
+    FT_SPI_DEBUG_I("***%s status******\r\n", tag);
+    FT_SPI_DEBUG_I("busy: %d", SPI_STATUS_REG(pCtrl)->val.Busy);
+    FT_SPI_DEBUG_I("tx fifo not empty: %d", SPI_STATUS_REG(pCtrl)->val.Tfnf);
+    FT_SPI_DEBUG_I("tx fifo empty: %d", SPI_STATUS_REG(pCtrl)->val.Tfe);
+    FT_SPI_DEBUG_I("rx fifo not empty: %d", SPI_STATUS_REG(pCtrl)->val.Rfne);
+    FT_SPI_DEBUG_I("rx fifo full: %d", SPI_STATUS_REG(pCtrl)->val.Rff);
+    FT_SPI_DEBUG_I("trans error: %d", SPI_STATUS_REG(pCtrl)->val.Txe);
+    FT_SPI_DEBUG_I("trans conflict error: %d", SPI_STATUS_REG(pCtrl)->val.Dcol);
+}
+
+u32 FSpi_ReadWriteByte(FT_INOUT FSpi_Ctrl_t *pCtrl, FT_IN u8 TxData,
+                       FT_OUT u8 *pRxData)
+{
+    u32 Retry = 0;
+    u32 Ret = ERR_SPI_OK;
+    u16 RxData;
+
+    if (!pCtrl->IsReady)
+    {
+        return ERR_SPI_NOT_READY;
+    }
+
+    while (FSPI_TX_FIFO_NOT_EMPTY(pCtrl))
+    {
+        //Ft_GenericTimer_UsDelay(2);
+        if ((Retry++) > SPI_TIMEOUT)
+        {
+            Ret = ERR_SPI_TX_TIMEOUT;
+            goto __EXIT;
+        }
+    }
+    FSPI_WRITE_DATA(pCtrl, (u16)TxData);
+
+    Retry = 0;
+
+    while (FSPI_RX_FIFO_EMPTY(pCtrl))
+    {
+        //Ft_GenericTimer_UsDelay(2);
+        if ((Retry++) > SPI_TIMEOUT)
+        {
+            Ret = ERR_SPI_RX_TIMEOUT;
+            goto __EXIT;
+        }
+    }
+    RxData = FSPI_READ_DATA(pCtrl);
+
+    if (pRxData)
+    {
+        *pRxData = (u8)RxData;
+    }
+
+__EXIT:
+    return Ret;
+}
+
+u32 FSpi_Init(FT_INOUT FSpi_Ctrl_t *pCtrl)
+{
+    u32 Ret = ERR_SPI_OK;
+
+    FSPI_DISABLE(pCtrl);
+
+    /* config spi ctrl register */
+    SPI_CTRL0_REG(pCtrl)->val.Dfs = SPI_DFS_DEFAULT;
+    SPI_CTRL0_REG(pCtrl)->val.Frf = SPI_FRF_DEFAULT;
+
+    if (SPI_CTRL_CPHA_1EDGE == pCtrl->Config.Cpha)
+    {
+        SPI_CTRL0_REG(pCtrl)->val.Scph = SPI_SCPH_SW_CLK_AT_DATA_BEG;
+    }
+    else if (SPI_CTRL_CPHA_2EDGE == pCtrl->Config.Cpha)
+    {
+        SPI_CTRL0_REG(pCtrl)->val.Scph = SPI_SCPH_SW_CLK_AT_DATA_MID;
+    }
+    else
+    {
+        Ft_assertNoneReturn(0);
+    }
+
+    if (SPI_CTRL_CPOL_LOW == pCtrl->Config.Cpol)
+    {
+        SPI_CTRL0_REG(pCtrl)->val.Scpol = SPI_SCPOL_NOT_ACT_LOW;
+    }
+    else if (SPI_CTRL_CPOL_HIGH == pCtrl->Config.Cpol)
+    {
+        SPI_CTRL0_REG(pCtrl)->val.Scpol = SPI_SCPOL_NOT_ACT_HIGH;
+    }
+    else
+    {
+        Ft_assertNoneReturn(0);
+    }
+
+    SPI_CTRL0_REG(pCtrl)->val.Tmod = SPI_TMOD_TX_RX_MODE;
+    SPI_CTRL0_REG(pCtrl)->val.SlvOE = SPI_SLV_OE_DISABLE;
+    SPI_CTRL0_REG(pCtrl)->val.Srl = SPI_SRL_NORMAL_MODE;
+    SPI_CTRL0_REG(pCtrl)->val.Cfs = SPI_CFS_DEFAULT;
+
+    /* config spi clock */
+    FSPI_SET_BAUDR(pCtrl, pCtrl->Config.BaudRDiv);
+
+    /* config rx and tx fifo, fifo depth to trigger intr */
+    SPI_TXFTL_REG(pCtrl)->val.Tft = 0;
+    SPI_RXFTL_REG(pCtrl)->val.Rft = 0;
+    SPI_TXFL_REG(pCtrl)->val.Txtfl = 0;
+    SPI_RXFL_REG(pCtrl)->val.Rxtfl = 0;
+
+    SPI_RXSAMPLE_DLY_REG(pCtrl)->val.Rsd = SPI_DEFAULT_RSD;
+
+    FSPI_ENABLE(pCtrl);
+
+    /* set spi ready flag */
+    if (ERR_SPI_OK == Ret)
+    {
+        pCtrl->IsReady = TRUE;
+    }
+
+    return Ret;
+}
+
+static void FSpi_ToggleCSPin(FT_INOUT FSpi_Ctrl_t *pCtrl, FT_IN FSpi_DevId_t DevId,
+                             FT_IN bool_t select)
+{
+    u32 setVal = ((TRUE == select) ? GPIO_OFF : GPIO_ON);
+
+    Ft_assertNoneReturn(NULL != pCtrl);
+
+    if (FGpio_ReadPinA(GPIO_CTRL_ID_1, pCtrl->CsPin) != setVal)
+    {
+        FGpio_WritePinA(GPIO_CTRL_ID_1, pCtrl->CsPin, setVal);
+    }
+
+    Ft_GenericTimer_UsDelay(10);
+    return;
+}
+
+void FSpi_SelectSlave(FT_INOUT FSpi_Ctrl_t *pCtrl, FT_IN FSpi_DevId_t DevId,
+                      FT_IN bool_t select)
+{
+    FSpi_SeReg_t *pSelReg;
+    u32 setVal = ((TRUE == select) ? SPI_SE_SELECTED : SPI_SE_UNSELECTED);
+
+    FSPI_DISABLE(pCtrl);
+    /* enable or disable specific spi slave device */
+    pSelReg = SPI_SE_REG(pCtrl);
+    switch (DevId)
+    {
+    case SPI_DEV_ID_0:
+        pSelReg->val.SelSlave_0 = setVal;
+        break;
+    case SPI_DEV_ID_1:
+        pSelReg->val.SelSlave_1 = setVal;
+        Ft_assertNoneReturn(0);
+        break;
+    case SPI_DEV_ID_2:
+        pSelReg->val.SelSlave_2 = setVal;
+        Ft_assertNoneReturn(0);
+        break;
+    case SPI_DEV_ID_3:
+        pSelReg->val.SelSlave_3 = setVal;
+        Ft_assertNoneReturn(0);
+        break;
+    default:
+        Ft_assertNoneReturn(0);
+        break;
+    }
+
+    FSpi_ToggleCSPin(pCtrl, DevId, select);
+    FSPI_ENABLE(pCtrl);
+
+    return;
+}

bsp/ft2004/libraries/bsp/ft_spi/ft_spi.h

@@ -0,0 +1,95 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-25 13:59:05
+ * @LastEditTime: 2021-04-30 16:11:46
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_BSP_SPI_H
+#define FT_BSP_SPI_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "ft_types.h"
+#include "ft_spi_hw.h"
+#include "ft_error_code.h"
+#include "ft_debug.h"
+
+        typedef struct
+        {
+                u8 WorkMode;
+#define SPI_CTRL_MASTER_MODE (u8)0x0
+#define SPI_CTRL_SLAVE_MODE (u8)0x1
+                u8 DevAddrLen;
+#define SPI_3_BYTE_ADDR (u8)0x3
+#define SPI_4_BYTE_ADDR (u8)0x4
+                u8 Cpol;
+#define SPI_CTRL_CPOL_LOW (u8)0x0
+#define SPI_CTRL_CPOL_HIGH (u8)0x1
+                u8 Cpha;
+#define SPI_CTRL_CPHA_1EDGE (u8)0x0
+#define SPI_CTRL_CPHA_2EDGE (u8)0x1
+                u8 DevAddr[4];
+                u32 BaudRDiv;
+        } FSpi_Conf_t;
+
+        typedef struct
+        {
+                FSpi_Conf_t Config;
+                FSpi_CtrlId_t CtrlId;
+                FSpi_DevId_t DevId; /* support only one slave at the moment */
+                bool_t IsReady;
+                u16 CsPin; /* cs pin in gpio group A */
+        } FSpi_Ctrl_t;
+
+/* misc marco */
+#define SPI_TIMEOUT 5000
+#define SPI_DUMMY_TX_DATA 0xFF
+
+/* ctrl member shortcut */
+#define FSPI_DEV_ADDR_LEN(pCtrl) (pCtrl->Config.DevAddrLen)
+#define FSPI_IS_3_BYTE_ADDR(pCtrl) (SPI_3_BYTE_ADDR == FSPI_DEV_ADDR_LEN(pCtrl))
+#define FSPI_DEV_ADDR(pCtrl) (pCtrl->Config.DevAddr)
+
+/* define error code */
+#define ERR_SPI_OK ERR_SUCCESS
+#define ERR_SPI_GENERAL FT_CODE_ERR(ERR_MODE_SPI, 0, 1)
+#define ERR_SPI_NOT_READY FT_CODE_ERR(ERR_MODE_SPI, 0, 2)
+#define ERR_SPI_TX_TIMEOUT FT_CODE_ERR(ERR_MODE_SPI, 0, 3)
+#define ERR_SPI_RX_TIMEOUT FT_CODE_ERR(ERR_MODE_SPI, 0, 4)
+
+/* spi flash error code */
+#define ERR_SPI_WAIT_TIMEOUT FT_CODE_ERR(ERR_MODE_SPI, 1, 1)
+
+/* define debug utilities */
+#define FT_SPI_DEBUG_TAG "FT_SPI"
+#define FT_SPI_ENABLE_DEBUG
+#define FT_SPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FT_SPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#ifdef FT_SPI_ENABLE_DEBUG
+#define FT_SPI_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FT_SPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FT_SPI_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FT_SPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#else
+#define FT_SPI_DEBUG_I(format, ...)
+#define FT_SPI_DEBUG_W(format, ...)
+#endif
+
+        u32 FSpi_Init(FT_INOUT FSpi_Ctrl_t *pCtrl);
+        u32 FSpi_ReadWriteByte(FT_INOUT FSpi_Ctrl_t *pCtrl, FT_IN u8 TxData,
+                               FT_OUT u8 *pRxData);
+        void FSpi_SelectSlave(FT_INOUT FSpi_Ctrl_t *pCtrl, FT_IN FSpi_DevId_t DevId,
+                              FT_IN bool_t select);
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ft2004/libraries/bsp/ft_spi/ft_spi_irq.c

@@ -0,0 +1,13 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-25 14:00:39
+ * @LastEditTime: 2021-04-25 14:00:39
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */

bsp/ft2004/libraries/bsp/ft_uart/ft_uart.h

@@ -0,0 +1,120 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-24 10:13:51
+ * @Description:  This files is for uart functions
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_UART_H
+#define FT_UART_H
+
+#include "ft_types.h"
+#include "ft_assert.h"
+#include "ft_status.h"
+#include "ft_uart_hw.h"
+
+#define FUART_BAUDRATE 115200U
+
+/* Config options */
+#define FUART_OPTION_UARTEN 0x1U
+#define FUART_OPTION_RXEN 0x2U
+#define FUART_OPTION_TXEN 0x4U
+#define FUART_OPTION_FIFOEN 0x8U
+
+/* Data format values  */
+#define FUART_FORMAT_WORDLENGTH_8BIT 0x3
+#define FUART_FORMAT_WORDLENGTH_7BIT 0x2
+#define FUART_FORMAT_WORDLENGTH_6BIT 0x1
+#define FUART_FORMAT_WORDLENGTH_5BIT 0x0
+
+#define FUART_FORMAT_NO_PARITY 0U
+#define FUART_FORMAT_MARK_PARITY 1U
+#define FUART_FORMAT_SPACE_PARITY 2U
+#define FUART_FORMAT_ODD_PARTY 3U
+#define FUART_FORMAT_EVEN_PARITY 4U
+
+#define FUART_FORMAT_2_STOP_BIT 0U
+#define FUART_FORMAT_1_STOP_BIT 1U
+
+/* Callback events  */
+
+#define FUART_EVENT_RECV_DATA 1U       /**< Data receiving done */
+#define FUART_EVENT_RECV_TOUT 2U       /**< A receive timeout occurred */
+#define FUART_EVENT_SENT_DATA 3U       /**< Data transmission done */
+#define FUART_EVENT_RECV_ERROR 4U      /**< A receive error detected */
+#define FUART_EVENT_MODEM 5U           /**< Modem status changed */
+#define FUART_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break \
+                                        *   error detected */
+#define FUART_EVENT_RECV_ORERR 7U      /**< A receive overrun error detected */
+
+/**************************** Type Definitions ******************************/
+typedef struct
+{
+    u32 InstanceId; /* Id of device*/
+    u32 BaseAddress;
+    u32 RefClockHz;
+    u32 IsrNum;
+} FUart_Config_t;
+
+typedef struct
+{
+    u8 *BytePtr;
+    u32 RequestedBytes;
+    u32 RemainingBytes;
+} FUart_Buffer_t;
+
+typedef struct
+{
+    u32 BaudRate; /**< In bps, ie 1200 */
+    u32 DataBits; /**< Number of data bits */
+    u32 Parity;   /**< Parity */
+    u8 StopBits;  /**< Number of stop bits */
+} FUart_Format_t;
+
+typedef void (*FUart_Handler_t)(void *Args, u32 Event, u32 EventData);
+
+typedef struct
+{
+    FUart_Config_t Config; /* Configuration data structure  */
+    u32 InputClockHz;
+    u32 IsReady; /* Device is ininitialized and ready*/
+    u32 BaudRate;
+
+    FUart_Buffer_t SendBuffer;
+    FUart_Buffer_t ReceiveBuffer;
+
+    FUart_Handler_t Handler;
+    void *Args;
+    uint8_t rxbs_error; /* 接收过程中出现错误 ，0 无错误，1 存在错误*/
+
+} Ft_Uart;
+
+/* define SD MMC error code */
+typedef enum
+{
+    ERR_SUB_MODE_UART_GENERAL = 0
+} FT_UART_ERR_SUB_MODE;
+
+#define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ERR_MODE_UART, ERR_SUB_MODE_UART_GENERAL, 0x1)
+
+void FUart_PutChar(Ft_Uart *UartPtr, s8 Data);
+u32 FUart_Send(Ft_Uart *UartPtr, u8 *Buffer, u32 Length);
+u32 FUart_Receive(Ft_Uart *UartPtr, u8 *BytePtr, u32 Length);
+s32 FUart_CfgInitialize(Ft_Uart *UartPtr, FUart_Config_t *Config);
+FUart_Config_t *FUart_LookupConfig(u32 InstanceId);
+void FUart_SetOptions(Ft_Uart *UartPtr, u32 Options);
+void FUart_SetSpecificOptions(Ft_Uart *UartPtr, u32 Options);
+void FUart_ClearSpecificOptions(Ft_Uart *UartPtr, u32 Options);
+void FUart_InterruptHandler(Ft_Uart *UartPtr);
+void FUart_SetHandler(Ft_Uart *UartPtr, FUart_Handler_t FuncPtr,
+                      void *Args);
+void FUart_SetInterruptMask(Ft_Uart *UartPtr, u32 Mask);
+u32 FUart_SetBaudRate(Ft_Uart *UartPtr, u32 BaudRate);
+#endif // !

bsp/ft2004/libraries/bsp/ft_uart/ft_uart_g.c

@@ -0,0 +1,34 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:42:30
+ * @Description:  This files is for uart config
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_uart.h"
+#include "ft_parameters.h"
+
+FUart_Config_t FUart_Config_tTable[FT_UART_NUM] = {
+    {FT_UART0_ID,
+     FT_UART0_BASE_ADDR,
+     FT_UART0_CLK_FREQ_HZ,
+     38},
+    {FT_UART1_ID,
+     FT_UART1_BASE_ADDR,
+     FT_UART1_CLK_FREQ_HZ,
+     39},
+    {FT_UART2_ID,
+     FT_UART2_BASE_ADDR,
+     FT_UART2_CLK_FREQ_HZ,
+     40},
+    {FT_UART3_ID,
+     FT_UART3_BASE_ADDR,
+     FT_UART3_CLK_FREQ_HZ,
+     41}};

bsp/ft2004/libraries/bsp/ft_uart/ft_uart_hw.c

@@ -0,0 +1,46 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-25 16:49:30
+ * @Description:  This files is for uart register function
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_uart_hw.h"
+
+void FUart_SendByte(u32 BaseAddress, u8 Byte)
+{
+    while (FT_UART_IsTransmitFull(BaseAddress))
+    {
+        ;
+    }
+    FT_UART_WriteReg(BaseAddress, UARTDR_OFFSET, (u32)Byte);
+}
+
+u8 FUart_RecvByte(u32 BaseAddress)
+{
+    u32 RecievedByte;
+    while (FT_UART_IsReceiveData(BaseAddress))
+    {
+        ;
+    }
+    RecievedByte = FT_UART_ReadReg(BaseAddress, UARTDR_OFFSET);
+    return RecievedByte;
+}
+
+u8 FUart_GetChar(u32 BaseAddress)
+{
+    u32 RecievedByte;
+    if (FT_UART_IsReceiveData(BaseAddress))
+    {
+        return 0xff;
+    }
+    RecievedByte = FT_UART_ReadReg(BaseAddress, UARTDR_OFFSET);
+    return RecievedByte;
+}

bsp/ft2004/libraries/bsp/ft_uart/ft_uart_intr.c

@@ -0,0 +1,196 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-25 16:49:42
+ * @Description:  This files is for uart irq functions
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_uart.h"
+
+extern u32 FUart_SendBuffer(Ft_Uart *UartPtr);
+extern u32 FUart_ReceiveBuffer(Ft_Uart *UartPtr);
+
+static void FUart_receiveErrorHandler(Ft_Uart *UartPtr, u32 InterruptStatus);
+static void FUart_receiveDataHandler(Ft_Uart *UartPtr);
+static void FUart_receiveTimeoutHandler(Ft_Uart *UartPtr);
+static void FUart_sendDataHandler(Ft_Uart *UartPtr, u32 InterruptStatus);
+
+/**
+ * @name: FUart_GetInterruptMask
+ * @msg:  此函数获取所有串口中断的mask。
+ * @param {Ft_Uart} *UartPtr
+ * @return {u32} mask
+ */
+u32 FUart_GetInterruptMask(Ft_Uart *UartPtr)
+{
+    Ft_assertNonvoid(UartPtr != NULL);
+
+    return FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET);
+}
+
+void FUart_SetInterruptMask(Ft_Uart *UartPtr, u32 Mask)
+{
+    u32 TempMask = Mask;
+    Ft_assertVoid(UartPtr != NULL);
+
+    TempMask &= UARTIMSC_ALLM;
+
+    FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, TempMask);
+}
+
+/**
+ * @name: FUart_SetHandler
+ * @msg:  设置中断回调函数
+ * @param {*}
+ * @return {*}
+ */
+void FUart_SetHandler(Ft_Uart *UartPtr, FUart_Handler_t FuncPtr,
+                      void *Args)
+{
+    Ft_assertVoid(UartPtr != NULL);
+    Ft_assertVoid(FuncPtr != NULL);
+    Ft_assertVoid(UartPtr->IsReady == FT_COMPONENT_IS_READLY);
+
+    UartPtr->Handler = FuncPtr;
+    UartPtr->Args = Args;
+}
+
+/**
+ * @name: FUart_InterruptHandler
+ * @msg:  串口中断函数入口
+ * @param {Ft_Uart} *UartPtr
+ * @return {*}
+ */
+void FUart_InterruptHandler(Ft_Uart *UartPtr)
+{
+    u32 RegValue = 0;
+    Ft_assertVoid(UartPtr != NULL);
+    Ft_assertVoid(UartPtr->IsReady == FT_COMPONENT_IS_READLY);
+    //Ft_printf("FUart_InterruptHandler %x\r\n", UartPtr);
+    RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET);
+
+    RegValue &= FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTMIS_OFFSET);
+
+    if ((RegValue & ((u32)UARTMIS_RXMIS)) != (u32)0)
+    {
+        /* Received data interrupt */
+        FUart_receiveDataHandler(UartPtr);
+    }
+
+    if ((RegValue & ((u32)UARTMIS_TXMIS)) != (u32)0)
+    {
+        /* Transmit data interrupt */
+        FUart_sendDataHandler(UartPtr, RegValue);
+    }
+
+    if (((RegValue) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != (u32)0)
+    {
+        /* Received Error Status interrupt */
+        FUart_receiveErrorHandler(UartPtr, RegValue);
+    }
+
+    if ((RegValue & ((u32)UARTMIS_RTMIS)) != (u32)0)
+    {
+        /* Received Timeout interrupt */
+        FUart_receiveTimeoutHandler(UartPtr);
+    }
+
+    if (((RegValue) & ((u32)UARTMIS_DSRMMIS | (u32)UARTMIS_DCDMMIS | (u32)UARTMIS_CTSMMIS | (u32)UARTMIS_RIMMIS)) != (u32)0)
+    {
+        /* Modem status interrupt */
+    }
+
+    /* Clear the interrupt status. */
+    FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTICR_OFFSET,
+                     RegValue);
+}
+
+static void FUart_receiveErrorHandler(Ft_Uart *UartPtr, u32 InterruptStatus)
+{
+    UartPtr->rxbs_error = 0;
+
+    if (((InterruptStatus) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != 0)
+    {
+        UartPtr->rxbs_error = 1;
+    }
+
+    (void)FUart_ReceiveBuffer(UartPtr);
+
+    if (0 == UartPtr->rxbs_error)
+    {
+        if (UartPtr->Handler)
+        {
+            UartPtr->Handler(UartPtr->Args, FUART_EVENT_RECV_ERROR, UartPtr->ReceiveBuffer.RequestedBytes - UartPtr->ReceiveBuffer.RemainingBytes);
+        }
+    }
+}
+
+static void FUart_receiveDataHandler(Ft_Uart *UartPtr)
+{
+    if ((u32)0 != UartPtr->ReceiveBuffer.RemainingBytes)
+    {
+        (void)FUart_ReceiveBuffer(UartPtr);
+    }
+
+    if ((u32)0 == UartPtr->ReceiveBuffer.RemainingBytes)
+    {
+        if (UartPtr->Handler)
+        {
+            UartPtr->Handler(UartPtr->Args, FUART_EVENT_RECV_DATA, UartPtr->ReceiveBuffer.RequestedBytes - UartPtr->ReceiveBuffer.RemainingBytes);
+        }
+    }
+}
+
+static void FUart_receiveTimeoutHandler(Ft_Uart *UartPtr)
+{
+    u32 Event;
+
+    if ((u32)0 != UartPtr->ReceiveBuffer.RemainingBytes)
+    {
+        (void)FUart_ReceiveBuffer(UartPtr);
+    }
+
+    if ((u32)0 == UartPtr->ReceiveBuffer.RemainingBytes)
+    {
+        Event = FUART_EVENT_RECV_TOUT;
+    }
+    else
+    {
+        Event = FUART_EVENT_RECV_DATA;
+    }
+
+    if (UartPtr->Handler)
+    {
+        UartPtr->Handler(UartPtr->Args, Event, UartPtr->ReceiveBuffer.RequestedBytes - UartPtr->ReceiveBuffer.RemainingBytes);
+    }
+}
+
+static void FUart_sendDataHandler(Ft_Uart *UartPtr, u32 InterruptStatus)
+{
+    u32 RegValue;
+    if (UartPtr->SendBuffer.RemainingBytes == (u32)0)
+    {
+        //<! close send isr
+        RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET);
+        RegValue &= ~UARTIMSC_TXIM;
+        FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, RegValue);
+        if (UartPtr->Handler)
+        {
+            UartPtr->Handler(UartPtr->Args, FUART_EVENT_RECV_DATA, UartPtr->ReceiveBuffer.RequestedBytes - UartPtr->ReceiveBuffer.RemainingBytes);
+        }
+    }
+    else if (InterruptStatus & UARTMIS_TXMIS)
+    {
+        FUart_SendBuffer(UartPtr);
+    }
+    else
+    {
+    }
+}

bsp/ft2004/libraries/bsp/ft_uart/ft_uart_options.c

@@ -0,0 +1,102 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-24 10:47:33
+ * @Description:  This files is for uart option setting
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_uart.h"
+#include "ft_uart_hw.h"
+#include "ft_types.h"
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct
+{
+    u32 Option;
+    u32 RegisterOffset;
+    u32 Mask;
+} Mapping;
+
+static Mapping OptionTable[] = {
+    {FUART_OPTION_UARTEN, UARTCR_OFFSET, UARTCR_UARTEN},
+    {FUART_OPTION_RXEN, UARTCR_OFFSET, UARTCR_RXE},
+    {FUART_OPTION_TXEN, UARTCR_OFFSET, UARTCR_TXE},
+    {FUART_OPTION_FIFOEN, UARTLCR_H_OFFSET, UARTLCR_H_FEN}};
+
+#define FT_UART_NUM_OPITIONS (sizeof(OptionTable) / sizeof(Mapping))
+
+void FUart_SetOptions(Ft_Uart *UartPtr, u32 Options)
+{
+    u32 Index;
+    u32 RegValue;
+    Ft_assertVoid(UartPtr != NULL);
+    Ft_assertVoid(UartPtr->IsReady == FT_COMPONENT_IS_READLY);
+
+    for (Index = 0; Index < FT_UART_NUM_OPITIONS; Index++)
+    {
+        RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset);
+
+        if ((Options & OptionTable[Index].Option) != (u32)(0))
+        {
+            RegValue |= OptionTable[Index].Mask;
+        }
+        else
+        {
+            RegValue &= ~OptionTable[Index].Mask;
+        }
+
+        FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue);
+    }
+}
+
+void FUart_SetSpecificOptions(Ft_Uart *UartPtr, u32 Options)
+{
+    u32 Index;
+    u32 RegValue;
+    Ft_assertVoid(UartPtr != NULL);
+
+    for (Index = 0; Index < FT_UART_NUM_OPITIONS; Index++)
+    {
+        if ((Options & OptionTable[Index].Option) == (u32)(0))
+        {
+            continue;
+        }
+
+        RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset);
+
+        /* set specific options */
+        RegValue |= OptionTable[Index].Mask;
+        FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue);
+    }
+}
+
+void FUart_ClearSpecificOptions(FT_IN Ft_Uart *UartPtr, FT_IN u32 Options)
+{
+    u32 Index;
+    u32 RegValue;
+    Ft_assertVoid(UartPtr != NULL);
+
+    for (Index = 0; Index < FT_UART_NUM_OPITIONS; Index++)
+    {
+        if ((Options & OptionTable[Index].Option) == (u32)(0))
+        {
+            continue;
+        }
+
+        RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset);
+
+        /* remove specific options */
+        RegValue &= ~OptionTable[Index].Mask;
+        FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue);
+    }
+}

bsp/ft2004/libraries/bsp/ft_uart/ft_uart_selftest.c

@@ -0,0 +1,13 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:44:41
+ * @Description:  This files is for uart test cases
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */

bsp/ft2004/libraries/bsp/ft_uart/ft_uart_sinit.c

@@ -0,0 +1,41 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-04-07 13:44:56
+ * @Description:  This files is for uart static init
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_uart.h"
+#include "ft_parameters.h"
+
+extern FUart_Config_t FUart_Config_tTable[FT_UART_NUM];
+
+/**
+ * @name: Ft_Uart_LookupConfig
+ * @msg:  获取串口的基本配置
+ * @param {u16} InstanceId FT_UARTX_ID
+ * @return {*}
+ */
+FUart_Config_t *FUart_LookupConfig(u32 InstanceId)
+{
+    FUart_Config_t *CfgPtr = NULL;
+    u32 Index;
+
+    for (Index = 0; Index < (u32)FT_UART_NUM; Index++)
+    {
+        if (FUart_Config_tTable[Index].InstanceId == InstanceId)
+        {
+            CfgPtr = &FUart_Config_tTable[Index];
+            break;
+        }
+    }
+
+    return (FUart_Config_t *)CfgPtr;
+}

bsp/ft2004/libraries/bsp/include/ft_parameters.h

@@ -0,0 +1,180 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ *  Date: 2021-03-30 14:57:03
+ * @LastEditTime: 2021-05-24 14:35:00
+ *  Description:  definitions of BSP parameters
+ *  Modify History:
+ * * * Ver   Who        Date            Changes
+ * * ----- ------     --------    ----------------------------------------------
+ *   1.00   Huanghe   2021/3/1     init
+ */
+
+#ifndef FT_PARAMETERS_H
+#define FT_PARAMETERS_H
+
+/*  Device register address */
+#define FT_DEV_BASE_ADDR 0x28000000
+#define FT_DEV_END_ADDR 0x2FFFFFFF
+
+/******** UART  ************/
+
+#define FT_UART_NUM 4
+#define FT_UART_REG_LENGTH 0x18000
+
+#define FT_UART0_ID 0
+#define FT_UART0_BASE_ADDR 0x28000000
+#define FT_UART0_CLK_FREQ_HZ 48000000
+
+#define FT_UART1_ID 1
+#define FT_UART1_BASE_ADDR 0x28001000
+#define FT_UART1_CLK_FREQ_HZ 48000000
+
+#define FT_UART2_ID 2
+#define FT_UART2_BASE_ADDR 0x28002000
+#define FT_UART2_CLK_FREQ_HZ 48000000
+
+#define FT_UART3_BASE_ADDR 0x28003000
+#define FT_UART3_ID 3
+#define FT_UART3_CLK_FREQ_HZ 48000000
+
+#define FT_STDOUT_BASEADDRESS FT_UART1_BASE_ADDR
+#define FT_STDIN_BASEADDRESS FT_UART1_BASE_ADDR
+
+/****** GIC v3  *****/
+#define FT_GICV3_INSTANCES_NUM 1U
+#define GICV3_REG_LENGTH 0x00009000
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define GICV3_MAX_INTR_PRIO_VAL 240U
+#define GICV3_INTR_PRIO_MASK 0x000000f0U
+
+#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count         */
+#define SGI_INT_MAX 16
+#define SPI_START_INT_NUM 32 /* SPI start at ID32        */
+#define PPI_START_INT_NUM 16 /* PPI start at ID16        */
+#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
+
+#define FT_GICV3_BASEADDRESS 0x29900000U
+#define FT_GICV3_DISTRIBUTOR_BASEADDRESS (FT_GICV3_BASEADDRESS + 0)
+#define FT_GICV3_RD_BASEADDRESS (FT_GICV3_BASEADDRESS + 0x80000U)
+#define FT_GICV3_SGI_BASEADDRESS (FT_GICV3_RD_BASEADDRESS + (1U << 16))
+
+#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
+
+/** Gmac **/
+#define FT_GMAC_INSTANCES_NUM 2U
+#define FT_GMAC_REG_LENGTH 0x00009000
+
+#define FT_GMAC_COMMON_ADDR 0x2820B000U
+
+#define FT_GMAC0_ID 0
+#define FT_GMAC0_BASEADDR 0x2820C000U
+#define FT_GMAC0_DEFAULT_ADDR          \
+  {                                    \
+    0x11, 0x1c, 0x2c, 0x5c, 0x66, 0x88 \
+  }
+
+#define FT_GMAC1_ID 1
+#define FT_GMAC1_BASEADDR 0x28210000U
+
+/** @defgroup ENET_Buffers_setting
+  * @{
+  */
+#define GMAC_MAX_PACKET_SIZE 1600 /* GMAC_HEADER + GMAC_EXTRA + VLAN_TAG + MAX_GMAC_PAYLOAD + GMAC_CRC */
+#define GMAC_HEADER 14            /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define GMAC_CRC 4                /* Gmac CRC */
+#define GMAC_EXTRA 2              /* Extra bytes in some cases */
+#define VLAN_TAG 4                /* optional 802.1q VLAN Tag */
+#define MIN_GMAC_PAYLOAD 46       /* Minimum Gmac payload size */
+#define MAX_GMAC_PAYLOAD 1500     /* Maximum Gmac payload size */
+#define JUMBO_FRAME_PAYLOAD 9000  /* Jumbo frame payload size */
+#define RX_DESCNUM 1024U          /* Rx buffers of size GMAC_MAX_PACKET_SIZE  */
+#define TX_DESCNUM 1024U          /* Tx buffers of size GMAC_MAX_PACKET_SIZE  */
+
+#define PHY_USING_AR8035
+
+#define GMAC0_ISRNUM 81
+#define GMAC0_ISRPRIORITY 0
+
+#define GMAC1_ISRNUM 82
+#define GMAC1_ISRPRIORITY 0
+
+/* SDC */
+#define FT_SDC_NUM 1
+#define FT_SDC_INSTANCE 0
+#define FT_SDC_BASEADDR 0x28207C00U
+#define FT_SDC_REG_LENGTH 0x4000
+#define FT_SDC_FREQ 600000000
+
+/* pin MUX/DEMUX */
+
+#define FT_PIN_MUX_BASEADDR 0x28180000
+#define FT_PIN_MUX_REG_LENGTH 0x10000
+
+/* CAN */
+
+#define FT_CAN_NUM 3
+#define FT_CAN_REG_LENGTH 0x1000
+#define FT_CAN0_BASEADDR 0x28207000
+#define FT_CAN1_BASEADDR 0x28207400
+#define FT_CAN2_BASEADDR 0x28207800
+#define FT_CAN0_IRQNUM 119
+#define FT_CAN1_IRQNUM 123
+#define FT_CAN2_IRQNUM 124
+#define FT_CAN_BAUDRATE 1000000 /* 1M */
+#define FT_CAN_CLK 600000000
+
+/* pci  */
+
+#define FT_PCI_CONFIG_BASEADDR 0x40000000
+#define FT_PCI_CONFIG_REG_LENGTH 0x10000000
+
+#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000
+#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000
+
+#define FT_PCI_MEM32_BASEADDR 0x58000000
+#define FT_PCI_MEM32_REG_LENGTH 0x27000000
+
+/*  qspi  */
+#define FT_QSPI_NUM 1U
+#define FT_QSPI_INSTANCE 0
+#define FT_QSPI_MAX_CS_NUM 4
+#define FT_QSPI_BASEADDR 0x28014000
+
+#define FT_QSPI_FLASH_CAP_4MB 0
+#define FT_QSPI_FLASH_CAP_8MB 1
+#define FT_QSPI_FLASH_CAP_16MB 2
+#define FT_QSPI_FLASH_CAP_32MB 3
+#define FT_QSPI_FLASH_CAP_64MB 4
+#define FT_QSPI_FLASH_CAP_128MB 5
+#define FT_QSPI_FLASH_CAP_256MB 6
+
+#define FT_QSPI_ADDR_SEL_3 0
+#define FT_QSPI_ADDR_SEL_4 1
+
+#define FT_QSPI_SCK_DIV_128 0
+#define FT_QSPI_SCK_DIV_2 1
+#define FT_QSPI_SCK_DIV_4 2
+#define FT_QSPI_SCK_DIV_8 3
+#define FT_QSPI_SCK_DIV_16 4
+#define FT_QSPI_SCK_DIV_32 5
+#define FT_QSPI_SCK_DIV_64 6
+
+#define FT_QSPI_TRANSFER_1_1_1 0
+#define FT_QSPI_TRANSFER_1_1_2 1
+#define FT_QSPI_TRANSFER_1_1_4 2
+#define FT_QSPI_TRANSFER_1_2_2 3
+#define FT_QSPI_TRANSFER_1_4_4 4
+#define FT_QSPI_TRANSFER_2_2_2 5
+#define FT_QSPI_TRANSFER_4_4_4 6
+
+/* smp */
+
+#define FT_SMP_EN
+
+#endif // !

bsp/ft2004/libraries/bsp/standlone/ft_assert.c

@@ -0,0 +1,43 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-18 13:43:09
+ * @Description:  This files is for type definition
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_types.h"
+#include "ft_assert.h"
+
+/************* 全局变量 用于判断驱动是否出现断言 *****************/
+u32 Ft_assertStatus;
+
+/************** 断言是否需要无限等待，1 等待，0不等待  ******************/
+s32 Ft_assertWait = 1;
+
+/* 当断言发生时，将会调用此函数 */
+static Ft_assertCallback Ft_assertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+void Ft_assert(FT_IN char *File, s32 Line)
+{
+    if (Ft_assertCallbackRoutine != NULL)
+    {
+        Ft_assertCallbackRoutine(File, Line);
+    }
+
+    while (Ft_assertWait != 0)
+    {
+    }
+}
+
+void Ft_assertSetCallBack(Ft_assertCallback Routine)
+{
+    Ft_assertCallbackRoutine = Routine;
+}

bsp/ft2004/libraries/bsp/standlone/ft_assert.h

@@ -0,0 +1,154 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-07 09:53:07
+ * @LastEditTime: 2021-05-18 13:43:19
+ * @Description:  This files is for assert function
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef Ft_assert_H
+#define Ft_assert_H
+
+#include "ft_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define Fassert_NONE 0U
+#define Fassert_OCCURRED 1U
+
+    extern u32 Ft_assertStatus;
+    extern s32 Ft_assertWait;
+    extern void Ft_assert(FT_IN char *File, s32 Line);
+
+    typedef void (*Ft_assertCallback)(FT_IN char *File, s32 Line);
+
+/**
+ * @name: Ft_assertVoid
+ * @msg:  断言函数不带返回值
+ * @param {*}
+ * @return {*}
+ */
+#define Ft_assertVoid(Expression)               \
+    {                                           \
+        if (Expression)                         \
+        {                                       \
+            Ft_assertStatus = Fassert_NONE;     \
+        }                                       \
+        else                                    \
+        {                                       \
+            Ft_assert(__FILE__, __LINE__);      \
+            Ft_assertStatus = Fassert_OCCURRED; \
+            return;                             \
+        }                                       \
+    }
+
+/**
+ * @name:
+ * @msg:
+ * @in param:
+ * @inout param:
+ * @out param:
+ * @return {*}
+ */
+#define Ft_assertBool(Expression)               \
+    {                                           \
+        if (Expression)                         \
+        {                                       \
+            Ft_assertStatus = Fassert_NONE;     \
+        }                                       \
+        else                                    \
+        {                                       \
+            Ft_assert(__FILE__, __LINE__);      \
+            Ft_assertStatus = Fassert_OCCURRED; \
+            return FALSE;                       \
+        }                                       \
+    }
+
+/**
+ * @name: Ft_assertZeroNum
+ * @msg:  断言函数带返回值0
+ * @param {*}
+ * @return {*}
+ */
+#define Ft_assertZeroNum(Expression)            \
+    {                                           \
+        if (Expression)                         \
+        {                                       \
+            Ft_assertStatus = Fassert_NONE;     \
+        }                                       \
+        else                                    \
+        {                                       \
+            Ft_assert(__FILE__, __LINE__);      \
+            Ft_assertStatus = Fassert_OCCURRED; \
+            return FST_ASSERT_RETURN;           \
+        }                                       \
+    }
+
+/**
+ * @name: Ft_assertNonvoid
+ * @msg:  断言函数带返回值FST_ASSERT_RETURN
+ * @param {*}
+ * @return {*}
+ */
+#define Ft_assertNonvoid(Expression)            \
+    {                                           \
+        if (Expression)                         \
+        {                                       \
+            Ft_assertStatus = Fassert_NONE;     \
+        }                                       \
+        else                                    \
+        {                                       \
+            Ft_assert(__FILE__, __LINE__);      \
+            Ft_assertStatus = Fassert_OCCURRED; \
+            return FST_ASSERT_RETURN;           \
+        }                                       \
+    }
+
+/**
+ * @name: Ft_assertNoneReturn
+ * @msg:  断言函数不返回
+ * @param {*}
+ * @return {*}
+ */
+#define Ft_assertNoneReturn(Expression)         \
+    {                                           \
+        if (Expression)                         \
+        {                                       \
+            Ft_assertStatus = Fassert_NONE;     \
+        }                                       \
+        else                                    \
+        {                                       \
+            Ft_assert(__FILE__, __LINE__);      \
+            Ft_assertStatus = Fassert_OCCURRED; \
+        }                                       \
+    }
+
+#define Ft_assertVoidAlways()               \
+    {                                       \
+        Ft_assert(__FILE__, __LINE__);      \
+        Ft_assertStatus = Fassert_OCCURRED; \
+        return;                             \
+    }
+
+#define Ft_assertNonvoidAlways()            \
+    {                                       \
+        Ft_assert(__FILE__, __LINE__);      \
+        Ft_assertStatus = Fassert_OCCURRED; \
+        return FST_ASSERT_RETURN;           \
+    }
+
+    void Ft_assertSetCallBack(Ft_assertCallback routine);
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !

bsp/ft2004/libraries/bsp/standlone/ft_cache.c

@@ -0,0 +1,86 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-16 14:00:59
+ * @LastEditTime: 2021-04-16 16:07:27
+ * @Description:  This files is for
+ *
+ * @Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_cache.h"
+
+__STATIC_INLINE u32 FCache_cacheLineSize(void)
+{
+    u32 ctr;
+    asm volatile("mrc p15, 0, %0, c0, c0, 1"
+                 : "=r"(ctr));
+    return 4 << ((ctr >> 16) & 0xF);
+}
+
+void FCache_cpuDcacheInvalidate(void *addr, ft_base_t size)
+{
+    u32 lineSize = FCache_cacheLineSize();
+    u32 startAddr = (u32)addr;
+    u32 endAddr = (u32)addr + size + lineSize - 1;
+
+    asm volatile("dmb" ::
+                     : "memory");
+
+    startAddr &= ~(lineSize - 1);
+    endAddr &= ~(lineSize - 1);
+
+    while (startAddr < endAddr)
+    {
+        asm volatile("mcr p15, 0, %0, c7, c6, 1" ::"r"(startAddr)); /* dcimvac */
+        startAddr += lineSize;
+    }
+
+    asm volatile("dsb" ::
+                     : "memory");
+}
+
+void FCache_cpuDcacheClean(void *addr, ft_base_t size)
+{
+    u32 lineSize = FCache_cacheLineSize();
+    u32 startAddr = (u32)addr;
+    u32 endAddr = (u32)addr + size + lineSize - 1;
+
+    asm volatile("dmb" ::
+                     : "memory");
+
+    startAddr &= ~(lineSize - 1);
+    endAddr &= ~(lineSize - 1);
+
+    while (startAddr < endAddr)
+    {
+        asm volatile("mcr p15, 0, %0, c7, c10, 1" ::"r"(startAddr)); /* dccmvac */
+        startAddr += lineSize;
+    }
+
+    asm volatile("dsb" ::
+                     : "memory");
+}
+
+void FCache_cpuIcacheInvalidate(void *addr, ft_base_t size)
+{
+    u32 lineSize = FCache_cacheLineSize();
+    u32 startAddr = (u32)addr;
+    u32 endAddr = (u32)addr + size + lineSize - 1;
+
+    asm volatile("dmb" ::
+                     : "memory");
+    startAddr &= ~(lineSize - 1);
+    endAddr &= ~(lineSize - 1);
+    while (startAddr < endAddr)
+    {
+        asm volatile("mcr p15, 0, %0, c7, c5, 1" ::"r"(startAddr)); /* icimvau */
+        startAddr += lineSize;
+    }
+    asm volatile("dsb\n\tisb" ::
+                     : "memory");
+}

bsp/ft2004/libraries/bsp/standlone/ft_cache.h

@@ -0,0 +1,32 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-13 21:52:20
+ * @LastEditTime: 2021-04-13 21:52:20
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_CACHE_H
+#define FT_CACHE_H
+
+#include "ft_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+    void FCache_cpuDcacheInvalidate(void *addr, ft_base_t size);
+    void FCache_cpuDcacheClean(void *addr, ft_base_t size);
+    void FCache_cpuIcacheInvalidate(void *addr, ft_base_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !FT_CACHE_H

bsp/ft2004/libraries/bsp/standlone/ft_cpu.c

@@ -0,0 +1,145 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-20 11:32:32
+ * @LastEditTime: 2021-05-25 10:51:19
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#include "ft_parameters.h"
+#include "ft_cpu.h"
+#include "ft_assert.h"
+#include "ft_printf.h"
+
+#ifdef FT_SMP_EN
+
+typedef union
+{
+    u32 Slock;
+    struct ArchTicket
+    {
+        u16 owner;
+        u16 next;
+    } Tickets;
+} FCpu_Lock_t;
+
+struct FCpu
+{
+    u32 IsReady;
+    FCpu_Lock_t Clock;
+};
+
+struct FCpu FCpu_Lock = {0};
+
+const u32 SoftAffiTable[4] = {0, 1, 0x100, 0x101};
+
+/**
+ * @name: FCpu_IdGet
+ * @msg: In a multiprocessor system, provides an additional PE identification mechanism for scheduling
+            purposes.
+ * @return {Aff0} Affinity level 0. The most significant affinity level field, for this PE in the system.
+ */
+s32 FCpu_IdGet(void)
+{
+    s32 cpu_id;
+    __asm__ volatile(
+        "mrc p15, 0, %0, c0, c0, 5"
+        : "=r"(cpu_id));
+    // Ft_printf("error cpu_id %x \r\n", cpu_id);
+    // cpu_id &= 0xf;
+
+    switch ((cpu_id & 0xfff))
+    {
+    case 1:
+        return 1;
+    case 0x100:
+        return 2;
+    case 0x101:
+        return 3;
+    default:
+        return (cpu_id & 0xf);
+    }
+}
+
+s32 FCpu_AffinityGet(void)
+{
+    s32 AffinityId;
+    __asm__ volatile(
+        "mrc p15, 0, %0, c0, c0, 5"
+        : "=r"(AffinityId));
+
+    return AffinityId & 0xfff;
+}
+
+void FCpu_SpinLockInit(void)
+{
+    FCpu_Lock.Clock.Slock = 0;
+    FCpu_Lock.IsReady = FT_COMPONENT_IS_READLY;
+}
+
+void FCpu_SpinLock(void)
+{
+    u32 Tmp;
+    u32 Newval;
+    FCpu_Lock_t LockVal;
+    Ft_assertVoid(FCpu_Lock.IsReady == FT_COMPONENT_IS_READLY);
+
+    __asm__ __volatile__(
+        "pld [%0]" ::"r"(&FCpu_Lock.Clock.Slock));
+
+    __asm__ __volatile__(
+        "1: ldrex   %0, [%3]\n"
+        "   add %1, %0, %4\n"
+        "   strex   %2, %1, [%3]\n"
+        "   teq %2, #0\n"
+        "   bne 1b"
+        : "=&r"(LockVal), "=&r"(Newval), "=&r"(Tmp)
+        : "r"(&FCpu_Lock.Clock.Slock), "I"(1 << 16)
+        : "cc");
+
+    while (LockVal.Tickets.next != LockVal.Tickets.owner)
+    {
+        __asm__ __volatile__("wfe" ::
+                                 : "memory");
+        LockVal.Tickets.owner = *(volatile unsigned short *)(&FCpu_Lock.Clock.Tickets.owner);
+    }
+
+    __asm__ volatile("dmb" ::
+                         : "memory");
+}
+
+void FCpu_SpinUnlock(void)
+{
+    Ft_assertVoid(FCpu_Lock.IsReady == FT_COMPONENT_IS_READLY);
+    __asm__ volatile("dmb" ::
+                         : "memory");
+    FCpu_Lock.Clock.Tickets.owner++;
+    __asm__ volatile("dsb ishst\nsev" ::
+                         : "memory");
+}
+
+#else /*RT_USING_SMP*/
+
+s32 FCpu_IdGet(void)
+{
+    return 0;
+}
+void FCpu_SpinLockInit(void)
+{
+    return;
+}
+void FCpu_SpinLock(void)
+{
+    return;
+}
+void FCpu_SpinUnlock(void)
+{
+    return;
+}
+
+#endif

bsp/ft2004/libraries/bsp/standlone/ft_cpu.h

@@ -0,0 +1,26 @@
+/*
+ * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0.
+ *
+ * @Date: 2021-04-20 11:33:54
+ * @LastEditTime: 2021-04-20 11:33:55
+ * @Description:  Description of file
+ * @Modify History:
+ * * * Ver   Who        Date         Changes
+ * * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef FT_CPU_H
+#define FT_CPU_H
+
+#include "ft_types.h"
+#include "ft_error_code.h"
+extern const u32 SoftAffiTable[4];
+s32 FCpu_IdGet(void);
+void FCpu_SpinLockInit(void);
+void FCpu_SpinLock(void);
+void FCpu_SpinUnlock(void);
+s32 FCpu_AffinityGet(void);
+
+#endif // !FT_SPIN_H