完善SWM320 BSP

2026-02-06 09:02:20 +08:00 · 2021-02-18 13:29:12 +08:00
parent 6420c27791
commit 0c2aef2c0b
116 changed files with 47792 additions and 51 deletions
--- a/.github/workflows/action.yml
+++ b/.github/workflows/action.yml
@@ -32,14 +32,14 @@ jobs:
         - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}         
+         - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -55,7 +55,7 @@ jobs:
         - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
         - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
         - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -63,10 +63,10 @@ jobs:
         - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -81,7 +81,7 @@ jobs:
         - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -91,45 +91,46 @@ jobs:
         - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}  
-         - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} 
-         - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
    steps:
      - uses: actions/checkout@v2
      - name: Set up Python
@@ -144,13 +145,13 @@ jobs:
          sudo apt-get -qq install gcc-multilib libsdl-dev scons
          echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV
          echo "RTT_CC=gcc" >> $GITHUB_ENV
-    
+
      - name: Install Arm ToolChains
        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
        shell: bash
        run: |
-          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 
-          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt  
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
+          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
          /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
          echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV

@@ -158,8 +159,8 @@ jobs:
        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
        shell: bash
        run: |
-          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 
-          sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt  
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2
+          sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt
          /opt/mips-2016.05/bin/mips-sde-elf-gcc --version
          echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV

--- a/bsp/swm320/.config
+++ b/bsp/swm320/.config
--- a/bsp/swm320/Kconfig
+++ b/bsp/swm320/Kconfig
@@ -0,0 +1,25 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "drivers/Kconfig"
+
+config SOC_SWM320
+    bool
+    select ARCH_ARM_CORTEX_M4
+    default y
--- a/bsp/swm320/README.md
+++ b/bsp/swm320/README.md
@@ -0,0 +1,169 @@
+# SWM320 BSP 说明
+
+标签： SYNWIT、Cortex-M4、SWM320、国产MCU
+
+---
+
+## 简介
+
+本文档为SWM320开发板提供的 BSP (板级支持包) 说明。
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+## 芯片介绍
+
+- 内核
+  - 32位ARM® Cortex™-M4 内核
+  - 24位系统定时器
+  - 工作频率最高120MHz
+  - 硬件单周期乘法
+  - 集成嵌套向量中断控制器（NVIC），提供最多240个、8级可配置优先级的中断
+  - 通过SWD接口烧录
+- 内置LDO
+  - 供电电压范围为2.0V至3.6V
+- 片上SRAM存储器
+  - 128KB
+- 片上FLASH存储器
+  - 128KB/256KB/512KB
+  - 支持用户定制ISP（在系统编程）更新用户程序
+- 串行接口
+  - UART模块，具有独立8字节FIFO，最高支持主时钟16分频
+  - SPI模块，具有8字节独立FIFO，支持SPI、SSI协议，支持Master/slave模式
+  - I2C模块，支持7位、10位地址方式，支持Master/slave模式
+  - CAN模块，支持协议2.0A(11Bit标识符)和2.0B（29Bit标识符）
+- PWM控制模块
+  - 12通道16位PWM产生器
+  - 可设置高电平结束或周期开始两种条件触发中断
+  - 具有普通、互补、中心对称等多种输出模式
+  - 支持死区控制
+  - ADC采样触发
+- 定时器模块
+  - 6路32位通用定时器
+  - 具备独立中断
+  - 可做计数器使用
+  - 支持输入单脉冲捕获功能
+  - 32位看门狗定时器，溢出后可配置触发中断或复位芯片
+- RTC模块
+  - 可自由设置日期（年、月、周、日）和时间（时、分、秒）
+  - 可自由设置闹钟（周、时、分、秒）
+  - 自动识别当前设置年份是否为闰年
+  - 支持RTC中断从Sleep模式下唤醒芯片
+- DMA模块
+  - 支持存储器到存储器之间的数据搬运
+- SRAMC模块
+  - 支持8位数据位宽和16位数据位宽的外部SRAM存储器
+  - 最大支持24位地址线
+- SDRAMC模块
+  - 支持16Bit位宽的SDRAM
+  - 支持兼容PC133标准的SDRAM颗粒
+  - 支持2MB到32MB的外部SDRAM颗粒
+- NORFLC模块
+  - 支持并行NOR FLASH接口
+  - 支持8位数据位宽和16位数据位宽的外部NOR FLASH存储器
+  - 最大支持24位地址线
+- SDIO接口模块
+  - 支持标准SDIO接口协议
+- TFT-LCD驱动模块
+  - 支持SYNC接口的外部LCD扩展
+  - 支持最高分辨率1024*768，实际分辨率可以配置
+  - 输出数据宽度16Bit
+  - 支持横屏和竖屏模式
+- GPIO
+  - 最多可达100个GPIO
+  - 可配置2种IO模式
+  - 上拉输入
+  - 下拉输入
+  - 灵活的中断配置
+  - 触发类型设置（边沿检测、电平检测）
+  - 触发电平设置（高电平、低电平）
+  - 触发边沿设置（上升沿、下降沿、双边沿）
+- 模拟外设
+  - 最多2个12位8通道高精度SAR ADC
+  - 采样率高达1M SPS
+  - 内建参考电压
+  - 支持single、scan两种模式
+  - 独立的结果寄存器
+  - 提供独立FIFO
+  - 可由软件、PWM触发
+- 欠压检测（BOD）
+  - 支持欠压检测
+  - 支持欠压中断和复位选择
+- 时钟源
+  - 20MHz/40MHz精度可达1%的片内时钟源
+  - 32K片内时钟源
+  - 2～32MHz片外晶振
+
+芯片更多详细信息请参考[华芯微特技术支持][http://www.synwit.cn/support-1/3.html]。
+
+## 编译说明
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板
+
+推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/swm320` 目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。
+
+## 烧写及执行
+
+### 硬件连接
+
+- 使用 USB B-Type 数据线连接开发板到 PC（注意：需要下载安装串口驱动支持 CH340 芯片，使用 MDK5 需要安装 SWM320 相关的 pack）。
+
+  >  USB B-Type 数据线用于串口通讯，同时供电
+
+- 使用 Jlink 连接开发板到 PC （需要 Jlink 驱动）
+
+将串口 0 引脚为：`[PA2/PA3]`和 USB 转串口模块 P2 相连，串口配置方式为115200-N-8-1。
+
+当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后，可以使用 ISP 的方式来烧写到设备中。
+
+**建议使用 keil 软件直接下载**。ISP 下载较复杂。
+
+### 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到板子上的蓝色LED闪烁。串口打印RT-Thread的启动logo信息：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Dec 11 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh />
+```
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设**        | **支持情况**  | **备注**                              |
+| :----------------- | :----------: | :----------------------------------- |
+| GPIO               |     支持     | PA0, PA1... PP23 ---> PIN: 0, 1...100 |
+| UART               |     支持     | UART0/1/2/3                           |
+| ADC                |     支持     | ADC0/1                                |
+| TIM                |     支持     | TIM0/1/2/3/4/5                        |
+| I2C                |     支持     | 软件 I2C0/1                            |
+| PWM                |     支持     | PWM0/1/2/3/4/5                        |
+| RTC                |     支持     | RTC                                   |
+| SPI                |     支持     | SPI0/1                                |
+| WDT                |     支持     | WDT                                   |
+| CRC                |     支持     | CRC                                   |
+| SDIO               |     支持     | SDIO                                  |
+| SRAM               |     支持     | SRAM                                  |
+| NOR FLASH          |     支持     | NOR FLASH                             |
+| CAN                |    暂不支持   |                                       |
+
+## 维护人信息
+
+- [yanmowudi](https://github.com/yanmowudi)
+- [邮箱](lik@synwit.cn)
+
+## 参考资料
+
+* [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+* [SWM320数据手册](http://www.synwit.cn/support-1/3.html)
--- a/bsp/swm320/SConscript
+++ b/bsp/swm320/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
--- a/bsp/swm320/SConstruct
+++ b/bsp/swm320/SConstruct
@@ -0,0 +1,41 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
--- a/bsp/swm320/applications/SConscript
+++ b/bsp/swm320/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+src     = Glob('*.c') + Glob('*.cpp')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
--- a/bsp/swm320/applications/main.c
+++ b/bsp/swm320/applications/main.c
--- a/bsp/swm320/drivers/Kconfig
+++ b/bsp/swm320/drivers/Kconfig
@@ -0,0 +1,306 @@
+menu "Hardware Drivers Config"
+
+config SOC_SWM320
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0 (A2/RX,A3/TX)"
+                default y
+            config BSP_USING_UART1
+                bool "Enable UART1 (C2/RX,C3/TX)"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2 (C4/RX,C5/TX)"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3 (C6/RX,C7/TX)"
+                default n
+        endif
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC0
+                bool "Enable ADC0"
+                default n
+                if BSP_USING_ADC0
+                    config BSP_USING_ADC0_CHN0
+                        bool "Enable ADC0_CHN0"
+                        default n
+                    config BSP_USING_ADC0_CHN1
+                        bool "Enable ADC0_CHN1"
+                        default n
+                    config BSP_USING_ADC0_CHN2
+                        bool "Enable ADC0_CHN2"
+                        default n
+                    config BSP_USING_ADC0_CHN3
+                        bool "Enable ADC0_CHN3"
+                        default n
+                    config BSP_USING_ADC0_CHN4
+                        bool "Enable ADC0_CHN4(A12)"
+                        default n
+                    config BSP_USING_ADC0_CHN5
+                        bool "Enable ADC0_CHN5(A11)"
+                        default n
+                    config BSP_USING_ADC0_CHN6
+                        bool "Enable ADC0_CHN6(A10)"
+                        default n
+                    config BSP_USING_ADC0_CHN7
+                        bool "Enable ADC0_CHN7(A9)"
+                        default n
+                endif
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+                if BSP_USING_ADC1
+                    config BSP_USING_ADC1_CHN0
+                        bool "Enable ADC1_CHN0(C7)"
+                        default n
+                    config BSP_USING_ADC1_CHN1
+                        bool "Enable ADC1_CHN1(C6)"
+                        default n
+                    config BSP_USING_ADC1_CHN2
+                        bool "Enable ADC1_CHN2(C5)"
+                        default n
+                    config BSP_USING_ADC1_CHN3
+                        bool "Enable ADC1_CHN3(C4)"
+                        default n
+                    config BSP_USING_ADC1_CHN4
+                        bool "Enable ADC1_CHN4(N0)"
+                        default n
+                    config BSP_USING_ADC1_CHN5
+                        bool "Enable ADC1_CHN5(N1)"
+                        default n
+                    config BSP_USING_ADC1_CHN6
+                        bool "Enable ADC1_CHN6(N2)"
+                        default n
+                    config BSP_USING_ADC1_CHN7
+                        bool "Enable ADC1_CHN7"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_TIM
+        bool "Enable HWTIMER"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIM
+            config BSP_USING_TIM0
+                bool "Enable TIM0"
+                default n
+            config BSP_USING_TIM1
+                bool "Enable TIM1"
+                default n
+            config BSP_USING_TIM2
+                bool "Enable TIM2"
+                default n
+            config BSP_USING_TIM3
+                bool "Enable TIM3"
+                default n
+
+            config BSP_USING_TIM4
+                bool "Enable TIM4"
+                default n
+            config BSP_USING_TIM5
+                bool "Enable TIM5"
+                default n
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C BUS (software simulation)"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default n
+                if BSP_USING_I2C0
+                    comment "Notice: PC2 --> 28; PC3 --> 29"
+                    config BSP_I2C0_SCL_PIN
+                        int "I2C0 scl pin number"
+                        range 0 99
+                        default 28
+                    config BSP_I2C0_SDA_PIN
+                        int "I2C0 sda pin number"
+                        range 0 99
+                        default 29
+                endif
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+                if BSP_USING_I2C1
+                    comment "Notice: PC6 --> 32; PC7 --> 33"
+                    config BSP_I2C1_SCL_PIN
+                        int "I2C1 scl pin number"
+                        range 0 99
+                        default 32
+                    config BSP_I2C1_SDA_PIN
+                        int "I2C1 sda pin number"
+                        range 0 99
+                        default 33
+                endif
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        config BSP_USING_PWM0
+            bool "Enable PWM0"
+            default n
+            if BSP_USING_PWM0
+                config BSP_USING_PWM0A
+                    bool "Enable PWM0A (C2)"
+                    default n
+                config BSP_USING_PWM0B
+                    bool "Enable PWM0B (C4)"
+                    default n
+            endif
+        config BSP_USING_PWM1
+            bool "Enable PWM1"
+            default n
+            if BSP_USING_PWM1
+                config BSP_USING_PWM1A
+                    bool "Enable PWM1A (C3)"
+                    default n
+                config BSP_USING_PWM1B
+                    bool "Enable PWM1B (C5)"
+                    default n
+            endif
+        config BSP_USING_PWM2
+            bool "Enable PWM2"
+            default n
+            if BSP_USING_PWM2
+                config BSP_USING_PWM2A
+                    bool "Enable PWM2A (N4)"
+                    default n
+                config BSP_USING_PWM2B
+                    bool "Enable PWM2B (N6)"
+                    default n
+            endif
+        config BSP_USING_PWM3
+            bool "Enable PWM3"
+            default n
+            if BSP_USING_PWM3
+                config BSP_USING_PWM3A
+                    bool "Enable PWM3A (N3)"
+                    default n
+                config BSP_USING_PWM3B
+                    bool "Enable PWM3B (N5)"
+                    default n
+            endif
+        config BSP_USING_PWM4
+            bool "Enable PWM4"
+            default n
+            if BSP_USING_PWM4
+                config BSP_USING_PWM4A
+                    bool "Enable PWM4A (N8)"
+                    default n
+                config BSP_USING_PWM4B
+                    bool "Enable PWM4B (N10)"
+                    default n
+            endif
+        config BSP_USING_PWM5
+            bool "Enable PWM5"
+            default n
+            if BSP_USING_PWM5
+                config BSP_USING_PWM5A
+                    bool "Enable PWM5A (N7)"
+                    default n
+                config BSP_USING_PWM5B
+                    bool "Enable PWM5B (N9)"
+                    default n
+            endif
+        endif
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        select RT_USING_LIBC
+        default n
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0 BUS(CS/A12,MISO/A11,MOSI/A10,CLK/A9)"
+                default n
+
+            config BSP_USING_SPI1
+                bool "Enable SPI1 BUS(CS/C4,MISO/C5,MOSI/C6,CLK/C7)"
+                default n
+        endif
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    config BSP_USING_CRC
+        bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
+        select RT_USING_HWCRYPTO
+        select RT_HWCRYPTO_USING_CRC
+        default n
+endmenu
+
+menu "Onboard Peripheral Drivers"
+    config BSP_USING_SDIO
+        bool "Enable SDCARD (sdio)"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        default n
+
+    menuconfig BSP_USING_EXT_SRAM
+        bool "Enable external sram"
+        select RT_USING_MEMHEAP
+        select RT_USING_MEMHEAP_AS_HEAP
+        default n
+        if BSP_USING_EXT_SRAM
+            config BSP_EXT_SRAM_SIZE
+            hex "external sram size"
+            default 0x100000
+        endif
+
+        menuconfig BSP_USING_NOR_FLASH
+        bool "Enable mtd nor flash"
+        select RT_USING_MTD_NOR
+        select PKG_USING_FTL_SRC
+        default n
+        if BSP_USING_NOR_FLASH
+            config BSP_NOR_FLASH_SIZE
+                hex "mtd nor flash size"
+                default 0x1000000
+            config BSP_NOR_FLASH_SECTOR_SIZE
+                hex "mtd nor flsah sector"
+                default 0x10000
+        endif
+endmenu
+
+menu "Offboard Peripheral Drivers"
+
+endmenu
+
+endmenu
--- a/bsp/swm320/drivers/SConscript
+++ b/bsp/swm320/drivers/SConscript
@@ -0,0 +1,52 @@
+from building import *
+
+cwd     = GetCurrentDir()
+
+CPPPATH = [cwd]
+
+src     = Split('''
+                board.c
+                ''')
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_uart.c']
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_I2C']):
+    src += ['drv_soft_i2c.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['RT_USING_SDIO']):
+    src += ['drv_sdio.c']
+
+if GetDepend(['RT_USING_HWCRYPTO']):
+    src += ['drv_crypto.c']
+
+if GetDepend(['BSP_USING_EXT_SRAM']):
+    src += ['drv_sram.c']
+
+if  GetDepend(['BSP_USING_NOR_FLASH']):
+    src += ['drv_nor_flash.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
--- a/bsp/swm320/drivers/board.c
+++ b/bsp/swm320/drivers/board.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ */
+
+#include "board.h"
+
+static void bsp_clock_config(void)
+{
+    SystemInit();
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    SysTick->CTRL |= 0x00000004UL;
+}
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void rt_hw_board_init()
+{
+    bsp_clock_config();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
--- a/bsp/swm320/drivers/board.h
+++ b/bsp/swm320/drivers/board.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <string.h>
+#include <SWM320.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define SRAM_BASE 0x20000000
+#define SRAM_SIZE 0x20000
+#define SRAM_END (SRAM_BASE + SRAM_SIZE)
+
+#ifdef BSP_USING_EXT_SRAM
+#define EXT_SRAM_BASE SRAMM_BASE
+#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE
+#define EXT_SRAM_BEGIN EXT_SRAM_BASE
+#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE)
+#endif
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section = "HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+
+#define HEAP_END SRAM_END
+#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
+
+    void rt_hw_board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */
--- a/bsp/swm320/drivers/drv_adc.c
+++ b/bsp/swm320/drivers/drv_adc.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-5-26      lik          first version
+ */
+
+#include "drv_adc.h"
+
+#ifdef RT_USING_ADC
+#ifdef BSP_USING_ADC
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.adc"
+#include <drv_log.h>
+
+static struct swm_adc_cfg adc_cfg[] =
+    {
+#ifdef BSP_USING_ADC0
+        ADC0_CFG,
+#endif
+#ifdef BSP_USING_ADC1
+        ADC1_CFG,
+#endif
+
+};
+
+static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])];
+
+static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    struct swm_adc_cfg *cfg = RT_NULL;
+    RT_ASSERT(adc_device != RT_NULL);
+    cfg = adc_device->parent.user_data;
+
+    if (enabled)
+    {
+        ADC_Open(cfg->ADCx);
+    }
+    else
+    {
+        ADC_Close(cfg->ADCx);
+    }
+
+    return RT_EOK;
+}
+
+static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
+{
+    rt_uint32_t swm_channel = 0;
+
+    switch (channel)
+    {
+    case 0:
+        swm_channel = ADC_CH0;
+        break;
+    case 1:
+        swm_channel = ADC_CH1;
+        break;
+    case 2:
+        swm_channel = ADC_CH2;
+        break;
+    case 3:
+        swm_channel = ADC_CH3;
+        break;
+    case 4:
+        swm_channel = ADC_CH4;
+        break;
+    case 5:
+        swm_channel = ADC_CH5;
+        break;
+    case 6:
+        swm_channel = ADC_CH6;
+        break;
+    case 7:
+        swm_channel = ADC_CH7;
+        break;
+    }
+
+    return swm_channel;
+}
+
+static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    uint32_t adc_chn;
+    struct swm_adc_cfg *cfg = RT_NULL;
+    RT_ASSERT(adc_device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+    cfg = adc_device->parent.user_data;
+
+    if (channel < 8)
+    {
+        /* set stm32 ADC channel */
+        adc_chn = swm_adc_get_channel(channel);
+    }
+    else
+    {
+        LOG_E("ADC channel must be between 0 and 7.");
+        return -RT_ERROR;
+    }
+
+    /* start ADC */
+    ADC_Start(cfg->ADCx);
+    /* Wait for the ADC to convert */
+    while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0)
+        ;
+
+    /* get ADC value */
+    *value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops swm_adc_ops =
+    {
+        .enabled = swm_adc_enabled,
+        .convert = swm_get_adc_value,
+};
+
+static int rt_hw_adc_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++)
+    {
+        /* ADC init */
+        adc_drv[i].cfg = &adc_cfg[i];
+
+        if (adc_drv[i].cfg->ADCx == ADC0)
+        {
+#ifdef BSP_USING_ADC0_CHN0
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
+#endif
+#ifdef BSP_USING_ADC0_CHN1
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
+#endif
+#ifdef BSP_USING_ADC0_CHN2
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
+#endif
+#ifdef BSP_USING_ADC0_CHN3
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
+#endif
+#ifdef BSP_USING_ADC0_CHN4
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
+            PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4
+#endif
+#ifdef BSP_USING_ADC0_CHN5
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
+            PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5
+#endif
+#ifdef BSP_USING_ADC0_CHN6
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
+            PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6
+#endif
+#ifdef BSP_USING_ADC0_CHN7
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
+            PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9  => ADC0.CH7
+#endif
+        }
+        else if (adc_drv[i].cfg->ADCx == ADC1)
+        {
+#ifdef BSP_USING_ADC1_CHN0
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
+            PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0
+#endif
+#ifdef BSP_USING_ADC1_CHN1
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
+            PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1
+#endif
+#ifdef BSP_USING_ADC1_CHN2
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
+            PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2
+#endif
+#ifdef BSP_USING_ADC1_CHN3
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
+            PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3
+#endif
+#ifdef BSP_USING_ADC1_CHN4
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
+            PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4
+#endif
+#ifdef BSP_USING_ADC1_CHN5
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
+            PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5
+#endif
+#ifdef BSP_USING_ADC1_CHN6
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
+            PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6
+#endif
+#ifdef BSP_USING_ADC1_CHN7
+            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
+#endif
+        }
+
+        ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct));
+        ADC_Open(adc_drv[i].cfg->ADCx);
+        /* register ADC device */
+        if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK)
+        {
+            LOG_D("%s init success", adc_drv[i].cfg->name);
+        }
+        else
+        {
+            LOG_E("%s register failed", adc_drv[i].cfg->name);
+            result = -RT_ERROR;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_adc_init);
+#endif /* BSP_USING_ADC */
+#endif /* RT_USING_ADC */
--- a/bsp/swm320/drivers/drv_adc.h
+++ b/bsp/swm320/drivers/drv_adc.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-5-26      lik          first version
+ */
+
+#ifndef __DRV_ADC_H__
+#define __DRV_ADC_H__
+
+#include "board.h"
+
+struct swm_adc_cfg
+{
+    const char *name;
+    ADC_TypeDef *ADCx;
+    ADC_InitStructure adc_initstruct;
+};
+
+struct swm_adc
+{
+    struct swm_adc_cfg *cfg;
+    struct rt_adc_device adc_device;
+};
+
+#ifdef BSP_USING_ADC0
+#ifndef ADC0_CFG
+#define ADC0_CFG                                        \
+    {                                                   \
+        .name = "adc0",                                 \
+        .ADCx = ADC0,                                   \
+        .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
+        .adc_initstruct.clk_div = 25,                   \
+        .adc_initstruct.pga_ref = PGA_REF_INTERNAL,     \
+        .adc_initstruct.channels = 0,                   \
+        .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1,     \
+        .adc_initstruct.trig_src = ADC_TRIGSRC_SW,      \
+        .adc_initstruct.Continue = 0,                   \
+        .adc_initstruct.EOC_IEn = 0,                    \
+        .adc_initstruct.OVF_IEn = 0,                    \
+        .adc_initstruct.HFULL_IEn = 0,                  \
+        .adc_initstruct.FULL_IEn = 0,                   \
+    }
+#endif /* ADC0_CFG */
+#endif /* BSP_USING_ADC0 */
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CFG
+#define ADC1_CFG                                        \
+    {                                                   \
+        .name = "adc1",                                 \
+        .ADCx = ADC1,                                   \
+        .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
+        .adc_initstruct.clk_div = 25,                   \
+        .adc_initstruct.pga_ref = PGA_REF_INTERNAL,     \
+        .adc_initstruct.channels = 0,                   \
+        .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1,     \
+        .adc_initstruct.trig_src = ADC_TRIGSRC_SW,      \
+        .adc_initstruct.Continue = 0,                   \
+        .adc_initstruct.EOC_IEn = 0,                    \
+        .adc_initstruct.OVF_IEn = 0,                    \
+        .adc_initstruct.HFULL_IEn = 0,                  \
+        .adc_initstruct.FULL_IEn = 0,                   \
+    }
+#endif /* ADC1_CFG */
+#endif /* BSP_USING_ADC1 */
+
+#endif /* __DRV_ADC_H__ */
--- a/bsp/swm320/drivers/drv_crypto.c
+++ b/bsp/swm320/drivers/drv_crypto.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-10     lik          first version
+ */
+
+#include "drv_crypto.h"
+#include <string.h>
+
+#ifdef RT_USING_HWCRYPTO
+
+struct swm_hwcrypto_device
+{
+    struct rt_hwcrypto_device dev;
+    struct rt_mutex mutex;
+};
+
+#ifdef BSP_USING_CRC
+
+struct hash_ctx_des
+{
+    struct swm_crc_cfg contex;
+};
+
+static struct hwcrypto_crc_cfg crc_backup_cfg;
+
+static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    rt_uint32_t result = 0;
+    struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data;
+
+    struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex);
+
+    rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER);
+
+    if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
+    {
+        hw_crc_cfg->CRCx = CRC;
+
+        hw_crc_cfg->inival = ctx->crc_cfg.last_val;
+
+        switch (ctx->crc_cfg.width)
+        {
+        case 8:
+            hw_crc_cfg->crc_inbits = 2;
+            break;
+        case 16:
+            hw_crc_cfg->crc_inbits = 1;
+            break;
+        case 32:
+            hw_crc_cfg->crc_inbits = 0;
+            break;
+        default:
+            goto _exit;
+        }
+        switch (ctx->crc_cfg.poly)
+        {
+        case 0x1021:
+            hw_crc_cfg->crc_1632 = 1;
+            break;
+        case 0x04C11DB7:
+            hw_crc_cfg->crc_1632 = 0;
+            break;
+        default:
+            goto _exit;
+        }
+
+        hw_crc_cfg->crc_out_not = 0;
+
+        switch (ctx->crc_cfg.flags)
+        {
+        case 0:
+        case CRC_FLAG_REFIN:
+            hw_crc_cfg->crc_out_rev = 0;
+            break;
+        case CRC_FLAG_REFOUT:
+        case CRC_FLAG_REFIN | CRC_FLAG_REFOUT:
+            hw_crc_cfg->crc_out_rev = 1;
+            break;
+        default:
+            goto _exit;
+        }
+
+        CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival);
+        memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg));
+    }
+
+    for (uint32_t i = 0; i < length; i++)
+        CRC_Write((uint32_t)in[i]);
+    result = CRC_Result();
+
+    ctx->crc_cfg.last_val = result;
+
+    crc_backup_cfg.last_val = ctx->crc_cfg.last_val;
+    result = (result ? result ^ (ctx->crc_cfg.xorout) : result);
+
+_exit:
+    rt_mutex_release(&swm_hw_dev->mutex);
+
+    return result;
+}
+
+static const struct hwcrypto_crc_ops crc_ops =
+    {
+        .update = _crc_update,
+};
+
+static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+    {
+        struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg));
+        if (RT_NULL == contex)
+        {
+            res = -RT_ERROR;
+            break;
+        }
+        contex->CRCx = DEFAULT_CRC;
+        contex->inival = DEFAULT_INIVAL;
+        contex->crc_inbits = DEFAULT_INBITS;
+        contex->crc_1632 = DEFAULT_CRC1632;
+        contex->crc_out_not = DEFAULT_OUT_NOT;
+        contex->crc_out_rev = DEFAULT_OUT_REV;
+
+        ctx->contex = contex;
+        ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
+        break;
+    }
+#endif /* BSP_USING_CRC */
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+    return res;
+}
+
+static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
+{
+    struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        break;
+    }
+
+    rt_free(ctx->contex);
+}
+
+static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+        }
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+    return res;
+}
+
+static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
+{
+    struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        break;
+    }
+}
+
+static const struct rt_hwcrypto_ops _ops =
+    {
+        .create = _crypto_create,
+        .destroy = _crypto_destroy,
+        .copy = _crypto_clone,
+        .reset = _crypto_reset,
+};
+
+int rt_hw_crypto_init(void)
+{
+    static struct swm_hwcrypto_device _crypto_dev;
+    rt_uint32_t cpuid[2] = {0};
+
+    _crypto_dev.dev.ops = &_ops;
+
+    cpuid[0] = SCB->CPUID;
+    _crypto_dev.dev.id = 0;
+    rt_memcpy(&_crypto_dev.dev.id, cpuid, 8);
+
+    _crypto_dev.dev.user_data = &_crypto_dev;
+
+    if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
+    {
+        return -1;
+    }
+    rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO);
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_crypto_init);
+
+#endif /* BSP_USING_WDT */
+#endif /* RT_USING_WDT */
--- a/bsp/swm320/drivers/drv_crypto.h
+++ b/bsp/swm320/drivers/drv_crypto.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-10     lik          first version
+ */
+
+#ifndef __DRV_CRYPTO_H__
+#define __DRV_CRYPTO_H__
+
+#include "board.h"
+
+/* swm config class */
+struct swm_crc_cfg
+{
+    CRC_TypeDef *CRCx;
+    uint32_t inival;
+    uint8_t crc_inbits;
+    uint8_t crc_1632;
+    uint8_t crc_out_not;
+    uint8_t crc_out_rev;
+};
+
+#ifdef BSP_USING_CRC
+
+#define DEFAULT_CRC (CRC)
+#define DEFAULT_INIVAL (0x00000000)
+#define DEFAULT_INBITS (2)
+#define DEFAULT_CRC1632 (0)
+#define DEFAULT_OUT_NOT (0)
+#define DEFAULT_OUT_REV (0)
+
+#endif /* BSP_USING_CRC */
+
+int rt_hw_crypto_init(void);
+
+#endif /* __DRV_CRYPTO_H__ */
--- a/bsp/swm320/drivers/drv_gpio.c
+++ b/bsp/swm320/drivers/drv_gpio.c
--- a/bsp/swm320/drivers/drv_gpio.h
+++ b/bsp/swm320/drivers/drv_gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include "board.h"
+
+#define __SWM_PIN(index, gpio, pin_index)                    \
+    {                                                        \
+        index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
+    }
+#define GPIO0 ((GPIO_TypeDef *)(0))
+#define GPIO0_IRQn (GPIOA0_IRQn)
+
+struct swm_pin_index
+{
+    uint32_t index;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+    IRQn_Type irq;
+};
+typedef struct swm_pin_index pin_t;
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */
--- a/bsp/swm320/drivers/drv_hwtimer.c
+++ b/bsp/swm320/drivers/drv_hwtimer.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10    Zohar_Lee    first version
+ * 2020-07-10    lik          format file
+ */
+
+#include "drv_hwtimer.h"
+
+#ifdef RT_USING_HWTIMER
+#ifdef BSP_USING_TIM
+
+enum
+{
+#ifdef BSP_USING_TIM0
+    TIM0_INDEX,
+#endif
+#ifdef BSP_USING_TIM1
+    TIM1_INDEX,
+#endif
+#ifdef BSP_USING_TIM2
+    TIM2_INDEX,
+#endif
+#ifdef BSP_USING_TIM3
+    TIM3_INDEX,
+#endif
+#ifdef BSP_USING_TIM4
+    TIM4_INDEX,
+#endif
+#ifdef BSP_USING_TIM5
+    TIM5_INDEX,
+#endif
+};
+
+static struct swm_hwtimer_cfg hwtimer_cfg[] =
+    {
+#ifdef BSP_USING_TIM0
+        TIM0_CFG,
+#endif
+#ifdef BSP_USING_TIM1
+        TIM1_CFG,
+#endif
+#ifdef BSP_USING_TIM2
+        TIM2_CFG,
+#endif
+#ifdef BSP_USING_TIM3
+        TIM3_CFG,
+#endif
+#ifdef BSP_USING_TIM4
+        TIM4_CFG,
+#endif
+#ifdef BSP_USING_TIM5
+        TIM5_CFG,
+#endif
+};
+
+static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0};
+
+static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state)
+{
+    struct swm_hwtimer_cfg *cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+
+    if (state)
+    {
+        cfg = timer_device->parent.user_data;
+        TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1);
+        timer_device->freq = SystemCoreClock;
+    }
+}
+
+static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode)
+{
+    rt_err_t result = RT_EOK;
+    struct swm_hwtimer_cfg *cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    cfg = timer_device->parent.user_data;
+
+    if (opmode == HWTIMER_MODE_ONESHOT)
+    {
+        /* set timer to single mode */
+        timer_device->mode = HWTIMER_MODE_ONESHOT;
+    }
+    else
+    {
+        timer_device->mode = HWTIMER_MODE_PERIOD;
+    }
+    TIMR_SetPeriod(cfg->TIMRx, cnt);
+    TIMR_Stop(cfg->TIMRx);
+    TIMR_Start(cfg->TIMRx);
+
+    return result;
+}
+
+static void swm_timer_stop(rt_hwtimer_t *timer_device)
+{
+    struct swm_hwtimer_cfg *cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    cfg = timer_device->parent.user_data;
+
+    /* stop timer */
+    TIMR_Stop(cfg->TIMRx);
+}
+
+static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device)
+{
+    struct swm_hwtimer_cfg *cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    cfg = timer_device->parent.user_data;
+
+    return TIMR_GetCurValue(cfg->TIMRx);
+}
+
+static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args)
+{
+    struct swm_hwtimer_cfg *cfg = RT_NULL;
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(timer_device != RT_NULL);
+    RT_ASSERT(args != RT_NULL);
+    cfg = timer_device->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        rt_uint32_t freq;
+        freq = *(rt_uint32_t *)args;
+
+        TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1);
+    }
+    break;
+    default:
+    {
+        result = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return result;
+}
+
+static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
+
+static struct rt_hwtimer_ops swm_hwtimer_ops =
+    {
+        .init = swm_timer_init,
+        .start = swm_timer_start,
+        .stop = swm_timer_stop,
+        .count_get = swm_timer_count_get,
+        .control = swm_timer_ctrl};
+
+void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device)
+{
+    struct swm_hwtimer_cfg *cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    cfg = timer_device->parent.user_data;
+
+    TIMR_INTClr(cfg->TIMRx);
+    rt_device_hwtimer_isr(timer_device);
+}
+#ifdef BSP_USING_TIM0
+void TIMR0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM0
+
+#ifdef BSP_USING_TIM1
+void TIMR1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM1
+
+#ifdef BSP_USING_TIM2
+void TIMR2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM2
+
+#ifdef BSP_USING_TIM3
+void TIMR3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM3
+
+#ifdef BSP_USING_TIM4
+void TIMR4_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM4
+
+#ifdef BSP_USING_TIM5
+void TIMR5_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM5
+
+static int rt_hw_hwtimer_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++)
+    {
+        hwtimer_drv[i].cfg = &hwtimer_cfg[i];
+        hwtimer_drv[i].time_device.info = &_info;
+        hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops;
+        if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK)
+        {
+            ;
+        }
+        else
+        {
+            result = -RT_ERROR;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
+
+#endif /* BSP_USING_TIM */
+#endif /* RT_USING_HWTIMER */
--- a/bsp/swm320/drivers/drv_hwtimer.h
+++ b/bsp/swm320/drivers/drv_hwtimer.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+#include "board.h"
+
+struct swm_hwtimer_cfg
+{
+    char *name;
+    TIMR_TypeDef *TIMRx;
+};
+
+struct swm_hwtimer
+{
+    struct swm_hwtimer_cfg *cfg;
+    rt_hwtimer_t time_device;
+};
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG            \
+    {                                  \
+        .maxfreq = 120000000,          \
+        .minfreq = 120000000,          \
+        .maxcnt = 0xFFFFFFFF,          \
+        .cntmode = HWTIMER_CNTMODE_DW, \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM0
+#ifndef TIM0_CFG
+#define TIM0_CFG          \
+    {                     \
+        .name = "timer0", \
+        .TIMRx = TIMR0,   \
+    }
+#endif /* TIM0_CFG */
+#endif /* BSP_USING_TIM0 */
+
+#ifdef BSP_USING_TIM1
+#ifndef TIM1_CFG
+#define TIM1_CFG          \
+    {                     \
+        .name = "timer1", \
+        .TIMRx = TIMR1,   \
+    }
+#endif /* TIM1_CFG */
+#endif /* BSP_USING_TIM1 */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CFG
+#define TIM2_CFG          \
+    {                     \
+        .name = "timer2", \
+        .TIMRx = TIMR2,   \
+    }
+#endif /* TIM2_CFG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CFG
+#define TIM3_CFG          \
+    {                     \
+        .name = "timer3", \
+        .TIMRx = TIMR3,   \
+    }
+#endif /* TIM3_CFG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CFG
+#define TIM4_CFG          \
+    {                     \
+        .name = "timer4", \
+        .TIMRx = TIMR4,   \
+    }
+#endif /* TIM4_CFG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CFG
+#define TIM5_CFG          \
+    {                     \
+        .name = "timer5", \
+        .TIMRx = TIMR5,   \
+    }
+#endif /* TIM5_CFG */
+#endif /* BSP_USING_TIM5 */
+
+int rt_hw_hwtimer_init(void);
+
+#endif /* __DRV_HWTIMER_H__ */
--- a/bsp/swm320/drivers/drv_log.h
+++ b/bsp/swm320/drivers/drv_log.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG "drv"
+#else
+#define DBG_TAG LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL DBG_LOG
+#else
+#define DBG_LVL DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>
--- a/bsp/swm320/drivers/drv_nor_flash.c
+++ b/bsp/swm320/drivers/drv_nor_flash.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          rewrite
+ */
+
+#include "drv_nor_flash.h"
+
+#ifdef BSP_USING_NOR_FLASH
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.norflash"
+#include <drv_log.h>
+
+static struct rt_mutex flash_lock;
+
+/* RT-Thread MTD device interface */
+static long swm_norflash_read_id(struct rt_mtd_nor_device *device)
+{
+    return 0xdeadbeef;
+}
+
+static rt_size_t swm_norflash_read(struct rt_mtd_nor_device *device,
+                                   rt_off_t position,
+                                   rt_uint8_t *data,
+                                   rt_uint32_t size)
+{
+    rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
+    memcpy(data, ((const void *)(NORFLM_BASE + position)), size);
+    rt_mutex_release(&flash_lock);
+    return size;
+}
+
+static rt_size_t swm_norflash_write(struct rt_mtd_nor_device *device,
+                                    rt_off_t position,
+                                    const rt_uint8_t *data,
+                                    rt_uint32_t size)
+{
+    rt_size_t i;
+    const rt_uint16_t *hwdata = (const rt_uint16_t *)data;
+    rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
+    for (i = 0; i < size / 2; i++)
+    {
+        NORFL_Write(position, hwdata[i]);
+        position += 2;
+    }
+    rt_mutex_release(&flash_lock);
+    return size;
+}
+
+static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device,
+                                         rt_off_t offset,
+                                         rt_uint32_t length)
+{
+    rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
+    NORFL_SectorErase(offset);
+    rt_mutex_release(&flash_lock);
+    return RT_EOK;
+}
+
+const static struct rt_mtd_nor_driver_ops mtd_ops =
+    {
+        swm_norflash_read_id,
+        swm_norflash_read,
+        swm_norflash_write,
+        swm_norflash_erase_block};
+
+static struct rt_mtd_nor_device mtd;
+int rt_hw_norflash_init(void)
+{
+    NORFL_InitStructure NORFL_InitStruct;
+
+    PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23
+    PORT->PORTP_SEL1 = 0xAAAA;
+
+    PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0
+    PORT->PORTM_INEN = 0xFFFF;
+
+    PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE
+
+    NORFL_InitStruct.DataWidth = 16;
+    NORFL_InitStruct.WELowPulseTime = 5;
+    NORFL_InitStruct.OEPreValidTime = 12;
+    NORFL_InitStruct.OperFinishIEn = 0;
+    NORFL_InitStruct.OperTimeoutIEn = 0;
+    NORFL_Init(&NORFL_InitStruct);
+
+    /* set page size and block size */
+    mtd.block_size = BLOCK_SIZE; /* 64kByte */
+    mtd.ops = &mtd_ops;
+
+    /* initialize mutex */
+    if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_FIFO) != RT_EOK)
+    {
+        rt_kprintf("init sd lock mutex failed\n");
+        return -RT_ERROR;
+    }
+    mtd.block_start = 0;
+    mtd.block_end = BLOCK_COUNTER;
+
+    /* register MTD device */
+    rt_mtd_nor_register_device("nor", &mtd);
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_norflash_init);
+
+#endif /* BSP_USING_NOR_FLASH */
--- a/bsp/swm320/drivers/drv_nor_flash.h
+++ b/bsp/swm320/drivers/drv_nor_flash.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef DRV_NOR_FLASH_H__
+#define DRV_NOR_FLASH_H__
+
+#include "board.h"
+
+#define BLOCK_SIZE (64 * 1024)
+#define FLASH_SIZE (BSP_NOR_FLASH_SIZE)
+#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE)
+
+int rt_hw_norflash_init(void);
+
+#endif
--- a/bsp/swm320/drivers/drv_pwm.c
+++ b/bsp/swm320/drivers/drv_pwm.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_pwm.h"
+
+#ifdef RT_USING_PWM
+#ifdef BSP_USING_PWM
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.pwm"
+#include <drv_log.h>
+
+#define MIN_PERIOD 2
+#define MIN_PULSE 1
+
+static struct swm_pwm_cfg pwm_cfg[] =
+    {
+#ifdef BSP_USING_PWM0
+        PWM0_CFG,
+#endif
+#ifdef BSP_USING_PWM1
+        PWM1_CFG,
+#endif
+#ifdef BSP_USING_PWM2
+        PWM2_CFG,
+#endif
+#ifdef BSP_USING_PWM3
+        PWM3_CFG,
+#endif
+#ifdef BSP_USING_PWM4
+        PWM4_CFG,
+#endif
+#ifdef BSP_USING_PWM5
+        PWM5_CFG,
+#endif
+};
+
+static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0};
+
+static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg);
+static struct rt_pwm_ops pwm_ops =
+    {
+        swm_pwm_control};
+
+static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    struct swm_pwm_cfg *cfg = RT_NULL;
+    RT_ASSERT(pwm_device != RT_NULL);
+    cfg = pwm_device->parent.user_data;
+
+    if (!enable)
+    {
+        if (PWM_CH_A == configuration->channel)
+        {
+            PWM_Stop(cfg->PWMx, 1, 0);
+        }
+        if (PWM_CH_B == configuration->channel)
+        {
+            PWM_Stop(cfg->PWMx, 0, 1);
+        }
+    }
+    else
+    {
+        if (PWM_CH_A == configuration->channel)
+        {
+            PWM_Start(cfg->PWMx, 1, 0);
+        }
+        if (PWM_CH_B == configuration->channel)
+        {
+            PWM_Start(cfg->PWMx, 0, 1);
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
+{
+    rt_uint64_t tim_clock;
+    tim_clock = SystemCoreClock / 8;
+
+    struct swm_pwm_cfg *cfg = RT_NULL;
+    RT_ASSERT(pwm_device != RT_NULL);
+    cfg = pwm_device->parent.user_data;
+
+    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+    tim_clock /= 1000000UL;
+    configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
+    configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
+{
+    rt_uint32_t period, pulse;
+    rt_uint64_t tim_clock;
+    tim_clock = SystemCoreClock / 8;
+
+    struct swm_pwm_cfg *cfg = RT_NULL;
+    RT_ASSERT(pwm_device != RT_NULL);
+    cfg = pwm_device->parent.user_data;
+
+    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+    /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */
+    /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */
+    tim_clock /= 1000000UL;
+    period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
+    pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL;
+    if (period < MIN_PERIOD)
+    {
+        period = MIN_PERIOD;
+    }
+    if (pulse < MIN_PULSE)
+    {
+        pulse = MIN_PULSE;
+    }
+    PWM_SetCycle(cfg->PWMx, configuration->channel, period);
+    PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg)
+{
+    RT_ASSERT(pwm_device != RT_NULL);
+
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return swm_pwm_enable(pwm_device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return swm_pwm_enable(pwm_device, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return swm_pwm_set(pwm_device, configuration);
+    case PWM_CMD_GET:
+        return swm_pwm_get(pwm_device, configuration);
+    default:
+        return RT_EINVAL;
+    }
+}
+
+int rt_hw_pwm_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++)
+    {
+        pwm_drv[i].cfg = &pwm_cfg[i];
+
+        if (pwm_drv[i].cfg->PWMx == PWM0)
+        {
+#ifdef BSP_USING_PWM0A
+            PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM0B
+            PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0);
+#endif
+        }
+        else if (pwm_drv[i].cfg->PWMx == PWM1)
+        {
+#ifdef BSP_USING_PWM1A
+            PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM1B
+            PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0);
+#endif
+        }
+        else if (pwm_drv[i].cfg->PWMx == PWM2)
+        {
+#ifdef BSP_USING_PWM2A
+            PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM2B
+            PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0);
+#endif
+        }
+        else if (pwm_drv[i].cfg->PWMx == PWM3)
+        {
+#ifdef BSP_USING_PWM3A
+            PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM3B
+            PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0);
+#endif
+        }
+        else if (pwm_drv[i].cfg->PWMx == PWM4)
+        {
+#ifdef BSP_USING_PWM4A
+            PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM4B
+            PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0);
+#endif
+        }
+        else if (pwm_drv[i].cfg->PWMx == PWM5)
+        {
+#ifdef BSP_USING_PWM5A
+            PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM5B
+            PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0);
+#endif
+        }
+
+        PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct));
+        if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK)
+        {
+            LOG_D("%s register success", pwm_drv[i].cfg->name);
+        }
+        else
+        {
+            LOG_E("%s register failed", pwm_drv[i].cfg->name);
+            result = -RT_ERROR;
+        }
+    }
+    return result;
+}
+INIT_DEVICE_EXPORT(rt_hw_pwm_init);
+
+#endif /* BSP_USING_PWM */
+#endif /* RT_USING_PWM */
--- a/bsp/swm320/drivers/drv_pwm.h
+++ b/bsp/swm320/drivers/drv_pwm.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_PWM_H__
+#define __DRV_PWM_H__
+
+#include "board.h"
+
+struct swm_pwm_cfg
+{
+    const char *name;
+    PWM_TypeDef *PWMx;
+    PWM_InitStructure pwm_initstruct;
+};
+
+struct swm_pwm
+{
+    struct swm_pwm_cfg *cfg;
+    struct rt_device_pwm pwm_device;
+};
+
+#ifdef BSP_USING_PWM0
+#ifndef PWM0_CFG
+#define PWM0_CFG                                \
+    {                                           \
+        .name = "pwm0",                         \
+        .PWMx = PWM0,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM0_CFG */
+#endif /* BSP_USING_PWM0 */
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CFG
+#define PWM1_CFG                                \
+    {                                           \
+        .name = "pwm1",                         \
+        .PWMx = PWM1,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM1_CFG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CFG
+#define PWM2_CFG                                \
+    {                                           \
+        .name = "pwm2",                         \
+        .PWMx = PWM2,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM2_CFG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CFG
+#define PWM3_CFG                                \
+    {                                           \
+        .name = "pwm3",                         \
+        .PWMx = PWM3,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM3_CFG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CFG
+#define PWM4_CFG                                \
+    {                                           \
+        .name = "pwm4",                         \
+        .PWMx = PWM4,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM4_CFG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CFG
+#define PWM5_CFG                                \
+    {                                           \
+        .name = "pwm5",                         \
+        .PWMx = PWM5,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM5_CFG */
+#endif /* BSP_USING_PWM5 */
+
+int rt_hw_pwm_init(void);
+
+#endif /* __DRV_PWM_H__ */
--- a/bsp/swm320/drivers/drv_rtc.c
+++ b/bsp/swm320/drivers/drv_rtc.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_rtc.h"
+
+#ifdef RT_USING_RTC
+#ifdef BSP_USING_RTC
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.rtc"
+#include <drv_log.h>
+
+static struct rt_device rtc_device;
+
+static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date)
+{
+    uint32_t i, cnt = 0;
+    const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
+
+    for (i = 1; i < month; i++)
+        cnt += daysOfMonth[i];
+
+    cnt += date;
+
+    if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3))
+        cnt += 1;
+
+    cnt += (year - 1901) * 365;
+
+    for (i = 1901; i < year; i++)
+    {
+        if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0)))
+            cnt += 1;
+    }
+
+    return (cnt + 1) % 7;
+}
+
+static time_t swm_get_rtc_time_stamp(void)
+{
+    RTC_DateTime get_datetime = {0};
+    struct tm tm_new;
+
+    RTC_GetDateTime(RTC, &get_datetime);
+
+    tm_new.tm_sec = get_datetime.Second;
+    tm_new.tm_min = get_datetime.Minute;
+    tm_new.tm_hour = get_datetime.Hour;
+    tm_new.tm_mday = get_datetime.Date;
+    tm_new.tm_mon = get_datetime.Month - 1;
+    tm_new.tm_year = get_datetime.Year - 1900;
+
+    LOG_D("get rtc time.");
+    return mktime(&tm_new);
+}
+static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
+{
+    RTC_DateTime set_datetime = {0};
+    struct tm *p_tm;
+
+    p_tm = gmtime(&time_stamp);
+
+    set_datetime.Second = p_tm->tm_sec;
+    set_datetime.Minute = p_tm->tm_min;
+    set_datetime.Hour = p_tm->tm_hour;
+    set_datetime.Date = p_tm->tm_mday;
+    set_datetime.Month = p_tm->tm_mon + 1;
+    set_datetime.Year = p_tm->tm_year + 1900;
+    //    datetime.Day = p_tm->tm_wday;
+
+    RTC_Stop(RTC);
+    while (RTC->CFGABLE == 0)
+        ;
+    RTC->MINSEC = (set_datetime.Second << RTC_MINSEC_SEC_Pos) |
+                  (set_datetime.Minute << RTC_MINSEC_MIN_Pos);
+    RTC->DATHUR = (set_datetime.Hour << RTC_DATHUR_HOUR_Pos) |
+                  ((set_datetime.Date) << RTC_DATHUR_DATE_Pos);
+    RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date)
+                   << RTC_MONDAY_DAY_Pos) |
+                  ((set_datetime.Month) << RTC_MONDAY_MON_Pos);
+    RTC->YEAR = set_datetime.Year - 1901;
+    RTC->LOAD = 1 << RTC_LOAD_TIME_Pos;
+    RTC_Start(RTC);
+
+    LOG_D("set rtc time.");
+    return RT_EOK;
+}
+
+static rt_err_t swm_rtc_control(rt_device_t rtc_device, int cmd, void *args)
+{
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(rtc_device != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = swm_get_rtc_time_stamp();
+        LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+        break;
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
+        {
+            result = -RT_ERROR;
+        }
+        LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+        break;
+    default:
+        break;
+    }
+
+    return result;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops swm_rtc_ops =
+    {
+        RT_NULL,
+        RT_NULL,
+        RT_NULL,
+        RT_NULL,
+        RT_NULL,
+        swm_rtc_control};
+#endif
+
+static void swm_rtc_init(void)
+{
+    RTC_InitStructure rtc_initstruct;
+
+    rtc_initstruct.Year = 2020;
+    rtc_initstruct.Month = 6;
+    rtc_initstruct.Date = 8;
+    rtc_initstruct.Hour = 12;
+    rtc_initstruct.Minute = 0;
+    rtc_initstruct.Second = 0;
+    rtc_initstruct.SecondIEn = 0;
+    rtc_initstruct.MinuteIEn = 0;
+    RTC_Init(RTC, &rtc_initstruct);
+    RTC_Start(RTC);
+}
+
+static rt_err_t rt_hw_rtc_register(rt_device_t rtc_device, const char *name, rt_uint32_t flag)
+{
+    RT_ASSERT(rtc_device != RT_NULL);
+
+    swm_rtc_init();
+
+#ifdef RT_USING_DEVICE_OPS
+    rtc_device->ops = &swm_rtc_ops;
+#else
+    rtc_device->init = RT_NULL;
+    rtc_device->open = RT_NULL;
+    rtc_device->close = RT_NULL;
+    rtc_device->read = RT_NULL;
+    rtc_device->write = RT_NULL;
+    rtc_device->control = swm_rtc_control;
+#endif
+    rtc_device->type = RT_Device_Class_RTC;
+    rtc_device->rx_indicate = RT_NULL;
+    rtc_device->tx_complete = RT_NULL;
+    rtc_device->user_data = RT_NULL;
+
+    /* register a character device */
+    return rt_device_register(rtc_device, name, flag);
+}
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t result;
+    result = rt_hw_rtc_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
+    if (result != RT_EOK)
+    {
+        LOG_E("rtc register err code: %d", result);
+        return result;
+    }
+    LOG_D("rtc init success");
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+
+#endif /* BSP_USING_RTC */
+#endif /* RT_USING_RTC */
--- a/bsp/swm320/drivers/drv_rtc.h
+++ b/bsp/swm320/drivers/drv_rtc.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_RTC_H__
+#define __DRV_RTC_H__
+
+#include "board.h"
+
+int rt_hw_rtc_init(void);
+
+#endif /* __DRV_RTC_H__ */
--- a/bsp/swm320/drivers/drv_sdio.c
+++ b/bsp/swm320/drivers/drv_sdio.c
--- a/bsp/swm320/drivers/drv_sdio.h
+++ b/bsp/swm320/drivers/drv_sdio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-10     lik          first version
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include "board.h"
+
+#define SDIO_BUFF_SIZE 4096
+#define SDIO_ALIGN_LEN 4
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ (30000000)
+#endif
+
+struct sdio_pkg
+{
+    struct rt_mmcsd_cmd *cmd;
+    void *buff;
+    rt_uint32_t flag;
+};
+
+typedef rt_err_t (*sdio_txconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size);
+typedef rt_err_t (*sdio_rxconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size);
+typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *hw_sdio);
+
+struct swm_sdio_des
+{
+    SDIO_TypeDef *hw_sdio;
+    sdio_txconfig txconfig;
+    sdio_rxconfig rxconfig;
+    sdio_clk_get clk_get;
+};
+
+#endif /* __DRV_SDIO_H__ */
--- a/bsp/swm320/drivers/drv_soft_i2c.c
+++ b/bsp/swm320/drivers/drv_soft_i2c.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          rewrite
+ */
+
+#include "drv_soft_i2c.h"
+
+#ifdef RT_USING_I2C
+#ifdef BSP_USING_I2C
+
+/***************************************************************
+*!!!!!!!!!!!!!!!!!!!!!!!!!!!!NOTICE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+*In order to use swm drv_soft_i2c,you need to commented out
+line 114 (SDA_H(ops);) and line 167 (SDA_H(ops);) in i2c-bit-ops.c
+At the same time, add one line (SDA_L(ops);)after line 154 (SCL_L(ops);)
+in i2c-bit-ops.c
+***************************************************************/
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.i2c"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
+#error "Please define at least one BSP_USING_I2Cx"
+/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+static const struct swm_soft_i2c_cfg soft_i2c_cfg[] =
+    {
+#ifdef BSP_USING_I2C0
+        I2C0_BUS_CFG,
+#endif
+#ifdef BSP_USING_I2C1
+        I2C1_BUS_CFG,
+#endif
+};
+
+static struct swm_i2c i2c_drv[sizeof(soft_i2c_cfg) / sizeof(soft_i2c_cfg[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param swm i2c dirver class.
+ */
+static void swm_i2c_gpio_init(struct swm_i2c *i2c)
+{
+    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)i2c->ops.data;
+
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param swm config class.
+ * @param The sda pin state.
+ */
+static void swm_set_sda(void *data, rt_int32_t state)
+{
+    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+    if (state)
+    {
+        rt_pin_write(cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->sda, PIN_LOW);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param swm config class.
+ * @param The scl pin state.
+ */
+static void swm_set_scl(void *data, rt_int32_t state)
+{
+    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    if (state)
+    {
+        rt_pin_write(cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->scl, PIN_LOW);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t swm_get_sda(void *data)
+{
+    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(cfg->sda, PIN_MODE_INPUT_PULLUP);
+    return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t swm_get_scl(void *data)
+{
+    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(cfg->scl, PIN_MODE_INPUT_PULLUP);
+    return rt_pin_read(cfg->scl);
+}
+
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void swm_udelay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+static const struct rt_i2c_bit_ops swm_bit_ops =
+    {
+        .data = RT_NULL,
+        .set_sda = swm_set_sda,
+        .set_scl = swm_set_scl,
+        .get_sda = swm_get_sda,
+        .get_scl = swm_get_scl,
+        .udelay = swm_udelay,
+        .delay_us = 1,
+        .timeout = 100};
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+    rt_err_t result;
+
+    for (int i = 0; i < sizeof(i2c_drv) / sizeof(struct swm_i2c); i++)
+    {
+        i2c_drv[i].ops = swm_bit_ops;
+        i2c_drv[i].ops.data = (void *)&soft_i2c_cfg[i];
+        i2c_drv[i].i2c2_bus.priv = &i2c_drv[i].ops;
+        swm_i2c_gpio_init(&i2c_drv[i]);
+        result = rt_i2c_bit_add_bus(&i2c_drv[i].i2c2_bus, soft_i2c_cfg[i].name);
+        RT_ASSERT(result == RT_EOK);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              soft_i2c_cfg[i].name,
+              soft_i2c_cfg[i].scl,
+              soft_i2c_cfg[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+#endif /* BSP_USING_I2C */
+#endif /* RT_USING_I2C */
--- a/bsp/swm320/drivers/drv_soft_i2c.h
+++ b/bsp/swm320/drivers/drv_soft_i2c.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_SOFT_I2C_H__
+#define __DRV_SOFT_I2C_H__
+
+#include "board.h"
+
+/* swm config class */
+struct swm_soft_i2c_cfg
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *name;
+};
+/* swm i2c dirver class */
+struct swm_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C0
+#define I2C0_BUS_CFG             \
+    {                            \
+        .scl = BSP_I2C0_SCL_PIN, \
+        .sda = BSP_I2C0_SDA_PIN, \
+        .name = "i2c0",          \
+    }
+#endif
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CFG             \
+    {                            \
+        .scl = BSP_I2C1_SCL_PIN, \
+        .sda = BSP_I2C1_SDA_PIN, \
+        .name = "i2c1",          \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif /* __DRV_SOFT_I2C_H__ */
--- a/bsp/swm320/drivers/drv_spi.c
+++ b/bsp/swm320/drivers/drv_spi.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_spi.h"
+
+#ifdef RT_USING_SPI
+#ifdef BSP_USING_SPI
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.spi"
+#include <drv_log.h>
+
+static struct swm_spi_cfg spi_cfg[] =
+    {
+#ifdef BSP_USING_SPI0
+        SPI0_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_SPI1
+        SPI1_BUS_CONFIG,
+#endif
+};
+
+static struct swm_spi spi_bus_drv[sizeof(spi_cfg) / sizeof(spi_cfg[0])] = {0};
+
+static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuration *configure)
+{
+    RT_ASSERT(spi_drv != RT_NULL);
+    RT_ASSERT(configure != RT_NULL);
+
+    struct swm_spi_cfg *cfg = spi_drv->cfg;
+
+    if (configure->mode & RT_SPI_SLAVE)
+    {
+        cfg->spi_initstruct.Master = 0;
+    }
+    else
+    {
+        cfg->spi_initstruct.Master = 1;
+    }
+
+    if (configure->mode & RT_SPI_3WIRE)
+    {
+        return RT_EINVAL;
+    }
+
+    if (configure->data_width == 8)
+    {
+        cfg->spi_initstruct.WordSize = 8;
+    }
+    else if (configure->data_width == 16)
+    {
+        cfg->spi_initstruct.WordSize = 16;
+    }
+    else
+    {
+        return RT_EIO;
+    }
+
+    if (configure->mode & RT_SPI_CPHA)
+    {
+        cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE;
+    }
+    else
+    {
+        cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE;
+    }
+
+    if (configure->mode & RT_SPI_CPOL)
+    {
+        cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL;
+    }
+    else
+    {
+        cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL;
+    }
+
+    if (configure->max_hz >= SystemCoreClock / 4)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4;
+    }
+    else if (configure->max_hz >= SystemCoreClock / 8)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8;
+    }
+    else if (configure->max_hz >= SystemCoreClock / 16)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16;
+    }
+    else if (configure->max_hz >= SystemCoreClock / 32)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32;
+    }
+    else if (configure->max_hz >= SystemCoreClock / 64)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64;
+    }
+    else if (configure->max_hz >= SystemCoreClock / 128)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128;
+    }
+    else if (configure->max_hz >= SystemCoreClock / 256)
+    {
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256;
+    }
+    else
+    {
+        /*  min prescaler 512 */
+        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512;
+    }
+
+    SPI_Init(cfg->SPIx, &(cfg->spi_initstruct));
+    SPI_Open(cfg->SPIx);
+    LOG_D("%s init done", cfg->name);
+    return RT_EOK;
+}
+
+#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
+#define SPISEND_1(reg, ptr, datalen)       \
+    do                                     \
+    {                                      \
+        if (datalen == 8)                  \
+        {                                  \
+            (reg) = *(rt_uint8_t *)(ptr);  \
+        }                                  \
+        else                               \
+        {                                  \
+            (reg) = *(rt_uint16_t *)(ptr); \
+        }                                  \
+    } while (0)
+#define SPIRECV_1(reg, ptr, datalen)      \
+    do                                    \
+    {                                     \
+        if (datalen == 8)                 \
+        {                                 \
+            *(rt_uint8_t *)(ptr) = (reg); \
+        }                                 \
+        else                              \
+        {                                 \
+            *(rt_uint16_t *)(ptr) = reg;  \
+        }                                 \
+    } while (0)
+
+static rt_err_t spitxrx1b(struct swm_spi *spi_drv, void *rcvb, const void *sndb)
+{
+    rt_uint32_t padrcv = 0;
+    rt_uint32_t padsnd = 0xFF;
+    if (!rcvb && !sndb)
+    {
+        return RT_ERROR;
+    }
+    if (!rcvb)
+    {
+        rcvb = &padrcv;
+    }
+    if (!sndb)
+    {
+        sndb = &padsnd;
+    }
+    while (SPI_IsTXFull(spi_drv->cfg->SPIx))
+        ;
+    SPISEND_1(spi_drv->cfg->SPIx->DATA, sndb, spi_drv->cfg->spi_initstruct.WordSize);
+    while (SPI_IsRXEmpty(spi_drv->cfg->SPIx))
+        ;
+    SPIRECV_1(spi_drv->cfg->SPIx->DATA, rcvb, spi_drv->cfg->spi_initstruct.WordSize);
+    return RT_EOK;
+}
+
+static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    rt_err_t res;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+
+    struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus);
+    struct swm_spi_cfg *cfg = spi_drv->cfg;
+    struct swm_spi_cs *cs = device->parent.user_data;
+
+    if (message->cs_take)
+    {
+        GPIO_ClrBit(cs->GPIOx, cs->gpio_pin);
+    }
+
+    LOG_D("%s transfer prepare and start", cfg->name);
+    LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
+          cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length);
+
+    const rt_uint8_t *sndb = message->send_buf;
+    rt_uint8_t *rcvb = message->recv_buf;
+    rt_int32_t length = message->length;
+
+    while (length)
+    {
+        res = spitxrx1b(spi_drv, rcvb, sndb);
+        if (rcvb)
+        {
+            rcvb += SPISTEP(cfg->spi_initstruct.WordSize);
+        }
+        if (sndb)
+        {
+            sndb += SPISTEP(cfg->spi_initstruct.WordSize);
+        }
+        if (res != RT_EOK)
+        {
+            break;
+        }
+        length--;
+    }
+    /* Wait until Busy flag is reset before disabling SPI */
+    while (!SPI_IsTXEmpty(cfg->SPIx) && !SPI_IsRXEmpty(cfg->SPIx))
+        ;
+    if (message->cs_release)
+    {
+        GPIO_SetBit(cs->GPIOx, cs->gpio_pin);
+    }
+    return message->length - length;
+}
+
+static rt_err_t swm_spi_configure(struct rt_spi_device *device,
+                                  struct rt_spi_configuration *configure)
+{
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configure != RT_NULL);
+
+    struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus);
+    spi_drv->configure = configure;
+
+    return swm_spi_init(spi_drv, configure);
+}
+const static struct rt_spi_ops swm_spi_ops =
+    {
+        .configure = swm_spi_configure,
+        .xfer = swm_spi_xfer,
+};
+
+//cannot be used before completion init
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint32_t cs_gpio_pin)
+{
+    RT_ASSERT(bus_name != RT_NULL);
+    RT_ASSERT(device_name != RT_NULL);
+
+    rt_err_t result;
+    struct rt_spi_device *spi_device;
+    struct swm_spi_cs *cs_pin;
+
+    GPIO_Init(cs_gpiox, cs_gpio_pin, 1, 0, 0);
+    GPIO_SetBit(cs_gpiox, cs_gpio_pin);
+
+    spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    cs_pin = (struct swm_spi_cs *)rt_malloc(sizeof(struct swm_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+    cs_pin->GPIOx = cs_gpiox;
+    cs_pin->gpio_pin = cs_gpio_pin;
+
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+    if (result != RT_EOK)
+    {
+        LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
+    }
+    RT_ASSERT(result == RT_EOK);
+    LOG_D("%s attach to %s done", device_name, bus_name);
+    return result;
+}
+
+int rt_hw_spi_init(void)
+{
+    rt_err_t result;
+
+#ifdef BSP_USING_SPI0
+    PORT_Init(PORTA, PIN9, FUNMUX1_SPI0_SCLK, 0);
+    PORT_Init(PORTA, PIN10, FUNMUX0_SPI0_MOSI, 0);
+    PORT_Init(PORTA, PIN11, FUNMUX1_SPI0_MISO, 1);
+#endif //BSP_USING_SPI0
+
+#ifdef BSP_USING_SPI1
+    PORT_Init(PORTC, PIN7, FUNMUX1_SPI1_SCLK, 0);
+    PORT_Init(PORTC, PIN6, FUNMUX0_SPI1_MOSI, 0);
+    PORT_Init(PORTC, PIN5, FUNMUX1_SPI1_MISO, 1);
+#endif //BSP_USING_SPI1
+    for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++)
+    {
+        spi_bus_drv[i].cfg = &spi_cfg[i];
+        spi_bus_drv[i].spi_bus.parent.user_data = &spi_cfg[i];
+        result = rt_spi_bus_register(&spi_bus_drv[i].spi_bus, spi_cfg[i].name, &swm_spi_ops);
+        RT_ASSERT(result == RT_EOK);
+
+        LOG_D("%s bus init done", spi_config[i].bus_name);
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif /* BSP_USING_SPI */
+#endif /* RT_USING_SPI */
--- a/bsp/swm320/drivers/drv_spi.h
+++ b/bsp/swm320/drivers/drv_spi.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include "board.h"
+
+struct swm_spi_cs
+{
+    GPIO_TypeDef *GPIOx;
+    uint32_t gpio_pin;
+};
+
+struct swm_spi_cfg
+{
+    const char *name;
+    SPI_TypeDef *SPIx;
+    SPI_InitStructure spi_initstruct;
+};
+
+/* swm spi dirver class */
+struct swm_spi
+{
+    struct swm_spi_cfg *cfg;
+    struct rt_spi_configuration *configure;
+    struct rt_spi_bus spi_bus;
+};
+
+#ifdef BSP_USING_SPI0
+#ifndef SPI0_BUS_CONFIG
+#define SPI0_BUS_CONFIG                               \
+    {                                                 \
+        .name = "spi0",                               \
+        .SPIx = SPI0,                                 \
+        .spi_initstruct.clkDiv = SPI_CLKDIV_32,       \
+        .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
+        .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
+        .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL,   \
+        .spi_initstruct.WordSize = 8,                 \
+        .spi_initstruct.Master = 1,                   \
+        .spi_initstruct.RXHFullIEn = 0,               \
+        .spi_initstruct.TXEmptyIEn = 0,               \
+        .spi_initstruct.TXCompleteIEn = 0,            \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                               \
+    {                                                 \
+        .name = "spi1",                               \
+        .SPIx = SPI1,                                 \
+        .spi_initstruct.clkDiv = SPI_CLKDIV_32,       \
+        .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
+        .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
+        .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL,   \
+        .spi_initstruct.WordSize = 8,                 \
+        .spi_initstruct.Master = 1,                   \
+        .spi_initstruct.RXHFullIEn = 0,               \
+        .spi_initstruct.TXEmptyIEn = 0,               \
+        .spi_initstruct.TXCompleteIEn = 0,            \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+//cannot be used before completion init
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *GPIOx, uint32_t n);
+int rt_hw_spi_init(void);
+
+#endif /* __DRV_SPI_H__ */
--- a/bsp/swm320/drivers/drv_sram.c
+++ b/bsp/swm320/drivers/drv_sram.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          rewrite
+ */
+
+#include "drv_sram.h"
+
+#ifdef BSP_USING_EXT_SRAM
+
+#define DRV_DEBUG
+#define LOG_TAG "drv.ext_sram"
+#include <drv_log.h>
+
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+static struct rt_memheap system_heap;
+#endif
+
+static int rt_hw_sram_init(void)
+{
+    SRAM_InitStructure SRAM_InitStruct;
+
+    PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23
+    PORT->PORTP_SEL1 = 0xAAAA;
+
+    PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0
+    PORT->PORTM_INEN = 0xFFFF;
+
+    PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN,PM17 => WEN,PM18 => NORFL_CSN,PM19 => SDRAM_CSN,PM20 => SRAM_CSN,PM21 => SDRAM_CKE
+
+    SRAM_InitStruct.ClkDiv = SRAM_CLKDIV_8;
+    SRAM_InitStruct.DataWidth = SRAM_DATAWIDTH_16;
+    SRAM_Init(&SRAM_InitStruct);
+
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+    /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
+    rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, EXT_SRAM_SIZE);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_sram_init);
+
+#endif /* BSP_USING_EXT_SRAM */
--- a/bsp/swm320/drivers/drv_sram.h
+++ b/bsp/swm320/drivers/drv_sram.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef DRV_SRAM_H__
+#define DRV_SRAM_H__
+
+#include "board.h"
+
+#define EXT_SRAM_BASE SRAMM_BASE
+#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE
+#define EXT_SRAM_BEGIN EXT_SRAM_BASE
+#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE)
+
+int rt_hw_sram_init(void);
+
+#endif
--- a/bsp/swm320/drivers/drv_uart.c
+++ b/bsp/swm320/drivers/drv_uart.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_uart.h"
+
+#ifdef RT_USING_SERIAL
+#ifdef BSP_USING_UART
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.uart"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
+    !defined(BSP_USING_UART3)
+#error "Please define at least one BSP_USING_UARTx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+};
+
+static struct swm_uart_cfg uart_cfg[] =
+    {
+#ifdef BSP_USING_UART0
+        UART0_CFG,
+#endif
+#ifdef BSP_USING_UART1
+        UART1_CFG,
+#endif
+#ifdef BSP_USING_UART2
+        UART2_CFG,
+#endif
+#ifdef BSP_USING_UART3
+        UART3_CFG,
+#endif
+};
+
+static struct swm_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0};
+
+static rt_err_t swm_uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure)
+{
+    struct swm_uart_cfg *cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    RT_ASSERT(configure != RT_NULL);
+    cfg = serial_device->parent.user_data;
+
+    cfg->uart_initstruct.Baudrate = configure->baud_rate;
+    switch (configure->data_bits)
+    {
+    case DATA_BITS_8:
+        cfg->uart_initstruct.DataBits = UART_DATA_8BIT;
+        break;
+    case DATA_BITS_9:
+        cfg->uart_initstruct.DataBits = UART_DATA_9BIT;
+        break;
+    default:
+        cfg->uart_initstruct.DataBits = UART_DATA_8BIT;
+        break;
+    }
+    switch (configure->stop_bits)
+    {
+    case STOP_BITS_1:
+        cfg->uart_initstruct.StopBits = UART_STOP_1BIT;
+        break;
+    case STOP_BITS_2:
+        cfg->uart_initstruct.StopBits = UART_STOP_2BIT;
+        break;
+    default:
+        cfg->uart_initstruct.StopBits = UART_STOP_1BIT;
+        break;
+    }
+    switch (configure->parity)
+    {
+    case PARITY_NONE:
+        cfg->uart_initstruct.Parity = UART_PARITY_NONE;
+        break;
+    case PARITY_ODD:
+        cfg->uart_initstruct.Parity = UART_PARITY_ODD;
+        break;
+    case PARITY_EVEN:
+        cfg->uart_initstruct.Parity = UART_PARITY_EVEN;
+        break;
+    default:
+        cfg->uart_initstruct.Parity = UART_PARITY_NONE;
+        break;
+    }
+    switch ((uint32_t)cfg->UARTx)
+    {
+    case ((uint32_t)UART0):
+        PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1);
+        PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0);
+        break;
+    case ((uint32_t)UART1):
+        PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1);
+        PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0);
+        break;
+    case ((uint32_t)UART2):
+        PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1);
+        PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0);
+        break;
+    case ((uint32_t)UART3):
+        PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1);
+        PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0);
+        break;
+    default:
+        break;
+    }
+    UART_Init(cfg->UARTx, &(cfg->uart_initstruct));
+    UART_Open(cfg->UARTx);
+    return RT_EOK;
+}
+
+static rt_err_t swm_uart_control(struct rt_serial_device *serial_device, int cmd, void *arg)
+{
+    struct swm_uart_cfg *cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    cfg = serial_device->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(cfg->irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(cfg->irq);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int swm_uart_putc(struct rt_serial_device *serial_device, char c)
+{
+    struct swm_uart_cfg *cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    cfg = serial_device->parent.user_data;
+
+    while (UART_IsTXFIFOFull(cfg->UARTx))
+        ;
+    UART_WriteByte(cfg->UARTx, c);
+    while (UART_IsTXBusy(cfg->UARTx))
+        ;
+    return 1;
+}
+
+static int swm_uart_getc(struct rt_serial_device *serial_device)
+{
+    int ch;
+    struct swm_uart_cfg *cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    cfg = serial_device->parent.user_data;
+
+    ch = -1;
+    if (UART_IsRXFIFOEmpty(cfg->UARTx) == 0)
+    {
+        UART_ReadByte(cfg->UARTx, (uint32_t *)&ch);
+    }
+    return ch;
+}
+
+static const struct rt_uart_ops swm_uart_ops =
+    {
+        .configure = swm_uart_init,
+        .control = swm_uart_control,
+        .putc = swm_uart_putc,
+        .getc = swm_uart_getc,
+        .dma_transmit = RT_NULL};
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void rt_hw_uart_isr(struct rt_serial_device *serial_device)
+{
+    struct swm_uart_cfg *cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    cfg = serial_device->parent.user_data;
+
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (UART_INTRXThresholdStat(cfg->UARTx) || UART_INTTimeoutStat(cfg->UARTx))
+    {
+        rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND);
+    }
+}
+
+#if defined(BSP_USING_UART0)
+void UART0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+void UART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void UART2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void UART3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+int rt_hw_uart_init(void)
+{
+    struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT;
+    int i = 0;
+    rt_err_t result = RT_EOK;
+
+    for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++)
+    {
+        uart_drv[i].cfg = &uart_cfg[i];
+        uart_drv[i].serial_device.ops = &swm_uart_ops;
+        uart_drv[i].serial_device.config = cfg;
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name,
+                                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif /* BSP_USING_UART */
+#endif /* RT_USING_SERIAL */
--- a/bsp/swm320/drivers/drv_uart.h
+++ b/bsp/swm320/drivers/drv_uart.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include "board.h"
+
+/* swm config class */
+struct swm_uart_cfg
+{
+    const char *name;
+    UART_TypeDef *UARTx;
+    IRQn_Type irq;
+    UART_InitStructure uart_initstruct;
+};
+
+/* swm uart dirver class */
+struct swm_uart
+{
+    struct swm_uart_cfg *cfg;
+    struct rt_serial_device serial_device;
+};
+
+#ifdef BSP_USING_UART0
+#ifndef UART0_CFG
+#define UART0_CFG                                   \
+    {                                               \
+        .name = "uart0",                            \
+        .UARTx = UART0,                             \
+        .irq = UART0_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART0_CFG */
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+#ifndef UART1_CFG
+#define UART1_CFG                                   \
+    {                                               \
+        .name = "uart1",                            \
+        .UARTx = UART1,                             \
+        .irq = UART1_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART1_CFG */
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+#ifndef UART2_CFG
+#define UART2_CFG                                   \
+    {                                               \
+        .name = "uart2",                            \
+        .UARTx = UART2,                             \
+        .irq = UART2_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART2_CFG */
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+#ifndef UART3_CFG
+#define UART3_CFG                                   \
+    {                                               \
+        .name = "uart3",                            \
+        .UARTx = UART3,                             \
+        .irq = UART3_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART3_CFG */
+#endif /* BSP_USING_UART3 */
+
+int rt_hw_serial_init(void);
+
+#endif /* __DRV_UART_H__ */
--- a/bsp/swm320/drivers/drv_wdt.c
+++ b/bsp/swm320/drivers/drv_wdt.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_wdt.h"
+
+#ifdef RT_USING_WDT
+#ifdef BSP_USING_WDT
+//#define DRV_DEBUG
+#define LOG_TAG "drv.wdt"
+#include <drv_log.h>
+
+static struct swm_wdt_cfg wdt_cfg =
+    {
+        .name = "wdt",
+        .WDTx = WDT,
+};
+
+static struct swm_wdt wdt_drv;
+
+static rt_err_t swm_wdt_init(rt_watchdog_t *wdt_device)
+{
+    return RT_EOK;
+}
+
+static rt_err_t swm_wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg)
+{
+    struct swm_wdt_cfg *cfg;
+    RT_ASSERT(wdt_device != RT_NULL);
+    cfg = wdt_device->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        WDT_Feed(cfg->WDTx);
+        break;
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        WDT_Init(cfg->WDTx, (SystemCoreClock * (*(rt_uint32_t *)arg)), WDT_MODE_RESET);
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        *(rt_uint32_t *)arg = (cfg->WDTx->LOAD) / SystemCoreClock;
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        *(rt_uint32_t *)arg = WDT_GetValue(cfg->WDTx) / SystemCoreClock;
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        WDT_Start(cfg->WDTx);
+        break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+        WDT_Stop(cfg->WDTx);
+        break;
+    default:
+        LOG_W("This command is not supported.");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_watchdog_ops swm_wdt_ops =
+    {
+        swm_wdt_init,
+        swm_wdt_control};
+
+int rt_hw_wdt_init(void)
+{
+    wdt_drv.cfg = &wdt_cfg;
+    wdt_drv.wdt_device.ops = &swm_wdt_ops;
+
+    if (rt_hw_watchdog_register(&wdt_drv.wdt_device, wdt_drv.cfg->name, RT_DEVICE_FLAG_RDWR, wdt_drv.cfg) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+    LOG_D("wdt device register success.");
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_wdt_init);
+
+#endif /* BSP_USING_WDT */
+#endif /* RT_USING_WDT */
--- a/bsp/swm320/drivers/drv_wdt.h
+++ b/bsp/swm320/drivers/drv_wdt.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_WDT_H__
+#define __DRV_WDT_H__
+
+#include "board.h"
+
+struct swm_wdt_cfg
+{
+    const char *name;
+    WDT_TypeDef *WDTx;
+};
+
+struct swm_wdt
+{
+    struct swm_wdt_cfg *cfg;
+    struct rt_watchdog_device wdt_device;
+};
+
+int rt_hw_wdt_init(void);
+
+#endif /* __DRV_WDT_H__ */
--- a/bsp/swm320/drivers/linker_scripts/link.icf
+++ b/bsp/swm320/drivers/linker_scripts/link.icf
@@ -0,0 +1,62 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x2001FFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__     = 0x1000;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__       = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region EROM_region   =   mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]
+                              | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__]
+                              | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with alignment = 8, size = __ICFEDIT_size_heap__       { };
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in IROM_region  { readonly };
+place in EROM_region  { readonly section application_specific_ro };
+place in IRAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };
+place in ERAM_region  { readwrite section application_specific_rw };
--- a/bsp/swm320/drivers/linker_scripts/link.lds
+++ b/bsp/swm320/drivers/linker_scripts/link.lds
@@ -0,0 +1,71 @@
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+	ROM   (arx) : ORIGIN = 0x00000000,    LENGTH = 0x00080000 /* 512k */
+    RAM   (arw) : ORIGIN = 0x20000000,    LENGTH = 0x00020000 /* 128k */
+}
+
+/* Define output sections */
+SECTIONS
+{
+    . = ORIGIN(ROM);
+    .text :
+    {
+        KEEP(*(.isr_vector))
+
+        *(.text)
+        *(.text*)
+        *(.rodata*)
+    } > ROM
+
+    . = ALIGN(4);
+    __data_load__ = LOADADDR(.data);
+
+    . = ALIGN(4);
+    .data :
+    {
+        __data_start__ = .;
+	    
+        *(.data)
+        *(.data*)
+
+        . = ALIGN(4);
+        __data_end__ = .;
+    } > RAM AT> ROM
+
+    . = ALIGN(4);
+    .bss :
+    {
+        __bss_start__ = .;
+
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+    . = ALIGN(4);
+
+    .heap :
+    {
+        end = .;
+        __HeapBase = .;
+
+        *(.heap)
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols.
+     * It is only used for linker to calculate size of stack sections */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    __StackTop   = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- a/bsp/swm320/drivers/linker_scripts/link.sct
+++ b/bsp/swm320/drivers/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
--- a/bsp/swm320/keilkill.bat
+++ b/bsp/swm320/keilkill.bat
@@ -0,0 +1,37 @@
+del *.bak /s
+del *.ddk /s
+del *.edk /s
+del *.lst /s
+::del *.lnp /s
+del *.mpf /s
+del *.mpj /s
+del *.obj /s
+del *.omf /s
+::del *.opt /s  ::不允许删除JLINK的设置
+del *.plg /s
+del *.rpt /s
+del *.tmp /s
+::del *.__i /s
+::del *._ia /s
+del *.crf /s
+del *.o /s
+del *.d /s
+del *.axf /s
+del *.tra /s
+del *.dep /s           
+::del JLinkLog.txt /s
+
+del *.iex /s
+del *.htm /s
+::del *.sct /s
+del *.map /s
+
+del *.whsj2 /s
+del *.SYNWIT_Lik /s
+del *.whsj2 /s
+del *.scvd /s
+
+rmdir /s/q .git
+rmdir /s/q .vscode
+
+exit
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/arm_math.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/arm_math.h
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm3.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm3.h
--- a/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm4.h
+++ b/bsp/swm320/libraries/CMSIS/CoreSupport/core_cm4.h
--- a/Show More
+++ b/Show More