[bsp][renesas]Add cortex-r52 rzt2m adaptation

2026-02-06 09:02:20 +08:00 · 2024-04-11 08:47:53 +08:00
parent 6fc3a0864d
commit 0afc067894
161 changed files with 119492 additions and 6 deletions
--- a/.github/workflows/bsp_buildings.yml
+++ b/.github/workflows/bsp_buildings.yml
@@ -222,6 +222,7 @@ jobs:
                - "renesas/ra8m1-ek"
                - "renesas/ra8d1-ek"
                - "renesas/ra8d1-vision-board"
+                - "renesas/rzt2m_rsk"
                - "frdm-k64f"
                - "xplorer4330/M4"
         -  RTT_BSP: "gd32_n32_apm32"   
--- a/bsp/renesas/README.md
+++ b/bsp/renesas/README.md
@@ -19,6 +19,7 @@ RA 系列 BSP 目前支持情况如下表所示：
 | [ra8m1-ek](ra8m1-ek)                     | Renesas 官方 EK-RA8M1 开发板                     |
 | [ra8d1-ek](ra8d1-ek)                     | Renesas 官方 EK-RA8D1 开发板                     |
 | [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 |
+| [rzt2m_rsk](rzt2m_rsk)                   | Renesas 官方 RSK-RZT2M 开发板                    |

 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

--- a/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
+++ b/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
@@ -141,6 +141,20 @@ extern "C"

 #endif /* SOC_SERIES_R7FA8M85 */

+#ifdef SOC_SERIES_R9A07G0
+#include "rzt/uart_config.h"
+#include "rzt/timer_config.h"
+
+#ifdef BSP_USING_PWM
+#include "rzt/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_ADC
+#include "rzt/adc_config.h"
+#endif
+
+#endif /* SOC_SERIES_R9A07G0 */
+
 #ifdef __cplusplus
 }
 #endif
--- a/bsp/renesas/libraries/HAL_Drivers/config/rzt/adc_config.h
+++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/adc_config.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+
+struct rt_adc_dev
+{
+    struct rt_adc_ops ops;
+    struct rt_adc_device adc_device;
+};
+
+struct ra_adc_map
+{
+    const char *device_name;
+    const adc_cfg_t *g_cfg;
+    const adc_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
--- a/bsp/renesas/libraries/HAL_Drivers/config/rzt/pwm_config.h
+++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/pwm_config.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-26     KevinXu           first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */
--- a/bsp/renesas/libraries/HAL_Drivers/config/rzt/timer_config.h
+++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/timer_config.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-09-04     Rbb666       first version
+ */
+
+#ifndef __TIMER_CONFIG_H__
+#define __TIMER_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define PLCKD_PRESCALER_MAX_SELECT     8
+
+/* RSK-RZN2L: Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64) */
+#define PLCKD_PRESCALER_400M           (BSP_PRV_PCLKGPTL_FREQ_400_MHZ)
+#define PLCKD_PRESCALER_200M           (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 2)
+#define PLCKD_PRESCALER_100M           (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 4)
+#define PLCKD_PRESCALER_50M            (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 8)
+#define PLCKD_PRESCALER_25M            (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 16)
+#define PLCKD_PRESCALER_12_5M          (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 32)
+#define PLCKD_PRESCALER_6_25M          (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 64)
+#define PLCKD_PRESCALER_3_125M         (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 128)
+#define PLCKD_PRESCALER_1_5625M        (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 256)
+
+#ifndef TMR_DEV_INFO_CONFIG
+#define TMR_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 400000000,                   \
+        .minfreq = 1562500,                     \
+        .maxcnt  = 0XFFFFFFFF,                  \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+enum
+{
+#ifdef BSP_USING_TIM0
+    BSP_TIMER0_INDEX,
+#endif
+#ifdef BSP_USING_TIM1
+    BSP_TIMER1_INDEX,
+#endif
+    BSP_TIMERS_NUM
+};
+
+#define TIMER_DRV_INITIALIZER(num)      \
+    {                                   \
+        .name = "timer" #num,           \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_CONFIG_H__ */
--- a/bsp/renesas/libraries/HAL_Drivers/config/rzt/uart_config.h
+++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/uart_config.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .p_api_ctrl = &g_uart0_ctrl,                                \
+        .p_cfg = &g_uart0_cfg,                                      \
+    }
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .p_api_ctrl = &g_uart1_ctrl,                                \
+        .p_cfg = &g_uart1_cfg,                                      \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .p_api_ctrl = &g_uart2_ctrl,                                \
+        .p_cfg = &g_uart2_cfg,                                      \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .p_api_ctrl = &g_uart3_ctrl,                                \
+        .p_cfg = &g_uart3_cfg,                                      \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .p_api_ctrl = &g_uart4_ctrl,                                \
+        .p_cfg = &g_uart4_cfg,                                      \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .p_api_ctrl = &g_uart5_ctrl,                                \
+        .p_cfg = &g_uart5_cfg,                                      \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .p_api_ctrl = &g_uart6_ctrl,                                \
+        .p_cfg = &g_uart6_cfg,                                      \
+    }
+#endif /* UART6_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .p_api_ctrl = &g_uart7_ctrl,                                \
+        .p_cfg = &g_uart7_cfg,                                      \
+    }
+#endif /* UART7_CONFIG */
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG                                                \
+    {                                                               \
+        .name = "uart8",                                            \
+        .p_api_ctrl = &g_uart8_ctrl,                                \
+        .p_cfg = &g_uart8_cfg,                                      \
+    }
+#endif /* UART8_CONFIG */
+#endif /* BSP_USING_UART8 */
+
+#if defined(BSP_USING_UART9)
+#ifndef UART9_CONFIG
+#define UART9_CONFIG                                                \
+    {                                                               \
+        .name = "uart9",                                            \
+        .p_api_ctrl = &g_uart9_ctrl,                                \
+        .p_cfg = &g_uart9_cfg,                                      \
+    }
+#endif /* UART9_CONFIG */
+#endif /* BSP_USING_UART9 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/renesas/libraries/HAL_Drivers/drv_common.c
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_common.c
@@ -24,11 +24,22 @@
    #endif
 #endif

+#ifdef SOC_SERIES_R9A07G0
+#include "gicv3.h"
+static uint64_t rtt_timer_delay;
+extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+static void SysTimerInterrupt(void);
+#endif
+
 #ifdef RT_USING_FINSH
 #include <finsh.h>
 static void reboot(uint8_t argc, char **argv)
 {
+#ifdef SOC_SERIES_R9A07G0
+    return;
+#else
    NVIC_SystemReset();
+#endif
 }
 MSH_CMD_EXPORT(reboot, Reboot System);
 #endif /* RT_USING_FINSH */
@@ -36,8 +47,12 @@ MSH_CMD_EXPORT(reboot, Reboot System);
 /* SysTick configuration */
 void rt_hw_systick_init(void)
 {
+#ifdef SOC_SERIES_R9A07G0
+    SysTimerInterrupt();
+#else
    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
    NVIC_SetPriority(SysTick_IRQn, 0xFF);
+#endif
 }

 /**
@@ -49,6 +64,10 @@ void SysTick_Handler(void)
    /* enter interrupt */
    rt_interrupt_enter();

+#ifdef SOC_SERIES_R9A07G0
+    __set_CNTP_CVAL(__get_CNTP_CVAL() + rtt_timer_delay);
+#endif
+
    rt_tick_increase();

    /* leave interrupt */
@@ -78,6 +97,7 @@ void _Error_Handler(char *s, int num)
 */
 void rt_hw_us_delay(rt_uint32_t us)
 {
+#ifdef ARCH_ARM_CORTEX_M
    rt_uint32_t ticks;
    rt_uint32_t told, tnow, tcnt = 0;
    rt_uint32_t reload = SysTick->LOAD;
@@ -104,13 +124,50 @@ void rt_hw_us_delay(rt_uint32_t us)
            }
        }
    }
+#endif
 }

+#ifdef SOC_SERIES_R9A07G0
+static void SysTimerInterrupt(void)
+{
+    uint64_t tempCNTPCT = __get_CNTPCT();
+
+    /* Wait for counter supply */
+    while (__get_CNTPCT() == tempCNTPCT)
+    {
+        R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
+    }
+
+    /* generic timer initialize */
+    /* set interrupt handler */
+    g_sgi_ppi_vector_table[(int32_t) BSP_VECTOR_NUM_OFFSET +
+                           NonSecurePhysicalTimerInt] = SysTick_Handler;
+
+    rtt_timer_delay = R_GSC->CNTFID0 / RT_TICK_PER_SECOND;
+
+    /* set timer expiration from current counter value */
+    __set_CNTP_CVAL(__get_CNTPCT() + rtt_timer_delay);
+
+    /* configure CNTP_CTL to enable timer interrupts */
+    __set_CNTP_CTL(1);
+    R_BSP_IrqCfgEnable(NonSecurePhysicalTimerInt, (int32_t) BSP_VECTOR_NUM_OFFSET +
+                           NonSecurePhysicalTimerInt, RT_NULL);
+}
+#endif
+
 /**
- * This function will initial STM32 board.
+ * This function will initial board.
 */
 rt_weak void rt_hw_board_init()
 {
+#ifdef SOC_SERIES_R9A07G0
+    /* initialize hardware interrupt */
+    rt_uint32_t redis_gic_base = platform_get_gic_dist_base();
+    rt_int32_t cpu_id = rt_hw_cpu_id();
+    arm_gic_redist_address_set(0, redis_gic_base, cpu_id);
+    rt_hw_interrupt_init();
+#endif
+
    rt_hw_systick_init();

    /* Heap initialization */
@@ -140,7 +197,11 @@ rt_weak void rt_hw_board_init()
 }

 FSP_CPP_HEADER
+#ifdef SOC_SERIES_R9A07G0
+void R_BSP_WarmStart(bsp_warm_start_event_t event) BSP_PLACE_IN_SECTION(".warm_start");
+#else
 void R_BSP_WarmStart(bsp_warm_start_event_t event);
+#endif
 FSP_CPP_FOOTER

 /*******************************************************************************************************************//**
--- a/bsp/renesas/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -118,7 +118,7 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
    switch (mode)
    {
    case PIN_MODE_OUTPUT:
-        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_OUTPUT);
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_OUTPUT);
        if (err != FSP_SUCCESS)
        {
            LOG_E("PIN_MODE_OUTPUT configuration failed");
@@ -127,7 +127,7 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
        break;

    case PIN_MODE_INPUT:
-        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_INPUT);
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_INPUT);
        if (err != FSP_SUCCESS)
        {
            LOG_E("PIN_MODE_INPUT configuration failed");
@@ -136,7 +136,7 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
        break;

    case PIN_MODE_OUTPUT_OD:
-        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, IOPORT_CFG_NMOS_ENABLE);
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, IOPORT_CFG_NMOS_ENABLE);
        if (err != FSP_SUCCESS)
        {
            LOG_E("PIN_MODE_OUTPUT_OD configuration failed");
@@ -156,7 +156,11 @@ static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
    }

    R_BSP_PinAccessEnable();
+#ifdef SOC_SERIES_R9A07G0
+    R_IOPORT_PinWrite(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, (bsp_io_level_t)level);
+#else
    R_BSP_PinWrite(pin, level);
+#endif
    R_BSP_PinAccessDisable();
 }

@@ -166,7 +170,13 @@ static rt_ssize_t ra_pin_read(rt_device_t dev, rt_base_t pin)
    {
        return -RT_EINVAL;
    }
+#ifdef SOC_SERIES_R9A07G0
+    bsp_io_level_t io_level;
+    R_IOPORT_PinRead(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, &io_level);
+    return io_level;
+#else
    return R_BSP_PinRead(pin);
+#endif
 }

 static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
--- a/bsp/renesas/libraries/HAL_Drivers/drv_gpio.h
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_gpio.h
@@ -23,8 +23,13 @@
 extern "C" {
 #endif

+#ifdef SOC_SERIES_R9A07G0
+#define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_0
+#define RA_MAX_PIN_VALUE    BSP_IO_PORT_24_PIN_7
+#else
 #define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_00
 #define RA_MAX_PIN_VALUE    BSP_IO_PORT_11_PIN_15
+#endif

 #ifdef R_ICU_H
 struct ra_pin_irq_map
--- a/bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c
@@ -7,6 +7,7 @@
 * Date           Author            Notes
 * 2021-07-29     KyleChan          first version
 * 2023-10-17     Rbb666            add ra8 adapt
+ * 2024-03-11    Wangyuqiang        add rzt2m adapt
 */

 #include <drv_usart_v2.h>
@@ -244,7 +245,7 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c)

    p_ctrl->p_reg->TDR = c;

-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0)
    while ((p_ctrl->p_reg->CSR_b.TEND) == 0);
 #else
    while ((p_ctrl->p_reg->SSR_b.TEND) == 0);
--- a/bsp/renesas/libraries/Kconfig
+++ b/bsp/renesas/libraries/Kconfig
@@ -38,3 +38,9 @@ config SOC_SERIES_R7FA8M85
    select ARCH_ARM_CORTEX_M85
    select SOC_FAMILY_RENESAS
    default n
+
+config SOC_SERIES_R9A07G0
+    bool
+    select ARCH_ARM_CORTEX_R52
+    select SOC_FAMILY_RENESAS
+    default n
--- a/bsp/renesas/rzt2m_rsk/.api_xml
+++ b/bsp/renesas/rzt2m_rsk/.api_xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<ddscApi/>
--- a/bsp/renesas/rzt2m_rsk/.config
+++ b/bsp/renesas/rzt2m_rsk/.config
--- a/bsp/renesas/rzt2m_rsk/.secure_azone
+++ b/bsp/renesas/rzt2m_rsk/.secure_azone
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<azone>
+    <rzone name="R9A07G075M24GBG.rzone"/>
+    <partition>
+        <peripheral name="SCI0" group="SCI" security=""/>
+        <peripheral name="ICU">
+            <slot name="IRQ288" secure="false"/>
+            <slot name="IRQ289" secure="false"/>
+            <slot name="IRQ290" secure="false"/>
+            <slot name="IRQ291" secure="false"/>
+        </peripheral>
+    </partition>
+</azone>
--- a/bsp/renesas/rzt2m_rsk/.secure_xml
+++ b/bsp/renesas/rzt2m_rsk/.secure_xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.rzt2mrsk.xspi0_x1"/>
+    <option key="CPU" value="RZT2M"/>
+    <option key="Core" value="CR52_0"/>
+    <option key="#TargetName#" value="R9A07G075M24GBG"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-r52"/>
+    <option key="#DeviceCommand#" value="R9A07G075M24_CR52_0"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R9A07G075M24GBG.pincfg"/>
+    <option key="#FSPVersion#" value="2.0.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzt2m_rsk##xspi0_x1_boot"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="iar.arm.toolchain"/>
+  </generalSettings>
+  <raBspConfiguration/>
+  <raClockConfiguration>
+    <node id="board.clock.main.freq" option="board.clock.main.freq.25m"/>
+    <node id="board.clock.loco.enable" option="board.clock.loco.enable.enabled"/>
+    <node id="board.clock.pll0.display" option="board.clock.pll0.display.value"/>
+    <node id="board.clock.pll1" option="board.clock.pll1.initial"/>
+    <node id="board.clock.pll1.display" option="board.clock.pll1.display.value"/>
+    <node id="board.clock.ethernet.source" option="board.clock.ethernet.source.pll1"/>
+    <node id="board.clock.reference.display" option="board.clock.reference.display.value"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.240k"/>
+    <node id="board.clock.clma0.enable" option="board.clock.clma0.enable.enabled"/>
+    <node id="board.clock.clma0.error" option="board.clock.clma0.error.not_mask"/>
+    <node id="board.clock.clma3.error" option="board.clock.clma3.error.not_mask"/>
+    <node id="board.clock.clma1.error" option="board.clock.clma1.error.mask"/>
+    <node id="board.clock.clma3.enable" option="board.clock.clma3.enable.enabled"/>
+    <node id="board.clock.clma1.enable" option="board.clock.clma1.enable.enabled"/>
+    <node id="board.clock.clma2.enable" option="board.clock.clma2.enable.enabled"/>
+    <node id="board.clock.clma0.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma1.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma2.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.clma3.cmpl" mul="1" option="_edit"/>
+    <node id="board.clock.alternative.source" option="board.clock.alternative.source.loco"/>
+    <node id="board.clock.clma0.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma1.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma2.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.clma3.cmph" mul="1023" option="_edit"/>
+    <node id="board.clock.iclk.freq" option="board.clock.iclk.freq.200m"/>
+    <node id="board.clock.sci0asyncclk.sel" option="board.clock.sci0asyncclk.sel.1"/>
+    <node id="board.clock.sci1asyncclk.sel" option="board.clock.sci1asyncclk.sel.1"/>
+    <node id="board.clock.sci2asyncclk.sel" option="board.clock.sci2asyncclk.sel.1"/>
+    <node id="board.clock.sci3asyncclk.sel" option="board.clock.sci3asyncclk.sel.1"/>
+    <node id="board.clock.sci4asyncclk.sel" option="board.clock.sci4asyncclk.sel.1"/>
+    <node id="board.clock.sci5asyncclk.sel" option="board.clock.sci5asyncclk.sel.1"/>
+    <node id="board.clock.spi0asyncclk.sel" option="board.clock.spi0asyncclk.sel.1"/>
+    <node id="board.clock.spi1asyncclk.sel" option="board.clock.spi1asyncclk.sel.1"/>
+    <node id="board.clock.spi2asyncclk.sel" option="board.clock.spi2asyncclk.sel.1"/>
+    <node id="board.clock.spi3asyncclk.sel" option="board.clock.spi3asyncclk.sel.1"/>
+    <node id="board.clock.pclkgptl.display" option="board.clock.pclkgptl.display.value"/>
+    <node id="board.clock.pclkh.display" option="board.clock.pclkh.display.value"/>
+    <node id="board.clock.pclkm.display" option="board.clock.pclkm.display.value"/>
+    <node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
+    <node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
+    <node id="board.clock.cpu0clk.mul" option="board.clock.cpu0clk.mul.1"/>
+    <node id="board.clock.cpu0clk.display" option="board.clock.cpu0clk.display.value"/>
+    <node id="board.clock.cpu1clk.mul" option="board.clock.cpu1clk.mul.1"/>
+    <node id="board.clock.cpu1clk.display" option="board.clock.cpu1clk.display.value"/>
+    <node id="board.clock.ckio.div" option="board.clock.ckio.div.4"/>
+    <node id="board.clock.ckio.display" option="board.clock.ckio.display.value"/>
+    <node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
+    <node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
+    <node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
+    <node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
+  </raClockConfiguration>
+  <raPinConfiguration>
+    <pincfg active="true" name="" symbol="">
+      <configSetting altId="canfd0.canrx0.p05_2" configurationId="canfd0.canrx0"/>
+      <configSetting altId="canfd0.cantx0.p05_3" configurationId="canfd0.cantx0"/>
+      <configSetting altId="ether_eth0.eth0_refclk.p09_1" configurationId="ether_eth0.eth0_refclk"/>
+      <configSetting altId="ether_eth0.eth0_rxclk_ref_clk_rxc.p08_6" configurationId="ether_eth0.eth0_rxclk_ref_clk_rxc"/>
+      <configSetting altId="ether_eth0.eth0_rxd0.p10_1" configurationId="ether_eth0.eth0_rxd0"/>
+      <configSetting altId="ether_eth0.eth0_rxd1.p10_2" configurationId="ether_eth0.eth0_rxd1"/>
+      <configSetting altId="ether_eth0.eth0_rxd2.p10_3" configurationId="ether_eth0.eth0_rxd2"/>
+      <configSetting altId="ether_eth0.eth0_rxd3.p08_4" configurationId="ether_eth0.eth0_rxd3"/>
+      <configSetting altId="ether_eth0.eth0_rxdv_crsdv_rxctl.p08_5" configurationId="ether_eth0.eth0_rxdv_crsdv_rxctl"/>
+      <configSetting altId="ether_eth0.eth0_txclk_txc.p09_7" configurationId="ether_eth0.eth0_txclk_txc"/>
+      <configSetting altId="ether_eth0.eth0_txd0.p09_6" configurationId="ether_eth0.eth0_txd0"/>
+      <configSetting altId="ether_eth0.eth0_txd1.p09_5" configurationId="ether_eth0.eth0_txd1"/>
+      <configSetting altId="ether_eth0.eth0_txd2.p09_4" configurationId="ether_eth0.eth0_txd2"/>
+      <configSetting altId="ether_eth0.eth0_txd3.p09_3" configurationId="ether_eth0.eth0_txd3"/>
+      <configSetting altId="ether_eth0.eth0_txen_txctl.p10_0" configurationId="ether_eth0.eth0_txen_txctl"/>
+      <configSetting altId="ether_eth1.eth1_refclk.p06_1" configurationId="ether_eth1.eth1_refclk"/>
+      <configSetting altId="ether_eth1.eth1_rxclk_ref_clk_rxc.p07_3" configurationId="ether_eth1.eth1_rxclk_ref_clk_rxc"/>
+      <configSetting altId="ether_eth1.eth1_rxd0.p06_6" configurationId="ether_eth1.eth1_rxd0"/>
+      <configSetting altId="ether_eth1.eth1_rxd1.p06_7" configurationId="ether_eth1.eth1_rxd1"/>
+      <configSetting altId="ether_eth1.eth1_rxd2.p07_0" configurationId="ether_eth1.eth1_rxd2"/>
+      <configSetting altId="ether_eth1.eth1_rxd3.p07_1" configurationId="ether_eth1.eth1_rxd3"/>
+      <configSetting altId="ether_eth1.eth1_rxdv_crsdv_rxctl.p07_2" configurationId="ether_eth1.eth1_rxdv_crsdv_rxctl"/>
+      <configSetting altId="ether_eth1.eth1_txclk_txc.p06_4" configurationId="ether_eth1.eth1_txclk_txc"/>
+      <configSetting altId="ether_eth1.eth1_txd0.p06_3" configurationId="ether_eth1.eth1_txd0"/>
+      <configSetting altId="ether_eth1.eth1_txd1.p06_2" configurationId="ether_eth1.eth1_txd1"/>
+      <configSetting altId="ether_eth1.eth1_txd2.p05_7" configurationId="ether_eth1.eth1_txd2"/>
+      <configSetting altId="ether_eth1.eth1_txd3.p06_0" configurationId="ether_eth1.eth1_txd3"/>
+      <configSetting altId="ether_eth1.eth1_txen_txctl.p06_5" configurationId="ether_eth1.eth1_txen_txctl"/>
+      <configSetting altId="ether_eth2.eth2_refclk.p00_3" configurationId="ether_eth2.eth2_refclk"/>
+      <configSetting altId="ether_eth2.eth2_rxclk_ref_clk_rxc.p24_1" configurationId="ether_eth2.eth2_rxclk_ref_clk_rxc"/>
+      <configSetting altId="ether_eth2.eth2_rxd0.p23_7" configurationId="ether_eth2.eth2_rxd0"/>
+      <configSetting altId="ether_eth2.eth2_rxd1.p24_0" configurationId="ether_eth2.eth2_rxd1"/>
+      <configSetting altId="ether_eth2.eth2_rxd2.p24_2" configurationId="ether_eth2.eth2_rxd2"/>
+      <configSetting altId="ether_eth2.eth2_rxd3.p00_0" configurationId="ether_eth2.eth2_rxd3"/>
+      <configSetting altId="ether_eth2.eth2_rxdv_crsdv_rxctl.p00_1" configurationId="ether_eth2.eth2_rxdv_crsdv_rxctl"/>
+      <configSetting altId="ether_eth2.eth2_txclk_txc.p00_6" configurationId="ether_eth2.eth2_txclk_txc"/>
+      <configSetting altId="ether_eth2.eth2_txd0.p01_5" configurationId="ether_eth2.eth2_txd0"/>
+      <configSetting altId="ether_eth2.eth2_txd1.p01_4" configurationId="ether_eth2.eth2_txd1"/>
+      <configSetting altId="ether_eth2.eth2_txd2.p01_3" configurationId="ether_eth2.eth2_txd2"/>
+      <configSetting altId="ether_eth2.eth2_txd3.p01_2" configurationId="ether_eth2.eth2_txd3"/>
+      <configSetting altId="ether_eth2.eth2_txen_txctl.p00_2" configurationId="ether_eth2.eth2_txen_txctl"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink0.p10_4" configurationId="ether_ethsw.ethsw_phylink0"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink1.p05_5" configurationId="ether_ethsw.ethsw_phylink1"/>
+      <configSetting altId="ether_ethsw.ethsw_phylink2.p00_5" configurationId="ether_ethsw.ethsw_phylink2"/>
+      <configSetting altId="ether_gmac.gmac_mdc.p08_7" configurationId="ether_gmac.gmac_mdc"/>
+      <configSetting altId="ether_gmac.gmac_mdio.p09_0" configurationId="ether_gmac.gmac_mdio"/>
+      <configSetting altId="iic0.iic_scl0.p20_5" configurationId="iic0.iic_scl0"/>
+      <configSetting altId="iic0.iic_sda0.p20_6" configurationId="iic0.iic_sda0"/>
+      <configSetting altId="iic1.iic_scl1.p22_6" configurationId="iic1.iic_scl1"/>
+      <configSetting altId="iic1.iic_sda1.p22_7" configurationId="iic1.iic_sda1"/>
+      <configSetting altId="irq.irq9.p17_2" configurationId="irq.irq9"/>
+      <configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk" isUsedByDriver="true"/>
+      <configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi" isUsedByDriver="true"/>
+      <configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo" isUsedByDriver="true"/>
+      <configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio" isUsedByDriver="true"/>
+      <configSetting altId="p04_2.input" configurationId="p04_2"/>
+      <configSetting altId="p08_2.output.low" configurationId="p08_2"/>
+      <configSetting altId="p10_5.input" configurationId="p10_5"/>
+      <configSetting altId="p10_6.input" configurationId="p10_6"/>
+      <configSetting altId="p11_0.input" configurationId="p11_0"/>
+      <configSetting altId="p11_3.input" configurationId="p11_3"/>
+      <configSetting altId="p11_4.input" configurationId="p11_4"/>
+      <configSetting altId="p11_6.input" configurationId="p11_6"/>
+      <configSetting altId="p13_2.input" configurationId="p13_2"/>
+      <configSetting altId="p13_7.input" configurationId="p13_7"/>
+      <configSetting altId="p14_1.input" configurationId="p14_1"/>
+      <configSetting altId="p14_5.input" configurationId="p14_5"/>
+      <configSetting altId="p16_3.input" configurationId="p16_3"/>
+      <configSetting altId="p18_7.output.toinput.low" configurationId="p18_7"/>
+      <configSetting altId="p19_3.output.low" configurationId="p19_3"/>
+      <configSetting altId="p19_4.output.low" configurationId="p19_4"/>
+      <configSetting altId="p19_6.output.low" configurationId="p19_6"/>
+      <configSetting altId="p19_7.output.low" configurationId="p19_7"/>
+      <configSetting altId="p20_0.output.low" configurationId="p20_0"/>
+      <configSetting altId="p20_1.output.low" configurationId="p20_1"/>
+      <configSetting altId="p20_2.output.low" configurationId="p20_2"/>
+      <configSetting altId="p20_3.output.low" configurationId="p20_3"/>
+      <configSetting altId="p20_4.output.low" configurationId="p20_4"/>
+      <configSetting altId="p20_7.output.low" configurationId="p20_7"/>
+      <configSetting altId="p21_0.output.low" configurationId="p21_0"/>
+      <configSetting altId="p23_4.output.low" configurationId="p23_4"/>
+      <configSetting altId="p23_6.output.high" configurationId="p23_6"/>
+      <configSetting altId="sci0.rxd_miso0.p16_6" configurationId="sci0.rxd_miso0" isUsedByDriver="true"/>
+      <configSetting altId="sci0.txd_mosi0.p16_5" configurationId="sci0.txd_mosi0" isUsedByDriver="true"/>
+      <configSetting altId="sci3.rxd_miso3.p17_7" configurationId="sci3.rxd_miso3"/>
+      <configSetting altId="sci3.txd_mosi3.p18_0" configurationId="sci3.txd_mosi3"/>
+      <configSetting altId="spi2.spi_miso2.p18_6" configurationId="spi2.spi_miso2"/>
+      <configSetting altId="spi2.spi_mosi2.p18_5" configurationId="spi2.spi_mosi2"/>
+      <configSetting altId="spi2.spi_rspck2.p18_4" configurationId="spi2.spi_rspck2"/>
+      <configSetting altId="trace.traceclk.p22_2" configurationId="trace.traceclk" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracectl.p22_1" configurationId="trace.tracectl" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata0.p21_1" configurationId="trace.tracedata0" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata1.p21_2" configurationId="trace.tracedata1" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata2.p21_3" configurationId="trace.tracedata2" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata3.p21_4" configurationId="trace.tracedata3" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata4.p21_5" configurationId="trace.tracedata4" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata5.p03_7" configurationId="trace.tracedata5" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata6.p21_7" configurationId="trace.tracedata6" isUsedByDriver="true"/>
+      <configSetting altId="trace.tracedata7.p22_0" configurationId="trace.tracedata7" isUsedByDriver="true"/>
+      <configSetting altId="usb_hs.usb_ovrcur.p17_5" configurationId="usb_hs.usb_ovrcur"/>
+      <configSetting altId="usb_hs.usb_vbusen.p19_0" configurationId="usb_hs.usb_vbusen"/>
+      <configSetting altId="usb_hs.usb_vbusin.p07_4" configurationId="usb_hs.usb_vbusin"/>
+      <configSetting altId="xspi0.xspi0_ckp.p14_6" configurationId="xspi0.xspi0_ckp"/>
+      <configSetting altId="xspi0.xspi0_cs0_hash.p15_7" configurationId="xspi0.xspi0_cs0_hash"/>
+      <configSetting altId="xspi0.xspi0_ds.p14_4" configurationId="xspi0.xspi0_ds"/>
+      <configSetting altId="xspi0.xspi0_ecs0_hash.p14_2" configurationId="xspi0.xspi0_ecs0_hash"/>
+      <configSetting altId="xspi0.xspi0_io0.p14_7" configurationId="xspi0.xspi0_io0"/>
+      <configSetting altId="xspi0.xspi0_io1.p15_0" configurationId="xspi0.xspi0_io1"/>
+      <configSetting altId="xspi0.xspi0_io2.p15_1" configurationId="xspi0.xspi0_io2"/>
+      <configSetting altId="xspi0.xspi0_io3.p15_2" configurationId="xspi0.xspi0_io3"/>
+      <configSetting altId="xspi0.xspi0_io4.p15_3" configurationId="xspi0.xspi0_io4"/>
+      <configSetting altId="xspi0.xspi0_io5.p15_4" configurationId="xspi0.xspi0_io5"/>
+      <configSetting altId="xspi0.xspi0_io6.p15_5" configurationId="xspi0.xspi0_io6"/>
+      <configSetting altId="xspi0.xspi0_io7.p15_6" configurationId="xspi0.xspi0_io7"/>
+      <configSetting altId="xspi0.xspi0_reset0_hash.p16_1" configurationId="xspi0.xspi0_reset0_hash"/>
+      <configSetting altId="xspi1.xspi1_ckn.p13_4" configurationId="xspi1.xspi1_ckn"/>
+      <configSetting altId="xspi1.xspi1_ckp.p13_3" configurationId="xspi1.xspi1_ckp"/>
+      <configSetting altId="xspi1.xspi1_cs0_hash.p13_1" configurationId="xspi1.xspi1_cs0_hash"/>
+      <configSetting altId="xspi1.xspi1_ds.p11_7" configurationId="xspi1.xspi1_ds"/>
+      <configSetting altId="xspi1.xspi1_io0.p13_0" configurationId="xspi1.xspi1_io0"/>
+      <configSetting altId="xspi1.xspi1_io1.p12_7" configurationId="xspi1.xspi1_io1"/>
+      <configSetting altId="xspi1.xspi1_io2.p12_6" configurationId="xspi1.xspi1_io2"/>
+      <configSetting altId="xspi1.xspi1_io3.p12_5" configurationId="xspi1.xspi1_io3"/>
+      <configSetting altId="xspi1.xspi1_io4.p12_3" configurationId="xspi1.xspi1_io4"/>
+      <configSetting altId="xspi1.xspi1_io5.p12_2" configurationId="xspi1.xspi1_io5"/>
+      <configSetting altId="xspi1.xspi1_io6.p12_1" configurationId="xspi1.xspi1_io6"/>
+      <configSetting altId="xspi1.xspi1_io7.p12_0" configurationId="xspi1.xspi1_io7"/>
+      <configSetting altId="xspi1.xspi1_reset0_hash.p12_4" configurationId="xspi1.xspi1_reset0_hash"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>
--- a/bsp/renesas/rzt2m_rsk/.settings/standalone.prefs
+++ b/bsp/renesas/rzt2m_rsk/.settings/standalone.prefs
--- a/bsp/renesas/rzt2m_rsk/Kconfig
+++ b/bsp/renesas/rzt2m_rsk/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+# you can change the RTT_ROOT default "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config ENV_DIR
+    string
+    option env="ENV_ROOT"
+    default "/"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "$BSP_DIR/board/Kconfig"
--- a/bsp/renesas/rzt2m_rsk/README.md
+++ b/bsp/renesas/rzt2m_rsk/README.md
@@ -0,0 +1,166 @@
+# Renesas RSK-RZT2M Development Board BSP Guide
+
+**English** | [**中文**](./README_zh.md)
+
+## Introduction
+
+This document provides the Board Support Package (BSP) guide for the Renesas RSK-RZT2M development board. By reading the quick start section, developers can quickly get started with this BSP and run RT-Thread on the development board.
+
+The main contents are as follows:
+
+- Board introduction
+- BSP quick start guide
+
+## Board Introduction
+
+The RSK-RZT2M MCU evaluation board, based on the Renesas RZ/T2M development, is designed to assist users in evaluating the features of the RA6M4 MCU group and developing embedded system applications through flexible configuration of software packages and IDEs.
+
+The front appearance of the development board is as follows:
+
+![](figures/board.png)
+
+The commonly used **on-board resources** of this development board are as follows:
+
+- MCU: R9A07G075M24GBG, with a maximum operating frequency of 800MHz, dual Arm Cortex®-R52 cores, tightly coupled memory 576KB (with ECC), internal RAM 2 MB (with ECC)
+- Debug interface: On-board J-Link interface
+- Expansion interface: Two PMOD connectors
+
+**More detailed information and tools**
+
+## Peripheral Support
+
+The current support status of peripherals in this BSP is as follows:
+
+| **On-chip Peripheral** | **Support Status** | **Remarks**                          |
+| :--------------------- | :----------------- | :----------------------------------- |
+| UART                   | Supported          | UART0 is the default log output port |
+| GPIO                   | Supported          |                                      |
+| HWIMER                 | Supported          |                                      |
+| I2C                    | Not supported      |                                      |
+| WDT                    | Not supported      |                                      |
+| RTC                    | Not supported      |                                      |
+| ADC                    | Not supported      |                                      |
+| DAC                    | Not supported      |                                      |
+| SPI                    | Not supported      |                                      |
+| FLASH                  | Not supported      |                                      |
+| PWM                    | Not supported      |                                      |
+| CAN                    | Not supported      |                                      |
+| ETH                    | Not supported      |                                      |
+| More to come...        |                    |                                      |
+
+## Usage Guide
+
+The usage guide is divided into the following two sections:
+
+- Quick Start
+
+  This section is prepared for beginners who are new to RT-Thread. Follow simple steps to run the RT-Thread operating system on this development board and see experimental results.
+
+- Advanced Usage
+
+  This section is prepared for developers who need to utilize more development board resources on the RT-Thread operating system. By using the ENV tool to configure the BSP, more on-board resources can be enabled to achieve more advanced functionalities.
+
+### Quick Start
+
+Currently, this BSP only provides an IAR project. Below is an example of how to get the system up and running using [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) development environment.
+
+**Hardware Connection**
+
+Connect the development board to the PC using a USB data cable and use the J-link interface for downloading and debugging programs.
+
+**Compilation and Download**
+
+- Navigate to the bsp directory, open ENV, and use the command `scons --target=iar` to generate an IAR project.
+- Compilation: Double-click the project.eww file to open the IAR project and compile the program.
+- Debugging: Click `Project->Download and Debug` on the top-left navigation bar of IAR to download and start debugging.
+
+**Viewing Execution Results**
+
+After successfully downloading the program, the system will automatically run and print system information.
+
+Connect the corresponding serial port of the development board to the PC, open the terminal tool, and select the corresponding serial port (115200-8-1-N). After resetting the device, you can see the output information from RT-Thread. Enter the help command to view the supported commands in the system.
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.1.0 build Mar 14 2024 18:26:01
+ 2006 - 2024 Copyright by RT-Thread team
+
+Hello RT-Thread!
+==================================================
+This is a iar project which mode is ram execution!
+==================================================
+msh >help
+RT-Thread shell commands:
+clear            - clear the terminal screen
+version          - show RT-Thread version information
+list             - list objects
+backtrace        - print backtrace of a thread
+help             - RT-Thread shell help
+ps               - List threads in the system
+free             - Show the memory usage in the system
+pin              - pin [option]
+
+msh >
+```
+
+**Application Entry Function**
+
+The entry function of the application layer is in **src\hal_entry.c** under `void hal_entry(void)`. User-written source files can be directly placed in the src directory.
+
+```c
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+    rt_kprintf("==================================================\n");
+    rt_kprintf("This is a iar project which mode is ram execution!\n");
+    rt_kprintf("==================================================\n");
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+```
+
+### Advanced Usage
+
+**Documentation and Resources**
+
+- [Development Board Official Page](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control#overview)
+- [Development Board Datasheet](https://www.renesas.cn/cn/zh/document/dst/rzt2m-group-datasheet?r=1574901)
+- [Development Board Hardware Manual](https://www.renesas.cn/cn/zh/document/mah/rzt2m-group-users-manual-hardware?r=1574901)
+- [RZ/T2M Easy Download Guide](https://www.renesas.cn/cn/zh/document/gde/rzt2m-easy-download-guide?r=1574901)
+- [Renesas RZ/T2M Group](https://www.renesas.cn/cn/zh/document/fly/renesas-rzt2m-group?r=1574901)
+
+**FSP Configuration**
+
+To modify Renesas BSP peripheral configurations or add new peripheral ports, the Renesas [Flexible Software Package (FSP)](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) configuration tool is required. Please follow the steps below for configuration. For any configuration issues, feel free to ask in the [RT-Thread Community Forum](https://club.rt-thread.org/).
+
+1. [Download Flexible Software Package (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v1.3.0/setup_rznfsp_v1_3_0_rzsc_v2023-07.exe), please use FSP version 1.3.0.
+
+2. Refer to the document [How to import the board support package](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) on how to add the "RSK-RZT2M board support package" to FSP.
+3. Refer to the document: [RA Series Using FSP to Configure Peripheral Drivers](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动).
+
+**ENV Configuration**
+
+- How to use the ENV tool: [RT-Thread env tool user manual](https://www.rt-thread.org/document/site/#/development-tools/env/env)
+
+This BSP only enables the UART1 function by default. If you need to use more advanced features such as components, software packages, etc., you need to configure it using the ENV tool.
+
+The steps are as follows:
+1. Open the env tool under bsp.
+2. Enter the `menuconfig` command to configure the project, save and exit after configuration.
+3. Enter the `pkgs --update` command to update the software packages.
+4. Enter the `scons --target=iar` command to regenerate the project.
+
+## Contact Information
+
+If you have any ideas or suggestions during use, we recommend contacting us through the [RT-Thread Community Forum](https://club.rt-thread.org/).
+
+## Code Contribution
+
+If you are interested in RSK-RZT2M and have some interesting projects to share with everyone, feel free to contribute code to us. You can refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github).
--- a/bsp/renesas/rzt2m_rsk/README_zh.md
+++ b/bsp/renesas/rzt2m_rsk/README_zh.md
@@ -0,0 +1,167 @@
+# 瑞萨 RSK-RZT2M 开发板 BSP 说明
+
+**中文** | [**English**](./README.md)
+
+## 简介
+
+本文档为瑞萨 RSK-RZT2M 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+主要内容如下：
+
+- 开发板介绍
+- BSP 快速上手指南
+
+## 开发板介绍
+
+基于瑞萨 RZ/T2M 开发的 RSK-RZT2M MCU 评估板，通过灵活配置软件包和 IDE，对嵌入系统应用程序进行开发。
+
+开发板正面外观如下图：
+
+![](figures/board.png)
+
+该开发板常用 **板载资源** 如下：
+
+- MPU：R9A07G075M24GBG，最大工作频率 800MHz，双Arm Cortex®-R52 内核，紧密耦合内存 576KB（带 ECC），内部 RAM 2 MB（带 ECC）
+- 调试接口：板载 J-Link 接口
+- 扩展接口：两个 PMOD 连接器
+
+**更多详细资料及工具**
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+| :----------------- | :----------------- | :------------- |
+| UART               | 支持               | UART0 为默认日志输出端口 |
+| GPIO               | 支持               |                |
+| HWIMER                | 支持           |            |
+| IIC                | 不支持           |            |
+| WDT                | 不支持              |                |
+| RTC                | 不支持              |                |
+| ADC                | 不支持              |                |
+| DAC                | 不支持              |                |
+| SPI                | 不支持              |                |
+| FLASH              | 不支持              |                |
+| PWM                | 不支持              |                |
+| CAN                | 不支持              |                |
+| ETH             | 不支持              |                |
+| 持续更新中...      |                    |                |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+- 进阶使用
+
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 目前仅提供 IAR 工程。下面以 [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) 开发环境为例，介绍如何将系统运行起来。
+
+**硬件连接**
+
+使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。
+
+**编译下载**
+
+- 进入 bsp 目录下，打开 ENV 使用命令 `scons --target=iar` 生成 IAR工程。
+- 编译：双击 project.eww 文件，打开 IAR 工程，编译程序。
+- 调试：IAR 左上方导航栏点击 `Project->Download and Debug`下载并启动调试。
+
+
+
+**查看运行结果**
+
+下载程序成功之后，系统会自动运行并打印系统信息。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.1.0 build Mar 14 2024 18:26:01
+ 2006 - 2024 Copyright by RT-Thread team
+
+Hello RT-Thread!
+==================================================
+This is a iar project which mode is ram execution!
+==================================================
+msh >help
+RT-Thread shell commands:
+clear            - clear the terminal screen
+version          - show RT-Thread version information
+list             - list objects
+backtrace        - print backtrace of a thread
+help             - RT-Thread shell help
+ps               - List threads in the system
+free             - Show the memory usage in the system
+pin              - pin [option]
+
+msh >
+```
+
+**应用入口函数**
+
+应用层的入口函数在 **src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
+
+```c
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+    rt_kprintf("==================================================\n");
+    rt_kprintf("This is a iar project which mode is ram execution!\n");
+    rt_kprintf("==================================================\n");
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+```
+
+### 进阶使用
+
+**资料及文档**
+
+- [开发板官网主页](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control#overview)
+- [开发板数据手册](https://www.renesas.cn/cn/zh/document/dst/rzt2m-group-datasheet?r=1574901)
+- [开发板硬件手册](https://www.renesas.cn/cn/zh/document/mah/rzt2m-group-users-manual-hardware?r=1574901)
+- [RZ/T2M Easy Download Guide](https://www.renesas.cn/cn/zh/document/gde/rzt2m-easy-download-guide?r=1574901)
+- [Renesas RZ/T2M Group](https://www.renesas.cn/cn/zh/document/fly/renesas-rzt2m-group?r=1574901)
+
+**FSP 配置**
+
+需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
+
+1. [下载灵活配置软件包 (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v1.3.0/setup_rznfsp_v1_3_0_rzsc_v2023-07.exe)，请使用 FSP 1.3.0 版本
+2. 如何将 **”RSK-RZT2M板级支持包“**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
+3. 请参考文档：[RA系列使用FSP配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)。
+
+**ENV 配置**
+
+- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
+
+此 BSP 默认只开启了 UART1 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
+
+步骤如下：
+1. 在 bsp 下打开 env 工具。
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+3. 输入`pkgs --update`命令更新软件包。
+4. 输入`scons --target=iar` 命令重新生成工程。
+
+## 联系人信息
+
+在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们  [RT-Thread 社区论坛](https://club.rt-thread.org/)
+
+## 贡献代码
+
+如果您对 RSK-RZT2M 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
--- a/bsp/renesas/rzt2m_rsk/SConscript
+++ b/bsp/renesas/rzt2m_rsk/SConscript
@@ -0,0 +1,28 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+CPPPATH = [cwd]
+group = []
+list = os.listdir(cwd)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    group = DefineGroup('', src, depend = [''], CPPPATH = CPPPATH)
+elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
+    if GetOption('target') != 'mdk5':
+        CPPPATH = [cwd]
+        src = Glob('./src/*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')
--- a/bsp/renesas/rzt2m_rsk/SConstruct
+++ b/bsp/renesas/rzt2m_rsk/SConstruct
@@ -0,0 +1,66 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+def startup_check():
+    import subprocess
+    startup_check_path = os.getcwd() + "/../tools/startup_check.py"
+
+    if os.path.exists(startup_check_path):
+        try:
+            subprocess.call(["python", startup_check_path])
+        except:
+            subprocess.call(["python3", startup_check_path])
+
+RegisterPreBuildingAction(startup_check)
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
--- a/bsp/renesas/rzt2m_rsk/board/Kconfig
+++ b/bsp/renesas/rzt2m_rsk/board/Kconfig
@@ -0,0 +1,167 @@
+menu "Hardware Drivers Config"
+
+    config SOC_R9A07G084
+        bool
+        select SOC_SERIES_R9A07G0
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
+        default y
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+        source "../libraries/HAL_Drivers/Kconfig"
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC1
+                    bool "Enable ADC1"
+                    default n
+            endif
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+            select RT_USING_SERIAL
+            select RT_USING_SERIAL_V2
+            if BSP_USING_UART
+
+                menuconfig BSP_USING_UART0
+                    bool "Enable UART0"
+                    default n
+                    if BSP_USING_UART0
+                        config BSP_UART0_RX_USING_DMA
+                            bool "Enable UART0 RX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_TX_USING_DMA
+                            bool "Enable UART0 TX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_RX_BUFSIZE
+                            int "Set UART0 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART0_TX_BUFSIZE
+                            int "Set UART0 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+            endif
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C BUS"
+            default n
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            if BSP_USING_I2C
+                config BSP_USING_HW_I2C
+                    bool "Enable Hardware I2C BUS"
+                    default n
+                if BSP_USING_HW_I2C
+                    config BSP_USING_HW_I2C0
+                        bool "Enable Hardware I2C0 BUS"
+                        default n
+                endif
+                if BSP_USING_HW_I2C
+                    config BSP_USING_HW_I2C1
+                        bool "Enable Hardware I2C1 BUS"
+                        default n
+                endif
+            if !BSP_USING_HW_I2C
+                    menuconfig BSP_USING_I2C1
+                        bool "Enable I2C1 BUS (software simulation)"
+                        default y
+                        if BSP_USING_I2C1
+                            config BSP_I2C1_SCL_PIN
+                                hex "i2c1 scl pin number"
+                                range 0x0000 0x0B0F
+                                default 0x0B03
+                            config BSP_I2C1_SDA_PIN
+                                hex "I2C1 sda pin number"
+                                range 0x0000 0x0B0F
+                                default 0x050E
+                    endif
+                endif
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI 
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
+                    default n
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
+                    default n
+                config BSP_USING_SPI2
+                    bool "Enable SPI2 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_TIM
+	        bool "Enable timer"
+	        default n
+	        select RT_USING_HWTIMER
+	        if BSP_USING_TIM
+	            config BSP_USING_TIM0
+	                bool "Enable TIM0"
+	                default n
+	            config BSP_USING_TIM1
+	                bool "Enable TIM1"
+	                default n
+	        endif
+
+    endmenu
+    
+    menu "Board extended module Drivers"
+         menuconfig BSP_USING_RW007
+                bool "Enable RW007"
+                default n
+                select PKG_USING_RW007
+                select BSP_USING_SPI
+                select BSP_USING_SPI2
+                select RT_USING_MEMPOOL
+                select RW007_NOT_USE_EXAMPLE_DRIVERS
+
+            if BSP_USING_RW007
+                config RA_RW007_SPI_BUS_NAME
+                    string "RW007 BUS NAME"
+                    default "spi2"
+
+                config RA_RW007_CS_PIN
+                    hex "(HEX)CS pin index"
+                    default 0x1207
+
+                config RA_RW007_BOOT0_PIN
+                    hex "(HEX)BOOT0 pin index (same as spi clk pin)"
+                    default 0x1204
+
+                config RA_RW007_BOOT1_PIN
+                    hex "(HEX)BOOT1 pin index (same as spi cs pin)"
+                    default 0x1207
+
+                config RA_RW007_INT_BUSY_PIN
+                    hex "(HEX)INT/BUSY pin index"
+                    default 0x1102
+
+                config RA_RW007_RST_PIN
+                    hex "(HEX)RESET pin index"
+                    default 0x1706
+            endif
+    endmenu
+endmenu
--- a/bsp/renesas/rzt2m_rsk/board/SConscript
+++ b/bsp/renesas/rzt2m_rsk/board/SConscript
@@ -0,0 +1,16 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+src = Glob('*.c')
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
--- a/bsp/renesas/rzt2m_rsk/board/board.h
+++ b/bsp/renesas/rzt2m_rsk/board/board.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-03-11    Wangyuqiang   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtdef.h>
+#include <cp15.h>
+#include <hal_data.h>
+
+#define RZ_SRAM_SIZE    1536 /* The SRAM size of the chip needs to be modified */
+#define RZ_SRAM_END     (0x10000000 + RZ_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RAM_END$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$RAM_END$$ZI$$Base)
+#else
+#define HEAP_BEGIN      (0x10000000)
+#endif
+
+#define HEAP_END        RZ_SRAM_END
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define MAX_HANDLERS    (512)
+#define GIC_IRQ_START   0
+#define GIC_ACK_INTID_MASK  (0x000003FFU)
+/* number of interrupts on board */
+#define ARM_GIC_NR_IRQS     (448)
+/* only one GIC available */
+#define ARM_GIC_MAX_NR      1
+/*  end defined */
+
+#define GICV3_DISTRIBUTOR_BASE_ADDR     (0x100000)
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    rt_uint32_t gic_base;
+
+    __get_cp(15, 1, gic_base, 15, 3, 0);
+    return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/renesas/rzt2m_rsk/board/ports/SConscript
+++ b/bsp/renesas/rzt2m_rsk/board/ports/SConscript
@@ -0,0 +1,16 @@
+import os
+from building import *
+
+objs = []
+src = Glob('*.c')
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
--- a/bsp/renesas/rzt2m_rsk/board/ports/gpio_cfg.h
+++ b/bsp/renesas/rzt2m_rsk/board/ports/gpio_cfg.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2024-03-11    Wangyuqiang   first version
+ */
+
+/* Number of IRQ channels on the device */
+#define RA_IRQ_MAX  16
+
+/* PIN to IRQx table */
+#define PIN2IRQX_TABLE                      \
+{                                           \
+    switch (pin)                            \
+    {                                       \
+    case BSP_IO_PORT_00_PIN_1:             \
+    case BSP_IO_PORT_09_PIN_2:             \
+    case BSP_IO_PORT_18_PIN_3:             \
+        return 0;                           \
+    case BSP_IO_PORT_00_PIN_3:             \
+    case BSP_IO_PORT_07_PIN_4:             \
+    case BSP_IO_PORT_18_PIN_4:             \
+        return 1;                           \
+    case BSP_IO_PORT_01_PIN_2:             \
+        return 2;                           \
+    case BSP_IO_PORT_01_PIN_4:             \
+        return 3;                           \
+    case BSP_IO_PORT_02_PIN_0:             \
+    case BSP_IO_PORT_22_PIN_2:             \
+        return 4;                           \
+    case BSP_IO_PORT_03_PIN_5:             \
+    case BSP_IO_PORT_13_PIN_2:             \
+        return 5;                           \
+    case BSP_IO_PORT_14_PIN_2:             \
+    case BSP_IO_PORT_21_PIN_5:             \
+        return 6;                           \
+    case BSP_IO_PORT_16_PIN_3:             \
+        return 7;                           \
+    case BSP_IO_PORT_03_PIN_6:             \
+    case BSP_IO_PORT_16_PIN_6:             \
+        return 8;                           \
+    case BSP_IO_PORT_03_PIN_7:             \
+    case BSP_IO_PORT_21_PIN_6:             \
+        return 9;                           \
+    case BSP_IO_PORT_04_PIN_4:             \
+    case BSP_IO_PORT_18_PIN_1:             \
+    case BSP_IO_PORT_21_PIN_7:             \
+        return 10;                          \
+    case BSP_IO_PORT_10_PIN_4:             \
+    case BSP_IO_PORT_18_PIN_6:             \
+        return 11;                          \
+    case BSP_IO_PORT_05_PIN_0:             \
+    case BSP_IO_PORT_05_PIN_4:             \
+    case BSP_IO_PORT_05_PIN_6:             \
+        return 12;                          \
+    case BSP_IO_PORT_00_PIN_4:             \
+    case BSP_IO_PORT_00_PIN_7:             \
+    case BSP_IO_PORT_05_PIN_1:             \
+        return 13;                          \
+    case BSP_IO_PORT_02_PIN_2:             \
+    case BSP_IO_PORT_03_PIN_0:             \
+    case BSP_IO_PORT_05_PIN_2:             \
+        return 14;                          \
+    case BSP_IO_PORT_02_PIN_3:             \
+    case BSP_IO_PORT_05_PIN_3:             \
+    case BSP_IO_PORT_22_PIN_0:             \
+        return 15;                          \
+    default  :                              \
+        return -1;                          \
+    }                                       \
+}
--- a/bsp/renesas/rzt2m_rsk/board/ports/wifi/SConscript
+++ b/bsp/renesas/rzt2m_rsk/board/ports/wifi/SConscript
@@ -0,0 +1,22 @@
+
+from building import *
+import rtconfig
+
+cwd = GetCurrentDir()
+
+src = []
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('drv_rw007.c')
+
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc', 'armclang']:
+    LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+    LOCAL_CFLAGS += ' --c99'
+
+group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
--- a/bsp/renesas/rzt2m_rsk/board/ports/wifi/drv_rw007.c
+++ b/bsp/renesas/rzt2m_rsk/board/ports/wifi/drv_rw007.c
@@ -0,0 +1,65 @@
+#include <rtthread.h>
+#include <rtdbg.h>
+#ifdef BSP_USING_RW007
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <spi_wifi_rw007.h>
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    /* Configure IO */
+    rt_pin_mode(RA_RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(RA_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(RA_RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(RA_RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while (!rt_pin_read(RA_RW007_INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200));
+    rt_pin_mode(RA_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    uint32_t cs_pin = RA_RW007_CS_PIN;
+
+    rw007_gpio_init();
+    rt_hw_spi_device_attach(RA_RW007_SPI_BUS_NAME, "wspi", cs_pin);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(RA_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(RA_RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+#endif /* BSP_USING_RW007 */
--- a/bsp/renesas/rzt2m_rsk/buildinfo.ipcf
+++ b/bsp/renesas/rzt2m_rsk/buildinfo.ipcf
@@ -0,0 +1,159 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<iarProjectConnection version="1.8" name="Flex Software">
+    <device>
+        <name>R9A07G075M24_CPU0</name>
+    </device>
+    <includePath>
+        <path>$PROJ_DIR$/rzt/arm/CMSIS_5/CMSIS/Core_R/Include</path>
+        <path>$PROJ_DIR$/rzt/fsp/inc</path>
+        <path>$PROJ_DIR$/rzt/fsp/inc/api</path>
+        <path>$PROJ_DIR$/rzt/fsp/inc/instances</path>
+        <path>$PROJ_DIR$/rzt/fsp/src/bsp/mcu/all/cr</path>
+        <path>$PROJ_DIR$/rzt_cfg/fsp_cfg</path>
+        <path>$PROJ_DIR$/rzt_cfg/fsp_cfg/bsp</path>
+        <path>$PROJ_DIR$/rzt_gen</path>
+        <path>$PROJ_DIR$/src</path>
+        <path>$PROJ_DIR$</path>
+    </includePath>
+    <defines>
+        <define>_RENESAS_RZT_</define>
+        <define>_RZT_CORE=CR52_0</define>
+        <define>_RZT_ORDINAL=1</define>
+    </defines>
+    <asmIncludePath>
+        <path>$PROJ_DIR$/rzt/arm/CMSIS_5/CMSIS/Core_R/Include</path>
+        <path>$PROJ_DIR$/rzt/fsp/inc</path>
+        <path>$PROJ_DIR$/rzt/fsp/inc/api</path>
+        <path>$PROJ_DIR$/rzt/fsp/inc/instances</path>
+        <path>$PROJ_DIR$/rzt/fsp/src/bsp/mcu/all/cr</path>
+        <path>$PROJ_DIR$/rzt_cfg/fsp_cfg</path>
+        <path>$PROJ_DIR$/rzt_cfg/fsp_cfg/bsp</path>
+        <path>$PROJ_DIR$/rzt_gen</path>
+        <path>$PROJ_DIR$/src</path>
+        <path>$PROJ_DIR$</path>
+    </asmIncludePath>
+    <asmDefines>
+        <define>_RENESAS_RZT_</define>
+        <define>_RZT_CORE=CR52_0</define>
+        <define>_RZT_ORDINAL=1</define>
+    </asmDefines>
+    <linkerFile>
+        <override>true</override>
+        <path>$PROJ_DIR$/script/fsp_xspi0_boot.icf</path>
+    </linkerFile>
+    <linkerExtraOptions>
+        <arg>--config_search "$PROJ_DIR$"</arg>
+    </linkerExtraOptions>
+    <programEntryPoint>
+        <symbol>system_init</symbol>
+    </programEntryPoint>
+    <customArgVars>
+        <group name="RA Smart Configurator">
+            <argVar>
+                <name>RASC_EXE_PATH</name>
+                <value>C:\Renesas\rzt\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe</value>
+            </argVar>
+        </group>
+    </customArgVars>
+    <files>
+        <group name="Components">
+            <path>rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h</path>
+            <path>rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h</path>
+            <path>rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h</path>
+            <path>rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h</path>
+            <path>rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h</path>
+            <path>rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h</path>
+            <path>rzt/arm/CMSIS_5/LICENSE.txt</path>
+            <path>rzt/board/rzt2m_rsk/board.h</path>
+            <path>rzt/board/rzt2m_rsk/board_ethernet_phy.h</path>
+            <path>rzt/board/rzt2m_rsk/board_init.c</path>
+            <path>rzt/board/rzt2m_rsk/board_init.h</path>
+            <path>rzt/board/rzt2m_rsk/board_leds.c</path>
+            <path>rzt/board/rzt2m_rsk/board_leds.h</path>
+            <path>rzt/fsp/inc/api/bsp_api.h</path>
+            <path>rzt/fsp/inc/api/r_ioport_api.h</path>
+            <path>rzt/fsp/inc/api/r_transfer_api.h</path>
+            <path>rzt/fsp/inc/api/r_uart_api.h</path>
+            <path>rzt/fsp/inc/fsp_common_api.h</path>
+            <path>rzt/fsp/inc/fsp_features.h</path>
+            <path>rzt/fsp/inc/fsp_version.h</path>
+            <path>rzt/fsp/inc/instances/r_ioport.h</path>
+            <path>rzt/fsp/inc/instances/r_sci_uart.h</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G074.h</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c</path>
+            <path>rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_cache.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_cache.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_clocks.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_clocks.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_common.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_common.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_compiler_support.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_delay.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_delay.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_exceptions.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_io.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_io.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_irq.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_irq.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_mcu_api.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_module_stop.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_register_protection.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_register_protection.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_reset.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_reset.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_sbrk.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_semaphore.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_semaphore.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/bsp_tfu.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h</path>
+            <path>rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c</path>
+            <path>rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h</path>
+            <path>rzt/fsp/src/bsp/mcu/rzt2m/bsp_elc.h</path>
+            <path>rzt/fsp/src/bsp/mcu/rzt2m/bsp_feature.h</path>
+            <path>rzt/fsp/src/bsp/mcu/rzt2m/bsp_irq_sense.c</path>
+            <path>rzt/fsp/src/bsp/mcu/rzt2m/bsp_loader_param.c</path>
+            <path>rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h</path>
+            <path>rzt/fsp/src/bsp/mcu/rzt2m/bsp_override.h</path>
+            <path>rzt/fsp/src/r_ioport/r_ioport.c</path>
+            <path>rzt/fsp/src/r_sci_uart/r_sci_uart.c</path>
+            <path>rzt/SConscript</path>
+        </group>
+        <group name="Build Configuration">
+            <path>rzt_cfg/fsp_cfg/bsp/board_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_memory_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/bsp/bsp_pin_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/r_ioport_cfg.h</path>
+            <path>rzt_cfg/fsp_cfg/r_sci_uart_cfg.h</path>
+            <path>rzt_cfg/SConscript</path>
+        </group>
+        <group name="Generated Data">
+            <path>rzt_gen/bsp_clock_cfg.h</path>
+            <path>rzt_gen/common_data.c</path>
+            <path>rzt_gen/common_data.h</path>
+            <path>rzt_gen/hal_data.c</path>
+            <path>rzt_gen/hal_data.h</path>
+            <path>rzt_gen/main.c</path>
+            <path>rzt_gen/pin_data.c</path>
+            <path>rzt_gen/SConscript</path>
+            <path>rzt_gen/vector_data.c</path>
+            <path>rzt_gen/vector_data.h</path>
+        </group>
+        <group name="Program Entry">
+            <path>src/hal_entry.c</path>
+        </group>
+    </files>
+</iarProjectConnection>
--- a/bsp/renesas/rzt2m_rsk/configuration.xml
+++ b/bsp/renesas/rzt2m_rsk/configuration.xml
--- a/bsp/renesas/rzt2m_rsk/figures/board.png
+++ b/bsp/renesas/rzt2m_rsk/figures/board.png
--- a/bsp/renesas/rzt2m_rsk/memory_regions.icf
+++ b/bsp/renesas/rzt2m_rsk/memory_regions.icf
@@ -0,0 +1,43 @@
+
+            /* generated memory regions file - do not edit */
+                            define symbol ATCM_START = 0x00000000;
+                define symbol ATCM_LENGTH = 0x80000;
+                define symbol BTCM_START = 0x00100000;
+                define symbol BTCM_LENGTH = 0x10000;
+                define symbol SYSTEM_RAM_START = 0x10000000;
+                define symbol SYSTEM_RAM_LENGTH = 0x200000;
+                define symbol SYSTEM_RAM_MIRROR_START = 0x30000000;
+                define symbol SYSTEM_RAM_MIRROR_LENGTH = 0x200000;
+                define symbol xSPI0_CS0_SPACE_MIRROR_START = 0x40000000;
+                define symbol xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol xSPI0_CS1_SPACE_MIRROR_START = 0x44000000;
+                define symbol xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol xSPI1_CS0_SPACE_MIRROR_START = 0x48000000;
+                define symbol xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol xSPI1_CS1_SPACE_MIRROR_START = 0x4C000000;
+                define symbol xSPI1_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol CS0_SPACE_MIRROR_START = 0x50000000;
+                define symbol CS0_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol CS2_SPACE_MIRROR_START = 0x54000000;
+                define symbol CS2_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol CS3_SPACE_MIRROR_START = 0x58000000;
+                define symbol CS3_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol CS5_SPACE_MIRROR_START = 0x5C000000;
+                define symbol CS5_SPACE_MIRROR_LENGTH = 0x4000000;
+                define symbol xSPI0_CS0_SPACE_START = 0x60000000;
+                define symbol xSPI0_CS0_SPACE_LENGTH = 0x4000000;
+                define symbol xSPI0_CS1_SPACE_START = 0x64000000;
+                define symbol xSPI0_CS1_SPACE_LENGTH = 0x4000000;
+                define symbol xSPI1_CS0_SPACE_START = 0x68000000;
+                define symbol xSPI1_CS0_SPACE_LENGTH = 0x4000000;
+                define symbol xSPI1_CS1_SPACE_START = 0x6C000000;
+                define symbol xSPI1_CS1_SPACE_LENGTH = 0x4000000;
+                define symbol CS0_SPACE_START = 0x70000000;
+                define symbol CS0_SPACE_LENGTH = 0x4000000;
+                define symbol CS2_SPACE_START = 0x74000000;
+                define symbol CS2_SPACE_LENGTH = 0x4000000;
+                define symbol CS3_SPACE_START = 0x78000000;
+                define symbol CS3_SPACE_LENGTH = 0x4000000;
+                define symbol CS5_SPACE_START = 0x7C000000;
+                define symbol CS5_SPACE_LENGTH = 0x4000000;
+                define symbol CR52_0 = 1;
--- a/bsp/renesas/rzt2m_rsk/project.custom_argvars
+++ b/bsp/renesas/rzt2m_rsk/project.custom_argvars
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<iarUserArgVars>
+    <group name="RA Smart Configurator" active="true">
+        <variable>
+            <name>RASC_EXE_PATH</name>
+            <value>C:\Renesas\rzt\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe</value>
+        </variable>
+    </group>
+</iarUserArgVars>
--- a/bsp/renesas/rzt2m_rsk/project.ewd
+++ b/bsp/renesas/rzt2m_rsk/project.ewd
--- a/bsp/renesas/rzt2m_rsk/project.ewp
+++ b/bsp/renesas/rzt2m_rsk/project.ewp
--- a/bsp/renesas/rzt2m_rsk/project.ewt
+++ b/bsp/renesas/rzt2m_rsk/project.ewt
--- a/bsp/renesas/rzt2m_rsk/project.eww
+++ b/bsp/renesas/rzt2m_rsk/project.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
--- a/bsp/renesas/rzt2m_rsk/rtconfig.h
+++ b/bsp/renesas/rzt2m_rsk/rtconfig.h
@@ -0,0 +1,274 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 512
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+#define RT_USING_HW_ATOMIC
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_R
+#define ARCH_ARM_CORTEX_R52
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V2
+#define RT_SERIAL_USING_DMA
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Memory protection */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+
+/* Kendryte SDK */
+
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_FAMILY_RENESAS
+#define SOC_SERIES_R9A07G0
+
+/* Hardware Drivers Config */
+
+#define SOC_R9A07G084
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_UART0_RX_BUFSIZE 256
+#define BSP_UART0_TX_BUFSIZE 0
+
+/* Board extended module Drivers */
+
+
+#endif
--- a/bsp/renesas/rzt2m_rsk/rtconfig.py
+++ b/bsp/renesas/rzt2m_rsk/rtconfig.py
@@ -0,0 +1,123 @@
+import os
+import sys
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-r52'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armclang'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'D:/IAR Systems/Embedded Workbench 9.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug' 
+# BUILD = 'release' 
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    NM = PREFIX + 'nm'
+
+    DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=neon-fp-armv8 -munaligned-access -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -funwind-tables'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=arm '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp_xspi0_boot.ld -L script/'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g -Wall'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -Os'
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
+    # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-R52'
+    CFLAGS += ' -e'
+    CFLAGS += ' --arm'
+    CFLAGS += ' --float-abi=hard'
+    CFLAGS += ' --fpu=neon-fp-armv8'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-R52'
+    AFLAGS += ' --arm'
+    AFLAGS += ' --float-abi hard'
+    AFLAGS += ' --fpu neon-fp-armv8'
+    # AFLAGS += ' --unaligned-access'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "script/fsp_xspi0_boot.icf"'
+    LFLAGS += ' --entry Reset_Handler'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
--- a/bsp/renesas/rzt2m_rsk/rzt/SConscript
+++ b/bsp/renesas/rzt2m_rsk/rzt/SConscript
@@ -0,0 +1,28 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+from gcc import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    Return('group')
+elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
+    if GetOption('target') != 'mdk5':
+        src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
+        src += Glob(cwd + '/fsp/src/bsp/mcu/all/cr/*.c')
+        src += Glob(cwd + '/fsp/src/bsp/mcu/r*/*.c')
+        src += Glob(cwd + '/fsp/src/r_*/*.c')
+        src += Glob(cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c')
+        src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
+        src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
+        CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include',
+                            cwd + '/fsp/inc',
+                            cwd + '/fsp/inc/api',
+                            cwd + '/fsp/inc/instances',]
+
+group = DefineGroup('rzt', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h
@@ -0,0 +1,290 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @date     31. August 2021
+ ******************************************************************************/
+/*
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\cmsis_compliler.h"
+ *
+ * Changes:
+ *    - No Changes.
+ */
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @date     31. August 2021
+ ******************************************************************************/
+/*
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\cmsis_version.h"
+ *
+ * Changes:
+ *    - No Changes.
+ */
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h
@@ -0,0 +1,312 @@
+/**************************************************************************//**
+ * @file     core_cr52.h
+ * @brief    CMSIS Cortex-R52 Core Peripheral Access Layer Header File
+ * @date     31. August 2021
+ ******************************************************************************/
+/*
+ * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
+ *
+ * This file is based on the "\CMSIS\Core\Include\core_armv8mml.h"
+ *
+ * Changes:
+ * Renesas Electronics Corporation on 2021-08-31
+ *    - Changed to be related to Cortex-R52 by
+ */
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CR52_H_GENERIC
+#define __CORE_CR52_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_R52
+  @{
+ */
+
+#if defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+      #define __FPU_D32        1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+      #ifndef __ARMVFP_D16__
+        #define __FPU_D32      1U
+      #endif
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+#endif
+
+#include "cmsis_version.h"
+
+/* CMSIS CR52 definitions */
+#define __CR52_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CR52_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CR52_CMSIS_VERSION       ((__CR52_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CR52_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_R                 (52U)                                      /*!< Cortex-R Core                    */
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CR52_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CR52_H_DEPENDANT
+#define __CORE_CR52_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_R52 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_GIC  Generic Interrupt Controller (GIC)
+  \brief      Type definitions for the GIC Registers
+  @{
+*/
+
+ /**
+  \brief  Structure type to access the Generic Interrupt Controller (GIC) for GICD.
+ */
+typedef struct
+{
+  __IOM uint32_t GICD_CTLR;                  /*!< Offset: 0x0000 (R/W)  Distributor Control Register */
+  __IM  uint32_t GICD_TYPER;                 /*!< Offset: 0x0004 (R/ )  Interrupt Controller Type Register */
+  __IM  uint32_t GICD_IIDR;                  /*!< Offset: 0x0008 (R/ )  Distributor Implementer Identification Register */
+        uint32_t RESERVED0[30U];
+  __IOM uint32_t GICD_IGROUPR[30U];          /*!< Offset: 0x0084 (R/W)  Interrupt Group Registers 1 - 30 */
+        uint32_t RESERVED1[2U];
+  __IOM uint32_t GICD_ISENABLER[30U];        /*!< Offset: 0x0104 (R/W)  Interrupt Set-Enable Registers 1 - 30 */
+        uint32_t RESERVED2[2U];
+  __IOM uint32_t GICD_ICENABLER[30U];        /*!< Offset: 0x0184 (R/W)  Interrupt Clear-Enable Registers 1 - 30 */
+        uint32_t RESERVED3[2U];
+  __IOM uint32_t GICD_ISPENDR[30U];          /*!< Offset: 0x0204 (R/W)  Interrupt Set-Pending Registers 1 - 30 */
+        uint32_t RESERVED4[2U];
+  __IOM uint32_t GICD_ICPENDR[30U];          /*!< Offset: 0x0284 (R/W)  Interrupt Clear-Pending Registers 1 - 30 */
+        uint32_t RESERVED5[2U];
+  __IOM uint32_t GICD_ISACTIVER[30U];        /*!< Offset: 0x0304 (R/W)  Interrupt Set-Active Registers 1 - 30 */
+        uint32_t RESERVED6[2U];
+  __IOM uint32_t GICD_ICACTIVER[30U];        /*!< Offset: 0x0384 (R/W)  Interrupt Clear-Active Registers 1 - 30 */
+        uint32_t RESERVED7[9U];
+  __IOM uint32_t GICD_IPRIORITYR[240U];      /*!< Offset: 0x0420 (R/W)  Interrupt Priority Registers 8 - 247 */
+        uint32_t RESERVED8[266U];
+  __IOM uint32_t GICD_ICFGR[60U];            /*!< Offset: 0x0C08 (R/W)  Interrupt Configuration Registers 2 - 61 */
+}  GICD_Type;
+
+ /**
+  \brief  Structure type to access the Generic Interrupt Controller (GIC) for GICR for Control target.
+ */
+typedef struct
+{
+  __IM  uint32_t GICR_CTLR;                  /*!< Offset: 0x0000 (R/ )  Redistributor Control Register */
+  __IM  uint32_t GICR_IIDR;                  /*!< Offset: 0x0004 (R/ )  Redistributor Implementer Identification Register */
+  __IM  uint32_t GICR_TYPER[2];              /*!< Offset: 0x0008 (R/ )  Redistributor Type Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t GICR_WAKER;                 /*!< Offset: 0x0014 (R/W)  Redistributor Wake Register */
+}  GICR_CONTROL_TARGET_Type;
+
+ /**
+  \brief  Structure type to access the Generic Interrupt Controller (GIC) for GICR for SGI and PPI.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[32];
+  __IOM uint32_t GICR_IGROUPR0;              /*!< Offset: 0x0080 (R/W)  Interrupt Group Register 0 */
+        uint32_t RESERVED1[31];
+  __IOM uint32_t GICR_ISENABLER0;            /*!< Offset: 0x0100 (R/W)  Interrupt Set-Enable Register 0 */
+        uint32_t RESERVED2[31];
+  __IOM uint32_t GICR_ICENABLER0;            /*!< Offset: 0x0180 (R/W)  Interrupt Clear-Enable Register 0 */
+        uint32_t RESERVED3[31];
+  __IOM uint32_t GICR_ISPENDR0;              /*!< Offset: 0x0200 (R/W)  Interrupt Set-Pending Register 0 */
+        uint32_t RESERVED4[31];
+  __IOM uint32_t GICR_ICPENDR0;              /*!< Offset: 0x0280 (R/W)  Interrupt Clear-Pending Register 0 */
+        uint32_t RESERVED5[31];
+  __IOM uint32_t GICR_ISACTIVER0;            /*!< Offset: 0x0300 (R/W)  Interrupt Set-Active Register 0 */
+        uint32_t RESERVED6[31];
+  __IOM uint32_t GICR_ICACTIVER0;            /*!< Offset: 0x0380 (R/W)  Interrupt Clear-Active Register 0 */
+        uint32_t RESERVED7[31];
+  __IOM uint32_t GICR_IPRIORITYR[8];         /*!< Offset: 0x0400 (R/W)  Interrupt Priority Registers 0 - 7 */
+        uint32_t RESERVED8[504];
+  __IM  uint32_t GICR_ICFGR0;                /*!< Offset: 0x0C00 (R/ )  Interrupt Configuration Register 0 */
+  __IOM uint32_t GICR_ICFGR1;                /*!< Offset: 0x0C04 (R/W)  Interrupt Configuration Register 1 */
+}  GICR_SGI_PPI_Type;
+
+/*@} end of group CMSIS_GIC */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define GIC0_BASE                     (0x94000000UL)              /*!< GIC0 Base Address */
+#define GIC1_BASE                     (0x9C000000UL)              /*!< GIC1 Base Address */
+#define GICR_TARGET0_BASE             (0x00100000UL)              /*!< GICR Base Address (for Control target 0) */
+#define GICR_TARGET0_SGI_PPI_BASE     (0x00110000UL)              /*!< GICR Base Address (for SGI and PPI target 0) */
+
+#define GICD0                         ((GICD_Type *) GIC0_BASE )   /*!< GICD configuration struct */
+#define GICD1                         ((GICD_Type *) GIC1_BASE )   /*!< GICD configuration struct */
+#define GICR0_TARGET0_IFREG           ((GICR_CONTROL_TARGET_Type *) (GIC0_BASE + GICR_TARGET0_BASE) )    /*!< GICR configuration struct for Control target 0 */
+#define GICR1_TARGET0_IFREG           ((GICR_CONTROL_TARGET_Type *) (GIC1_BASE + GICR_TARGET0_BASE) )    /*!< GICR configuration struct for Control target 0 */
+#define GICR0_TARGET0_INTREG          ((GICR_SGI_PPI_Type *) (GIC0_BASE + GICR_TARGET0_SGI_PPI_BASE) )   /*!< GICR configuration struct for SGI and PPI target 0 */
+#define GICR1_TARGET0_INTREG          ((GICR_SGI_PPI_Type *) (GIC1_BASE + GICR_TARGET0_SGI_PPI_BASE) )   /*!< GICR configuration struct for SGI and PPI target 0 */
+
+/*@} */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  Get CPSR Register
+
+    This function returns the content of the CPSR Register.
+
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+
+
+#include <intrinsics.h>
+
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __CORE_CR52_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
--- a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/LICENSE.txt
+++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
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+
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+   2. Grant of Copyright License. Subject to the terms and conditions of
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--- a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board.h
@@ -0,0 +1,67 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
+ * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.
+ * Renesas products are sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for
+ * the selection and use of Renesas products and Renesas assumes no liability.  No license, express or implied, to any
+ * intellectual property right is granted by Renesas.  This software is protected under all applicable laws, including
+ * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
+ * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
+ * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
+ * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
+ * SOFTWARE OR DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
+ * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
+ * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
+ * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
+ * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * File Name    : board.h
+ * Description  : Includes and API function available for this board.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARDS
+ * @defgroup BOARD_RZT2M_RSK
+ * @brief BSP for the RZT2M_RSK Board
+ *
+ * The RZT2M_RSK is a development kit for the Renesas RZT2M microcontroller.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/***********************************************************************************************************************
+ * Includes   <System Includes> , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP Board Specific Includes. */
+#include "board_init.h"
+#include "board_leds.h"
+#include "board_ethernet_phy.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BOARD_RZT2M_RSK
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BSP_CONFIG_RZT2M) */
+
+#endif
--- a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_ethernet_phy.h
+++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_ethernet_phy.h
@@ -0,0 +1,60 @@
+/***********************************************************************************************************************
+ * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
+ * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.
+ * Renesas products are sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for
+ * the selection and use of Renesas products and Renesas assumes no liability.  No license, express or implied, to any
+ * intellectual property right is granted by Renesas.  This software is protected under all applicable laws, including
+ * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
+ * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
+ * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
+ * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
+ * SOFTWARE OR DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
+ * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
+ * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
+ * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
+ * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_RZT2M_RSK
+ * @defgroup BOARD_RZT2M_RSK_ETHERNET_PHY Board Ethernet Phy
+ * @brief Ethernet Phy information for this board.
+ *
+ * This is code specific to the RZT2M_RSK board.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BSP_ETHERNET_PHY_H
+#define BSP_ETHERNET_PHY_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE    (1)
+#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT       ETHER_PHY_LSI_TYPE_VSC8541
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Public Functions
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/** @} (end defgroup BOARD_RZT2M_RSK_ETHERNET_PHY) */
--- a/Show More
+++ b/Show More