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Merge pull request #3849 from OpenNuvoton/m480

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Remove legacy.
This commit is contained in:
Bernard Xiong authored and GitHub committed 2020-08-27 12:40:35 +08:00
2 parents 5b3ec9490c ce5822eb39
commit 07ee531c22
438 files changed
+2 -282094
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.travis.yml
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@@ -66,8 +66,8 @@ env:
# - RTT_BSP='mini4020' # no scons
# - RTT_BSP='mm32l07x' # not support gcc
# - RTT_BSP='nios_ii' # no scons
- RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='pic32ethernet' # no scons
- RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
bsp/nuvoton_m05x/.config
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bsp/nuvoton_m05x/.gitignore
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Nu_Link_Driver.ini
*.uvoptx
*.uvguix.*
scons-cmd.bat
obj
bsp/nuvoton_m05x/Kconfig
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_M051
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config RT_USING_UART0
bool "Using Uart0"
select RT_USING_SERIAL
default y
bsp/nuvoton_m05x/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 13/09/14 1:29p $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef[6144];
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
#endif /* ARM_COMMON_TABLES_H */
bsp/nuvoton_m05x/Libraries/CMSIS/Include/arm_math.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm0plus.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cm4_simd.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmFunc.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_cmInstr.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc000.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Include/core_sc300.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/M051Series.h
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bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Include/system_M051Series.h
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/**************************************************************************//**
* @file system_M051Series.h
* @version V3.00
* $Revision: 9 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series System Setting Header File
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __SYSTEM_M051Series_H__
#define __SYSTEM_M051Series_H__
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------------------------------------------------*/
/* Macro Definition */
/*---------------------------------------------------------------------------------------------------------*/
#ifndef DEBUG_PORT
# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
#endif
/**
*
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
* default clock source (External crystal or internal 22.1184MHz IRC).
* Enable this option will casue system booting in 50MHz(By XTAL) or 50.1918MHz(By IRC22M) according to
* user configuration setting in CONFIG0
*
*/
//#define INIT_SYSCLK_AT_BOOTING
/*----------------------------------------------------------------------------
Define SYSCLK
*----------------------------------------------------------------------------*/
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
#define __HSI (50000000UL) /*!< PLL default output is 48MHz@12M X'tal */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
#if USE_ASSERT
/**
* @brief Assert Function
*
* @param[in] expr Expression to be evaluated
*
* @return None
*
* @details If the expression is false, an error message will be printed out
* from debug port (UART0 or UART1).
*/
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
void AssertError(uint8_t* file, uint32_t line);
#else
#define ASSERT_PARAM(expr)
#endif
#define assert_param(expr) ASSERT_PARAM(expr)
/**
* @brief System Initializaiton
*
* @param None
*
* @return None
*
* @details The necessary initializaiton of system.
*/
extern void SystemInit(void);
/**
* @brief Update the Variable SystemCoreClock
*
* @param None
*
* @return None
*
* @details This function is used to update the variable SystemCoreClock
* and must be called whenever the core clock is changed.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif
/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s
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bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/GCC/startup_M051Series.s
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bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s
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;/**************************************************************************//**
; * @file startup_M051Series.s
; * @version V2.00
; * $Revision: 8 $
; * $Date: 14/02/12 10:11a $
; * @brief M051 Series Startup Source File for IAR Platform
; *
; * @note
; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
; *
; ******************************************************************************/
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
EXTERN SystemInit
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD __iar_program_start
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD BOD_IRQHandler ; Brownout low voltage detected interrupt
DCD WDT_IRQHandler ; Watch Dog Timer interrupt
DCD EINT0_IRQHandler ; External signal interrupt from PB.14 pin
DCD EINT1_IRQHandler ; External signal interrupt from PB.15 pin
DCD GPIOP0P1_IRQHandler ; External signal interrupt from P0[15:0] / P1[13:0]
DCD GPIOP2P3P4_IRQHandler ; External interrupt from P2[15:0]/P3[15:0]/P4[15:0]
DCD PWMA_IRQHandler ; PWM0 or PWM2 interrupt
DCD PWMB_IRQHandler ; PWM1 or PWM3 interrupt
DCD TMR0_IRQHandler ; Timer 0 interrupt
DCD TMR1_IRQHandler ; Timer 1 interrupt
DCD TMR2_IRQHandler ; Timer 2 interrupt
DCD TMR3_IRQHandler ; Timer 3 interrupt
DCD UART0_IRQHandler ; UART0 interrupt
DCD UART1_IRQHandler ; UART1 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD Default_Handler ; SPI2 interrupt
DCD Default_Handler ; SPI3 interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD ACMP01_IRQHandler ; ACMP0/1 interrupt
DCD ACMP23_IRQHandler ; ACMP2/3 interrupt
DCD Default_Handler ; Reserved
DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power-
DCD ADC_IRQHandler ; ADC interrupt
DCD Default_Handler ; Reserved
DCD RTC_IRQHandler ; Real time clock interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2) ; 4 bytes alignment
Reset_Handler
LDR R0, =0x50000100
; Unlock Register
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Init POR
LDR R2, =0x50000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Disable NMI (Assign to reserved IRQ)
LDR R2, =0x50000380
LDR R1, =0x0000001F
STR R1, [R2]
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK SVC_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK BOD_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK GPIOP0P1_IRQHandler
PUBWEAK GPIOP2P3P4_IRQHandler
PUBWEAK PWMA_IRQHandler
PUBWEAK PWMB_IRQHandler
PUBWEAK TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK ACMP01_IRQHandler
PUBWEAK ACMP23_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(2)
HardFault_Handler
NMI_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPIOP0P1_IRQHandler
GPIOP2P3P4_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
ACMP01_IRQHandler
ACMP23_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
Default_Handler
B Default_Handler
END
bsp/nuvoton_m05x/Libraries/CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
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/**************************************************************************//**
* @file system_M051Series.c
* @version V2.00
* $Revision: 13 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series System Setting Source File
*
* @note
* Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include "M051Series.h"
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
const uint32_t gau32ClkSrcTbl[] = {__HXT, NULL, __HSI, __LIRC, NULL, NULL, NULL, __HIRC};
/**
* @brief Update the Variable SystemCoreClock
*
* @param None
*
* @return None
*
* @details This function is used to update the variable SystemCoreClock
* and must be called whenever the core clock is changed.
*/
void SystemCoreClockUpdate(void)
{
uint32_t u32Freq, u32ClkSrc;
uint32_t u32HclkDiv;
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
/* Update PLL Clock */
PllClock = CLK_GetPLLClockFreq();
if(u32ClkSrc != CLK_CLKSEL0_HCLK_S_PLL)
{
/* Use the clock sources directly */
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
}
else
{
/* Use PLL clock */
u32Freq = PllClock;
}
u32HclkDiv = (CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1;
/* Update System Core Clock */
SystemCoreClock = u32Freq / u32HclkDiv;
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
}
/**
* @brief System Initialization
*
* @param None
*
* @return None
*
* @details The necessary initialization of system. Global variables are forbidden here.
*/
void SystemInit(void)
{
#ifdef INIT_SYSCLK_AT_BOOTING
int32_t i32TimeoutCnt;
uint32_t u32HclkSelect;
int8_t i8IsPllEn;
PllClock = 0;
i8IsPllEn = 0;
u32HclkSelect = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
if(u32HclkSelect == CLK_CLKSEL0_HCLK_S_HXT)
{
/* Set to 50MHz system clock frequency when clock source is from external 12MHz */
CLK->PLLCON = CLK_PLLCON_50MHz_HXT;
/* Waiting for PLL ready */
i32TimeoutCnt = (__HXT / 1000); /* Timeout is about 1ms */
while((CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk) == 0)
{
if(i32TimeoutCnt-- <= 0)
break;
}
i8IsPllEn = 1;
}
else if(u32HclkSelect == CLK_CLKSEL0_HCLK_S_HIRC)
{
/* Set to 50.1918MHz system clock frequency when clock source is from internal 22.1184MHz RC clock */
CLK->PLLCON = CLK_PLLCON_50MHz_HIRC;
/* Waiting for PLL ready */
i32TimeoutCnt = (__HIRC / 1000); /* Timeout is about 1ms */
while((CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk) == 0)
{
if(i32TimeoutCnt-- <= 0)
break;
}
i8IsPllEn = 1;
}
if(i8IsPllEn)
{
/* Set PLL as HCLK clock source (HCLK_S is locked setting)*/
SYS_UnlockReg();
CLK->CLKSEL0 = CLK_CLKSEL0_HCLK_S_PLL;
SYS_LockReg();
}
#endif
}
#if USE_ASSERT
/**
* @brief Assert Error Message
*
* @param[in] file the source file name
* @param[in] line line number
*
* @return None
*
* @details The function prints the source file name and line number where
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
*/
void AssertError(uint8_t * file, uint32_t line)
{
printf("[%s] line %d : wrong parameters.\r\n", file, line);
/* Infinite loop */
while(1) ;
}
#endif
bsp/nuvoton_m05x/Libraries/CMSIS/README.txt
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* -------------------------------------------------------------------
* Copyright (C) 2011-2012 ARM Limited. All rights reserved.
*
* Date: 07 March 2012
* Revision: V3.01
*
* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
* Title: Release Note for CMSIS
*
* -------------------------------------------------------------------
NOTE - Open the index.html file to access CMSIS documentation
The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
and reduces time-to-market for new embedded applications.
CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
Any user of the software package is bound to the terms and conditions of the end user license agreement.
You will find the following sub-directories:
Documentation - Contains CMSIS documentation.
DSP_Lib - MDK project files, Examples and source files etc.. to build the
CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
Include - CMSIS Core Support and CMSIS DSP Include Files.
Lib - CMSIS DSP Libraries.
RTOS - CMSIS RTOS API template header file.
SVD - CMSIS SVD Schema files and Conversion Utility.
bsp/nuvoton_m05x/Libraries/CMSIS/index.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Redirect to the CMSIS main page after 0 seconds</title>
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
</body>
</html>
bsp/nuvoton_m05x/Libraries/SConscript
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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
CMSIS/Nuvoton/M051Series/Source/system_M051Series.c
""")
src += Glob('StdDriver/src/*.c')
#add for startup script
if rtconfig.CROSS_TOOL == 'iar':
src = src + ['CMSIS/Nuvoton/M051Series/Source/IAR/startup_M051Series.s']
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['CMSIS/Nuvoton/M051Series/Source/ARM/startup_M051Series.s']
elif rtconfig.CROSS_TOOL == 'gcc':
src = src + ['CMSIS/Nuvoton/M051Series/Source/GCC/startup_M051Series.s']
path = [cwd + '/StdDriver/inc',
cwd + '/CMSIS/Nuvoton/M051Series/Include',
cwd + '/CMSIS/Include']
#CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
CPPDEFINES = ['INIT_SYSCLK_AT_BOOTING']
group = DefineGroup('M05X_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/nuvoton_m05x/Libraries/StdDriver/inc/acmp.h
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/**************************************************************************//**
* @file acmp.h
* @version V3.00
* $Revision: 6 $
* $Date: 1/28/14 11:32a $
* @brief M051 series Analog Comparator(ACMP) driver header file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_H__
#define __ACMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup M051_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* ACMP_CR constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ACMP_CR_OUTPUT_INV (1UL << ACMP_CR_ACMPOINV_Pos) /*!< ACMP_CR setting for ACMP output inverse function. */
#define ACMP_CR_VNEG_BANDGAP (1UL << ACMP_CR_NEGSEL_Pos) /*!< ACMP_CR setting for selecting band-gap voltage as the source of ACMP V-. */
#define ACMP_CR_VNEG_PIN (0UL << ACMP_CR_NEGSEL_Pos) /*!< ACMP_CR setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
#define ACMP_CR_HYSTERESIS_ENABLE (1UL << ACMP_CR_HYSEN_Pos) /*!< ACMP_CR setting for enabling the hysteresis function. */
#define ACMP_CR_HYSTERESIS_DISABLE (0UL << ACMP_CR_HYSEN_Pos) /*!< ACMP_CR setting for disabling the hysteresis function. */
#define ACMP_CR_INT_ENABLE (1UL << ACMP_CR_ACMPIE_Pos) /*!< ACMP_CR setting for enabling the interrupt function. */
#define ACMP_CR_INT_DISABLE (0UL << ACMP_CR_ACMPIE_Pos) /*!< ACMP_CR setting for disabling the interrupt function. */
#define ACMP_CR_ACMP_ENABLE (1UL << ACMP_CR_ACMPEN_Pos) /*!< ACMP_CR setting for enabling the ACMP analog circuit. */
#define ACMP_CR_ACMP_DISABLE (0UL << ACMP_CR_ACMPEN_Pos) /*!< ACMP_CR setting for disabling the ACMP analog circuit. */
/*@}*/ /* end of group M051_ACMP_EXPORTED_CONSTANTS */
/** @addtogroup M051_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief This macro is used to enable output inverse
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPOINV_Msk)
/**
* @brief This macro is used to disable output inverse
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPOINV_Msk)
/**
* @brief This macro is used to select ACMP negative input source
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Src is comparator0 negative input selection. Including :
* - \ref ACMP_CR_VNEG_PIN
* - \ref ACMP_CR_VNEG_BANDGAP
* @return None
*/
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CR[(u32ChNum)%2] = ((acmp)->CR[(u32ChNum)%2] & ~ACMP_CR_NEGSEL_Msk) | (u32Src))
/**
* @brief This macro is used to enable hysteresis function
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_HYSEN_Msk)
/**
* @brief This macro is used to disable hysteresis function
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_HYSEN_Msk)
/**
* @brief This macro is used to enable interrupt
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPIE_Msk)
/**
* @brief This macro is used to disable interrupt
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPIE_Msk)
/**
* @brief This macro is used to enable ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] |= ACMP_CR_ACMPEN_Msk)
/**
* @brief This macro is used to disable ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CR[(u32ChNum)%2] &= ~ACMP_CR_ACMPEN_Msk)
/**
* @brief This macro is used to get ACMP output value
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return 1 or 0
*/
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->SR & (ACMP_SR_ACMPO0_Msk<<((u32ChNum)%2)))?1:0)
/**
* @brief This macro is used to get ACMP interrupt flag
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return ACMP interrupt occurred or not
*/
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->SR & (ACMP_SR_ACMPF0_Msk<<((u32ChNum)%2)))?1:0)
/**
* @brief This macro is used to clear ACMP interrupt flag
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
*/
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->SR = (ACMP_SR_ACMPF0_Msk<<((u32ChNum)%2)))
void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
/*@}*/ /* end of group M051_ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ACMP_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__ACMP_H__
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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/**************************************************************************//**
* @file ebi.h
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series EBI driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_H__
#define __EBI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_EBI_Driver EBI Driver
@{
*/
/** @addtogroup M051_EBI_EXPORTED_CONSTANTS EBI Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BASE_ADDR 0x60000000UL /*!< EBI base address */
#define EBI_MAX_SIZE 0x00020000UL /*!< Maximum EBI size */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI data bus width */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI MCLK divider and Timing */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest */
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast */
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast */
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal */
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow */
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow */
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest */
/*@}*/ /* end of group M051_EBI_EXPORTED_CONSTANTS */
/** @addtogroup M051_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @details This macro read 8-bit data from specify EBI address.
*/
#define EBI_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BASE_ADDR+u32Addr)))
/**
* @details This macro write 8-bit data to specify EBI address.
*/
#define EBI_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BASE_ADDR+u32Addr)) = u32Data)
/**
* @details This macro read 16-bit data from specify EBI address.
*/
#define EBI_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BASE_ADDR+u32Addr)))
/**
* @details This macro write 16-bit data to specify EBI address.
*/
#define EBI_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BASE_ADDR+u32Addr)) = u32Data)
/**
* @details This macro read 32-bit data from specify EBI address.
*/
#define EBI_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BASE_ADDR+u32Addr)))
/**
* @details This macro write 32-bit data to specify EBI address.
*/
#define EBI_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BASE_ADDR+u32Addr)) = u32Data)Write 32-bit data to EBI bank 0
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
void EBI_Close(uint32_t u32Bank);
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
/*@}*/ /* end of group M051_EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_EBI_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__EBI_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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/**************************************************************************//**
* @file DIV.h
* @version V2.1
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 Series DIV Driver Header File
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __DIVIDER_H__
#define __DIVIDER_H__
/**
* @brief Division function to calculate (x/y)
*
* @param[in] x the dividend of the division
* @param[in] y the divisor of the division
*
* @return The result of (x/y)
*
* @details This is a division function to calculate x/y
*
*/
static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)
{
uint32_t *p32;
p32 = (uint32_t *)HDIV_BASE;
*p32++ = x;
*p32++ = y;
return *p32;
}
/**
* @brief To calculate the remainder of x/y, i.e., the result of x mod y.
*
* @param[in] x the dividend of the division
* @param[in] y the divisor of the division
*
* @return The remainder of (x/y)
*
* @details This function is used to calculate the remainder of x/y.
*/
static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)
{
uint32_t *p32;
p32 = (uint32_t *)HDIV_BASE;
*p32++ = x;
*p32++ = y;
return p32[1];
}
#endif
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/**************************************************************************//**
* @file I2C.h
* @version V3.0
* $Revision: 9 $
* $Date: 14/02/10 3:04p $
* @brief M051 Series I2C Driver Header File
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __I2C_H__
#define __I2C_H__
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_I2C_Driver I2C Driver
@{
*/
/** @addtogroup M051_I2C_EXPORTED_CONSTANTS I2C Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* I2CON constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_I2CON_STA_STO_SI 0x38UL /*!< I2CON setting for I2C control bits. It would set STA, STO and SI bits */
#define I2C_I2CON_STA_STO_SI_AA 0x3CUL /*!< I2CON setting for I2C control bits. It would set STA, STO, SI and AA bits */
#define I2C_I2CON_STA_SI 0x28UL /*!< I2CON setting for I2C control bits. It would set STA and SI bits */
#define I2C_I2CON_STA_SI_AA 0x2CUL /*!< I2CON setting for I2C control bits. It would set STA, SI and AA bits */
#define I2C_I2CON_STO_SI 0x18UL /*!< I2CON setting for I2C control bits. It would set STO and SI bits */
#define I2C_I2CON_STO_SI_AA 0x1CUL /*!< I2CON setting for I2C control bits. It would set STO, SI and AA bits */
#define I2C_I2CON_SI 0x08UL /*!< I2CON setting for I2C control bits. It would set SI bit */
#define I2C_I2CON_SI_AA 0x0CUL /*!< I2CON setting for I2C control bits. It would set SI and AA bits */
#define I2C_I2CON_STA 0x20UL /*!< I2CON setting for I2C control bits. It would set STA bit */
#define I2C_I2CON_STO 0x10UL /*!< I2CON setting for I2C control bits. It would set STO bit */
#define I2C_I2CON_AA 0x04UL /*!< I2CON setting for I2C control bits. It would set AA bit */
/*@}*/ /* end of group M051_I2C_EXPORTED_CONSTANTS */
/** @addtogroup M051_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
@{
*/
/**
* @brief The macro is used to set I2C bus condition at One Time
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details To control I2C bus conditions of START, STOP, SI, ACK.
*/
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->I2CON = ((i2c)->I2CON & ~0x3c) | u8Ctrl)
/**
* @brief The macro is used to set START condition of I2C Bus
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details To set the I2C bus START condition
*/
#define I2C_START(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STA_Msk)
/**
* @brief The macro is used to set STOP condition of I2C Bus
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details To set the I2C bus STOP condition
*/
#define I2C_STOP(i2c) ((i2c)->I2CON = ((i2c)->I2CON & ~I2C_I2CON_SI_Msk) | I2C_I2CON_STO_Msk)
/**
* @brief The macro is used to wait I2C bus status get ready
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details When a new status is presented of I2C bus, SI flag will be set.
*/
#define I2C_WAIT_READY(i2c) while(!((i2c)->I2CON & I2C_I2CON_SI_Msk))
/**
* @brief The macro is used to Read I2C Bus Data Register
*
* @param[in] i2c Specify I2C port
* @return A byte of I2C data register
*
* @details I2C controller read data from bus and save it in I2CDAT
*/
#define I2C_GET_DATA(i2c) ((i2c)->I2CDAT)
/**
* @brief The macro is used to write a Data to I2C Data Register
*
* @param[in] i2c Specify I2C port
* @return None
*
* @details I2C controller send a byte data to bus.
*/
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->I2CDAT = u8Data)
/**
* @brief The macro is used to get I2C Bus Status Code
*
* @param[in] i2c Specify I2C port
* @return I2C status code
*
* @details To get ths status code of I2C Bus.
*/
#define I2C_GET_STATUS(i2c) ((i2c)->I2CSTATUS)
/**
* @brief The macro is used to get time-out flag
*
* @param[in] i2c Specify I2C port
* @return Time-out flag status
* @retval 0 Bus time-out is not happened
* @retval 1 Bus time-out is happened
*
* @details To get time-out flag of I2C bus
*/
#define I2C_GET_TIMEOUT_FLAG(i2c) ( (i2c->I2CTOC & I2C_I2CTOC_TIF_Msk) == I2C_I2CTOC_TIF_Msk ? 1:0 )
/**
* @brief The macro is used to get wake-up flag
*
* @param[in] i2c Specify I2C port
* @return Wake-up flag status
* @retval 0 Chip is not woken-up from power-down mode
* @retval 1 Chip is woken-up from power-down mode
*
* @detail To get wake-up status of I2C bus
*/
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->I2CWKUPSTS & I2C_I2CWKUPSTS_WKUPIF_Msk) == I2C_I2CWKUPSTS_WKUPIF_Msk ? 1:0 )
/**
* @brief The macro is used to clear wake-up flag
*
* @param[in] i2c Specify I2C port
* @return None
*
* @detail To clear wake-up flag of I2C bus when wake-up flag is set.
*/
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->I2CWKUPSTS |= I2C_I2CWKUPSTS_WKUPIF_Msk)
void I2C_ClearTimeoutFlag(I2C_T *i2c);
void I2C_Close(I2C_T *i2c);
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
void I2C_DisableInt(I2C_T *i2c);
void I2C_EnableInt(I2C_T *i2c);
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
uint32_t I2C_GetIntFlag(I2C_T *i2c);
uint32_t I2C_GetStatus(I2C_T *i2c);
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
uint8_t I2C_GetData(I2C_T *i2c);
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
uint32_t I2C_SetClockBusFreq(I2C_T *i2c, uint32_t u32BusClock);
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
void I2C_DisableTimeout(I2C_T *i2c);
void I2C_EnableWakeup(I2C_T *i2c);
void I2C_DisableWakeup(I2C_T *i2c);
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
/*@}*/ /* end of group M051_I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_I2C_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__I2C_H__
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/**************************************************************************//**
* @file wdt.h
* @version V3.00
* $Revision: 3 $
* $Date: 14/01/28 10:49a $
* @brief M051 series WDT driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_H__
#define __WDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_WDT_Driver WDT Driver
@{
*/
/** @addtogroup M051_WDT_EXPORTED_CONSTANTS WDT Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* WTCR Constants Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_TIMEOUT_2POW4 (0UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
#define WDT_TIMEOUT_2POW6 (1UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
#define WDT_TIMEOUT_2POW8 (2UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
#define WDT_TIMEOUT_2POW10 (3UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
#define WDT_TIMEOUT_2POW12 (4UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
#define WDT_TIMEOUT_2POW14 (5UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
#define WDT_TIMEOUT_2POW16 (6UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
#define WDT_TIMEOUT_2POW18 (7UL << WDT_WTCR_WTIS_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
/*---------------------------------------------------------------------------------------------------------*/
/* WTCRALT Constants Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
#define WDT_RESET_DELAY_130CLK (1UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
#define WDT_RESET_DELAY_18CLK (2UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
#define WDT_RESET_DELAY_3CLK (3UL << WDT_WTCRALT_WTRDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
/*@}*/ /* end of group M051_WDT_EXPORTED_CONSTANTS */
/** @addtogroup M051_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
@{
*/
/**
* @details This macro clear WDT time-out reset system flag.
*/
#define WDT_CLEAR_RESET_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTRF_Msk)
/**
* @details This macro clear WDT time-out interrupt flag.
*/
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTWKF_Msk)) | WDT_WTCR_WTIF_Msk)
/**
* @details This macro clear WDT time-out wake-up system flag.
*/
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk)) | WDT_WTCR_WTWKF_Msk)
/**
* @brief Get WDT Time-out Reset Flag
*
* @return WDT reset system or not
* @retval 0 WDT did not cause system reset
* @retval 1 WDT caused system reset
*
* @details This macro indicate WDT time-out to reset system or not.
*/
#define WDT_GET_RESET_FLAG() (WDT->WTCR & WDT_WTCR_WTRF_Msk ? 1 : 0)
/**
* @brief Get WDT Time-out Interrupt Flag
*
* @return WDT time-out interrupt occurred or not
* @retval 0 WDT time-out interrupt did not occur
* @retval 1 WDT time-out interrupt occurred
*
* @details This macro indicate WDT time-out interrupt occurred or not.
*/
#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->WTCR & WDT_WTCR_WTIF_Msk ? 1 : 0)
/**
* @brief Get WDT Time-out Wake-up Flag
*
* @return WDT time-out waked system up or not
* @retval 0 WDT did not wake up system
* @retval 1 WDT waked up system
*
* @details This macro indicate WDT time-out waked system up or not
*/
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->WTCR & WDT_WTCR_WTWKF_Msk ? 1 : 0)
/**
* @details This macro is used to reset 18-bit WDT counter.
* @note If WDT is activated and enabled to reset system, software must reset WDT counter \n
* before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
*/
#define WDT_RESET_COUNTER() (WDT->WTCR = (WDT->WTCR & ~(WDT_WTCR_WTIF_Msk | WDT_WTCR_WTWKF_Msk | WDT_WTCR_WTRF_Msk)) | WDT_WTCR_WTR_Msk)
/**
* @brief Stop WDT Counting
*
* @param None
*
* @return None
*
* @details This function stops WDT counting and disable WDT module.
*/
static __INLINE void WDT_Close(void)
{
WDT->WTCR = 0;
return;
}
/**
* @brief Enable WDT Time-out Interrupt
*
* @param None
*
* @return None
*
* @details This function enable the WDT time-out interrupt.
*/
static __INLINE void WDT_EnableInt(void)
{
WDT->WTCR |= WDT_WTCR_WTIE_Msk;
return;
}
/**
* @brief Disable WDT Time-out Interrupt
*
* @param None
*
* @return None
*
* @details This function disables the WDT time-out interrupt.
*/
static __INLINE void WDT_DisableInt(void)
{
// Do not touch write 1 clear bits
WDT->WTCR &= ~(WDT_WTCR_WTIE_Msk | WDT_WTCR_WTRF_Msk | WDT_WTCR_WTIF_Msk);
return;
}
void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
/*@}*/ /* end of group M051_WDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_WDT_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__WDT_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/inc/wwdt.h
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/**************************************************************************//**
* @file wwdt.h
* @version V3.00
* $Revision: 6 $
* $Date: 14/01/28 10:49a $
* @brief M051 series WWDT driver header file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_H__
#define __WWDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup M051_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* WWDTCR Constants Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WWDT_PRESCALER_1 (0 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_2 (1 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_4 (2 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_8 (3 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_16 (4 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_32 (5 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_64 (6 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_128 (7 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_192 (8 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_256 (9 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_384 (10 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_512 (11 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_768 (12 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_1024 (13 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_1536 (14 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_2048 (15 << WWDT_WWDTCR_PERIODSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDTRLD register to reload WWDT counter */
/*@}*/ /* end of group M051_WWDT_EXPORTED_CONSTANTS */
/** @addtogroup M051_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
@{
*/
/**
* @details This macro clear WWDT counter time-out reset system flag.
*/
#define WWDT_CLEAR_RESET_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTRF_Msk)
/**
* @details This macro clear WWDT counter compare match interrupt flag.
*/
#define WWDT_CLEAR_INT_FLAG() (WWDT->WWDTSR = WWDT_WWDTSR_WWDTIF_Msk)
/**
* @brief Get WWDT Reset Flag
*
* @return WWDT counter time-out reset system or not
* @retval 0 WWDT did not cause system reset
* @retval 1 WWDT counter time-out caused system reset
*
* @details This macro is used to indicate WWDT counter time-out reset system flag.
*/
#define WWDT_GET_RESET_FLAG() ((((WWDT->WWDTSR) & WWDT_WWDTSR_WWDTRF_Msk) == WWDT_WWDTSR_WWDTRF_Msk)? 1:0)
/**
* @brief Get WWDT Compared Match Interrupt Flag
*
* @return WWDT compare match interrupt occurred or not
* @retval 0 WWDT counter compare match interrupt did not occur
* @retval 1 WWDT counter compare match interrupt occurred
*
* @details This macro indicate WWDT counter compare match interrupt occurred or not.
*/
#define WWDT_GET_INT_FLAG() ((((WWDT->WWDTSR) & WWDT_WWDTSR_WWDTIF_Msk) == WWDT_WWDTSR_WWDTIF_Msk)? 1:0)
/**
* @details This macro to reflects the current WWDT counter value.
*/
#define WWDT_GET_COUNTER() (WWDT->WWDTCVR)
/**
* @details This macro is used to reload the WWDT counter value to 0x3F.
* @note After WWDT enabled, application must reload WWDT counter while current counter is less than compare value \n
* and larger than 0, otherwise WWDT will cause system reset immediately.
*/
#define WWDT_RELOAD_COUNTER() (WWDT->WWDTRLD = WWDT_RELOAD_WORD)
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
/*@}*/ /* end of group M051_WWDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_WWDT_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__WWDT_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/acmp.c
-78
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/**************************************************************************//**
* @file acmp.c
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series Analog Comparator(ACMP) driver source file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup M051_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief Configure the specified ACMP module
*
* @param[in] Acmp The base address of ACMP module
* @param[in] u32ChNum comparator number.
* @param[in] u32NegSrc is comparator negative input selection. Including:
* - \ref ACMP_CR_VNEG_PIN
* - \ref ACMP_CR_VNEG_BANDGAP
*
* @param[in] u32HysteresisEn is the hysteresis function option. Including:
* - \ref ACMP_CR_HYSTERESIS_ENABLE
* - \ref ACMP_CR_HYSTERESIS_DISABLE
* @return None
*/
void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
{
Acmp->CR[u32ChNum % 2] = (Acmp->CR[u32ChNum % 2] & (~(ACMP_CR_NEGSEL_Msk | ACMP_CR_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CR_ACMPEN_Msk);
}
/**
* @brief This function close comparator
*
* @param[in] Acmp The base address of ACMP module
* @param[in] u32ChNum comparator number.
*
* @return None
*/
void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
{
Acmp->CR[u32ChNum % 2] &= (~ACMP_CR_ACMPEN_Msk);
}
/*@}*/ /* end of group M051_ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ACMP_Driver */
/*@}*/ /* end of group M051_Device_Driver */
#ifdef __cplusplus
}
#endif
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/adc.c
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/**************************************************************************//**
* @file adc.c
* @version V3.00
* $Revision: 5 $
* $Date: 14/02/10 2:47p $
* @brief M051 series ADC driver source file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_ADC_Driver ADC Driver
@{
*/
/** @addtogroup M051_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
@{
*/
/**
* @brief This API configures ADC module to be ready for convert the input from selected channel
* @param[in] adc Base address of ADC module
* @param[in] u32InputMode Decides the ADC analog input mode. Valid values are:
* - \ref ADC_ADCR_DIFFEN_SINGLE_END :Single end input mode
* - \ref ADC_ADCR_DIFFEN_DIFFERENTIAL :Differential input type
* @param[in] u32OpMode Decides the ADC operation mode. Valid values are:
* - \ref ADC_ADCR_ADMD_SINGLE :Single mode.
* - \ref ADC_ADCR_ADMD_BURST :Burst mode.
* - \ref ADC_ADCR_ADMD_SINGLE_CYCLE :Single cycle scan mode.
* - \ref ADC_ADCR_ADMD_CONTINUOUS :Continuous scan mode.
* @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7.
* @return None
* @note M051 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
* with smallest number will be convert.
* @note This API does not turn on ADC power nor does trigger ADC conversion
*/
void ADC_Open(ADC_T *adc,
uint32_t u32InputMode,
uint32_t u32OpMode,
uint32_t u32ChMask)
{
ADC->ADCR = (ADC->ADCR & (~(ADC_ADCR_DIFFEN_Msk | ADC_ADCR_ADMD_Msk))) | \
u32InputMode | \
u32OpMode;
ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32ChMask);
return;
}
/**
* @brief Disable ADC module
* @param[in] adc Base address of ADC module
* @return None
*/
void ADC_Close(ADC_T *adc)
{
SYS->IPRSTC2 |= SYS_IPRSTC2_ADC_RST_Msk;
SYS->IPRSTC2 &= ~SYS_IPRSTC2_ADC_RST_Msk;
return;
}
/**
* @brief Configure the hardware trigger condition and enable hardware trigger
* @param[in] adc Base address of ADC module
* @param[in] u32Source Decides the hardware trigger source. Valid values are:
* - \ref ADC_ADCR_TRGS_STADC :A/D conversion is started by external STADC pin.
* - \ref ADC_ADCR_TRGS_PWM :A/D conversion is started by PWM.
* @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
* trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
* time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
* is used to set trigger condition. Valid values are:
* - \ref ADC_ADCR_TRGCOND_LOW_LEVEL :STADC Low level active
* - \ref ADC_ADCR_TRGCOND_HIGH_LEVEL :STADC High level active
* - \ref ADC_ADCR_TRGCOND_FALLING_EDGE :STADC Falling edge active
* - \ref ADC_ADCR_TRGCOND_RISING_EDGE :STADC Rising edge active
* @return None
* @note ADC hardware trigger source does not support PWM trigger (M05xxBN only).
*/
void ADC_EnableHWTrigger(ADC_T *adc,
uint32_t u32Source,
uint32_t u32Param)
{
ADC->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
if(u32Source == ADC_ADCR_TRGS_STADC)
{
ADC->ADCR |= u32Source | u32Param | ADC_ADCR_TRGEN_Msk;
}
else
{
ADC->ADTDCR = (ADC->ADTDCR & ~ADC_ADTDCR_PTDT_Msk) | u32Param;
ADC->ADCR |= u32Source | ADC_ADCR_TRGEN_Msk;
}
return;
}
/**
* @brief Disable hardware trigger ADC function.
* @param[in] adc Base address of ADC module
* @return None
*/
void ADC_DisableHWTrigger(ADC_T *adc)
{
ADC->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
return;
}
/**
* @brief Enable the interrupt(s) selected by u32Mask parameter.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
* corresponds to a interrupt status. This parameter decides which
* interrupts will be enabled.
* - \ref ADC_ADF_INT :ADC convert complete interrupt
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
* @return None
*/
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
{
if(u32Mask & ADC_ADF_INT)
ADC->ADCR |= ADC_ADCR_ADIE_Msk;
if(u32Mask & ADC_CMP0_INT)
ADC->ADCMPR[0] |= ADC_ADCMPR_CMPIE_Msk;
if(u32Mask & ADC_CMP1_INT)
ADC->ADCMPR[1] |= ADC_ADCMPR_CMPIE_Msk;
return;
}
/**
* @brief Disable the interrupt(s) selected by u32Mask parameter.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
* corresponds to a interrupt status. This parameter decides which
* interrupts will be disabled.
* - \ref ADC_ADF_INT :ADC convert complete interrupt
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
* @return None
*/
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
{
if(u32Mask & ADC_ADF_INT)
ADC->ADCR &= ~ADC_ADCR_ADIE_Msk;
if(u32Mask & ADC_CMP0_INT)
ADC->ADCMPR[0] &= ~ADC_ADCMPR_CMPIE_Msk;
if(u32Mask & ADC_CMP1_INT)
ADC->ADCMPR[1] &= ~ADC_ADCMPR_CMPIE_Msk;
return;
}
/*@}*/ /* end of group M051_ADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_ADC_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/clk.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/ebi.c
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/**************************************************************************//**
* @file ebi.c
* @version V3.00
* $Revision: 3 $
* $Date: 14/01/28 10:49a $
* @brief M051 series EBI driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_EBI_Driver EBI Driver
@{
*/
/** @addtogroup M051_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @brief Initialize EBI function
*
* @param[in] u32Bank Bank number for EBI. This parameter is current not used.
* @param[in] u32DataWidth Data bus width. Valid values are:
* - \ref EBI_BUSWIDTH_8BIT
* - \ref EBI_BUSWIDTH_16BIT
* @param[in] u32TimingClass Default timing configuration. Valid values are:
* - \ref EBI_TIMING_FASTEST
* - \ref EBI_TIMING_VERYFAST
* - \ref EBI_TIMING_FAST
* - \ref EBI_TIMING_NORMAL
* - \ref EBI_TIMING_SLOW
* - \ref EBI_TIMING_VERYSLOW
* - \ref EBI_TIMING_SLOWEST
* @param[in] u32BusMode Enable EBI separate mode. This parameter is current not used.
* @param[in] u32CSActiveLevel CS is active High/Low. This parameter is current not used.
*
* @return none
*
* @details This function make EBI module be ready for read and write operation.
* @note Only u32DataWidth and u32TimingClass is valid in M051 series.
*/
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
{
if(u32DataWidth == EBI_BUSWIDTH_8BIT)
EBI->EBICON &= ~EBI_EBICON_ExtBW16_Msk;
else
EBI->EBICON |= EBI_EBICON_ExtBW16_Msk;
switch(u32TimingClass)
{
case EBI_TIMING_FASTEST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk;
EBI->EXTIME = 0x0;
break;
case EBI_TIMING_VERYFAST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_1 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x3 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x03003318;
break;
case EBI_TIMING_FAST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk;
EBI->EXTIME = 0x0;
break;
case EBI_TIMING_NORMAL:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x3 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x03003318;
break;
case EBI_TIMING_SLOW:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x7 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x07007738;
break;
case EBI_TIMING_VERYSLOW:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_4 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x7 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x07007738;
break;
case EBI_TIMING_SLOWEST:
EBI->EBICON = (EBI->EBICON & ~(EBI_EBICON_MCLKDIV_Msk | EBI_EBICON_ExttALE_Msk)) |
(EBI_MCLKDIV_8 << EBI_EBICON_MCLKDIV_Pos) | EBI_EBICON_ExtEN_Msk |
(0x7 << EBI_EBICON_ExttALE_Pos) ;
EBI->EXTIME = 0x07007738;
break;
default:
EBI->EBICON &= ~EBI_EBICON_ExtEN_Msk;
break;
}
}
/**
* @brief Disable EBI function
*
* @param[in] u32Bank Bank number for EBI. This parameter is current not used.
*
* @return none
*
* @details This function close EBI module.
*/
void EBI_Close(uint32_t u32Bank)
{
EBI->EBICON &= ~EBI_EBICON_ExtEN_Msk;
}
/**
* @brief Set EBI bus timings
*
* @param[in] u32Bank Bank number for EBI. This parameter is current not used.
*
* @param[in] u32TimingConfig Configure EBI timing settings, ExttACC, ExttAHD, ExtIW2X and ExtIR2R.
* @param[in] u32MclkDiv Divider for MCLK. Valid values are:
* - \ref EBI_MCLKDIV_1
* - \ref EBI_MCLKDIV_2
* - \ref EBI_MCLKDIV_4
* - \ref EBI_MCLKDIV_8
* - \ref EBI_MCLKDIV_16
* - \ref EBI_MCLKDIV_32
*
* @return none
*
* @details This function make EBI module be ready for read and write operation.
*/
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
{
EBI->EBICON = (EBI->EBICON & ~EBI_EBICON_MCLKDIV_Msk) | (u32MclkDiv << EBI_EBICON_MCLKDIV_Pos);
EBI->EXTIME = u32TimingConfig;
}
/*@}*/ /* end of group M051_EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_EBI_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/fmc.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/gpio.c
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/**************************************************************************//**
* @file gpio.c
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series GPIO driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup M051_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
@{
*/
/**
* @brief Set GPIO operation mode
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. It could be BIT0 ~ BIT7.
* @param[in] u32Mode Operation mode. GPIO_PMD_INPUT, GPIO_PMD_OUTPUT, GPIO_PMD_OPEN_DRAIN, GPIO_PMD_QUASI
*
* @return None
*
* @details This function is used to set specified GPIO operation mode.
*/
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{
uint32_t i;
for(i = 0; i < GPIO_PIN_MAX; i++)
{
if(u32PinMask & (1 << i))
{
port->PMD = (port->PMD & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
}
}
}
/**
* @brief Enable GPIO interrupt
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
{
port->IMD |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
port->IEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
}
/**
* @brief Disable GPIO interrupt
*
* @param[in] port GPIO port. It could be P0, P1, P2, P3 or P4.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
{
port->IMD &= ~(1UL << u32Pin);
port->IEN &= ~((0x00010001UL) << u32Pin);
}
/*@}*/ /* end of group M051_GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_GPIO_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/i2c.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/pwm.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/spi.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/sys.c
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/**************************************************************************//**
* @file sys.c
* @version V3.00
* $Revision: 6 $
* $Date: 14/01/28 6:58p $
* @brief M051 series SYS driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_SYS_Driver SYS Driver
@{
*/
/** @addtogroup M051_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
@{
*/
/**
* @brief This function clear the selected system reset source
* @param u32Src is system reset source
* @return None
*/
void SYS_ClearResetSrc(uint32_t u32Src)
{
SYS->RSTSRC |= u32Src;
}
/**
* @brief This function get Brown-out detector output status
* @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
* 1: System voltage is lower than BOD_VL setting.
* Note : If the BOD_EN is 0, this function always return 0.
*/
uint32_t SYS_GetBODStatus(void)
{
return (SYS->BODCR & SYS_BODCR_BOD_OUT_Msk) ? 1 : 0;
}
/**
* @brief This function get the system reset source register value
* @return Reset source
*/
uint32_t SYS_GetResetSrc(void)
{
return (SYS->RSTSRC);
}
/**
* @brief This function check register write-protection bit setting
* @return 0: Write-protection function is disabled.
* 1: Write-protection function is enabled.
*/
uint32_t SYS_IsRegLocked(void)
{
return !(SYS->REGWRPROT & SYS_REGWRPROT_REGPROTDIS_Msk);
}
/**
* @brief This function get product ID.
* @return Product ID
*/
uint32_t SYS_ReadPDID(void)
{
return SYS->PDID;
}
/**
* @brief This function reset chip.
* @return None
*/
void SYS_ResetChip(void)
{
SYS->IPRSTC1 |= SYS_IPRSTC1_CHIP_RST_Msk;
}
/**
* @brief This function reset CPU.
* @return None
*/
void SYS_ResetCPU(void)
{
SYS->IPRSTC1 |= SYS_IPRSTC1_CPU_RST_Msk;
}
/**
* @brief This function reset selected modules.
* @param u32ModuleIndex is module index. Including :
* - \ref CHIP_RST
* - \ref CPU_RST
* - \ref EBI_RST
* - \ref HDIV_RST
* - \ref GPIO_RST
* - \ref TMR0_RST
* - \ref TMR1_RST
* - \ref TMR2_RST
* - \ref TMR3_RST
* - \ref I2C0_RST
* - \ref I2C1_RST
* - \ref SPI0_RST
* - \ref SPI1_RST
* - \ref UART0_RST
* - \ref UART1_RST
* - \ref PWM03_RST
* - \ref PWM47_RST
* - \ref ACMP01_RST
* - \ref ACMP23_RST
* - \ref ADC_RST
* @return None
*/
void SYS_ResetModule(uint32_t u32ModuleIndex)
{
*(volatile uint32_t *)(&(SYS->IPRSTC1) + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
*(volatile uint32_t *)(&(SYS->IPRSTC1) + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
}
/**
* @brief This function configure BOD function.
* Configure BOD reset or interrupt mode and set Brown-out voltage level.
* Enable Brown-out function
* @param i32Mode is reset or interrupt mode. Including :
* - \ref SYS_BODCR_BOD_RST_EN
* - \ref SYS_BODCR_BOD_INTERRUPT_EN
* @param u32BODLevel is Brown-out voltage level. Including :
* - \ref SYS_BODCR_BOD_VL_4_4V
* - \ref SYS_BODCR_BOD_VL_3_7V
* - \ref SYS_BODCR_BOD_VL_2_7V
* - \ref SYS_BODCR_BOD_VL_2_2V
* @return None
*/
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
{
SYS->BODCR |= SYS_BODCR_BOD_EN_Msk;
SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_RSTEN_Msk) | i32Mode;
SYS->BODCR = (SYS->BODCR & ~SYS_BODCR_BOD_VL_Msk) | u32BODLevel;
}
/**
* @brief This function disable BOD function.
* @return None
*/
void SYS_DisableBOD(void)
{
SYS->BODCR &= ~SYS_BODCR_BOD_EN_Msk;
}
/*@}*/ /* end of group M051_SYS_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_SYS_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/timer.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/uart.c
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bsp/nuvoton_m05x/Libraries/StdDriver/src/wdt.c
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/**************************************************************************//**
* @file wdt.c
* @version V3.00
* $Revision: 2 $
* $Date: 14/01/28 10:49a $
* @brief M051 series WDT driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_WDT_Driver WDT Driver
@{
*/
/** @addtogroup M051_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
@{
*/
/**
* @brief Initialize WDT counter and start counting
*
* @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
* - \ref WDT_TIMEOUT_2POW4
* - \ref WDT_TIMEOUT_2POW6
* - \ref WDT_TIMEOUT_2POW8
* - \ref WDT_TIMEOUT_2POW10
* - \ref WDT_TIMEOUT_2POW12
* - \ref WDT_TIMEOUT_2POW14
* - \ref WDT_TIMEOUT_2POW16
* - \ref WDT_TIMEOUT_2POW18
* @param[in] u32ResetDelay Configure reset delay period while WDT time-out happened. Valid values are:
* - \ref WDT_RESET_DELAY_1026CLK
* - \ref WDT_RESET_DELAY_130CLK
* - \ref WDT_RESET_DELAY_18CLK
* - \ref WDT_RESET_DELAY_3
* @param[in] u32EnableReset Enable WDT rest system function. Valid values are TRUE and FALSE.
* @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are TRUE and FALSE.
*
* @return None
*
* @details This function make WDT module start counting with different time-out interval and reset delay period.
*/
void WDT_Open(uint32_t u32TimeoutInterval,
uint32_t u32ResetDelay,
uint32_t u32EnableReset,
uint32_t u32EnableWakeup)
{
WDT->WTCRALT = u32ResetDelay;
WDT->WTCR = u32TimeoutInterval | WDT_WTCR_WTE_Msk |
(u32EnableReset << WDT_WTCR_WTRE_Pos) |
(u32EnableWakeup << WDT_WTCR_WTWKE_Pos);
return;
}
/*@}*/ /* end of group M051_WDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_WDT_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/Libraries/StdDriver/src/wwdt.c
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/**************************************************************************//**
* @file wwdt.c
* @version V3.00
* $Revision: 4 $
* $Date: 14/01/28 10:49a $
* @brief M051 series WWDT driver source file
*
* @note
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M051Series.h"
/** @addtogroup M051_Device_Driver M051 Device Driver
@{
*/
/** @addtogroup M051_WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup M051_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
@{
*/
/**
* @brief Open WWDT function to start counting
*
* @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are:
* - \ref WWDT_PRESCALER_1
* - \ref WWDT_PRESCALER_2
* - \ref WWDT_PRESCALER_4
* - \ref WWDT_PRESCALER_8
* - \ref WWDT_PRESCALER_16
* - \ref WWDT_PRESCALER_32
* - \ref WWDT_PRESCALER_64
* - \ref WWDT_PRESCALER_128
* - \ref WWDT_PRESCALER_192
* - \ref WWDT_PRESCALER_256
* - \ref WWDT_PRESCALER_384
* - \ref WWDT_PRESCALER_512
* - \ref WWDT_PRESCALER_768
* - \ref WWDT_PRESCALER_1024
* - \ref WWDT_PRESCALER_1536
* - \ref WWDT_PRESCALER_2048
* @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.
* @param[in] u32EnableInt Enable WWDT interrupt function. Valid values are TRUE and FALSE.
*
* @return None
*
* @details This function make WWDT module start counting with different counter period and compared window value.
* @note Application can call this function only once after boot up.
*/
void WWDT_Open(uint32_t u32PreScale,
uint32_t u32CmpValue,
uint32_t u32EnableInt)
{
WWDT->WWDTCR = u32PreScale |
(u32CmpValue << WWDT_WWDTCR_WINCMP_Pos) |
((u32EnableInt == TRUE) ? WWDT_WWDTCR_WWDTIE_Msk : 0) |
WWDT_WWDTCR_WWDTEN_Msk;
return;
}
/*@}*/ /* end of group M051_WWDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M051_WWDT_Driver */
/*@}*/ /* end of group M051_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
bsp/nuvoton_m05x/SConscript
-14
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# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/nuvoton_m05x/SConstruct
-35
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-nuvotan_m05x.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)
bsp/nuvoton_m05x/applications/SConscript
-11
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@@ -1,11 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/nuvoton_m05x/applications/main.c
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/*
* File : main.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2018-09-01 ZYH first implementation
*/
#include <stdio.h>
int main()
{
return 0;
}
bsp/nuvoton_m05x/drivers/SConscript
-11
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@@ -1,11 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/nuvoton_m05x/drivers/board.c
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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-11-23 Bright first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "usart.h"
/**
* @addtogroup NUVOTON_M05X
*/
/*@{*/
/*******************************************************************************
* Function Name : NVIC_Configuration
* Description : Configures Vector Table base location.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_Configuration(void)
{
// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
}
/**
* @brief Inserts a delay time.
* @param nCount: specifies the delay time length.
* @retval None
*/
static void delay(__IO uint32_t nCount)
{
/* Decrement nCount value */
while (nCount != 0)
{
nCount--;
}
}
static void rt_hw_system_init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
SYS_UnlockReg();
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(BOARD_PLL_CLOCK);
/* Set SysTick clock source to HCLK source divide 2 */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2);
SYS_LockReg();
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial Nuvoton board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the system clock */
rt_hw_system_init();
/* Configure the SysTick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* Initial usart deriver, and set console device */
rt_hw_usart_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)M05X_SRAM_BEGIN, (void *)M05X_SRAM_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/*@}*/
bsp/nuvoton_m05x/drivers/board.h
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-11-23 Bright add board.h to this bsp
*/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef __BOARD_H__
#define __BOARD_H__
#include "M051Series.h"
#define BOARD_PLL_CLOCK 50000000
/* board configuration */
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define M05X_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define M05X_SRAM_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define M05X_SRAM_BEGIN (&__bss_end)
#endif
#define M05X_SRAM_SIZE 4
#define M05X_SRAM_END (0x20000000 + M05X_SRAM_SIZE * 1024)
void rt_hw_board_init(void);
//#define PRINT_RCC_FREQ_INFO
#endif
// <<< Use Configuration Wizard in Context Menu >>>
bsp/nuvoton_m05x/drivers/led.c
-43
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/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-11-23 Bright first implementation
*/
#include "led.h"
/*
LED: P3.6
*/
#define LED_PORT P3
#define LED_DATA(dat) (P36 = dat)
#define LED_BIT BIT6
/* Initial led gpio pin */
int rt_hw_led_init(void)
{
/* Configure the GPIO_LED pin */
GPIO_SetMode(LED_PORT, LED_BIT, GPIO_PMD_OUTPUT);
return 0;
}
void rt_hw_led_on(void)
{
LED_DATA(0);
}
void rt_hw_led_off(void)
{
LED_DATA(1);
}
/* Initial components for device */
INIT_DEVICE_EXPORT(rt_hw_led_init);
bsp/nuvoton_m05x/drivers/led.h
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@@ -1,25 +0,0 @@
/*
* File : led.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-11-23 Bright first implementation
*/
#ifndef __LED_H__
#define __LED_H__
#include <rthw.h>
#include <rtthread.h>
#include "M051Series.h"
void rt_hw_led_on(void);
void rt_hw_led_off(void);
#endif
bsp/nuvoton_m05x/drivers/usart.c
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/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-11-29 Bright the first version
*/
#include "M051Series.h"
#include <rtdevice.h>
#include "usart.h"
static rt_err_t m05x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
UART_T* uart;
uart = (UART_T *)serial->parent.user_data;
#if defined(RT_USING_UART0)
if (uart == UART0) {
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_PLL, CLK_CLKDIV_UART(1));
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);
SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0);
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, cfg->baud_rate);
/* Enable Interrupt */
UART_EnableInt(UART0, UART_IER_RDA_IEN_Msk);
}
#endif /* RT_USING_UART0 */
#if defined(RT_USING_UART1)
#endif /* RT_USING_UART1 */
return RT_EOK;
}
static rt_err_t m05x_control(struct rt_serial_device *serial, int cmd, void *arg)
{
UART_T* uart;
uart = (UART_T *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT: {
/* Disable Interrupt */
UART_DisableInt(uart, UART_IER_RDA_IEN_Msk);
break;
}
case RT_DEVICE_CTRL_SET_INT: {
UART_EnableInt(uart, UART_IER_RDA_IEN_Msk);
break;
}
}
return RT_EOK;
}
static int m05x_putc(struct rt_serial_device *serial, char c)
{
UART_T* uart;
uart = (UART_T *)serial->parent.user_data;
if (UART_IS_TX_FULL(uart)) {
UART_WAIT_TX_EMPTY(uart);
}
UART_WRITE(uart, c);
return 1;
}
static int m05x_getc(struct rt_serial_device *serial)
{
int ch = -1;
UART_T* uart;
uart = (UART_T *)serial->parent.user_data;
if (UART_IS_RX_READY(uart))
ch = UART_READ(uart);
return ch;
}
static const struct rt_uart_ops m05x_uart_ops =
{
m05x_configure,
m05x_control,
m05x_putc,
m05x_getc,
};
#if defined(RT_USING_UART0)
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if (UART_IS_RX_READY(UART0)) {
rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART0 */
void rt_hw_usart_init(void)
{
#ifdef RT_USING_UART0
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
config.baud_rate = BAUD_RATE_115200;
serial0.ops = &m05x_uart_ops;
serial0.config = config;
/* register UART0 device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
UART0);
#endif /* RT_USING_UART0 */
}
bsp/nuvoton_m05x/drivers/usart.h
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/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-11-29 Bright the first version
*/
#ifndef __USART_H__
#define __USART_H__
#include <rthw.h>
#include <rtthread.h>
#define RT_USING_UART0
//#define RT_USING_UART1
void rt_hw_usart_init(void);
#endif
bsp/nuvoton_m05x/nuvoton_m05x.ld
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/*
* linker script for M051X with GNU ld
* Bright 2014-11-24
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 64k /* 64KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 4k /* 4K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x100;
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/nuvoton_m05x/nuvoton_m05x.sct
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00010000 { ; load region size_region
ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00001000 { ; RW data
.ANY (+RW +ZI)
}
}
bsp/nuvoton_m05x/project.uvprojx
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bsp/nuvoton_m05x/readme.txt
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board info:
Nu-Tiny-SDK
http://www.nuvoton.com
bsp/nuvoton_m05x/rtconfig.h
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bsp/nuvoton_m05x/rtconfig.py
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import os
# toolchains options
ARCH='arm'
CPU='cortex-m0'
CROSS_TOOL='keil'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'iar': # not support gcc
PLATFORM = 'iar'
EXEC_PATH = 'C:/IAR'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil'
elif CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:/GCC'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -std=gnu9x'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nuvoton_m05x.map,-cref,-u,Reset_Handler -T nuvoton_m05x.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread-nuvoton_m05x.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread-nuvoton_m05x.hex\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMSTM'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nuvoton_m05x.map --scatter nuvoton_m05x.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib'
EXEC_PATH += '/ARM/ARMCC/bin'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread-nuvoton_m05x.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M0'
AFLAGS += ' --fpu None'
LFLAGS = ' --config stm32f0xx_flash.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = ''
bsp/nuvoton_m05x/template.uvprojx
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bsp/nuvoton_m451/.gitignore
-6
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Nu_Link_Driver.ini
rmf.py
*.ewd
*.ewt
*.uvoptx
*.uvguix.*
bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 14/06/07 1:58a $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef[6144];
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
#endif /* ARM_COMMON_TABLES_H */
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bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmFunc.h
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bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmInstr.h
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bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc000.h
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bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc300.h
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bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/M451Series.h
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bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/system_M451Series.h
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/******************************************************************************
* @file system_M451Series.h
* @version V0.10
* $Revision: 7 $
* $Date: 15/09/02 10:02a $
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
*
* @note
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SYSTEM_M451SERIES_H__
#define __SYSTEM_M451SERIES_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*---------------------------------------------------------------------------------------------------------*/
/* Macro Definition */
/*---------------------------------------------------------------------------------------------------------*/
#ifndef DEBUG_PORT
# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __HSI (12000000UL) /*!< PLL default output is 72MHz */
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
#define __SYSTEM_CLOCK (1*__HXT)
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
/**
* Initialize the system
*
* @param None
* @return None
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param None
* @return None
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_M451SERIES_H__ */
/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/ARM/startup_M451Series.s
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bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/GCC/startup_M451Series.s
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bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/IAR/startup_M451Series.s
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bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/system_M451Series.c
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/******************************************************************************
* @file system_M451Series.c
* @version V0.10
* $Revision: 11 $
* $Date: 15/09/02 10:02a $
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
*
* @note
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M451Series.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
{
#if 1
uint32_t u32Freq, u32ClkSrc;
uint32_t u32HclkDiv;
/* Update PLL Clock */
PllClock = CLK_GetPLLClockFreq();
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
{
/* Use PLL clock */
u32Freq = PllClock;
}
else
{
/* Use the clock sources directly */
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
}
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
/* Update System Core Clock */
SystemCoreClock = u32Freq / u32HclkDiv;
//if(SystemCoreClock == 0)
// __BKPT(0);
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
#endif
}
/**
* Initialize the system
*
* @param None
* @return None
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
SYS_UnlockReg();
/* One-time POR18 */
if((SYS->PDID >> 12) == 0x945)
{
M32(GCR_BASE+0x14) |= BIT7;
}
/* Force to use INV type with HXT */
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
SYS_LockReg();
#ifdef EBI_INIT
extern void SYS_Init();
extern void EBI_Init();
SYS_UnlockReg();
SYS_Init();
EBI_Init();
SYS_LockReg();
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11 * 2)); /* set CP11 Full Access */
#endif
}
/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
bsp/nuvoton_m451/Libraries/Device/SConscript
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# RT-Thread building script for component
Import('rtconfig')
import os
from building import *
CPPDEFINES = []
cwd = GetCurrentDir()
src = Split('''
Nuvoton/M451Series/Source/system_M451Series.c
''')
CPPPATH = [cwd + '/Nuvoton/M451Series/Include']
CPPPATH += [os.path.dirname(cwd) + '/CMSIS/Include']
#add for startup script
if rtconfig.CROSS_TOOL == 'iar':
src = src + ['Nuvoton/M451Series/Source/IAR/startup_M451Series.s']
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['Nuvoton/M451Series/Source/ARM/startup_M451Series.s']
elif rtconfig.CROSS_TOOL == 'gcc':
src = src + ['Nuvoton/M451Series/Source/GCC/startup_M451Series.s']
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/nuvoton_m451/Libraries/SConscript
-15
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# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/nuvoton_m451/Libraries/StdDriver/SConscript
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import os
import rtconfig
Import('RTT_ROOT')
from building import *
CPPDEFINES = []
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('src/*.c')
# Remove retarget.c As there is a HardFaultHandler in it
for src_f in src:
if 'retarget.c' in src_f.path:
src.remove(src_f)
path = [cwd + '/inc']
group = DefineGroup('StdDriver', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/nuvoton_m451/Libraries/StdDriver/inc/acmp.h
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/**************************************************************************//**
* @file can.h
* @version V2.00
* $Revision: 9 $
* $Date: 15/08/11 10:26a $
* @brief M451 Series CAN Driver Header File
*
* @note
* Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __CAN_H__
#define __CAN_H__
#include "M451Series.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CAN_Driver CAN Driver
@{
*/
/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CAN Test Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAN_NORMAL_MODE 0
#define CAN_BASIC_MODE 1
/*---------------------------------------------------------------------------------------------------------*/
/* Message ID Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAN_STD_ID 0
#define CAN_EXT_ID 1
/*---------------------------------------------------------------------------------------------------------*/
/* Message Frame Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CAN_REMOTE_FRAME 0
#define CAN_DATA_FRAME 1
/*---------------------------------------------------------------------------------------------------------*/
/* CAN message structure */
/*---------------------------------------------------------------------------------------------------------*/
typedef struct
{
uint32_t IdType;
uint32_t FrameType;
uint32_t Id;
uint8_t DLC;
uint8_t Data[8];
} STR_CANMSG_T;
/*---------------------------------------------------------------------------------------------------------*/
/* CAN mask message structure */
/*---------------------------------------------------------------------------------------------------------*/
typedef struct
{
uint8_t u8Xtd;
uint8_t u8Dir;
uint32_t u32Id;
uint8_t u8IdType;
} STR_CANMASK_T;
#define MSG(id) (id)
/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
@{
*/
/**
* @brief Get interrupt status.
*
* @param[in] can The base address of can module.
*
* @return CAN module status register value.
*
* @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
* EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
*/
#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
/**
* @brief Get specified interrupt pending status.
*
* @param[in] can The base address of can module.
*
* @return The source of the interrupt.
*
* @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
* with the highest priority, disregarding their chronological order.
*/
#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
/**
* @brief Disable wake-up function.
*
* @param[in] can The base address of can module.
*
* @return None
*
* @details The macro is used to disable wake-up function.
*/
#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)
/**
* @brief Enable wake-up function.
*
* @param[in] can The base address of can module.
*
* @return None
*
* @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
*/
#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WUEN_WAKUP_EN_Msk)
/**
* @brief Get specified Message Object new data into bit value.
*
* @param[in] can The base address of can module.
* @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
*
* @return Specified Message Object new data into bit value.
*
* @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
* or by the Message Handler after reception of a Data Frame or after a successful transmission.
*/
#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
/*---------------------------------------------------------------------------------------------------------*/
/* Define CAN functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
void CAN_Close(CAN_T *tCAN);
void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CAN_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__CAN_H__
/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
bsp/nuvoton_m451/Libraries/StdDriver/inc/clk.h
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bsp/nuvoton_m451/Libraries/StdDriver/inc/crc.h
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/**************************************************************************//**
* @file crc.h
* @version V3.00
* $Revision: 6 $
* $Date: 15/08/11 10:26a $
* @brief M451 series CRC driver header file
*
* @note
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_H__
#define __CRC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CRC Polynomial Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CCITT 0x00000000UL /*!<CRC Polynomial Mode - CCITT */
#define CRC_8 0x40000000UL /*!<CRC Polynomial Mode - CRC8 */
#define CRC_16 0x80000000UL /*!<CRC Polynomial Mode - CRC16 */
#define CRC_32 0xC0000000UL /*!<CRC Polynomial Mode - CRC32 */
/*---------------------------------------------------------------------------------------------------------*/
/* Checksum, Write data Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CHECKSUM_COM 0x08000000UL /*!<CRC Checksum Complement */
#define CRC_CHECKSUM_RVS 0x02000000UL /*!<CRC Checksum Reverse */
#define CRC_WDATA_COM 0x04000000UL /*!<CRC Write Data Complement */
#define CRC_WDATA_RVS 0x01000000UL /*!<CRC Write Data Reverse */
/*---------------------------------------------------------------------------------------------------------*/
/* CPU Write Data Length Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CPU_WDATA_8 0x00000000UL /*!<CRC CPU Write Data length is 8-bit */
#define CRC_CPU_WDATA_16 0x10000000UL /*!<CRC CPU Write Data length is 16-bit */
#define CRC_CPU_WDATA_32 0x20000000UL /*!<CRC CPU Write Data length is 32-bit */
/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
@{
*/
/**
* @brief Set CRC Seed Value
*
* @param[in] u32Seed Seed value
*
* @return None
*
* @details This macro is used to set CRC seed value.
*
* @note User must to perform CRC_RST(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
* to CRC controller.
*/
#define CRC_SET_SEED(u32Seed) { CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CRCRST_Msk; }
/**
* @brief Get CRC Seed Value
*
* @param None
*
* @return CRC seed value
*
* @details This macro gets the current CRC seed value.
*/
#define CRC_GET_SEED() (CRC->SEED)
/**
* @brief CRC Write Data
*
* @param[in] u32Data Write data
*
* @return None
*
* @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
*/
#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
uint32_t CRC_GetChecksum(void);
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CRC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__CRC_H__
/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
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