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[BSP][STM32][F469-DISCO]Add lcd drivers

Browse Source 
Signed-off-by: Willian Chan <chentingwei@rt-thread.com>
This commit is contained in:
Willian Chan
2019-04-22 16:03:03 +08:00
parent d8bbf27d3c
commit 07ec9ec64c
20 changed files with 1628 additions and 1531 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/stm32/stm32f469-st-disco/.config
+20 -39
View File
@@ -14,15 +14,17 @@ CONFIG_RT_ALIGN_SIZE=4
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
@@ -99,7 +101,7 @@ CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
@@ -258,7 +260,6 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
#
# tools packages
@@ -288,12 +289,22 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
@@ -306,10 +317,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
#
# miscellaneous packages
@@ -335,35 +343,6 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F4=y
@@ -376,6 +355,7 @@ CONFIG_SOC_STM32F469NI=y
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_LCD_OTM8009A is not set
# CONFIG_BSP_USING_QSPI_FLASH is not set
#
@@ -389,6 +369,7 @@ CONFIG_BSP_USING_UART3=y
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_FMC is not set
# CONFIG_BSP_USING_USBD_FS is not set
# CONFIG_BSP_USING_LTDC is not set
#
# Board extended module Drivers
bsp/stm32/stm32f469-st-disco/applications/SConscript
+1
View File
@@ -5,6 +5,7 @@ cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Split("""
main.c
lcd_init.c
""")
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
+28
View File
@@ -0,0 +1,28 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-06-12 Tanek first version
*/
#include <rtthread.h>
#if defined(PKG_USING_GUIENGINE)
#include <rtgui/driver.h>
int lcd_init(void)
{
struct rt_device *device;
device = rt_device_find("lcd");
if (device)
{
rtgui_graphic_set_device(device);
}
return 0;
}
INIT_ENV_EXPORT(lcd_init);
#endif
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/.mxproject
+4 -4
View File
File diff suppressed because one or more lines are too long
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/CubeMX_Config.ioc
+112 -84
View File
@@ -1,4 +1,16 @@
#MicroXplorer Configuration settings - do not modify
DSIHOST_CKN.Mode=DSIHost_Video
DSIHOST_CKN.Signal=DSIHOST_CKN
DSIHOST_CKP.Mode=DSIHost_Video
DSIHOST_CKP.Signal=DSIHOST_CKP
DSIHOST_D0N.Mode=DSIHost_Video
DSIHOST_D0N.Signal=DSIHOST_D0N
DSIHOST_D0P.Mode=DSIHost_Video
DSIHOST_D0P.Signal=DSIHOST_D0P
DSIHOST_D1N.Mode=DSIHost_Video
DSIHOST_D1N.Signal=DSIHOST_D1N
DSIHOST_D1P.Mode=DSIHost_Video
DSIHOST_D1P.Signal=DSIHOST_D1P
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3
FMC.ExitSelfRefreshDelay1=7
FMC.IPParameters=CASLatency1,ReadBurst1,ReadBurst2,SDClockPeriod1,SDClockPeriod2,LoadToActiveDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1
@@ -16,29 +28,32 @@ FMC.SelfRefreshTime1=4
FMC.WriteRecoveryTime1=3
File.Version=6
I2S3.AudioFreq=I2S_AUDIOFREQ_16K
I2S3.ErrorAudioFreq=0.0 %
I2S3.ErrorAudioFreq=-0.26 %
I2S3.FullDuplexMode=I2S_FULLDUPLEXMODE_DISABLE
I2S3.IPParameters=Instance,VirtualMode,FullDuplexMode,RealAudioFreq,ErrorAudioFreq,AudioFreq,Standard,Mode
I2S3.Instance=SPI$Index
I2S3.Mode=I2S_MODE_MASTER_RX
I2S3.RealAudioFreq=16.0 KHz
I2S3.RealAudioFreq=15.957 KHz
I2S3.Standard=I2S_STANDARD_LSB
I2S3.VirtualMode=I2S_MODE_MASTER
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=CRC
Mcu.IP1=FMC
Mcu.IP10=USART3
Mcu.IP11=USB_OTG_FS
Mcu.IP2=GFXSIMULATOR
Mcu.IP3=I2S3
Mcu.IP4=NVIC
Mcu.IP5=PDM2PCM
Mcu.IP6=QUADSPI
Mcu.IP7=RCC
Mcu.IP8=SYS
Mcu.IP9=TIM4
Mcu.IPNb=12
Mcu.IP1=DMA2D
Mcu.IP10=RCC
Mcu.IP11=SYS
Mcu.IP12=TIM4
Mcu.IP13=USART3
Mcu.IP14=USB_OTG_FS
Mcu.IP2=DSIHOST
Mcu.IP3=FMC
Mcu.IP4=GFXSIMULATOR
Mcu.IP5=I2S3
Mcu.IP6=LTDC
Mcu.IP7=NVIC
Mcu.IP8=PDM2PCM
Mcu.IP9=QUADSPI
Mcu.IPNb=15
Mcu.Name=STM32F469NIHx
Mcu.Package=TFBGA216
Mcu.Pin0=PE1
@@ -65,64 +80,72 @@ Mcu.Pin27=PH14
Mcu.Pin28=PI0
Mcu.Pin29=PC15/OSC32_OUT
Mcu.Pin3=PA15
Mcu.Pin30=PH0/OSC_IN
Mcu.Pin31=PF2
Mcu.Pin32=PH1/OSC_OUT
Mcu.Pin33=PF3
Mcu.Pin34=PG8
Mcu.Pin35=PF4
Mcu.Pin36=PH3
Mcu.Pin37=PF7
Mcu.Pin38=PF6
Mcu.Pin39=PF5
Mcu.Pin30=DSIHOST_D1P
Mcu.Pin31=DSIHOST_D1N
Mcu.Pin32=PH0/OSC_IN
Mcu.Pin33=PF2
Mcu.Pin34=PH1/OSC_OUT
Mcu.Pin35=PF3
Mcu.Pin36=DSIHOST_CKP
Mcu.Pin37=DSIHOST_CKN
Mcu.Pin38=PG8
Mcu.Pin39=PF4
Mcu.Pin4=PA14
Mcu.Pin40=PH2
Mcu.Pin41=PD15
Mcu.Pin42=PD10
Mcu.Pin43=PF10
Mcu.Pin44=PF9
Mcu.Pin45=PF8
Mcu.Pin46=PD14
Mcu.Pin47=PD9
Mcu.Pin48=PD8
Mcu.Pin49=PC0
Mcu.Pin40=PH3
Mcu.Pin41=DSIHOST_D0P
Mcu.Pin42=DSIHOST_D0N
Mcu.Pin43=PF7
Mcu.Pin44=PF6
Mcu.Pin45=PF5
Mcu.Pin46=PH2
Mcu.Pin47=PD15
Mcu.Pin48=PD10
Mcu.Pin49=PF10
Mcu.Pin5=PA13
Mcu.Pin50=PF12
Mcu.Pin51=PG1
Mcu.Pin52=PF15
Mcu.Pin53=PD12
Mcu.Pin54=PD13
Mcu.Pin55=PH12
Mcu.Pin56=PF13
Mcu.Pin57=PG0
Mcu.Pin58=PE8
Mcu.Pin59=PG5
Mcu.Pin50=PF9
Mcu.Pin51=PF8
Mcu.Pin52=PD14
Mcu.Pin53=PD9
Mcu.Pin54=PD8
Mcu.Pin55=PC0
Mcu.Pin56=PF12
Mcu.Pin57=PG1
Mcu.Pin58=PF15
Mcu.Pin59=PD12
Mcu.Pin6=PB6
Mcu.Pin60=PG4
Mcu.Pin61=PH9
Mcu.Pin62=PH11
Mcu.Pin63=PF14
Mcu.Pin64=PF11
Mcu.Pin65=PE9
Mcu.Pin66=PE11
Mcu.Pin67=PE14
Mcu.Pin68=PB10
Mcu.Pin69=PH8
Mcu.Pin60=PD13
Mcu.Pin61=PH12
Mcu.Pin62=PF13
Mcu.Pin63=PG0
Mcu.Pin64=PE8
Mcu.Pin65=PG5
Mcu.Pin66=PG4
Mcu.Pin67=PH9
Mcu.Pin68=PH11
Mcu.Pin69=PF14
Mcu.Pin7=PG15
Mcu.Pin70=PH10
Mcu.Pin71=PE7
Mcu.Pin72=PE10
Mcu.Pin73=PE12
Mcu.Pin74=PE15
Mcu.Pin75=PE13
Mcu.Pin76=PB11
Mcu.Pin77=VP_CRC_VS_CRC
Mcu.Pin78=VP_PDM2PCM_VS_PDM2PCM
Mcu.Pin79=VP_SYS_VS_Systick
Mcu.Pin70=PF11
Mcu.Pin71=PE9
Mcu.Pin72=PE11
Mcu.Pin73=PE14
Mcu.Pin74=PB10
Mcu.Pin75=PH8
Mcu.Pin76=PH10
Mcu.Pin77=PE7
Mcu.Pin78=PE10
Mcu.Pin79=PE12
Mcu.Pin8=PD6
Mcu.Pin80=VP_TIM4_VS_ControllerModeClock
Mcu.Pin80=PE15
Mcu.Pin81=PE13
Mcu.Pin82=PB11
Mcu.Pin83=VP_CRC_VS_CRC
Mcu.Pin84=VP_DMA2D_VS_DMA2D
Mcu.Pin85=VP_LTDC_DSIMode
Mcu.Pin86=VP_PDM2PCM_VS_PDM2PCM
Mcu.Pin87=VP_SYS_VS_Systick
Mcu.Pin88=VP_TIM4_VS_ControllerModeClock
Mcu.Pin9=PD0
Mcu.PinsNb=81
Mcu.PinsNb=89
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F469NIHx
@@ -292,7 +315,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_USART3_UART_Init-USART3-false-HAL-true,3-MX_FMC_Init-FMC-false-HAL-true,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_GFXSIMULATOR_Init-GFXSIMULATOR-false-HAL-true,6-MX_CRC_Init-CRC-false-HAL-true,7-MX_I2S3_Init-I2S3-false-HAL-true,8-MX_TIM4_Init-TIM4-false-HAL-true,9-MX_PDM2PCM_Init-PDM2PCM-false-HAL-true,10-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,11-SystemClock_Config-RCC-false-HAL-false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_USART3_UART_Init-USART3-false-HAL-true,3-MX_FMC_Init-FMC-false-HAL-true,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_GFXSIMULATOR_Init-GFXSIMULATOR-false-HAL-true,6-MX_CRC_Init-CRC-false-HAL-true,7-MX_I2S3_Init-I2S3-false-HAL-true,8-MX_TIM4_Init-TIM4-false-HAL-true,9-MX_PDM2PCM_Init-PDM2PCM-false-HAL-true,10-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,11-SystemClock_Config-RCC-false-HAL-false,12-MX_LTDC_Init-LTDC-false-HAL-true,13-MX_DMA2D_Init-DMA2D-false-HAL-true,14-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true
QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_5_CYCLE
QUADSPI.ClockPrescaler=1
QUADSPI.FifoThreshold=4
@@ -307,29 +330,30 @@ RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=90000000
RCC.APB2TimFreq_Value=180000000
RCC.CortexFreq_Value=180000000
RCC.DSIFreq_Value=20000000
RCC.DSITXEscFreq_Value=5000000
RCC.DSIFreq_Value=32000000
RCC.DSITXEscFreq_Value=8000000
RCC.EthernetFreq_Value=180000000
RCC.FCLKCortexFreq_Value=180000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=180000000
RCC.HSE_VALUE=8000000
RCC.I2SFreq_Value=192000000
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DSIFreq_Value,DSITXEscFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2SFreq_Value,LCDTFTFreq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLDSIFreq_Value,PLLDSIVCOFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLRFreq_Value,PLLSAIN,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBCLockSelection,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.I2SFreq_Value=96000000
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DSIFreq_Value,DSITXEscFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2SFreq_Value,LCDTFTFreq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLDSIFreq_Value,PLLDSINDIV,PLLDSIVCOFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLR,PLLRCLKFreq_Value,PLLRFreq_Value,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBCLockSelection,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.LCDTFTFreq_Value=48000000
RCC.MCO2PinFreq_Value=180000000
RCC.PLLCLKFreq_Value=180000000
RCC.PLLDSIFreq_Value=160000000
RCC.PLLDSIVCOFreq_Value=320000000
RCC.PLLI2SQCLKFreq_Value=96000000
RCC.PLLI2SRCLKFreq_Value=192000000
RCC.PLLM=4
RCC.PLLN=180
RCC.PLLQ=3
RCC.PLLQCLKFreq_Value=120000000
RCC.PLLRCLKFreq_Value=180000000
RCC.PLLRFreq_Value=180000000
RCC.PLLSAIN=96
RCC.PLLDSIFreq_Value=256000000
RCC.PLLDSINDIV=32
RCC.PLLDSIVCOFreq_Value=512000000
RCC.PLLI2SQCLKFreq_Value=48000000
RCC.PLLI2SRCLKFreq_Value=96000000
RCC.PLLM=8
RCC.PLLN=360
RCC.PLLQ=9
RCC.PLLQCLKFreq_Value=40000000
RCC.PLLR=6
RCC.PLLRCLKFreq_Value=60000000
RCC.PLLRFreq_Value=60000000
RCC.PLLSAIP=RCC_PLLSAIP_DIV4
RCC.PLLSAIPCLKFreq_Value=48000000
RCC.PLLSAIQCLKFreq_Value=48000000
@@ -344,8 +368,8 @@ RCC.SYSCLKFreq_VALUE=180000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.USBCLockSelection=RCC_CLK48CLKSOURCE_PLLSAIP
RCC.USBFreq_Value=48000000
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOI2SOutputFreq_Value=192000000
RCC.VCOInputFreq_Value=1000000
RCC.VCOOutputFreq_Value=360000000
RCC.VCOSAIOutputFreq_Value=192000000
SH.FMC_A0.0=FMC_A0,12b-sda1
@@ -472,6 +496,10 @@ USB_OTG_FS.IPParameters=VirtualMode
USB_OTG_FS.VirtualMode=Device_Only
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate
VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D
VP_LTDC_DSIMode.Mode=RGB888
VP_LTDC_DSIMode.Signal=LTDC_DSIMode
VP_PDM2PCM_VS_PDM2PCM.Mode=PDM2PCM_Channel
VP_PDM2PCM_VS_PDM2PCM.Signal=PDM2PCM_VS_PDM2PCM
VP_SYS_VS_Systick.Mode=SysTick
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
+3 -3
View File
@@ -56,7 +56,7 @@
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_DMA2D_MODULE_ENABLED
/* #define HAL_ETH_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
@@ -67,7 +67,7 @@
/* #define HAL_I2C_MODULE_ENABLED */
#define HAL_I2S_MODULE_ENABLED
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
#define HAL_LTDC_MODULE_ENABLED
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
@@ -82,7 +82,7 @@
/* #define HAL_WWDG_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
#define HAL_DSI_MODULE_ENABLED
/* #define HAL_QSPI_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED
/* #define HAL_CEC_MODULE_ENABLED */
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h
-97
View File
@@ -1,97 +0,0 @@
/**
******************************************************************************
* @file pdm2pcm_glo.h
* @author MCD Application Team
* @version V3.0.0
* @date 28-February-2017
* @brief Global header for PDM2PCM conversion code
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Image SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_image_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PDM2PCM_FILTER_H
#define __PDM2PCM_FILTER_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/* Exported constants --------------------------------------------------------*/
#define PDM_FILTER_ENDIANNESS_LE ((uint16_t)0x0000)
#define PDM_FILTER_ENDIANNESS_BE ((uint16_t)0x0001)
#define PDM_FILTER_BIT_ORDER_LSB ((uint16_t)0x0000)
#define PDM_FILTER_BIT_ORDER_MSB ((uint16_t)0x0001)
#define PDM_FILTER_DEC_FACTOR_48 ((uint16_t)0x0001)
#define PDM_FILTER_DEC_FACTOR_64 ((uint16_t)0x0002)
#define PDM_FILTER_DEC_FACTOR_80 ((uint16_t)0x0003)
#define PDM_FILTER_DEC_FACTOR_128 ((uint16_t)0x0004)
#define PDM_FILTER_DEC_FACTOR_16 ((uint16_t)0x0005)
#define PDM_FILTER_DEC_FACTOR_24 ((uint16_t)0x0006)
#define PDM_FILTER_DEC_FACTOR_32 ((uint16_t)0x0007)
#define PDM_FILTER_INIT_ERROR ((uint16_t)0x0010)
#define PDM_FILTER_CONFIG_ERROR ((uint16_t)0x0020)
#define PDM_FILTER_ENDIANNESS_ERROR ((uint16_t)0x0001)
#define PDM_FILTER_BIT_ORDER_ERROR ((uint16_t)0x0002)
#define PDM_FILTER_CRC_LOCK_ERROR ((uint16_t)0x0004)
#define PDM_FILTER_DECIMATION_ERROR ((uint16_t)0x0008)
#define PDM_FILTER_GAIN_ERROR ((uint16_t)0x0040)
#define PDM_FILTER_SAMPLES_NUMBER_ERROR ((uint16_t)0x0080)
#define PDM2PCM_INTERNAL_MEMORY_SIZE 16
/* Exported types ------------------------------------------------------------*/
typedef struct{
uint16_t bit_order;
uint16_t endianness;
uint32_t high_pass_tap;
uint16_t in_ptr_channels;
uint16_t out_ptr_channels;
uint32_t pInternalMemory[PDM2PCM_INTERNAL_MEMORY_SIZE];
}PDM_Filter_Handler_t;
typedef struct{
uint16_t decimation_factor;
uint16_t output_samples_number;
int16_t mic_gain;
}PDM_Filter_Config_t;
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
uint32_t PDM_Filter_Init(PDM_Filter_Handler_t *pHandler);
uint32_t PDM_Filter_setConfig(PDM_Filter_Handler_t *pHandler, PDM_Filter_Config_t *pConfig);
uint32_t PDM_Filter_getConfig(PDM_Filter_Handler_t *pHandler, PDM_Filter_Config_t *pConfig);
uint32_t PDM_Filter_deInterleave(void *pDataIn, void *pDataOut, PDM_Filter_Handler_t * pHandler);
uint32_t PDM_Filter(void *pDataIn, void *pDataOut, PDM_Filter_Handler_t *pHandler);
#ifdef __cplusplus
}
#endif
#endif /* __PDM2PCM_FILTER_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/main.c
+247 -6
View File
@@ -45,8 +45,14 @@
/* Private variables ---------------------------------------------------------*/
CRC_HandleTypeDef hcrc;
DMA2D_HandleTypeDef hdma2d;
DSI_HandleTypeDef hdsi;
I2S_HandleTypeDef hi2s3;
LTDC_HandleTypeDef hltdc;
QSPI_HandleTypeDef hqspi;
TIM_HandleTypeDef htim4;
@@ -72,6 +78,9 @@ static void MX_CRC_Init(void);
static void MX_I2S3_Init(void);
static void MX_TIM4_Init(void);
static void MX_USB_OTG_FS_PCD_Init(void);
static void MX_LTDC_Init(void);
static void MX_DMA2D_Init(void);
static void MX_DSIHOST_DSI_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@@ -118,6 +127,9 @@ int main(void)
MX_TIM4_Init();
MX_PDM2PCM_Init();
MX_USB_OTG_FS_PCD_Init();
MX_LTDC_Init();
MX_DMA2D_Init();
MX_DSIHOST_DSI_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@@ -155,11 +167,11 @@ void SystemClock_Config(void)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 180;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 360;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 3;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLR = 6;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
@@ -183,11 +195,14 @@ void SystemClock_Config(void)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_CLK48
|RCC_PERIPHCLK_LTDC;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
@@ -222,6 +237,150 @@ static void MX_CRC_Init(void)
}
/**
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
/* USER CODE BEGIN DMA2D_Init 0 */
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
hdma2d.Init.Mode = DMA2D_M2M;
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
hdma2d.Init.OutputOffset = 0;
hdma2d.LayerCfg[1].InputOffset = 0;
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
hdma2d.LayerCfg[1].InputAlpha = 0;
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
{
Error_Handler();
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
/**
* @brief DSIHOST Initialization Function
* @param None
* @retval None
*/
static void MX_DSIHOST_DSI_Init(void)
{
/* USER CODE BEGIN DSIHOST_Init 0 */
/* USER CODE END DSIHOST_Init 0 */
DSI_PLLInitTypeDef PLLInit = {0};
DSI_HOST_TimeoutTypeDef HostTimeouts = {0};
DSI_PHY_TimerTypeDef PhyTimings = {0};
DSI_VidCfgTypeDef VidCfg = {0};
/* USER CODE BEGIN DSIHOST_Init 1 */
/* USER CODE END DSIHOST_Init 1 */
hdsi.Instance = DSI;
hdsi.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE;
hdsi.Init.TXEscapeCkdiv = 4;
hdsi.Init.NumberOfLanes = DSI_ONE_DATA_LANE;
PLLInit.PLLNDIV = 32;
PLLInit.PLLIDF = DSI_PLL_IN_DIV1;
PLLInit.PLLODF = DSI_PLL_OUT_DIV1;
if (HAL_DSI_Init(&hdsi, &PLLInit) != HAL_OK)
{
Error_Handler();
}
HostTimeouts.TimeoutCkdiv = 1;
HostTimeouts.HighSpeedTransmissionTimeout = 0;
HostTimeouts.LowPowerReceptionTimeout = 0;
HostTimeouts.HighSpeedReadTimeout = 0;
HostTimeouts.LowPowerReadTimeout = 0;
HostTimeouts.HighSpeedWriteTimeout = 0;
HostTimeouts.HighSpeedWritePrespMode = DSI_HS_PM_DISABLE;
HostTimeouts.LowPowerWriteTimeout = 0;
HostTimeouts.BTATimeout = 0;
if (HAL_DSI_ConfigHostTimeouts(&hdsi, &HostTimeouts) != HAL_OK)
{
Error_Handler();
}
PhyTimings.ClockLaneHS2LPTime = 20;
PhyTimings.ClockLaneLP2HSTime = 18;
PhyTimings.DataLaneHS2LPTime = 10;
PhyTimings.DataLaneLP2HSTime = 13;
PhyTimings.DataLaneMaxReadTime = 0;
PhyTimings.StopWaitTime = 0;
if (HAL_DSI_ConfigPhyTimer(&hdsi, &PhyTimings) != HAL_OK)
{
Error_Handler();
}
if (HAL_DSI_ConfigFlowControl(&hdsi, DSI_FLOW_CONTROL_BTA) != HAL_OK)
{
Error_Handler();
}
if (HAL_DSI_SetLowPowerRXFilter(&hdsi, 10000) != HAL_OK)
{
Error_Handler();
}
if (HAL_DSI_ConfigErrorMonitor(&hdsi, HAL_DSI_ERROR_NONE) != HAL_OK)
{
Error_Handler();
}
VidCfg.VirtualChannelID = 0;
VidCfg.ColorCoding = DSI_RGB888;
VidCfg.LooselyPacked = DSI_LOOSELY_PACKED_DISABLE;
VidCfg.Mode = DSI_VID_MODE_NB_PULSES;
VidCfg.PacketSize = 1;
VidCfg.NumberOfChunks = 640;
VidCfg.NullPacketSize = 0;
VidCfg.HSPolarity = DSI_HSYNC_ACTIVE_LOW;
VidCfg.VSPolarity = DSI_VSYNC_ACTIVE_LOW;
VidCfg.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH;
VidCfg.HorizontalSyncActive = 5;
VidCfg.HorizontalBackPorch = 5;
VidCfg.HorizontalLine = 441;
VidCfg.VerticalSyncActive = 4;
VidCfg.VerticalBackPorch = 2;
VidCfg.VerticalFrontPorch = 2;
VidCfg.VerticalActive = 480;
VidCfg.LPCommandEnable = DSI_LP_COMMAND_DISABLE;
VidCfg.LPLargestPacketSize = 0;
VidCfg.LPVACTLargestPacketSize = 0;
VidCfg.LPHorizontalFrontPorchEnable = DSI_LP_HFP_DISABLE;
VidCfg.LPHorizontalBackPorchEnable = DSI_LP_HBP_DISABLE;
VidCfg.LPVerticalActiveEnable = DSI_LP_VACT_DISABLE;
VidCfg.LPVerticalFrontPorchEnable = DSI_LP_VFP_DISABLE;
VidCfg.LPVerticalBackPorchEnable = DSI_LP_VBP_DISABLE;
VidCfg.LPVerticalSyncActiveEnable = DSI_LP_VSYNC_DISABLE;
VidCfg.FrameBTAAcknowledgeEnable = DSI_FBTAA_DISABLE;
if (HAL_DSI_ConfigVideoMode(&hdsi, &VidCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_DSI_SetGenericVCID(&hdsi, 0) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DSIHOST_Init 2 */
/* USER CODE END DSIHOST_Init 2 */
}
/**
* @brief GFXSIMULATOR Initialization Function
* @param None
@@ -277,6 +436,88 @@ static void MX_I2S3_Init(void)
}
/**
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
LTDC_LayerCfgTypeDef pLayerCfg1 = {0};
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
hltdc.Init.HorizontalSync = 7;
hltdc.Init.VerticalSync = 3;
hltdc.Init.AccumulatedHBP = 14;
hltdc.Init.AccumulatedVBP = 5;
hltdc.Init.AccumulatedActiveW = 654;
hltdc.Init.AccumulatedActiveH = 485;
hltdc.Init.TotalWidth = 660;
hltdc.Init.TotalHeigh = 487;
hltdc.Init.Backcolor.Blue = 0;
hltdc.Init.Backcolor.Green = 0;
hltdc.Init.Backcolor.Red = 0;
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
{
Error_Handler();
}
pLayerCfg.WindowX0 = 0;
pLayerCfg.WindowX1 = 0;
pLayerCfg.WindowY0 = 0;
pLayerCfg.WindowY1 = 0;
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
pLayerCfg.Alpha = 0;
pLayerCfg.Alpha0 = 0;
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
pLayerCfg.FBStartAdress = 0;
pLayerCfg.ImageWidth = 0;
pLayerCfg.ImageHeight = 0;
pLayerCfg.Backcolor.Blue = 0;
pLayerCfg.Backcolor.Green = 0;
pLayerCfg.Backcolor.Red = 0;
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
{
Error_Handler();
}
pLayerCfg1.WindowX0 = 0;
pLayerCfg1.WindowX1 = 0;
pLayerCfg1.WindowY0 = 0;
pLayerCfg1.WindowY1 = 0;
pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
pLayerCfg1.Alpha = 0;
pLayerCfg1.Alpha0 = 0;
pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
pLayerCfg1.FBStartAdress = 0;
pLayerCfg1.ImageWidth = 0;
pLayerCfg1.ImageHeight = 0;
pLayerCfg1.Backcolor.Blue = 0;
pLayerCfg1.Backcolor.Green = 0;
pLayerCfg1.Backcolor.Red = 0;
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
/**
* @brief QUADSPI Initialization Function
* @param None
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
+132
View File
@@ -123,6 +123,94 @@ void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
}
/**
* @brief DMA2D MSP Initialization
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
if(hdma2d->Instance==DMA2D)
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
/* USER CODE BEGIN DMA2D_MspInit 1 */
/* USER CODE END DMA2D_MspInit 1 */
}
}
/**
* @brief DMA2D MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
{
if(hdma2d->Instance==DMA2D)
{
/* USER CODE BEGIN DMA2D_MspDeInit 0 */
/* USER CODE END DMA2D_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DMA2D_CLK_DISABLE();
/* USER CODE BEGIN DMA2D_MspDeInit 1 */
/* USER CODE END DMA2D_MspDeInit 1 */
}
}
/**
* @brief DSI MSP Initialization
* This function configures the hardware resources used in this example
* @param hdsi: DSI handle pointer
* @retval None
*/
void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
{
if(hdsi->Instance==DSI)
{
/* USER CODE BEGIN DSI_MspInit 0 */
/* USER CODE END DSI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DSI_CLK_ENABLE();
/* USER CODE BEGIN DSI_MspInit 1 */
/* USER CODE END DSI_MspInit 1 */
}
}
/**
* @brief DSI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdsi: DSI handle pointer
* @retval None
*/
void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
{
if(hdsi->Instance==DSI)
{
/* USER CODE BEGIN DSI_MspDeInit 0 */
/* USER CODE END DSI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DSI_CLK_DISABLE();
/* USER CODE BEGIN DSI_MspDeInit 1 */
/* USER CODE END DSI_MspDeInit 1 */
}
}
/**
* @brief I2S MSP Initialization
* This function configures the hardware resources used in this example
@@ -215,6 +303,50 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s)
}
/**
* @brief LTDC MSP Initialization
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
if(hltdc->Instance==LTDC)
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
/**
* @brief LTDC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
{
if(hltdc->Instance==LTDC)
{
/* USER CODE BEGIN LTDC_MspDeInit 0 */
/* USER CODE END LTDC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LTDC_CLK_DISABLE();
/* USER CODE BEGIN LTDC_MspDeInit 1 */
/* USER CODE END LTDC_MspDeInit 1 */
}
}
/**
* @brief QSPI MSP Initialization
* This function configures the hardware resources used in this example
bsp/stm32/stm32f469-st-disco/board/Kconfig
+12 -2
View File
@@ -6,11 +6,17 @@ config SOC_STM32F469NI
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
select BSP_USING_FMC
default n
config BSP_USING_LCD_OTM8009A
bool "Enable LCD OTM8009A"
select BSP_USING_SDRAM
select BSP_USING_LTDC
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (N25Q128A qspi1)"
select BSP_USING_QSPI
@@ -19,6 +25,7 @@ menu "Onboard Peripheral Drivers"
select PKG_USING_FAL
select FAL_USING_SFUD_PORT
default n
config BSP_MOUNT_QSPI_WITH_LFS
bool "Mount QSPI flash to / with little fs"
depends on BSP_USING_QSPI_FLASH
@@ -29,7 +36,6 @@ menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
@@ -68,6 +74,10 @@ menu "On-chip Peripheral Drivers"
bool "Enable OTGFS as USB device"
select RT_USING_USB_DEVICE
default n
config BSP_USING_LTDC
bool "Enable LTDC"
default n
endmenu
menu "Board extended module Drivers"
bsp/stm32/stm32f469-st-disco/board/SConscript
+3
View File
@@ -17,6 +17,9 @@ if GetDepend(['BSP_USING_QSPI_FLASH']):
if GetDepend(['PKG_USING_FAL']):
src += Glob('ports/qspi_mnt.c')
if GetDepend(['BSP_USING_LCD_OTM8009A']):
src += Glob('ports/drv_lcd_otm8009a.c')
path = [cwd]
path += [cwd + '/CubeMX_Config/Inc']
bsp/stm32/stm32f469-st-disco/board/board.c
+9 -6
View File
@@ -27,11 +27,11 @@ void SystemClock_Config(void)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 180;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 360;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 3;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLR = 6;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
@@ -55,11 +55,14 @@ void SystemClock_Config(void)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_CLK48
|RCC_PERIPHCLK_LTDC;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
bsp/stm32/stm32f469-st-disco/board/ports/drv_lcd_otm8009a.c
+525
View File
File diff suppressed because it is too large Load Diff
bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
+23
View File
@@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-07-28 liu2guang the first version for STM32F469NI-Discovery.
*/
#ifndef __DRV_LCD_H_
#define __DRV_LCD_H_
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
rt_err_t otm8009a_init(void);
void otm8009a_layer_init(uint16_t index, uint32_t framebuffer);
void lcd_clear(uint32_t color);
void lcd_fill_rect(uint16_t x_pos, uint16_t y_pos, uint16_t width, uint16_t height);
#endif
bsp/stm32/stm32f469-st-disco/project.ewp
+36 -1
View File
@@ -346,6 +346,7 @@
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\board\ports</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\applications</state>
@@ -1375,6 +1376,7 @@
<state>$PROJ_DIR$\..\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\board\ports</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\applications</state>
@@ -2086,7 +2088,7 @@
<name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\mem.c</name>
<name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
@@ -2112,6 +2114,9 @@
<file>
<name>$PROJ_DIR$\applications\main.c</name>
</file>
<file>
<name>$PROJ_DIR$\applications\lcd_init.c</name>
</file>
</group>
<group>
<name>Drivers</name>
@@ -2202,6 +2207,36 @@
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\msh_file.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_error.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_init.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_node.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c</name>
</file>
<file>
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<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_var.c</name>
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<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c</name>
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<name>$PROJ_DIR$\..\..\..\components\finsh\finsh_token.c</name>
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<name>STM32_HAL</name>
bsp/stm32/stm32f469-st-disco/project.uvopt
+3 -1003
View File
File diff suppressed because it is too large Load Diff
bsp/stm32/stm32f469-st-disco/project.uvoptx
+175 -43
View File
@@ -392,6 +392,18 @@
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@@ -550,7 +562,7 @@
<RteFlg>0</RteFlg>
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -562,7 +574,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -574,7 +586,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -586,7 +598,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -598,7 +610,7 @@
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<FileNumber>33</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -610,7 +622,7 @@
</File>
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<FileNumber>33</FileNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -622,7 +634,7 @@
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<File>
<GroupNumber>5</GroupNumber>
<FileNumber>34</FileNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -634,7 +646,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>35</FileNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -646,7 +658,7 @@
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<File>
<GroupNumber>5</GroupNumber>
<FileNumber>36</FileNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -666,7 +678,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>37</FileNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -678,7 +690,7 @@
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>38</FileNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -690,7 +702,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>39</FileNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -702,7 +714,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>40</FileNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -714,7 +726,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>41</FileNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -726,7 +738,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>42</FileNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -736,6 +748,126 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<File>
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<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\finsh_compiler.c</PathWithFileName>
<FilenameWithoutPath>finsh_compiler.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<GroupNumber>6</GroupNumber>
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\finsh_error.c</PathWithFileName>
<FilenameWithoutPath>finsh_error.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\finsh_heap.c</PathWithFileName>
<FilenameWithoutPath>finsh_heap.c</FilenameWithoutPath>
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<PathWithFileName>..\..\..\components\finsh\finsh_init.c</PathWithFileName>
<FilenameWithoutPath>finsh_init.c</FilenameWithoutPath>
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<PathWithFileName>..\..\..\components\finsh\finsh_node.c</PathWithFileName>
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<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<PathWithFileName>..\..\..\components\finsh\finsh_ops.c</PathWithFileName>
<FilenameWithoutPath>finsh_ops.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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<PathWithFileName>..\..\..\components\finsh\finsh_parser.c</PathWithFileName>
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\finsh_var.c</PathWithFileName>
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\finsh_vm.c</PathWithFileName>
<FilenameWithoutPath>finsh_vm.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<GroupNumber>6</GroupNumber>
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<PathWithFileName>..\..\..\components\finsh\finsh_token.c</PathWithFileName>
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<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
@@ -746,7 +878,7 @@
<RteFlg>0</RteFlg>
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -758,7 +890,7 @@
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@@ -770,7 +902,7 @@
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@@ -782,7 +914,7 @@
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@@ -794,7 +926,7 @@
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@@ -806,7 +938,7 @@
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@@ -818,7 +950,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -830,7 +962,7 @@
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@@ -842,7 +974,7 @@
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@@ -854,7 +986,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
@@ -866,7 +998,7 @@
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@@ -878,7 +1010,7 @@
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@@ -890,7 +1022,7 @@
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@@ -902,7 +1034,7 @@
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@@ -914,7 +1046,7 @@
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@@ -926,7 +1058,7 @@
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@@ -938,7 +1070,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
bsp/stm32/stm32f469-st-disco/project.uvproj
+234 -57
View File
File diff suppressed because it is too large Load Diff
bsp/stm32/stm32f469-st-disco/project.uvprojx
+55
View File
@@ -467,6 +467,11 @@
<FileType>1</FileType>
<FilePath>applications\main.c</FilePath>
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<FileName>lcd_init.c</FileName>
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<FilePath>applications\lcd_init.c</FilePath>
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@@ -617,6 +622,56 @@
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<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
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<FilePath>..\..\..\components\finsh\finsh_compiler.c</FilePath>
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<FileName>finsh_error.c</FileName>
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bsp/stm32/stm32f469-st-disco/rtconfig.h
+6 -186
View File
@@ -7,32 +7,19 @@
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
/* RT_USING_ARCH_DATA_TYPE is not set */
/* RT_USING_SMP is not set */
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* RT_DEBUG_INIT_CONFIG is not set */
/* RT_DEBUG_THREAD_CONFIG is not set */
/* RT_DEBUG_SCHEDULER_CONFIG is not set */
/* RT_DEBUG_IPC_CONFIG is not set */
/* RT_DEBUG_TIMER_CONFIG is not set */
/* RT_DEBUG_IRQ_CONFIG is not set */
/* RT_DEBUG_MEM_CONFIG is not set */
/* RT_DEBUG_SLAB_CONFIG is not set */
/* RT_DEBUG_MEMHEAP_CONFIG is not set */
/* RT_DEBUG_MODULE_CONFIG is not set */
/* Inter-Thread communication */
@@ -41,23 +28,17 @@
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* RT_USING_SIGNALS is not set */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
/* RT_USING_SMALL_MEM is not set */
/* RT_USING_SLAB is not set */
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
/* RT_USING_DEVICE_OPS is not set */
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart3"
@@ -65,7 +46,6 @@
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
/* RT-Thread Components */
@@ -76,7 +56,6 @@
/* C++ features */
/* RT_USING_CPLUSPLUS is not set */
/* Command shell */
@@ -86,247 +65,95 @@
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
/* FINSH_ECHO_DISABLE_DEFAULT is not set */
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* RT_USING_DFS is not set */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
/* RT_USING_SYSTEM_WORKQUEUE is not set */
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_CPUTIME is not set */
/* RT_USING_I2C is not set */
#define RT_USING_PIN
/* RT_USING_ADC is not set */
/* RT_USING_PWM is not set */
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
/* RT_USING_MTD is not set */
/* RT_USING_PM is not set */
/* RT_USING_RTC is not set */
/* RT_USING_SDIO is not set */
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_AUDIO is not set */
/* RT_USING_SENSOR is not set */
/* Using WiFi */
/* RT_USING_WIFI is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
/* RT_USING_LIBC is not set */
/* RT_USING_PTHREADS is not set */
/* Network */
/* Socket abstraction layer */
/* RT_USING_SAL is not set */
/* light weight TCP/IP stack */
/* RT_USING_LWIP is not set */
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* AT commands */
/* RT_USING_AT is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* RT_USING_ULOG is not set */
/* RT_USING_UTEST is not set */
/* RT_USING_LWP is not set */
/* RT-Thread online packages */
/* IoT - internet of things */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_WEBNET is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_JSMN is not set */
/* PKG_USING_LIBMODBUS is not set */
/* PKG_USING_LJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* Wi-Fi */
/* Marvell WiFi */
/* PKG_USING_WLANMARVELL is not set */
/* Wiced WiFi */
/* PKG_USING_WLAN_WICED is not set */
/* PKG_USING_RW007 is not set */
/* PKG_USING_COAP is not set */
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
/* PKG_USING_AT_DEVICE is not set */
/* PKG_USING_WIZNET is not set */
/* IoT Cloud */
/* PKG_USING_ONENET is not set */
/* PKG_USING_GAGENT_CLOUD is not set */
/* PKG_USING_ALI_IOTKIT is not set */
/* PKG_USING_AZURE is not set */
/* PKG_USING_TENCENT_IOTKIT is not set */
/* PKG_USING_NIMBLE is not set */
/* PKG_USING_OTA_DOWNLOADER is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* PKG_USING_TINYCRYPT is not set */
/* language packages */
/* PKG_USING_LUA is not set */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* PKG_USING_OPENMV is not set */
/* PKG_USING_MUPDF is not set */
/* PKG_USING_STEMWIN is not set */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYFLASH is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* PKG_USING_RDB is not set */
/* PKG_USING_QRCODE is not set */
/* PKG_USING_ULOG_EASYFLASH is not set */
/* PKG_USING_ADBD is not set */
/* system packages */
/* PKG_USING_GUIENGINE is not set */
/* PKG_USING_PERSIMMON is not set */
/* PKG_USING_CAIRO is not set */
/* PKG_USING_PIXMAN is not set */
/* PKG_USING_LWEXT4 is not set */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_FAL is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* PKG_USING_LITTLEVGL2RTT is not set */
/* PKG_USING_CMSIS is not set */
/* PKG_USING_DFS_YAFFS is not set */
/* PKG_USING_LITTLEFS is not set */
/* PKG_USING_THREAD_POOL is not set */
/* peripheral libraries and drivers */
/* PKG_USING_SENSORS_DRIVERS is not set */
/* PKG_USING_REALTEK_AMEBA is not set */
/* PKG_USING_SHT2X is not set */
/* PKG_USING_AHT10 is not set */
/* PKG_USING_AP3216C is not set */
/* PKG_USING_STM32_SDIO is not set */
/* PKG_USING_ICM20608 is not set */
/* PKG_USING_U8G2 is not set */
/* PKG_USING_BUTTON is not set */
/* PKG_USING_MPU6XXX is not set */
/* PKG_USING_PCF8574 is not set */
/* PKG_USING_SX12XX is not set */
/* PKG_USING_SIGNAL_LED is not set */
/* PKG_USING_WM_LIBRARIES is not set */
/* PKG_USING_KENDRYTE_SDK is not set */
/* PKG_USING_INFRARED is not set */
/* PKG_USING_ROSSERIAL is not set */
/* sensors drivers */
/* miscellaneous packages */
/* PKG_USING_LIBCSV is not set */
/* PKG_USING_OPTPARSE is not set */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* PKG_USING_QUICKLZ is not set */
/* PKG_USING_MULTIBUTTON is not set */
/* PKG_USING_CANFESTIVAL is not set */
/* PKG_USING_ZLIB is not set */
/* PKG_USING_DSTR is not set */
/* PKG_USING_TINYFRAME is not set */
/* PKG_USING_KENDRYTE_DEMO is not set */
/* samples: kernel and components samples */
/* PKG_USING_KERNEL_SAMPLES is not set */
/* PKG_USING_FILESYSTEM_SAMPLES is not set */
/* PKG_USING_NETWORK_SAMPLES is not set */
/* PKG_USING_PERIPHERAL_SAMPLES is not set */
/* PKG_USING_HELLO is not set */
/* PKG_USING_VI is not set */
/* PKG_USING_NNOM is not set */
/* Privated Packages of RealThread */
/* PKG_USING_CODEC is not set */
/* PKG_USING_PLAYER is not set */
/* PKG_USING_MPLAYER is not set */
/* PKG_USING_PERSIMMON_SRC is not set */
/* PKG_USING_JS_PERSIMMON is not set */
/* PKG_USING_JERRYSCRIPT_WIN32 is not set */
/* Network Utilities */
/* PKG_USING_WICED is not set */
/* PKG_USING_CLOUDSDK is not set */
/* PKG_USING_COREMARK is not set */
/* PKG_USING_POWER_MANAGER is not set */
/* PKG_USING_RT_OTA is not set */
/* PKG_USING_RDBD_SRC is not set */
/* PKG_USING_RTINSIGHT is not set */
/* PKG_USING_SMARTCONFIG is not set */
/* PKG_USING_RTX is not set */
/* RT_USING_TESTCASE is not set */
/* PKG_USING_NGHTTP2 is not set */
/* PKG_USING_AVS is not set */
/* PKG_USING_STS is not set */
/* PKG_USING_DLMS is not set */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F4
@@ -336,19 +163,12 @@
/* Onboard Peripheral Drivers */
/* BSP_USING_SDRAM is not set */
/* BSP_USING_QSPI_FLASH is not set */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART3
/* BSP_UART3_RX_USING_DMA is not set */
/* BSP_USING_QSPI is not set */
/* BSP_USING_ON_CHIP_FLASH is not set */
/* BSP_USING_FMC is not set */
/* BSP_USING_USBD_FS is not set */
/* Board extended module Drivers */