mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-02 14:23:19 +08:00
fix bl808-d0 && cv1800b compile error (#8513)
This commit is contained in:
flyingcys
File diff suppressed because it is too large
Load Diff
@@ -6,6 +6,8 @@ config BSP_USING_BL808
|
||||
select RT_USING_CACHE
|
||||
select ARCH_MM_MMU
|
||||
select BL808_CORE_D0
|
||||
select RT_USING_SYSTEM_WORKQUEUE
|
||||
select RT_USING_DEVICE_OPS
|
||||
default y
|
||||
|
||||
config BL808_CORE_D0
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
|
||||
#define RT_NAME_MAX 20
|
||||
#define RT_USING_SMART
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
@@ -46,14 +47,13 @@
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_MEMTRACE
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_DEVICE_OPS
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart3"
|
||||
#define RT_VER_NUM 0x50002
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
#define ARCH_CPU_64BIT
|
||||
#define RT_USING_CACHE
|
||||
#define ARCH_MM_MMU
|
||||
@@ -88,22 +88,26 @@
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_V1
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define RT_USING_DFS_V2
|
||||
#define RT_USING_DFS_DEVFS
|
||||
#define RT_USING_LWP
|
||||
#define RT_LWP_MAX_NR 30
|
||||
#define LWP_TASK_STACK_SIZE 16384
|
||||
#define RT_CH_MSG_MAX_NR 1024
|
||||
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
|
||||
#define LWP_TID_MAX_NR 64
|
||||
#define RT_LWP_SHM_MAX_NR 64
|
||||
#define RT_USING_PAGECACHE
|
||||
|
||||
/* page cache config */
|
||||
|
||||
#define RT_PAGECACHE_COUNT 4096
|
||||
#define RT_PAGECACHE_ASPACE_COUNT 1024
|
||||
#define RT_PAGECACHE_PRELOAD 4
|
||||
#define RT_PAGECACHE_HASH_NR 1024
|
||||
#define RT_PAGECACHE_GC_WORK_LEVEL 90
|
||||
#define RT_PAGECACHE_GC_STOP_LEVEL 70
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
@@ -156,6 +160,9 @@
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
#define RT_USING_RESOURCE_ID
|
||||
@@ -164,6 +171,17 @@
|
||||
#define RT_USING_ADT_BITMAP
|
||||
#define RT_USING_ADT_HASHMAP
|
||||
#define RT_USING_ADT_REF
|
||||
#define RT_USING_LWP
|
||||
#define RT_LWP_MAX_NR 30
|
||||
#define LWP_TASK_STACK_SIZE 16384
|
||||
#define RT_CH_MSG_MAX_NR 1024
|
||||
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
|
||||
#define LWP_TID_MAX_NR 64
|
||||
#define RT_LWP_SHM_MAX_NR 64
|
||||
#define RT_USING_LDSO
|
||||
|
||||
/* Memory management */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
@@ -181,6 +199,15 @@
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Executable
+2
@@ -0,0 +1,2 @@
|
||||
fip.bin
|
||||
boot.sd
|
||||
Executable
+13
@@ -0,0 +1,13 @@
|
||||
# cvitek bsp
|
||||
|
||||
## 支持芯片
|
||||
针对算能系列 RISC-V 芯片的 bsp，包括：
|
||||
|
||||
| 芯片名称 | 内存大小 |
|
||||
| ------- | ------- |
|
||||
| cv1800b | 64MByte |
|
||||
| | |
|
||||
|
||||
## FAQ
|
||||
1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。
|
||||
2. 编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件。
|
||||
Executable
+23
@@ -0,0 +1,23 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
LITTLE_BIN=$1
|
||||
|
||||
. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \
|
||||
./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \
|
||||
'fip.bin' \
|
||||
--MONITOR_RUNADDR="${MONITOR_RUNADDR}" \
|
||||
--BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \
|
||||
--CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \
|
||||
--NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \
|
||||
--NAND_INFO='00000000'\
|
||||
--BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \
|
||||
--BLCP_IMG_RUNADDR=0x05200200 \
|
||||
--BLCP_PARAM_LOADADDR=0 \
|
||||
--BLCP=pre-build/fsbl/test/empty.bin \
|
||||
--DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \
|
||||
--BLCP_2ND=$LITTLE_BIN \
|
||||
--MONITOR='pre-build/fw_dynamic.bin' \
|
||||
--LOADER_2ND='pre-build/u-boot-raw.bin' \
|
||||
--compress='lzma'
|
||||
Regular → Executable
+55
-19
@@ -9,6 +9,7 @@
|
||||
CONFIG_RT_NAME_MAX=8
|
||||
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
|
||||
CONFIG_RT_USING_SMART=y
|
||||
# CONFIG_RT_USING_NANO is not set
|
||||
# CONFIG_RT_USING_AMP is not set
|
||||
# CONFIG_RT_USING_SMP is not set
|
||||
CONFIG_RT_CPUS_NR=1
|
||||
@@ -21,6 +22,7 @@ CONFIG_RT_TICK_PER_SECOND=1000
|
||||
CONFIG_RT_USING_OVERFLOW_CHECK=y
|
||||
CONFIG_RT_USING_HOOK=y
|
||||
CONFIG_RT_HOOK_USING_FUNC_PTR=y
|
||||
# CONFIG_RT_USING_HOOKLIST is not set
|
||||
CONFIG_RT_USING_IDLE_HOOK=y
|
||||
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_THREAD_STACK_SIZE=1024
|
||||
@@ -39,7 +41,7 @@ CONFIG_RT_KPRINTF_USING_LONGLONG=y
|
||||
CONFIG_RT_USING_DEBUG=y
|
||||
CONFIG_RT_DEBUGING_COLOR=y
|
||||
CONFIG_RT_DEBUGING_CONTEXT=y
|
||||
# CONFIG_RT_DEBUGING_INIT is not set
|
||||
# CONFIG_RT_DEBUGING_AUTO_INIT is not set
|
||||
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
|
||||
|
||||
#
|
||||
@@ -70,8 +72,9 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
|
||||
# CONFIG_RT_USING_HEAP_ISR is not set
|
||||
CONFIG_RT_USING_HEAP=y
|
||||
CONFIG_RT_USING_DEVICE=y
|
||||
# CONFIG_RT_USING_DEVICE_OPS is not set
|
||||
CONFIG_RT_USING_DEVICE_OPS=y
|
||||
# CONFIG_RT_USING_INTERRUPT_INFO is not set
|
||||
# CONFIG_RT_USING_THREDSAFE_PRINTF is not set
|
||||
CONFIG_RT_USING_CONSOLE=y
|
||||
CONFIG_RT_CONSOLEBUF_SIZE=256
|
||||
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
|
||||
@@ -120,29 +123,26 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
|
||||
CONFIG_RT_USING_DFS=y
|
||||
CONFIG_DFS_USING_POSIX=y
|
||||
CONFIG_DFS_USING_WORKDIR=y
|
||||
# CONFIG_RT_USING_DFS_MNTTABLE is not set
|
||||
CONFIG_DFS_FD_MAX=16
|
||||
CONFIG_RT_USING_DFS_V1=y
|
||||
# CONFIG_RT_USING_DFS_V2 is not set
|
||||
CONFIG_DFS_FILESYSTEMS_MAX=4
|
||||
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
|
||||
CONFIG_RT_USING_DFS_V2=y
|
||||
# CONFIG_RT_USING_DFS_ELMFAT is not set
|
||||
CONFIG_RT_USING_DFS_DEVFS=y
|
||||
# CONFIG_RT_USING_DFS_ROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_CROMFS is not set
|
||||
# CONFIG_RT_USING_DFS_RAMFS is not set
|
||||
# CONFIG_RT_USING_DFS_TMPFS is not set
|
||||
# CONFIG_RT_USING_DFS_MQUEUE is not set
|
||||
CONFIG_RT_USING_PAGECACHE=y
|
||||
|
||||
#
|
||||
# page cache config
|
||||
#
|
||||
CONFIG_RT_PAGECACHE_COUNT=4096
|
||||
CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024
|
||||
CONFIG_RT_PAGECACHE_PRELOAD=4
|
||||
CONFIG_RT_PAGECACHE_HASH_NR=1024
|
||||
CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90
|
||||
CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70
|
||||
# CONFIG_RT_USING_FAL is not set
|
||||
CONFIG_RT_USING_LWP=y
|
||||
# CONFIG_LWP_DEBUG is not set
|
||||
CONFIG_RT_LWP_MAX_NR=30
|
||||
CONFIG_LWP_TASK_STACK_SIZE=16384
|
||||
CONFIG_RT_CH_MSG_MAX_NR=1024
|
||||
CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
|
||||
CONFIG_LWP_TID_MAX_NR=64
|
||||
CONFIG_RT_LWP_SHM_MAX_NR=64
|
||||
# CONFIG_LWP_UNIX98_PTY is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
@@ -259,6 +259,12 @@ CONFIG_RT_USING_POSIX_TIMER=y
|
||||
# CONFIG_RT_USING_LWIP is not set
|
||||
# CONFIG_RT_USING_AT is not set
|
||||
|
||||
#
|
||||
# Memory protection
|
||||
#
|
||||
# CONFIG_RT_USING_MEM_PROTECTION is not set
|
||||
# CONFIG_RT_USING_HW_STACK_GUARD is not set
|
||||
|
||||
#
|
||||
# Utilities
|
||||
#
|
||||
@@ -274,6 +280,18 @@ CONFIG_RT_USING_ADT_HASHMAP=y
|
||||
CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_RT_USING_RT_LINK is not set
|
||||
# CONFIG_RT_USING_VBUS is not set
|
||||
CONFIG_RT_USING_LWP=y
|
||||
# CONFIG_LWP_DEBUG is not set
|
||||
CONFIG_RT_LWP_MAX_NR=30
|
||||
CONFIG_LWP_TASK_STACK_SIZE=16384
|
||||
CONFIG_RT_CH_MSG_MAX_NR=1024
|
||||
CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
|
||||
CONFIG_LWP_TID_MAX_NR=64
|
||||
CONFIG_RT_LWP_SHM_MAX_NR=64
|
||||
# CONFIG_LWP_UNIX98_PTY is not set
|
||||
CONFIG_RT_USING_LDSO=y
|
||||
# CONFIG_ELF_DEBUG_ENABLE is not set
|
||||
# CONFIG_ELF_LOAD_RANDOMIZE is not set
|
||||
|
||||
#
|
||||
# Memory management
|
||||
@@ -325,6 +343,16 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CYW43012 WiFi
|
||||
#
|
||||
# CONFIG_PKG_USING_WLAN_CYW43012 is not set
|
||||
|
||||
#
|
||||
# BL808 WiFi
|
||||
#
|
||||
# CONFIG_PKG_USING_WLAN_BL808 is not set
|
||||
|
||||
#
|
||||
# CYW43439 WiFi
|
||||
#
|
||||
# CONFIG_PKG_USING_WLAN_CYW43439 is not set
|
||||
# CONFIG_PKG_USING_COAP is not set
|
||||
# CONFIG_PKG_USING_NOPOLL is not set
|
||||
# CONFIG_PKG_USING_NETUTILS is not set
|
||||
@@ -346,7 +374,6 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_JIOT-C-SDK is not set
|
||||
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
|
||||
# CONFIG_PKG_USING_JOYLINK is not set
|
||||
# CONFIG_PKG_USING_EZ_IOT_OS is not set
|
||||
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
|
||||
# CONFIG_PKG_USING_NIMBLE is not set
|
||||
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
|
||||
@@ -388,6 +415,7 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_WOL is not set
|
||||
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
|
||||
# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
|
||||
# CONFIG_PKG_USING_LHC_MODBUS is not set
|
||||
|
||||
#
|
||||
# security packages
|
||||
@@ -586,6 +614,9 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_MLIBC is not set
|
||||
# CONFIG_PKG_USING_TASK_MSG_BUS is not set
|
||||
# CONFIG_PKG_USING_SFDB is not set
|
||||
# CONFIG_PKG_USING_RTP is not set
|
||||
# CONFIG_PKG_USING_REB is not set
|
||||
# CONFIG_PKG_USING_R_RHEALSTONE is not set
|
||||
|
||||
#
|
||||
# peripheral libraries and drivers
|
||||
@@ -753,6 +784,9 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_BT_ECB02C is not set
|
||||
# CONFIG_PKG_USING_UAT is not set
|
||||
# CONFIG_PKG_USING_ST7789 is not set
|
||||
# CONFIG_PKG_USING_VS1003 is not set
|
||||
# CONFIG_PKG_USING_X9555 is not set
|
||||
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
|
||||
# CONFIG_PKG_USING_SPI_TOOLS is not set
|
||||
|
||||
#
|
||||
@@ -767,6 +801,7 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_ULAPACK is not set
|
||||
# CONFIG_PKG_USING_QUEST is not set
|
||||
# CONFIG_PKG_USING_NAXOS is not set
|
||||
# CONFIG_PKG_USING_R_TINYMAIX is not set
|
||||
|
||||
#
|
||||
# Signal Processing and Control Algorithm Packages
|
||||
@@ -776,7 +811,6 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_UKAL is not set
|
||||
# CONFIG_PKG_USING_DIGITALCTRL is not set
|
||||
# CONFIG_PKG_USING_KISSFFT is not set
|
||||
# CONFIG_PKG_USING_CMSIS_DSP is not set
|
||||
|
||||
#
|
||||
# miscellaneous packages
|
||||
@@ -814,6 +848,7 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
# CONFIG_PKG_USING_MINILZO is not set
|
||||
# CONFIG_PKG_USING_QUICKLZ is not set
|
||||
# CONFIG_PKG_USING_LZMA is not set
|
||||
# CONFIG_PKG_USING_RALARAM is not set
|
||||
# CONFIG_PKG_USING_MULTIBUTTON is not set
|
||||
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_CANFESTIVAL is not set
|
||||
@@ -1066,6 +1101,7 @@ CONFIG_RT_USING_ADT_REF=y
|
||||
#
|
||||
CONFIG_BSP_USING_UART=y
|
||||
CONFIG_RT_USING_UART0=y
|
||||
CONFIG_UART_IRQ_BASE=30
|
||||
# CONFIG_RT_USING_UART1 is not set
|
||||
# CONFIG_RT_USING_UART2 is not set
|
||||
# CONFIG_RT_USING_UART3 is not set
|
||||
Regular → Executable
Regular → Executable
+3
-2
@@ -8,7 +8,7 @@ config BSP_DIR
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../.."
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
@@ -17,7 +17,7 @@ config PKGS_DIR
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "drivers/Kconfig"
|
||||
source "board/Kconfig"
|
||||
|
||||
config BSP_USING_CV1800B
|
||||
bool
|
||||
@@ -27,6 +27,7 @@ config BSP_USING_CV1800B
|
||||
select RT_USING_USER_MAIN
|
||||
select RT_USING_CACHE
|
||||
select ARCH_MM_MMU
|
||||
select RT_USING_DEVICE_OPS
|
||||
default y
|
||||
|
||||
config C906_PLIC_PHY_ADDR
|
||||
Regular → Executable
Regular → Executable
Regular → Executable
Regular → Executable
+13
-3
@@ -24,9 +24,6 @@ Export('rtconfig')
|
||||
rtconfig.CPU='virt64'
|
||||
rtconfig.ARCH='risc-v'
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
|
||||
|
||||
stack_size = 4096
|
||||
|
||||
stack_lds = open('link_stacksize.lds', 'w')
|
||||
@@ -34,5 +31,18 @@ if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
|
||||
stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size)
|
||||
stack_lds.close()
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/drivers'):
|
||||
drivers_path_prefix = SDK_ROOT + '/drivers'
|
||||
else:
|
||||
drivers_path_prefix = os.path.dirname(SDK_ROOT) + '/drivers'
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
Regular → Executable
@@ -10,6 +10,10 @@ menu "General Drivers Configuration"
|
||||
bool "Enable UART 0"
|
||||
default y
|
||||
|
||||
config UART_IRQ_BASE
|
||||
int
|
||||
default 30
|
||||
|
||||
config RT_USING_UART1
|
||||
bool "Enable UART 1"
|
||||
default n
|
||||
Regular → Executable
Regular → Executable
Regular → Executable
@@ -4,4 +4,4 @@ echo "start compress kernel..."
|
||||
|
||||
lzma -c -9 -f -k Image > Image.lzma
|
||||
|
||||
./mkimage -f multi.its -r boot.sd
|
||||
./mkimage -f multi.its -r ../boot.sd
|
||||
Regular → Executable
+30
-10
@@ -47,6 +47,7 @@
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_DEVICE_OPS
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
@@ -86,17 +87,18 @@
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_V1
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define RT_USING_DFS_V2
|
||||
#define RT_USING_DFS_DEVFS
|
||||
#define RT_USING_LWP
|
||||
#define RT_LWP_MAX_NR 30
|
||||
#define LWP_TASK_STACK_SIZE 16384
|
||||
#define RT_CH_MSG_MAX_NR 1024
|
||||
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
|
||||
#define LWP_TID_MAX_NR 64
|
||||
#define RT_LWP_SHM_MAX_NR 64
|
||||
#define RT_USING_PAGECACHE
|
||||
|
||||
/* page cache config */
|
||||
|
||||
#define RT_PAGECACHE_COUNT 4096
|
||||
#define RT_PAGECACHE_ASPACE_COUNT 1024
|
||||
#define RT_PAGECACHE_PRELOAD 4
|
||||
#define RT_PAGECACHE_HASH_NR 1024
|
||||
#define RT_PAGECACHE_GC_WORK_LEVEL 90
|
||||
#define RT_PAGECACHE_GC_STOP_LEVEL 70
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
@@ -150,6 +152,9 @@
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
#define RT_USING_RESOURCE_ID
|
||||
@@ -158,6 +163,14 @@
|
||||
#define RT_USING_ADT_BITMAP
|
||||
#define RT_USING_ADT_HASHMAP
|
||||
#define RT_USING_ADT_REF
|
||||
#define RT_USING_LWP
|
||||
#define RT_LWP_MAX_NR 30
|
||||
#define LWP_TASK_STACK_SIZE 16384
|
||||
#define RT_CH_MSG_MAX_NR 1024
|
||||
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
|
||||
#define LWP_TID_MAX_NR 64
|
||||
#define RT_LWP_SHM_MAX_NR 64
|
||||
#define RT_USING_LDSO
|
||||
|
||||
/* Memory management */
|
||||
|
||||
@@ -181,6 +194,12 @@
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
@@ -285,6 +304,7 @@
|
||||
|
||||
#define BSP_USING_UART
|
||||
#define RT_USING_UART0
|
||||
#define UART_IRQ_BASE 30
|
||||
#define BSP_USING_CV1800B
|
||||
#define C906_PLIC_PHY_ADDR 0x70000000
|
||||
#define IRQ_MAX_NR 64
|
||||
Regular → Executable
+2
-2
@@ -9,7 +9,7 @@ CROSS_TOOL ='gcc'
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = r'../..'
|
||||
RTT_ROOT = r'../../..'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
@@ -56,4 +56,4 @@ if PLATFORM == 'gcc':
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n' + 'cd ../ && ./combine-fip.sh\n'
|
||||
Executable
+16
@@ -0,0 +1,16 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
|
||||
CPPDEFINES = []
|
||||
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if GetDepend('BSP_USING_CV1800B'):
|
||||
CPPPATH += [cwd + r'/cv1800b']
|
||||
|
||||
CPPDEFINES += ['-DCONFIG_64BIT']
|
||||
|
||||
group = DefineGroup('drivers', src, depend = [''], CPPDEFINES = CPPDEFINES, CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
+407
File diff suppressed because it is too large
Load Diff
Executable
+51
@@ -0,0 +1,51 @@
|
||||
#ifndef _CV180X_PINMUX_H_
|
||||
#define _CV180X_PINMUX_H_
|
||||
|
||||
/*
|
||||
* Pinmux definitions
|
||||
*/
|
||||
#define PINMUX_UART0 0
|
||||
#define PINMUX_UART1 1
|
||||
#define PINMUX_UART2 2
|
||||
#define PINMUX_UART3 3
|
||||
#define PINMUX_UART3_2 4
|
||||
#define PINMUX_I2C0 5
|
||||
#define PINMUX_I2C1 6
|
||||
#define PINMUX_I2C2 7
|
||||
#define PINMUX_I2C3 8
|
||||
#define PINMUX_I2C4 9
|
||||
#define PINMUX_I2C4_2 10
|
||||
#define PINMUX_SPI0 11
|
||||
#define PINMUX_SPI1 12
|
||||
#define PINMUX_SPI2 13
|
||||
#define PINMUX_SPI2_2 14
|
||||
#define PINMUX_SPI3 15
|
||||
#define PINMUX_SPI3_2 16
|
||||
#define PINMUX_I2S0 17
|
||||
#define PINMUX_I2S1 18
|
||||
#define PINMUX_I2S2 19
|
||||
#define PINMUX_I2S3 20
|
||||
#define PINMUX_USBID 21
|
||||
#define PINMUX_SDIO0 22
|
||||
#define PINMUX_SDIO1 23
|
||||
#define PINMUX_ND 24
|
||||
#define PINMUX_EMMC 25
|
||||
#define PINMUX_SPI_NOR 26
|
||||
#define PINMUX_SPI_NAND 27
|
||||
#define PINMUX_CAM0 28
|
||||
#define PINMUX_CAM1 29
|
||||
#define PINMUX_PCM0 30
|
||||
#define PINMUX_PCM1 31
|
||||
#define PINMUX_CSI0 32
|
||||
#define PINMUX_CSI1 33
|
||||
#define PINMUX_CSI2 34
|
||||
#define PINMUX_DSI 35
|
||||
#define PINMUX_VI0 36
|
||||
#define PINMUX_VO 37
|
||||
#define PINMUX_RMII1 38
|
||||
#define PINMUX_EPHY_LED 39
|
||||
#define PINMUX_I80 40
|
||||
#define PINMUX_LVDS 41
|
||||
#define PINMUX_USB 42
|
||||
|
||||
#endif // end of _CV180X_PINMUX_H_
|
||||
+337
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __MMIO_H__
|
||||
#define __MMIO_H__
|
||||
#include <stdint.h>
|
||||
#include "types.h"
|
||||
|
||||
#define __raw_readb(a) (*(volatile unsigned char *)(a))
|
||||
#define __raw_readw(a) (*(volatile unsigned short *)(a))
|
||||
#define __raw_readl(a) (*(volatile unsigned int *)(a))
|
||||
#define __raw_readq(a) (*(volatile unsigned long long *)(a))
|
||||
|
||||
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v))
|
||||
|
||||
/*
|
||||
* I/O memory access primitives. Reads are ordered relative to any
|
||||
* following Normal memory access. Writes are ordered relative to any prior
|
||||
* Normal memory access. The memory barriers here are necessary as RISC-V
|
||||
* doesn't define any ordering between the memory space and the I/O space.
|
||||
*/
|
||||
#define __io_br() do {} while (0)
|
||||
#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
|
||||
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
|
||||
//#define __io_aw() mmiowb_set_pending()
|
||||
#define __io_aw() do {} while (0)
|
||||
|
||||
#define readb(c) ({ u8 __v; __io_br(); __v = __raw_readb(c); __io_ar(__v); __v; })
|
||||
#define readw(c) ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(__v); __v; })
|
||||
#define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(__v); __v; })
|
||||
|
||||
#define writeb(v, c) ({ __io_bw(); __raw_writeb((v), (c)); __io_aw(); })
|
||||
#define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); })
|
||||
#define writel(v, c) ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); })
|
||||
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; })
|
||||
#define writeq(v, c) ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); })
|
||||
#endif // CONFIG_64BIT
|
||||
|
||||
/*
|
||||
#define __raw_readb(a) (*(volatile unsigned char *)(a))
|
||||
#define __raw_readw(a) (*(volatile unsigned short *)(a))
|
||||
#define __raw_readl(a) (*(volatile unsigned int *)(a))
|
||||
#define __raw_readq(a) (*(volatile unsigned long long *)(a))
|
||||
|
||||
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v))
|
||||
|
||||
#define readb(a) __raw_readb(a)
|
||||
#define readw(a) __raw_readw(a)
|
||||
#define readl(a) __raw_readl(a)
|
||||
#define readq(a) __raw_readq(a)
|
||||
|
||||
#define writeb(v, a) __raw_writeb(v,a)
|
||||
#define writew(v, a) __raw_writew(v,a)
|
||||
#define writel(v, a) __raw_writel(v,a)
|
||||
#define writeq(v, a) __raw_writeq(v,a)
|
||||
|
||||
#define cpu_write8(a, v) writeb(a, v)
|
||||
#define cpu_write16(a, v) writew(a, v)
|
||||
#define cpu_write32(a, v) writel(a, v)
|
||||
*/
|
||||
|
||||
#define mmio_wr32 mmio_write_32
|
||||
#define mmio_rd32 mmio_read_32
|
||||
|
||||
static inline void mmio_write_8(uintptr_t addr, uint8_t value)
|
||||
{
|
||||
writeb(value, (void *) addr);
|
||||
}
|
||||
|
||||
static inline uint8_t mmio_read_8(uintptr_t addr)
|
||||
{
|
||||
return readb((void *) addr);
|
||||
}
|
||||
|
||||
static inline void mmio_write_16(uintptr_t addr, uint16_t value)
|
||||
{
|
||||
writew(value, (void *) addr);
|
||||
}
|
||||
|
||||
static inline uint16_t mmio_read_16(uintptr_t addr)
|
||||
{
|
||||
return readw((void *) addr);
|
||||
}
|
||||
|
||||
static inline void mmio_write_32(uintptr_t addr, uint32_t value)
|
||||
{
|
||||
writel(value, (void *) addr);
|
||||
}
|
||||
|
||||
static inline uint32_t mmio_read_32(uintptr_t addr)
|
||||
{
|
||||
return readl((void *) addr);
|
||||
}
|
||||
|
||||
static inline void mmio_write_64(uintptr_t addr, uint64_t value)
|
||||
{
|
||||
writeq(value, (void *) addr);
|
||||
}
|
||||
|
||||
static inline uint64_t mmio_read_64(uintptr_t addr)
|
||||
{
|
||||
return readq((void *) addr);
|
||||
}
|
||||
|
||||
static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear)
|
||||
{
|
||||
writel(readl((void *) addr) & ~clear , (void *) addr);
|
||||
}
|
||||
|
||||
static inline void mmio_setbits_32(uintptr_t addr, uint32_t set)
|
||||
{
|
||||
writel(readl((void *) addr) | set , (void *) addr);
|
||||
}
|
||||
|
||||
static inline void mmio_clrsetbits_32(uintptr_t addr, uint32_t clear,
|
||||
uint32_t set)
|
||||
{
|
||||
writel((readl((void *) addr) & ~clear) | set , (void *) addr);
|
||||
}
|
||||
|
||||
/* from Linux usage */
|
||||
#define ioremap(a, l) (a)
|
||||
|
||||
#define _reg_read(addr) mmio_read_32((addr))
|
||||
#define _reg_write(addr, data) mmio_write_32((addr), (data))
|
||||
#define _reg_write_mask(addr, mask, data) mmio_clrsetbits_32(addr, mask, data)
|
||||
|
||||
#define ioread8 readb
|
||||
#define ioread16 readw
|
||||
#define ioread32 readl
|
||||
#define ioread64 readq
|
||||
|
||||
#define iowrite8 writeb
|
||||
#define iowrite16 writew
|
||||
#define iowrite32 writel
|
||||
#define iowrite64 writeq
|
||||
|
||||
#endif /* __MMIO_H__ */
|
||||
Executable
+34
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
|
||||
*
|
||||
* File Name: pinctrl.h
|
||||
* Description:
|
||||
*/
|
||||
|
||||
#ifndef __PINCTRL_CV180X_H__
|
||||
#define __PINCTRL_CV180X_H__
|
||||
|
||||
#include "cv180x_pinlist_swconfig.h"
|
||||
#include "cv180x_reg_fmux_gpio.h"
|
||||
|
||||
#define PAD_MIPI_TXM4__MIPI_TXM4 0
|
||||
#define PAD_MIPI_TXP4__MIPI_TXP4 0
|
||||
#define PAD_MIPI_TXM3__MIPI_TXM3 0
|
||||
#define PAD_MIPI_TXP3__MIPI_TXP3 0
|
||||
#define PAD_MIPI_TXM2__MIPI_TXM2 0
|
||||
#define PAD_MIPI_TXP2__MIPI_TXP2 0
|
||||
#define PAD_MIPI_TXM1__MIPI_TXM1 0
|
||||
#define PAD_MIPI_TXP1__MIPI_TXP1 0
|
||||
#define PAD_MIPI_TXM0__MIPI_TXM0 0
|
||||
#define PAD_MIPI_TXP0__MIPI_TXP0 0
|
||||
|
||||
#define PINMUX_BASE 0x03001000
|
||||
#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
|
||||
#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
|
||||
#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
|
||||
#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
|
||||
mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
|
||||
FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \
|
||||
PIN_NAME##__##FUNC_NAME)
|
||||
|
||||
#endif /* __PINCTRL_CV180X_H__ */
|
||||
Executable
+43
@@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _LINUX_TYPES_H
|
||||
#define _LINUX_TYPES_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_64BIT
|
||||
typedef unsigned long uintptr_t;
|
||||
typedef unsigned long size_t;
|
||||
/* bsd */
|
||||
typedef unsigned char u_char;
|
||||
typedef unsigned short u_short;
|
||||
typedef unsigned int u_int;
|
||||
typedef unsigned long u_long;
|
||||
|
||||
/* sysv */
|
||||
typedef unsigned char unchar;
|
||||
typedef unsigned short ushort;
|
||||
typedef unsigned int uint;
|
||||
typedef unsigned long ulong;
|
||||
|
||||
typedef signed char s8;
|
||||
typedef signed short s16;
|
||||
typedef signed int s32;
|
||||
typedef signed long s64;
|
||||
|
||||
typedef unsigned char u8;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned int u32;
|
||||
typedef unsigned long u64;
|
||||
|
||||
typedef signed char __s8;
|
||||
typedef signed short __s16;
|
||||
typedef signed int __s32;
|
||||
typedef signed long __s64;
|
||||
|
||||
typedef unsigned char __u8;
|
||||
typedef unsigned short __u16;
|
||||
typedef unsigned int __u32;
|
||||
typedef unsigned long __u64;
|
||||
|
||||
#endif /* CONFIG_64BIT */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _LINUX_TYPES_H */
|
||||
Regular → Executable
Regular → Executable
@@ -1,12 +1,11 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023/06/25 flyingcys first version
|
||||
* 2023/10/25 flyingcys update uart configure
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
@@ -250,20 +249,34 @@ int rt_hw_uart_init(void)
|
||||
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial##no, "uart" #no);
|
||||
|
||||
#ifdef RT_USING_UART0
|
||||
PINMUX_CONFIG(UART0_RX, UART0_RX);
|
||||
PINMUX_CONFIG(UART0_TX, UART0_TX);
|
||||
BSP_INSTALL_UART_DEVICE(0);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
PINMUX_CONFIG(IIC0_SDA, UART1_RX);
|
||||
PINMUX_CONFIG(IIC0_SCL, UART1_TX);
|
||||
BSP_INSTALL_UART_DEVICE(1);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART2
|
||||
PINMUX_CONFIG(SD1_D1, UART2_RX);
|
||||
PINMUX_CONFIG(SD1_D2, UART2_TX);
|
||||
BSP_INSTALL_UART_DEVICE(2);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART3
|
||||
PINMUX_CONFIG(SD1_D1, UART3_RX);
|
||||
PINMUX_CONFIG(SD1_D2, UART3_TX);
|
||||
BSP_INSTALL_UART_DEVICE(3);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART4
|
||||
PINMUX_CONFIG(SD1_GP0, UART4_RX);
|
||||
PINMUX_CONFIG(SD1_GP1, UART4_TX);
|
||||
BSP_INSTALL_UART_DEVICE(4);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -14,6 +14,9 @@
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
|
||||
#include "pinctrl.h"
|
||||
#include "mmio.h"
|
||||
|
||||
#define UART_REG_SHIFT 0x2 /* Register Shift*/
|
||||
#define UART_INPUT_CLK 25000000
|
||||
|
||||
@@ -23,7 +26,6 @@
|
||||
#define UART3_BASE 0x04170000
|
||||
#define UART4_BASE 0x041C0000
|
||||
|
||||
#define UART_IRQ_BASE (44)
|
||||
#define UART0_IRQ (UART_IRQ_BASE + 0)
|
||||
#define UART1_IRQ (UART_IRQ_BASE + 1)
|
||||
#define UART2_IRQ (UART_IRQ_BASE + 2)
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
ﾭ�
|
||||
@@ -0,0 +1,2 @@
|
||||
MONITOR_RUNADDR=0x0000000080000000
|
||||
BLCP_2ND_RUNADDR=0x0000000083f40000
|
||||
Binary file not shown.
+35
@@ -0,0 +1,35 @@
|
||||
#ifndef __BOARD_MMAP__83494f74__
|
||||
#define __BOARD_MMAP__83494f74__
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */
|
||||
#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */
|
||||
#define CVIMMAP_BOOTLOGO_ADDR 0x82473000 /* offset 36.44921875MiB */
|
||||
#define CVIMMAP_BOOTLOGO_SIZE 0x0 /* 0.0KiB */
|
||||
#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000 /* offset 35.0MiB */
|
||||
#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00 /* offset 19.9990234375MiB */
|
||||
#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */
|
||||
#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */
|
||||
#define CVIMMAP_DRAM_SIZE 0x4000000 /* 64.0MiB */
|
||||
#define CVIMMAP_FREERTOS_ADDR 0x83f40000 /* offset 63.25MiB */
|
||||
#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0 /* 0.0KiB */
|
||||
#define CVIMMAP_FREERTOS_SIZE 0xc0000 /* 768.0KiB */
|
||||
#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000 /* offset 63.25MiB */
|
||||
#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000 /* offset 20.0MiB */
|
||||
#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000 /* 15.0MiB */
|
||||
#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000 /* offset 36.44921875MiB */
|
||||
#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0 /* 0.0KiB */
|
||||
#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000 /* offset 36.44921875MiB */
|
||||
#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */
|
||||
#define CVIMMAP_ION_ADDR 0x82473000 /* offset 36.44921875MiB */
|
||||
#define CVIMMAP_ION_SIZE 0x1acd000 /* 26.80078125MiB */
|
||||
#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000 /* offset 36.44921875MiB */
|
||||
#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0 /* 0.0KiB */
|
||||
#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000 /* 63.25MiB */
|
||||
#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */
|
||||
#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */
|
||||
#define CVIMMAP_UIMAG_ADDR 0x81400000 /* offset 20.0MiB */
|
||||
#define CVIMMAP_UIMAG_SIZE 0xf00000 /* 15.0MiB */
|
||||
|
||||
#endif /* __BOARD_MMAP__83494f74__ */
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import logging
|
||||
import struct
|
||||
import argparse
|
||||
|
||||
CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD
|
||||
CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE
|
||||
|
||||
CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0
|
||||
|
||||
|
||||
def gen_chip_conf(args):
|
||||
logging.info("gen_chip_conf")
|
||||
regs = [
|
||||
(0x0E00000C, 0xA0000001), # ATF_DBG_REG = 0x0E00000C
|
||||
(0x0E00000C, 0xA0000002),
|
||||
# (CHIP_CONF_CMD_DELAY_MS, 100),
|
||||
# (CHIP_CONF_CMD_DELAY_US, 100),
|
||||
(CHIP_CONF_SCAN_START_1, 0xFFFFFFFF),
|
||||
]
|
||||
|
||||
chip_conf = b"".join(struct.pack("<II", a, v) for a, v in regs)
|
||||
logging.info("chip_conf=%d bytes", len(chip_conf))
|
||||
|
||||
with open(args.CHIP_CONF, "wb") as fp:
|
||||
fp.write(chip_conf)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="generate test cases")
|
||||
parser.add_argument("CHIP_CONF", type=str)
|
||||
args = parser.parse_args()
|
||||
gen_chip_conf(args)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
+252
File diff suppressed because it is too large
Load Diff
+802
File diff suppressed because it is too large
Load Diff
+85
@@ -0,0 +1,85 @@
|
||||
#
|
||||
# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Enable workarounds for selected Cortex-A53 errata
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 1
|
||||
|
||||
PAGE_SIZE_64KB := 1
|
||||
TEST_FROM_SPINOR1 := 0
|
||||
|
||||
DEFINES += -DLZ4_USER_MEMORY_FUNCTIONS=1
|
||||
|
||||
# ifeq ($(FSBL_SECURE_BOOT_SUPPORT),1)
|
||||
DEFINES += \
|
||||
-DNO_ALLOCS \
|
||||
-DARGTYPE=3 \
|
||||
-DLTC_NO_FILE \
|
||||
-DLTM_NO_FILE \
|
||||
-DLTM_DESC \
|
||||
-DLTC_SOURCE
|
||||
|
||||
CRYPT_INCLUDES := \
|
||||
-Ilib/libtommath \
|
||||
-Ilib/libtomcrypt/src/headers \
|
||||
-Ilib/BigDigits
|
||||
|
||||
CRYPT_SOURCES := \
|
||||
lib/BigDigits/bigdigits.c \
|
||||
lib/libtomcrypt/src/hashes/sha2/sha256.c
|
||||
# endif
|
||||
|
||||
INCLUDES += \
|
||||
-Iinclude \
|
||||
${CPU_INCLUDES} \
|
||||
-Iplat/ \
|
||||
-Iplat/${CHIP_ARCH}/include/uart \
|
||||
-Iplat/${CHIP_ARCH}/include/usb \
|
||||
-Iplat/${CHIP_ARCH}/include \
|
||||
-Iplat/${CHIP_ARCH}/include/${BOOT_CPU} \
|
||||
-Ilib/utils \
|
||||
-Ilib/lzma \
|
||||
-Ilib/lz4 \
|
||||
-Ilib/crc \
|
||||
${STDLIB_INCLUDES} \
|
||||
${CRYPT_INCLUDES}
|
||||
|
||||
#BL_COMMON_SOURCES = \
|
||||
${CPU_SOURCES} \
|
||||
lib/tf_printf/tf_printf.c \
|
||||
plat/${CHIP_ARCH}/platform.c \
|
||||
plat/${CHIP_ARCH}/security/security.c \
|
||||
${STDLIB_SRCS} \
|
||||
${CRYPT_SOURCES}
|
||||
|
||||
#DECOMPRESSION_SOURCES = \
|
||||
lib/lzma/LzmaDec.c \
|
||||
lib/lz4/lz4_all.c \
|
||||
lib/lz4/xxhash.c
|
||||
|
||||
#BL2_SRCS = \
|
||||
${BL_COMMON_SOURCES} \
|
||||
plat/${CHIP_ARCH}/platform_device.c \
|
||||
plat/${CHIP_ARCH}/bl2/bl2_opt.c \
|
||||
lib/utils/decompress.c \
|
||||
plat/${CHIP_ARCH}/usb/cps_cvi.c \
|
||||
plat/${CHIP_ARCH}/usb/usb_tty.c \
|
||||
plat/${CHIP_ARCH}/usb/dwc2_udc_otg.c \
|
||||
plat/${CHIP_ARCH}/usb/dwc2_udc_otg_xfer_dma.c \
|
||||
plat/${CHIP_ARCH}/usb/cv_usb.c \
|
||||
lib/crc/crc16.c \
|
||||
${DECOMPRESSION_SOURCES}
|
||||
|
||||
BL2_SOURCES = \
|
||||
${BL2_CPU_SOURCES} \
|
||||
${BL2_SRCS} \
|
||||
plat/${CHIP_ARCH}/bl2/bl2_main.c
|
||||
|
||||
#include plat/${CHIP_ARCH}/ddr/ddr.mk
|
||||
|
||||
BL2_LINKERFILE := plat/${CHIP_ARCH}/bl2/bl2.ld.S
|
||||
BL2_RLS_OBJS := plat/${CHIP_ARCH}/bl2_objs/${PROJECT_FULLNAME}/bl2/*.o
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,16 @@
|
||||
sys.up
|
||||
|
||||
; Reset
|
||||
break;
|
||||
WAIT !ISRUN() ;wait until target stop
|
||||
|
||||
; MWriteS32 PM:0x0C000000++0x3ffff 0x14000000
|
||||
MWriteS32 PM:0x4400000++0xf 0x14000000
|
||||
MWriteS32 0x4400000++0xf 0x14000000
|
||||
Register.Set pc 0x04400000
|
||||
|
||||
; MWriteS32 PM:0x03000008 0x4 // wdt reset enable
|
||||
; MWriteS32 PM:0x03010004 0x1 // Set timeout range reigster
|
||||
; MWriteS32 PM:0x0301000c 0x76 // Counter restart register
|
||||
; MWriteS32 PM:0x03010000 0x13
|
||||
print "CLEAR ROM"
|
||||
@@ -0,0 +1,14 @@
|
||||
DO up.cmm
|
||||
|
||||
MWriteS32 PM:0x4400000++0xf 0x14000000
|
||||
MWriteS32 PM:0x4418000++0xf 0x6F
|
||||
Register.Set pc 0x04400000
|
||||
print "clear ROM"
|
||||
|
||||
LoadBINARY ..\cv181x_c906b_bl1.bin 0x04418000 %S32
|
||||
print "C906B BL1 loaded"
|
||||
|
||||
Data.Set PM:0x3003024 %LONG Data.Long(PM:0x3003024)|(1<<5)
|
||||
print "Release C906B"
|
||||
|
||||
END
|
||||
@@ -0,0 +1,13 @@
|
||||
DO up.cmm
|
||||
|
||||
MWriteS32 PM:0x4400000++0xf 0x14000000
|
||||
Register.Set pc 0x04400000
|
||||
print "clear ROM"
|
||||
|
||||
LoadBINARY ..\cv181x_ca53_bl1.bin 0x04400000 %S32
|
||||
print "CA53 BL1 loaded"
|
||||
|
||||
Register.Set r0 0
|
||||
Register.Set pc 0x04400000
|
||||
|
||||
END
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
|
||||
;winclear
|
||||
system.reset
|
||||
translation.reset
|
||||
|
||||
system.cpu cortexa53
|
||||
system.config debugaccessport 0
|
||||
system.config apbaccessport 0
|
||||
system.config axiaccessport 1
|
||||
system.config memoryaccessport 1
|
||||
; set corenumber first
|
||||
sys.config corenumber 1
|
||||
; then set corebase and ctibase
|
||||
sys.config corebase 0x81010000
|
||||
sys.config ctibase 0x81020000
|
||||
sys.jc 5mhz
|
||||
|
||||
Wait 10.ms
|
||||
system.option enreset on
|
||||
system.option trst on
|
||||
system.option resetbreak on
|
||||
system.option waitreset 500.ms
|
||||
OPTION.SerialWire ON
|
||||
|
||||
sys.down
|
||||
Wait 50.ms
|
||||
sys.up
|
||||
|
||||
if system.up()
|
||||
(
|
||||
; data.list
|
||||
)
|
||||
else
|
||||
(
|
||||
dialog.ok "system.up failed"
|
||||
)
|
||||
|
||||
; Reset
|
||||
break;
|
||||
WAIT !ISRUN() ;wait until target stop
|
||||
Binary file not shown.
Binary file not shown.
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Executable
BIN
Binary file not shown.
Reference in New Issue
Block a user