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https://github.com/RT-Thread/rt-thread.git
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【更新】STM32CubeG4_V1.2.0
This commit is contained in:
Mr.Tiger
@@ -8847,19 +8847,19 @@ typedef struct
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#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
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/******************** Bits definition for TAMP_FLTCR register ***************/
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#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
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#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
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#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
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#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
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#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
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#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
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#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
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#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
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#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
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#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
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#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
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#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
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#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
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#define TAMP_FLTCR_TAMPFLT_Pos (3U)
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#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
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#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
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#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
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#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
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#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
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#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
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#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
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#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
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#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
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@@ -9903,35 +9903,35 @@ typedef struct
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/****************** Bit definition for SYSCFG_SWPR register ****************/
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#define SYSCFG_SWPR_PAGE0_Pos (0U)
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#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE1_Pos (1U)
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#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
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#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
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#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
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#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
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#define SYSCFG_SWPR_PAGE2_Pos (2U)
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#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
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#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
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#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
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#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
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#define SYSCFG_SWPR_PAGE3_Pos (3U)
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#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
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#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
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#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
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#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
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#define SYSCFG_SWPR_PAGE4_Pos (4U)
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#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
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#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
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#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
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#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
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#define SYSCFG_SWPR_PAGE5_Pos (5U)
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#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
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#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
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#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
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#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
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#define SYSCFG_SWPR_PAGE6_Pos (6U)
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#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
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#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
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#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
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#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
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#define SYSCFG_SWPR_PAGE7_Pos (7U)
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#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
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#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
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#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
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#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
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#define SYSCFG_SWPR_PAGE8_Pos (8U)
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#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
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#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
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#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
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#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
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#define SYSCFG_SWPR_PAGE9_Pos (9U)
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#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
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#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
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#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
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#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
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/****************** Bit definition for SYSCFG_SKR register ****************/
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#define SYSCFG_SKR_KEY_Pos (0U)
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#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
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@@ -12978,9 +12978,6 @@ typedef struct
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((INSTANCE) == TIM16) || \
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((INSTANCE) == TIM17))
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/****************** TIM Instances : supporting synchronization ****************/
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#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
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/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
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#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM8))
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@@ -9078,19 +9078,19 @@ typedef struct
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#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
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/******************** Bits definition for TAMP_FLTCR register ***************/
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#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
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#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
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#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
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#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
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#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
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#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
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#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
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#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
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#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
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#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
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#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
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#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
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#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
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#define TAMP_FLTCR_TAMPFLT_Pos (3U)
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#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
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#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
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#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
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#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
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#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
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#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
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#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
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#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
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#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
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@@ -10134,35 +10134,35 @@ typedef struct
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/****************** Bit definition for SYSCFG_SWPR register ****************/
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#define SYSCFG_SWPR_PAGE0_Pos (0U)
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#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE1_Pos (1U)
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#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
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#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
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#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
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#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
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#define SYSCFG_SWPR_PAGE2_Pos (2U)
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#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
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#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
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#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
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#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
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#define SYSCFG_SWPR_PAGE3_Pos (3U)
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#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
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#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
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#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
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#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
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#define SYSCFG_SWPR_PAGE4_Pos (4U)
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#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
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#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
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#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
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#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
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#define SYSCFG_SWPR_PAGE5_Pos (5U)
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#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
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#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
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#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
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#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
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#define SYSCFG_SWPR_PAGE6_Pos (6U)
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#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
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#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
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#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
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#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
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#define SYSCFG_SWPR_PAGE7_Pos (7U)
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#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
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#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
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#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
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#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
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#define SYSCFG_SWPR_PAGE8_Pos (8U)
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#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
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#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
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#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
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#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
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#define SYSCFG_SWPR_PAGE9_Pos (9U)
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#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
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#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
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#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
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#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
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/****************** Bit definition for SYSCFG_SKR register ****************/
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#define SYSCFG_SKR_KEY_Pos (0U)
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#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
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@@ -13211,9 +13211,6 @@ typedef struct
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((INSTANCE) == TIM16) || \
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((INSTANCE) == TIM17))
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/****************** TIM Instances : supporting synchronization ****************/
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#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
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/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
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#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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((INSTANCE) == TIM8))
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@@ -9206,19 +9206,19 @@ typedef struct
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#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
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/******************** Bits definition for TAMP_FLTCR register ***************/
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#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
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#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
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#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
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#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
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#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
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#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
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#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
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#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
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#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
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#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
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#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
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#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
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#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
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#define TAMP_FLTCR_TAMPFLT_Pos (3U)
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#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
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#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
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#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
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#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
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#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
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#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
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#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
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#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
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#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
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@@ -10345,101 +10345,101 @@ typedef struct
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/****************** Bit definition for SYSCFG_SWPR register ****************/
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#define SYSCFG_SWPR_PAGE0_Pos (0U)
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#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
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#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
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#define SYSCFG_SWPR_PAGE1_Pos (1U)
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#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE2_Pos (2U)
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE3_Pos (3U)
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE4_Pos (4U)
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE5_Pos (5U)
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE6_Pos (6U)
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE7_Pos (7U)
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE8_Pos (8U)
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE9_Pos (9U)
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE10_Pos (10U)
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE11_Pos (11U)
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE12_Pos (12U)
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE13_Pos (13U)
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE14_Pos (14U)
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE15_Pos (15U)
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE16_Pos (16U)
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE17_Pos (17U)
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE18_Pos (18U)
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE19_Pos (19U)
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE20_Pos (20U)
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE21_Pos (21U)
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE22_Pos (22U)
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE23_Pos (23U)
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE24_Pos (24U)
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE25_Pos (25U)
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE26_Pos (26U)
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE27_Pos (27U)
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE28_Pos (28U)
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE29_Pos (29U)
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE30_Pos (30U)
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE31_Pos (31U)
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
/****************** Bit definition for SYSCFG_SKR register ****************/
|
||||
#define SYSCFG_SKR_KEY_Pos (0U)
|
||||
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
|
||||
@@ -13525,9 +13525,6 @@ typedef struct
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
@@ -9980,19 +9980,19 @@ typedef struct
|
||||
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
|
||||
|
||||
/******************** Bits definition for TAMP_FLTCR register ***************/
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
|
||||
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
|
||||
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
|
||||
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
|
||||
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
|
||||
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
|
||||
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
|
||||
@@ -11119,101 +11119,101 @@ typedef struct
|
||||
|
||||
/****************** Bit definition for SYSCFG_SWPR register ****************/
|
||||
#define SYSCFG_SWPR_PAGE0_Pos (0U)
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE1_Pos (1U)
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE2_Pos (2U)
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE3_Pos (3U)
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE4_Pos (4U)
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE5_Pos (5U)
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE6_Pos (6U)
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE7_Pos (7U)
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE8_Pos (8U)
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE9_Pos (9U)
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE10_Pos (10U)
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE11_Pos (11U)
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE12_Pos (12U)
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE13_Pos (13U)
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE14_Pos (14U)
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE15_Pos (15U)
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE16_Pos (16U)
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE17_Pos (17U)
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE18_Pos (18U)
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE19_Pos (19U)
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE20_Pos (20U)
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE21_Pos (21U)
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE22_Pos (22U)
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE23_Pos (23U)
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE24_Pos (24U)
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE25_Pos (25U)
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE26_Pos (26U)
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE27_Pos (27U)
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE28_Pos (28U)
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE29_Pos (29U)
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE30_Pos (30U)
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE31_Pos (31U)
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
/****************** Bit definition for SYSCFG_SKR register ****************/
|
||||
#define SYSCFG_SKR_KEY_Pos (0U)
|
||||
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
|
||||
@@ -14376,9 +14376,6 @@ typedef struct
|
||||
((INSTANCE) == TIM17) || \
|
||||
((INSTANCE) == TIM20))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
|
||||
@@ -13342,19 +13342,19 @@ typedef struct {
|
||||
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
|
||||
|
||||
/******************** Bits definition for TAMP_FLTCR register ***************/
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
|
||||
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
|
||||
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
|
||||
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
|
||||
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
|
||||
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
|
||||
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
|
||||
@@ -14481,101 +14481,101 @@ typedef struct {
|
||||
|
||||
/****************** Bit definition for SYSCFG_SWPR register ****************/
|
||||
#define SYSCFG_SWPR_PAGE0_Pos (0U)
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE1_Pos (1U)
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE2_Pos (2U)
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE3_Pos (3U)
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE4_Pos (4U)
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE5_Pos (5U)
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE6_Pos (6U)
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE7_Pos (7U)
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE8_Pos (8U)
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE9_Pos (9U)
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE10_Pos (10U)
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE11_Pos (11U)
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE12_Pos (12U)
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE13_Pos (13U)
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE14_Pos (14U)
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE15_Pos (15U)
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE16_Pos (16U)
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE17_Pos (17U)
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE18_Pos (18U)
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE19_Pos (19U)
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE20_Pos (20U)
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE21_Pos (21U)
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE22_Pos (22U)
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE23_Pos (23U)
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE24_Pos (24U)
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE25_Pos (25U)
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE26_Pos (26U)
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE27_Pos (27U)
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE28_Pos (28U)
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE29_Pos (29U)
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE30_Pos (30U)
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE31_Pos (31U)
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
/****************** Bit definition for SYSCFG_SKR register ****************/
|
||||
#define SYSCFG_SKR_KEY_Pos (0U)
|
||||
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
|
||||
@@ -17738,9 +17738,6 @@ typedef struct {
|
||||
((INSTANCE) == TIM17) || \
|
||||
((INSTANCE) == TIM20))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
|
||||
@@ -10211,19 +10211,19 @@ typedef struct
|
||||
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
|
||||
|
||||
/******************** Bits definition for TAMP_FLTCR register ***************/
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
|
||||
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
|
||||
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
|
||||
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
|
||||
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
|
||||
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
|
||||
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
|
||||
@@ -11350,101 +11350,101 @@ typedef struct
|
||||
|
||||
/****************** Bit definition for SYSCFG_SWPR register ****************/
|
||||
#define SYSCFG_SWPR_PAGE0_Pos (0U)
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE1_Pos (1U)
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE2_Pos (2U)
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE3_Pos (3U)
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE4_Pos (4U)
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE5_Pos (5U)
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE6_Pos (6U)
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE7_Pos (7U)
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE8_Pos (8U)
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE9_Pos (9U)
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE10_Pos (10U)
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE11_Pos (11U)
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE12_Pos (12U)
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE13_Pos (13U)
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE14_Pos (14U)
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE15_Pos (15U)
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE16_Pos (16U)
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE17_Pos (17U)
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE18_Pos (18U)
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE19_Pos (19U)
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE20_Pos (20U)
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE21_Pos (21U)
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE22_Pos (22U)
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE23_Pos (23U)
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE24_Pos (24U)
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE25_Pos (25U)
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE26_Pos (26U)
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE27_Pos (27U)
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE28_Pos (28U)
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE29_Pos (29U)
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE30_Pos (30U)
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE31_Pos (31U)
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
/****************** Bit definition for SYSCFG_SKR register ****************/
|
||||
#define SYSCFG_SKR_KEY_Pos (0U)
|
||||
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
|
||||
@@ -14609,9 +14609,6 @@ typedef struct
|
||||
((INSTANCE) == TIM17) || \
|
||||
((INSTANCE) == TIM20))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
|
||||
@@ -13573,19 +13573,19 @@ typedef struct {
|
||||
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
|
||||
|
||||
/******************** Bits definition for TAMP_FLTCR register ***************/
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
|
||||
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
|
||||
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
|
||||
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
|
||||
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
|
||||
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
|
||||
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
|
||||
@@ -14712,101 +14712,101 @@ typedef struct {
|
||||
|
||||
/****************** Bit definition for SYSCFG_SWPR register ****************/
|
||||
#define SYSCFG_SWPR_PAGE0_Pos (0U)
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE1_Pos (1U)
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE2_Pos (2U)
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE3_Pos (3U)
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE4_Pos (4U)
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE5_Pos (5U)
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE6_Pos (6U)
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE7_Pos (7U)
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE8_Pos (8U)
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE9_Pos (9U)
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE10_Pos (10U)
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
|
||||
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
|
||||
#define SYSCFG_SWPR_PAGE11_Pos (11U)
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
|
||||
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
|
||||
#define SYSCFG_SWPR_PAGE12_Pos (12U)
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
|
||||
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
|
||||
#define SYSCFG_SWPR_PAGE13_Pos (13U)
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
|
||||
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
|
||||
#define SYSCFG_SWPR_PAGE14_Pos (14U)
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
|
||||
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
|
||||
#define SYSCFG_SWPR_PAGE15_Pos (15U)
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
|
||||
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
|
||||
#define SYSCFG_SWPR_PAGE16_Pos (16U)
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
|
||||
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
|
||||
#define SYSCFG_SWPR_PAGE17_Pos (17U)
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
|
||||
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
|
||||
#define SYSCFG_SWPR_PAGE18_Pos (18U)
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
|
||||
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
|
||||
#define SYSCFG_SWPR_PAGE19_Pos (19U)
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
|
||||
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
|
||||
#define SYSCFG_SWPR_PAGE20_Pos (20U)
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
|
||||
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
|
||||
#define SYSCFG_SWPR_PAGE21_Pos (21U)
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
|
||||
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
|
||||
#define SYSCFG_SWPR_PAGE22_Pos (22U)
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
|
||||
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
|
||||
#define SYSCFG_SWPR_PAGE23_Pos (23U)
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
|
||||
#define SYSCFG_SWPR_PAGE24_Pos (24U)
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
|
||||
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
|
||||
#define SYSCFG_SWPR_PAGE25_Pos (25U)
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
|
||||
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
|
||||
#define SYSCFG_SWPR_PAGE26_Pos (26U)
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
|
||||
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
|
||||
#define SYSCFG_SWPR_PAGE27_Pos (27U)
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
|
||||
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
|
||||
#define SYSCFG_SWPR_PAGE28_Pos (28U)
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
|
||||
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
|
||||
#define SYSCFG_SWPR_PAGE29_Pos (29U)
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
|
||||
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
|
||||
#define SYSCFG_SWPR_PAGE30_Pos (30U)
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
|
||||
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
|
||||
#define SYSCFG_SWPR_PAGE31_Pos (31U)
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
|
||||
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
|
||||
/****************** Bit definition for SYSCFG_SKR register ****************/
|
||||
#define SYSCFG_SKR_KEY_Pos (0U)
|
||||
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
|
||||
@@ -17971,9 +17971,6 @@ typedef struct {
|
||||
((INSTANCE) == TIM17) || \
|
||||
((INSTANCE) == TIM20))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
|
||||
@@ -58,7 +58,7 @@
|
||||
*/
|
||||
|
||||
#if !defined (STM32G431xx) && !defined (STM32G441xx) && \
|
||||
!defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G483xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB)
|
||||
!defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB)
|
||||
/* #define STM32G431xx */ /*!< STM32G431xx Devices */
|
||||
/* #define STM32G441xx */ /*!< STM32G441xx Devices */
|
||||
/* #define STM32G471xx */ /*!< STM32G471xx Devices */
|
||||
@@ -82,11 +82,11 @@
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number $VERSION$
|
||||
* @brief CMSIS Device version number V1.1.1
|
||||
*/
|
||||
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
||||
@@ -8819,19 +8819,19 @@ typedef struct
|
||||
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
|
||||
|
||||
/******************** Bits definition for TAMP_FLTCR register ***************/
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
|
||||
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
|
||||
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
|
||||
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
|
||||
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
|
||||
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
|
||||
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
|
||||
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
|
||||
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
|
||||
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
|
||||
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
|
||||
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
|
||||
@@ -9875,35 +9875,35 @@ typedef struct
|
||||
|
||||
/****************** Bit definition for SYSCFG_SWPR register ****************/
|
||||
#define SYSCFG_SWPR_PAGE0_Pos (0U)
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_SWPR_PAGE1_Pos (1U)
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_SWPR_PAGE2_Pos (2U)
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
|
||||
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_SWPR_PAGE3_Pos (3U)
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
|
||||
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_SWPR_PAGE4_Pos (4U)
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
|
||||
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_SWPR_PAGE5_Pos (5U)
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
|
||||
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_SWPR_PAGE6_Pos (6U)
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
|
||||
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_SWPR_PAGE7_Pos (7U)
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
|
||||
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_SWPR_PAGE8_Pos (8U)
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
|
||||
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_SWPR_PAGE9_Pos (9U)
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
|
||||
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
|
||||
/****************** Bit definition for SYSCFG_SKR register ****************/
|
||||
#define SYSCFG_SKR_KEY_Pos (0U)
|
||||
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
|
||||
@@ -12925,9 +12925,6 @@ typedef struct
|
||||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM8))
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="../../../../../_htmresc/mini-st.css" />
|
||||
<link rel="stylesheet" href="_htmresc/mini-st.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
@@ -25,7 +25,7 @@
|
||||
<h1 id="release-notes-for-stm32g4xx-cmsis"><small>Release Notes for</small> STM32G4xx CMSIS</h1>
|
||||
<p>Copyright © 2019 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="../../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
@@ -51,11 +51,11 @@
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
|
||||
<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 14-February-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<h3 id="maintenance-release">Maintenance release</h3>
|
||||
<p>Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, <strong>STM32G483xx</strong>, STM32G474xx and STM32G484xx devices</p>
|
||||
<p>General updates to fix known defects and enhancements implementation</p>
|
||||
<h2 id="contents">Contents</h2>
|
||||
<table>
|
||||
<caption>Additional features<br />
|
||||
@@ -67,6 +67,61 @@
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">- General updates to fix known defects and enhancements implementation</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<table>
|
||||
<caption>Fixed bugs list<br />
|
||||
</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>Update STM32G473/483 startup files to support FDCAN2/3 intances</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td>Remove IS_TIM_SYNCHRO_INSTANCE macro from device header files</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="known-limitations">Known Limitations</h2>
|
||||
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
|
||||
<li>STM32CubeIDE toolchain v1.3.0</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32G431xx, STM32G441xx devices</li>
|
||||
<li>STM32G471xx devices</li>
|
||||
<li>STM32G473xx, STM32G483xx devices</li>
|
||||
<li>STM32G474xx, STM32G484xx devices</li>
|
||||
</ul>
|
||||
<p>Note: in the section above, main changes are highlighted in <strong>bold</strong> since previous release.</p>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<h3 id="maintenance-release-1">Maintenance release</h3>
|
||||
<p>Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, <strong>STM32G483xx</strong>, STM32G474xx and STM32G484xx devices</p>
|
||||
<h2 id="contents-1">Contents</h2>
|
||||
<table>
|
||||
<caption>Additional features<br />
|
||||
</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th style="text-align: left;">Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[STM32G483xx} New CMSIS driver files to support STM32G483xx</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
@@ -97,14 +152,14 @@
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="known-limitations">Known Limitations</h2>
|
||||
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
|
||||
<h2 id="known-limitations-1">Known Limitations</h2>
|
||||
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
|
||||
<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32G431xx, STM32G441xx devices</li>
|
||||
<li>STM32G471xx devices</li>
|
||||
@@ -117,12 +172,12 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.0.0 / 12-April-2019</label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<h3 id="first-release">First release</h3>
|
||||
<p>First official release for STM32G4xx devices</p>
|
||||
<h2 id="contents-1">Contents</h2>
|
||||
<h2 id="contents-2">Contents</h2>
|
||||
<p>CMSIS devices files for STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, STM32G474xx and STM32G484xx.</p>
|
||||
<h2 id="known-limitations-1">Known Limitations</h2>
|
||||
<h2 id="known-limitations-2">Known Limitations</h2>
|
||||
<table>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
@@ -135,13 +190,13 @@
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
|
||||
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
|
||||
<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32G431xx, STM32G441xx devices</li>
|
||||
<li>STM32G471xx devices</li>
|
||||
|
||||
+18
-6
@@ -100,8 +100,8 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_IRQHandler ; USB Device High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Device Low Priority
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
@@ -165,10 +165,10 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 error
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
@@ -267,6 +267,8 @@ Default_Handler PROC
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
@@ -321,6 +323,10 @@ Default_Handler PROC
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN3_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN3_IT1_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
@@ -355,6 +361,8 @@ DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
@@ -409,6 +417,10 @@ FPU_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
FDCAN3_IT0_IRQHandler
|
||||
FDCAN3_IT1_IRQHandler
|
||||
RNG_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
|
||||
+17
-5
@@ -164,11 +164,11 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 event
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 error
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES_IRQHandler ; AES global interrupt
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
@@ -267,6 +267,8 @@ Default_Handler PROC
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
@@ -322,6 +324,10 @@ Default_Handler PROC
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN3_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN3_IT1_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
@@ -356,6 +362,8 @@ DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
@@ -411,6 +419,10 @@ I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
AES_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
FDCAN3_IT0_IRQHandler
|
||||
FDCAN3_IT1_IRQHandler
|
||||
RNG_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
|
||||
+4
-7
@@ -79,7 +79,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -97,13 +97,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
|
||||
+4
-7
@@ -79,7 +79,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -97,13 +97,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
|
||||
+4
-7
@@ -79,7 +79,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -97,13 +97,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
|
||||
+28
-13
@@ -79,7 +79,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -97,13 +97,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
@@ -169,8 +166,8 @@ g_pfnVectors:
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word FDCAN1_IT0_IRQHandler
|
||||
.word FDCAN1_IT1_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_TIM15_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
@@ -234,10 +231,10 @@ g_pfnVectors:
|
||||
.word I2C4_ER_IRQHandler
|
||||
.word SPI4_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word FDCAN2_IT0_IRQHandler
|
||||
.word FDCAN2_IT1_IRQHandler
|
||||
.word FDCAN3_IT0_IRQHandler
|
||||
.word FDCAN3_IT1_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
@@ -349,6 +346,12 @@ g_pfnVectors:
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
@@ -511,6 +514,18 @@ g_pfnVectors:
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN3_IT0_IRQHandler
|
||||
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN3_IT1_IRQHandler
|
||||
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+4
-7
@@ -79,7 +79,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -97,13 +97,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
|
||||
+27
-13
@@ -79,7 +79,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -97,13 +97,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
@@ -169,8 +166,8 @@ g_pfnVectors:
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word FDCAN1_IT0_IRQHandler
|
||||
.word FDCAN1_IT1_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_TIM15_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
@@ -234,10 +231,10 @@ g_pfnVectors:
|
||||
.word I2C4_ER_IRQHandler
|
||||
.word SPI4_IRQHandler
|
||||
.word AES_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word FDCAN2_IT0_IRQHandler
|
||||
.word FDCAN2_IT1_IRQHandler
|
||||
.word FDCAN3_IT0_IRQHandler
|
||||
.word FDCAN3_IT1_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
@@ -349,6 +346,12 @@ g_pfnVectors:
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
@@ -514,6 +517,17 @@ g_pfnVectors:
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN3_IT0_IRQHandler
|
||||
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN3_IT1_IRQHandler
|
||||
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
+4
-7
@@ -78,7 +78,7 @@ LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
@@ -96,13 +96,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
|
||||
+3
-6
@@ -93,13 +93,10 @@ LoopFillZerobss:
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
|
||||
+36
-6
@@ -94,8 +94,8 @@ __vector_table
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_IRQHandler ; USB Device High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Device Low Priority
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
@@ -159,10 +159,10 @@ __vector_table
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 error
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
@@ -339,6 +339,16 @@ USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
@@ -609,6 +619,26 @@ I2C4_ER_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT0_IRQHandler
|
||||
B FDCAN2_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT1_IRQHandler
|
||||
B FDCAN2_IT1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN3_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN3_IT0_IRQHandler
|
||||
B FDCAN3_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN3_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN3_IT1_IRQHandler
|
||||
B FDCAN3_IT1_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
|
||||
+37
-7
@@ -94,8 +94,8 @@ __vector_table
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_IRQHandler ; USB Device High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Device Low Priority
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
@@ -158,11 +158,11 @@ __vector_table
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 event
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 error
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES_IRQHandler ; AES global interrupt
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
|
||||
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
@@ -339,6 +339,16 @@ USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
@@ -614,6 +624,26 @@ SPI4_IRQHandler
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT0_IRQHandler
|
||||
B FDCAN2_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT1_IRQHandler
|
||||
B FDCAN2_IT1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN3_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN3_IT0_IRQHandler
|
||||
B FDCAN3_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN3_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN3_IT1_IRQHandler
|
||||
B FDCAN3_IT1_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
|
||||
+158
-28
@@ -236,12 +236,12 @@
|
||||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
||||
#if defined(STM32G4)
|
||||
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
|
||||
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
|
||||
#if defined(STM32G4) || defined(STM32H7)
|
||||
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
|
||||
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
|
||||
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@@ -306,8 +306,17 @@
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||
#endif
|
||||
|
||||
#endif /* STM32L4 */
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
|
||||
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
|
||||
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
||||
@@ -365,6 +374,9 @@
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
|
||||
|
||||
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
|
||||
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
@@ -460,7 +472,9 @@
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#endif
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -564,7 +578,14 @@
|
||||
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
|
||||
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
|
||||
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
|
||||
#endif
|
||||
|
||||
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
|
||||
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
|
||||
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
@@ -735,6 +756,66 @@
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F3)
|
||||
/** @brief Constants defining available sources associated to external events.
|
||||
*/
|
||||
#define HRTIM_EVENTSRC_1 (0x00000000U)
|
||||
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
|
||||
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
|
||||
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
|
||||
|
||||
/** @brief Constants defining the events that can be selected to configure the
|
||||
* set/reset crossbar of a timer output
|
||||
*/
|
||||
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
|
||||
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
|
||||
|
||||
/** @brief Constants defining the event filtering applied to external events
|
||||
* by a timer
|
||||
*/
|
||||
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
|
||||
/** @brief Constants defining the DLL calibration periods (in micro seconds)
|
||||
*/
|
||||
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
|
||||
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
|
||||
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
|
||||
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
|
||||
|
||||
#endif /* STM32F3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -874,7 +955,7 @@
|
||||
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4)
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
|
||||
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
|
||||
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@@ -933,7 +1014,7 @@
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
@@ -965,6 +1046,16 @@
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1358,6 +1449,30 @@
|
||||
|
||||
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
|
||||
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
|
||||
|
||||
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
|
||||
|
||||
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
|
||||
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
|
||||
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
|
||||
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
|
||||
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
|
||||
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
|
||||
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
|
||||
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
|
||||
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
|
||||
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
|
||||
|
||||
#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1380,6 +1495,13 @@
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
|
||||
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1409,16 +1531,18 @@
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||
@@ -1437,6 +1561,13 @@
|
||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#endif
|
||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
|
||||
@@ -1509,14 +1640,14 @@
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
|
||||
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
|
||||
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -3112,9 +3243,8 @@
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4)
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
@@ -3242,7 +3372,7 @@
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
@@ -3350,22 +3480,22 @@
|
||||
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
|
||||
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
|
||||
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
/* alias CMSIS for compatibilities */
|
||||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
|
||||
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
|
||||
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
|
||||
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
|
||||
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
|
||||
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#if defined(STM32H7) || defined(STM32L5)
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
|
||||
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
|
||||
@@ -3606,12 +3736,12 @@
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
|
||||
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
@@ -3620,9 +3750,9 @@
|
||||
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32L4)
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||
#endif
|
||||
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
||||
@@ -64,9 +64,10 @@ typedef struct
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer in word */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
@@ -182,10 +183,12 @@ typedef struct
|
||||
|
||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
||||
|
||||
uint32_t Size_saved; /*!< copy of input buffer size */
|
||||
uint16_t Size_saved; /*!< copy of input buffer size */
|
||||
|
||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
|
||||
|
||||
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
|
||||
|
||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
||||
|
||||
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
|
||||
@@ -259,6 +262,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -565,6 +579,13 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
|
||||
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
|
||||
(((((ALGO) == CRYP_AES_CTR)) && \
|
||||
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
|
||||
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
|
||||
(((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
|
||||
((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -2,8 +2,7 @@
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_fmac.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the FMAC firmware
|
||||
* library.
|
||||
* @brief Header for stm32g4xx_hal_fmac.c module
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
@@ -135,7 +134,7 @@ typedef struct
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief FMAC Callback ID structure definition
|
||||
* @brief FMAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
@@ -165,31 +164,31 @@ typedef struct
|
||||
{
|
||||
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
|
||||
Ignored if InputBufferSize is set to 0 (previous configuration kept).
|
||||
NB: the buffers can overlap or even coincide exactly. */
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
|
||||
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
|
||||
in the buffer is inferior to this threshold.
|
||||
in the buffer is lower than this threshold.
|
||||
This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
|
||||
Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
|
||||
NB: the buffers can overlap or even coincide exactly. */
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer.
|
||||
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
|
||||
Ignored if OuputBufferSize is set to 0 (previous configuration kept).
|
||||
NB: the buffers can overlap or even coincide exactly. */
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
|
||||
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
|
||||
in the buffer is inferior to this threshold.
|
||||
in the buffer is lower than this threshold.
|
||||
This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
|
||||
@@ -202,13 +201,15 @@ typedef struct
|
||||
|
||||
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None.
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded).
|
||||
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
|
||||
is done when the clipping feature is disabled and saturation is done when the
|
||||
clipping feature is enabled.
|
||||
This parameter can be a value of @ref FMAC_Clip_State. */
|
||||
|
||||
uint32_t Filter; /*!< Filter type.
|
||||
@@ -237,17 +238,17 @@ typedef struct
|
||||
/** @defgroup FMAC_Error_Code FMAC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */
|
||||
#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */
|
||||
#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */
|
||||
#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */
|
||||
#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */
|
||||
#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */
|
||||
#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */
|
||||
#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
|
||||
#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
|
||||
#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
|
||||
#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
|
||||
#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
|
||||
#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */
|
||||
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */
|
||||
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -256,11 +257,11 @@ typedef struct
|
||||
/** @defgroup FMAC_Functions FMAC Functions
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
|
||||
#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
|
||||
#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
|
||||
#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
|
||||
#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
|
||||
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
|
||||
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
|
||||
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
|
||||
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
|
||||
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -269,15 +270,15 @@ typedef struct
|
||||
* @{
|
||||
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
|
||||
*/
|
||||
#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
|
||||
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
|
||||
#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
|
||||
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
|
||||
#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
|
||||
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
|
||||
#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
|
||||
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
|
||||
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */
|
||||
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -286,7 +287,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
|
||||
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */
|
||||
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
|
||||
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
|
||||
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
|
||||
/**
|
||||
@@ -296,7 +297,7 @@ typedef struct
|
||||
/** @defgroup FMAC_Clip_State FMAC Clip State
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */
|
||||
#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
|
||||
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
|
||||
/**
|
||||
* @}
|
||||
@@ -326,52 +327,13 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_DMAR DMA Read Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_DMAW DMA Write Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_DMAS DMA START bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_START FMAC_PARAM_START /*!< DMA Start */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* External variables --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
@@ -391,10 +353,10 @@ typedef struct
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the FMAC interrupt when result is ready
|
||||
* @brief Enable the specified FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
@@ -409,7 +371,7 @@ typedef struct
|
||||
* @brief Disable the FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
@@ -423,7 +385,7 @@ typedef struct
|
||||
/** @brief Check whether the specified FMAC interrupt occurred or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
@@ -445,7 +407,7 @@ typedef struct
|
||||
/** @brief Check whether the specified FMAC status flag is set or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
@@ -482,7 +444,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
@@ -499,7 +460,7 @@ typedef struct
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function.
|
||||
* @brief Verify the FMAC load function used for input data, output data or coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
@@ -508,7 +469,7 @@ typedef struct
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function.
|
||||
* @brief Verify the FMAC load function used with N values as input or output data.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
@@ -516,7 +477,7 @@ typedef struct
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function.
|
||||
* @brief Verify the FMAC load function used with N + M values as coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
@@ -591,6 +552,19 @@ typedef struct
|
||||
#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
|
||||
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
|
||||
|
||||
/**
|
||||
* @brief Check whether the threshold is applicable.
|
||||
* @param __SIZE__ Size of the matching buffer.
|
||||
* @param __WM__ Watermark value.
|
||||
* @param __ACCESS__ Access to the buffer (polling, it, dma, none).
|
||||
* @retval THRESHOLD
|
||||
*/
|
||||
#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
|
||||
((__WM__) == FMAC_THRESHOLD_2)? 2U: \
|
||||
((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
|
||||
((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
|
||||
((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -623,8 +597,8 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
int16_t *pOutput, uint8_t OutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
|
||||
@@ -82,6 +82,7 @@ extern "C" {
|
||||
#endif /* TIM5 */
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
|
||||
#if defined(TIM20)
|
||||
#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
|
||||
#endif /* TIM20 */
|
||||
@@ -214,6 +215,7 @@ extern "C" {
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
|
||||
@@ -245,6 +247,7 @@ extern "C" {
|
||||
#define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
|
||||
#endif /* FDCAN3 */
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
|
||||
|
||||
@@ -252,7 +255,8 @@ extern "C" {
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
@@ -1244,8 +1244,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
|
||||
/* Timer Events mapping for Timer C */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
|
||||
@@ -1268,7 +1268,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
|
||||
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
|
||||
@@ -1336,8 +1336,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
|
||||
/* Timer Events mapping for Timer C */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
|
||||
@@ -1360,7 +1360,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
|
||||
@@ -2368,7 +2368,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
* @{
|
||||
* @brief Constants defining the DLL calibration periods (in micro seconds)
|
||||
*/
|
||||
#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
|
||||
#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
|
||||
#define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
|
||||
#define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
|
||||
#define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
|
||||
@@ -3361,47 +3361,66 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
|
||||
((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
|
||||
|
||||
#define IS_HRTIM_EVENTSRC(EVENTSRC)\
|
||||
(((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \
|
||||
((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \
|
||||
((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))
|
||||
#define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \
|
||||
((((EVENT) == HRTIM_EVENT_1) && \
|
||||
(((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_2) && \
|
||||
(((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_3) && \
|
||||
(((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_4) && \
|
||||
(((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_5) && \
|
||||
(((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_6) && \
|
||||
(((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_7) && \
|
||||
(((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_8) && \
|
||||
(((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_9) && \
|
||||
(((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \
|
||||
((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \
|
||||
|| \
|
||||
(((EVENT) == HRTIM_EVENT_10) && \
|
||||
(((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \
|
||||
((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))))
|
||||
|
||||
#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
|
||||
((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
|
||||
@@ -3627,26 +3646,19 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
|
||||
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F))
|
||||
|
||||
#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
|
||||
(((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
|
||||
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \
|
||||
(((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
|
||||
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \
|
||||
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \
|
||||
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \
|
||||
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3))
|
||||
|
||||
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
|
||||
((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
|
||||
|| \
|
||||
(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| \
|
||||
(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| \
|
||||
(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| \
|
||||
(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| \
|
||||
(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| \
|
||||
(((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
|
||||
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
|
||||
((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
|
||||
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|
||||
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
|
||||
|
||||
#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
|
||||
(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
|
||||
|
||||
@@ -123,6 +123,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LPTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
@@ -13,7 +13,8 @@
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* ******************************************************************************
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
@@ -411,6 +412,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @note The following sequence is required to solve LPTIM disable HW limitation.
|
||||
* Please check Errata Sheet ES0335 for more details under "MCU may remain
|
||||
* stuck in LPTIM interrupt when entering Stop mode" section.
|
||||
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
|
||||
* check for TIMEOUT.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
|
||||
@@ -447,6 +450,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Autoreload value
|
||||
* @retval None
|
||||
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
||||
|
||||
@@ -455,6 +459,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Compare value
|
||||
* @retval None
|
||||
* @note The CMP register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
||||
|
||||
@@ -503,6 +508,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
@@ -519,6 +525,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
@@ -572,6 +579,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
@@ -579,7 +590,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
/* MSP functions *************************************************************/
|
||||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
@@ -628,12 +646,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
@@ -651,9 +683,19 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Group5
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -745,7 +787,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_9))
|
||||
#endif /* STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */
|
||||
#endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
|
||||
|
||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
||||
@@ -807,7 +849,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
|
||||
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -172,8 +172,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef;
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OPAMP_MSP_INIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */
|
||||
HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */
|
||||
HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */
|
||||
HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */
|
||||
HAL_OPAMP_ALL_CB_ID = 0x03UL /*!< OPAMP All ID */
|
||||
} HAL_OPAMP_CallbackIDTypeDef;
|
||||
|
||||
|
||||
@@ -196,7 +196,7 @@ typedef struct
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
|
||||
|
||||
@@ -1355,6 +1355,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
|
||||
@@ -132,7 +132,11 @@ typedef struct
|
||||
* @brief SMBUS handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __SMBUS_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
||||
|
||||
@@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
||||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
|
||||
@@ -582,11 +587,12 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
|
||||
|
||||
@@ -174,7 +174,7 @@ typedef struct
|
||||
This parameter can be a value of @ref TIM_Encoder_Mode */
|
||||
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
|
||||
|
||||
uint32_t IC1Selection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
@@ -186,7 +186,7 @@ typedef struct
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
|
||||
|
||||
uint32_t IC2Selection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
@@ -315,6 +315,26 @@ typedef enum
|
||||
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
|
||||
} HAL_TIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
|
||||
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
|
||||
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
|
||||
} HAL_TIM_ChannelStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Burst States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
|
||||
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
|
||||
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
|
||||
} HAL_TIM_DMABurstStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Active channel structures definition
|
||||
*/
|
||||
@@ -338,13 +358,16 @@ typedef struct __TIM_HandleTypeDef
|
||||
typedef struct
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
|
||||
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
|
||||
@@ -554,6 +577,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
|
||||
* @{
|
||||
*/
|
||||
#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
|
||||
#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ClockDivision TIM Clock Division
|
||||
* @{
|
||||
*/
|
||||
@@ -647,6 +679,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
|
||||
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
|
||||
* @{
|
||||
*/
|
||||
@@ -1182,25 +1223,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
@@ -1426,6 +1491,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
*/
|
||||
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
|
||||
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval None
|
||||
mode.
|
||||
*/
|
||||
#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
|
||||
|
||||
/**
|
||||
* @brief Disable update interrupt flag (UIF) remapping.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval None
|
||||
mode.
|
||||
*/
|
||||
#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
|
||||
|
||||
/**
|
||||
* @brief Get update interrupt flag (UIF) copy status.
|
||||
* @param __COUNTER__ Counter value.
|
||||
* @retval The state of UIFCPY (TRUE or FALSE).
|
||||
mode.
|
||||
*/
|
||||
#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
|
||||
|
||||
/**
|
||||
* @brief Indicates whether or not the TIM Counter is used as downcounter.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
@@ -1445,6 +1535,8 @@ mode.
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Counter Register value on runtime.
|
||||
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
|
||||
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __COUNTER__ specifies the Counter register new value.
|
||||
* @retval None
|
||||
@@ -1804,6 +1896,9 @@ mode.
|
||||
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
|
||||
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
|
||||
|
||||
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
|
||||
((__MODE__) == TIM_UIFREMAP_ENALE))
|
||||
|
||||
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
|
||||
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
|
||||
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
|
||||
@@ -1826,6 +1921,9 @@ mode.
|
||||
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
|
||||
((__STATE__) == TIM_OCNIDLESTATE_RESET))
|
||||
|
||||
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
|
||||
|
||||
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
|
||||
@@ -2046,22 +2144,6 @@ mode.
|
||||
((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
|
||||
|
||||
#if defined (TIM5) && defined(TIM20)
|
||||
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR3) || \
|
||||
((__SELECTION__) == TIM_TS_TI1F_ED) || \
|
||||
((__SELECTION__) == TIM_TS_TI1FP1) || \
|
||||
((__SELECTION__) == TIM_TS_TI2FP2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR4) || \
|
||||
((__SELECTION__) == TIM_TS_ITR5) || \
|
||||
((__SELECTION__) == TIM_TS_ITR6) || \
|
||||
((__SELECTION__) == TIM_TS_ITR7) || \
|
||||
((__SELECTION__) == TIM_TS_ITR8) || \
|
||||
((__SELECTION__) == TIM_TS_ITR9) || \
|
||||
((__SELECTION__) == TIM_TS_ITR10) || \
|
||||
((__SELECTION__) == TIM_TS_ITR11) || \
|
||||
((__SELECTION__) == TIM_TS_ETRF))
|
||||
|
||||
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
@@ -2077,22 +2159,6 @@ mode.
|
||||
((__SELECTION__) == TIM_TS_ITR11)|| \
|
||||
((__SELECTION__) == TIM_TS_NONE))
|
||||
#elif defined (TIM5)
|
||||
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR3) || \
|
||||
((__SELECTION__) == TIM_TS_TI1F_ED) || \
|
||||
((__SELECTION__) == TIM_TS_TI1FP1) || \
|
||||
((__SELECTION__) == TIM_TS_TI2FP2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR4) || \
|
||||
((__SELECTION__) == TIM_TS_ITR5) || \
|
||||
((__SELECTION__) == TIM_TS_ITR6) || \
|
||||
((__SELECTION__) == TIM_TS_ITR7) || \
|
||||
((__SELECTION__) == TIM_TS_ITR8) || \
|
||||
((__SELECTION__) == TIM_TS_ITR10) || \
|
||||
((__SELECTION__) == TIM_TS_ITR11) || \
|
||||
((__SELECTION__) == TIM_TS_ETRF))
|
||||
|
||||
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
@@ -2106,21 +2172,6 @@ mode.
|
||||
((__SELECTION__) == TIM_TS_ITR11)|| \
|
||||
((__SELECTION__) == TIM_TS_NONE))
|
||||
#else
|
||||
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR3) || \
|
||||
((__SELECTION__) == TIM_TS_TI1F_ED) || \
|
||||
((__SELECTION__) == TIM_TS_TI1FP1) || \
|
||||
((__SELECTION__) == TIM_TS_TI2FP2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR5) || \
|
||||
((__SELECTION__) == TIM_TS_ITR6) || \
|
||||
((__SELECTION__) == TIM_TS_ITR7) || \
|
||||
((__SELECTION__) == TIM_TS_ITR8) || \
|
||||
((__SELECTION__) == TIM_TS_ITR10) || \
|
||||
((__SELECTION__) == TIM_TS_ITR11) || \
|
||||
((__SELECTION__) == TIM_TS_ETRF))
|
||||
|
||||
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
@@ -2150,15 +2201,15 @@ mode.
|
||||
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
|
||||
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
|
||||
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
|
||||
@@ -2215,6 +2266,50 @@ mode.
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
|
||||
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
|
||||
(__HANDLE__)->ChannelState[5])
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
|
||||
(__HANDLE__)->ChannelNState[3])
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -2440,6 +2535,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Peripheral Channel state functions ************************************************/
|
||||
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -2459,7 +2559,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
||||
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
||||
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
|
||||
|
||||
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMAError(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
|
||||
|
||||
@@ -1839,6 +1839,7 @@ void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -226,6 +226,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -350,6 +351,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
|
||||
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
|
||||
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
|
||||
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
|
||||
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
|
||||
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
|
||||
@@ -404,6 +406,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
|
||||
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
|
||||
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -460,6 +463,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
* @arg @ref USART_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
|
||||
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
|
||||
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
|
||||
* @arg @ref USART_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref USART_FLAG_NE Noise Error flag
|
||||
@@ -480,6 +484,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
|
||||
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
|
||||
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
@@ -630,6 +635,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
|
||||
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
|
||||
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
|
||||
@@ -46,7 +46,7 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
/**
|
||||
* @}
|
||||
@@ -169,7 +169,6 @@ extern "C" {
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame length is valid.
|
||||
* @param __LENGTH__ USART frame length.
|
||||
|
||||
@@ -303,6 +303,6 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32G4xx_HAL_WWDG_H */
|
||||
#endif /* STM32G4xx_HAL_WWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@@ -2734,11 +2734,13 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set parameter common to several ADC: measurement path to internal
|
||||
* channels (VrefInt, temperature sensor, ...).
|
||||
* @brief Set parameter common to several ADC: measurement path to
|
||||
* internal channels (VrefInt, temperature sensor, ...).
|
||||
* Configure all paths (overwrite current configuration).
|
||||
* @note One or several values can be selected.
|
||||
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
|
||||
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
|
||||
* The values not selected are removed from configuration.
|
||||
* @note Stabilization time of measurement path to internal channel:
|
||||
* After enabling internal paths, before starting ADC conversion,
|
||||
* a delay is required for internal voltage reference and
|
||||
@@ -2767,6 +2769,65 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO
|
||||
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set parameter common to several ADC: measurement path to
|
||||
* internal channels (VrefInt, temperature sensor, ...).
|
||||
* Add paths to the current configuration.
|
||||
* @note One or several values can be selected.
|
||||
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
|
||||
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
|
||||
* @note Stabilization time of measurement path to internal channel:
|
||||
* After enabling internal paths, before starting ADC conversion,
|
||||
* a delay is required for internal voltage reference and
|
||||
* temperature sensor stabilization time.
|
||||
* Refer to device datasheet.
|
||||
* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
|
||||
* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
|
||||
* @note ADC internal channel sampling time constraint:
|
||||
* For ADC conversion of internal channels,
|
||||
* a sampling time minimum value is required.
|
||||
* Refer to device datasheet.
|
||||
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
|
||||
* CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
|
||||
* CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
|
||||
* @param ADCxy_COMMON ADC common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||
* @param PathInternal This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
|
||||
{
|
||||
SET_BIT(ADCxy_COMMON->CCR, PathInternal);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set parameter common to several ADC: measurement path to
|
||||
* internal channels (VrefInt, temperature sensor, ...).
|
||||
* Remove paths to the current configuration.
|
||||
* @note One or several values can be selected.
|
||||
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
|
||||
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
|
||||
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
|
||||
* CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
|
||||
* CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
|
||||
* @param ADCxy_COMMON ADC common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||
* @param PathInternal This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
|
||||
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
|
||||
{
|
||||
CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get parameter common to several ADC: measurement path to internal
|
||||
* channels (VrefInt, temperature sensor, ...).
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1248,7 +1248,7 @@ static const uint32_t REG_MASK_TAB_CPT[] =
|
||||
#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
|
||||
#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
|
||||
#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
|
||||
| HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
|
||||
| HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1379,9 +1379,8 @@ static const uint32_t REG_MASK_TAB_CPT[] =
|
||||
#define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
|
||||
#define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
|
||||
#define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
|
||||
|
||||
/* Timer Events mapping for Timer A */
|
||||
#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its ictive state */
|
||||
#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
|
||||
#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
|
||||
#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
|
||||
#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
|
||||
@@ -8038,7 +8037,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3
|
||||
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
|
||||
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
|
||||
* @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
|
||||
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
|
||||
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
|
||||
@@ -8544,7 +8543,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3
|
||||
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
|
||||
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
|
||||
* @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
|
||||
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
|
||||
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
|
||||
{
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LPTIM LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
@@ -301,7 +301,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -383,7 +382,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -436,7 +435,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -487,7 +486,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
|
||||
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
|
||||
* @note After a write to the LPTIMx_ARR register a new write operation to the
|
||||
* same register can only be performed when the previous write operation
|
||||
* is completed. Any successive write before the ARROK flag be set, will
|
||||
* is completed. Any successive write before the ARROK flag is set, will
|
||||
* lead to unpredictable results.
|
||||
* @note autoreload value be strictly greater than the compare value.
|
||||
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
|
||||
@@ -515,7 +514,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
|
||||
* @brief Set the compare value
|
||||
* @note After a write to the LPTIMx_CMP register a new write operation to the
|
||||
* same register can only be performed when the previous write operation
|
||||
* is completed. Any successive write before the CMPOK flag be set, will
|
||||
* is completed. Any successive write before the CMPOK flag is set, will
|
||||
* lead to unpredictable results.
|
||||
* @rmtoll CMP CMP LL_LPTIM_SetCompare
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
@@ -703,7 +702,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
|
||||
|
||||
/**
|
||||
* @brief Set LPTIM input 1 source (default GPIO).
|
||||
* @rmtoll OR IN1 LL_LPTIM_SetInput1Src
|
||||
* @rmtoll OR IN1 LL_LPTIM_SetInput1Src
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @param Src This parameter can be one of the following values:
|
||||
* @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
|
||||
@@ -716,12 +715,12 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
|
||||
{
|
||||
WRITE_REG(LPTIMx->OR, Src);
|
||||
MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LPTIM input 2 source (default GPIO).
|
||||
* @rmtoll OR IN2 LL_LPTIM_SetInput2Src
|
||||
* @rmtoll OR IN2 LL_LPTIM_SetInput2Src
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @param Src This parameter can be one of the following values:
|
||||
* @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
|
||||
@@ -733,7 +732,7 @@ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
|
||||
{
|
||||
WRITE_REG(LPTIMx->OR, Src);
|
||||
MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -783,7 +782,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1061,7 +1060,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1091,7 +1090,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1106,14 +1105,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Inform application whether a autoreload match interrupt has occured.
|
||||
* @brief Inform application whether a autoreload match interrupt has occurred.
|
||||
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1135,7 +1134,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1157,7 +1156,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1179,7 +1178,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1201,7 +1200,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1223,7 +1222,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1264,7 +1263,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1297,7 +1296,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1330,7 +1329,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1363,7 +1362,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1392,11 +1391,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
|
||||
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1425,11 +1424,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
|
||||
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
|
||||
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1458,11 +1457,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
|
||||
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
|
||||
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -470,50 +470,48 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBStandByModePD(void)
|
||||
|
||||
#if defined(PWR_CR3_UCPD_DBDIS)
|
||||
/**
|
||||
* @brief Enable (write 0) USB Type-C dead battery pull-down behavior
|
||||
* on UCPD1_CC1 and UCPD1_CC2 pins.
|
||||
* @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
|
||||
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
|
||||
* in all cases, either to stop this pull-down or to hand over control to the UCPD1
|
||||
* (which should therefore be initialized before doing the disable).
|
||||
* @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_EnableUSBDeadBattery
|
||||
* @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
|
||||
* on UCPD CC1 and CC2 pins.
|
||||
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
|
||||
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
|
||||
* to disable it in all cases, either to stop this pull-down or to hand over
|
||||
* control to the UCPD (which should therefore be initialized before doing the disable).
|
||||
* @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableUSBDeadBattery(void)
|
||||
__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable (write 1) USB Type-C dead battery pull-down behavior
|
||||
* on UCPD1_CC1 and UCPD1_CC2 pins.
|
||||
* @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
|
||||
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
|
||||
* in all cases, either to stop this pull-down or to hand over control to the UCPD1
|
||||
* (which should therefore be initialized before doing the disable).
|
||||
* @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_DisableUSBDeadBattery
|
||||
* @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
|
||||
* on UCPD CC1 and CC2 pins.
|
||||
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
|
||||
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
|
||||
* to disable it in all cases, either to stop this pull-down or to hand over
|
||||
* control to the UCPD (which should therefore be initialized before doing the disable).
|
||||
* @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableUSBDeadBattery(void)
|
||||
__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
|
||||
{
|
||||
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check USB Type-C dead battery pull-down behavior
|
||||
* on UCPD1_CC1 and UCPD1_CC2 pins.
|
||||
* @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
|
||||
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
|
||||
* in all cases, either to stop this pull-down or to hand over control to the UCPD1
|
||||
* (which should therefore be initialized before doing the disable).
|
||||
* @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_IsEnabledUSBDeadBattery
|
||||
* @retval State of bit.
|
||||
* @brief Check the USB Type-C and power delivery dead battery pull-down behavior
|
||||
* on UCPD CC1 and CC2 pins.
|
||||
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
|
||||
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
|
||||
* to disable it in all cases, either to stop this pull-down or to hand over
|
||||
* control to the UCPD (which should therefore be initialized before doing the disable).
|
||||
* @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
|
||||
* @retval State of feature (1 : enabled; 0 : disabled).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBDeadBattery(void)
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
|
||||
{
|
||||
|
||||
return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))?1UL:0UL);
|
||||
|
||||
return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
|
||||
}
|
||||
#endif /* PWR_CR3_UCPD_DBDIS */
|
||||
|
||||
@@ -753,28 +751,6 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
|
||||
return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
|
||||
}
|
||||
|
||||
#if defined (PWR_CR3_UCPD_DBDIS)
|
||||
/**
|
||||
* @brief Enable USB Type-C and Power Delivery Dead Battery disable
|
||||
* @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableDeadBatteryPD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableDeadBatteryPD(void)
|
||||
{
|
||||
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable USB Type-C and Power Delivery Dead Battery disable
|
||||
* @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableDeadBatteryPD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableDeadBatteryPD(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
|
||||
}
|
||||
#endif /* PWR_CR3_UCPD_DBDIS */
|
||||
|
||||
#if defined(PWR_CR3_UCPD_STDBY)
|
||||
/**
|
||||
* @brief Enable USB Type-C and Power Delivery standby mode.
|
||||
@@ -1613,6 +1589,12 @@ ErrorStatus LL_PWR_DeInit(void);
|
||||
/* Old functions name kept for legacy purpose, to be replaced by the */
|
||||
/* current functions name. */
|
||||
#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
|
||||
#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
|
||||
#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
|
||||
#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
|
||||
#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
|
||||
#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
@@ -3180,15 +3180,14 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
|
||||
{
|
||||
register uint32_t tmp = 0U;
|
||||
register __IO uint32_t *tmp;
|
||||
|
||||
UNUSED(RTCx);
|
||||
|
||||
tmp = (uint32_t)(&(TAMP->BKP0R));
|
||||
tmp += (BackupRegister * 4U);
|
||||
tmp = &(TAMP->BKP0R) + BackupRegister;
|
||||
|
||||
/* Write the specified register */
|
||||
*(__IO uint32_t *)tmp = (uint32_t)Data;
|
||||
*tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3205,15 +3204,14 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
|
||||
{
|
||||
register uint32_t tmp = 0U;
|
||||
const register __IO uint32_t *tmp;
|
||||
|
||||
UNUSED(RTCx);
|
||||
|
||||
tmp = (uint32_t)(&(TAMP->BKP0R));
|
||||
tmp += (BackupRegister * 4U);
|
||||
tmp = &(TAMP->BKP0R) + BackupRegister;
|
||||
|
||||
/* Read the specified register */
|
||||
return (*(__IO uint32_t *)tmp);
|
||||
return *tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -1314,7 +1314,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return (uint32_t) &(SPIx->DR);
|
||||
return (uint32_t) & (SPIx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user