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[lpc21] cleanup the VIC slot assignments

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see sw/airborne/arch/lpc21/vic_slots.txt for a summary of used VIC slots
This commit is contained in:
Felix Ruess
2013-02-05 23:49:48 +01:00
parent 92aa49534d
commit e981f80475
34 changed files with 132 additions and 121 deletions
Download Patch File Download Diff File Expand all files Collapse all files
conf/airframes/flixr_discovery.xml
-1
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@@ -17,7 +17,6 @@
<configure name="GPS_LED" value="none"/>
<!-- for airspeed sensor
<define name="USE_I2C0"/>
<define name="I2C0_VIC_SLOT" value="12"/>
-->
</target>
<target name="sim" board="pc"/>
conf/firmwares/booz2_test_progs.makefile
+10 -13
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@@ -75,7 +75,7 @@ test_max1168.srcs += $(SRC_ARCH)/mcu_periph/uart_arch.c
test_max1168.CFLAGS += -DDOWNLINK -DDOWNLINK_TRANSPORT=PprzTransport -DDOWNLINK_DEVICE=Uart1
test_max1168.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_transport.c
test_max1168.CFLAGS += -DMAX1168_EOC_VIC_SLOT=8 -DSSP_VIC_SLOT=9
test_max1168.CFLAGS += -DMAX1168_EOC_VIC_SLOT=11
test_max1168.srcs += peripherals/max1168.c \
$(SRC_ARCH)/peripherals/max1168_arch.c
@@ -100,7 +100,7 @@ test_micromag.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_tr
#test_micromag.CFLAGS += -I$(BOOZ)
#test_micromag.srcs += pprz_debug.c
test_micromag.CFLAGS += -DMICROMAG_DRDY_VIC_SLOT=8 -DSSP_VIC_SLOT=9
test_micromag.CFLAGS += -DMICROMAG_DRDY_VIC_SLOT=12
test_micromag.srcs += micromag.c $(SRC_ARCH)/micromag_hw.c
@@ -256,7 +256,7 @@ test_ami.srcs += $(SRC_ARCH)/mcu_periph/uart_arch.c
test_ami.CFLAGS += -DDOWNLINK -DDOWNLINK_TRANSPORT=PprzTransport -DDOWNLINK_DEVICE=Uart1
test_ami.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_transport.c
test_ami.CFLAGS += -DUSE_I2C1 -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_VIC_SLOT=11 -DI2C1_BUF_LEN=16
test_ami.CFLAGS += -DUSE_I2C1 -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_BUF_LEN=16
test_ami.srcs += i2c.c $(SRC_ARCH)/i2c_hw.c
test_ami.CFLAGS += -DUSE_AMI601
test_ami.srcs += AMI601.c
@@ -294,8 +294,7 @@ test_micromag2.ARCHDIR = $(ARCH)
test_micromag2.CFLAGS += -DBOARD_CONFIG=$(BOARD_CFG) -I$(SRC_BOOZ) -I$(SRC_BOOZ_ARCH)
test_micromag2.srcs += $(SRC_BOOZ_TEST)/booz2_test_micromag_2.c
test_micromag2.CFLAGS += -DSSP_VIC_SLOT=9
test_micromag2.CFLAGS += -DMICROMAG_DRDY_VIC_SLOT=8
test_micromag2.CFLAGS += -DMICROMAG_DRDY_VIC_SLOT=12
test_micromag2.CFLAGS += -DPERIODIC_FREQUENCY='50.' -DSYS_TIME_LED=1
test_micromag2.CFLAGS += -DUSE_LED
test_micromag2.srcs += mcu_periph/sys_time.c $(SRC_ARCH)/mcu_periph/sys_time_arch.c $(SRC_ARCH)/armVIC.c
@@ -333,9 +332,8 @@ test_imu_b2.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_tran
test_imu_b2.srcs += $(SRC_BOOZ)/booz_trig_int.c
test_imu_b2.CFLAGS += -DBOOZ2_IMU_TYPE=\"booz2_imu_b2.h\"
test_imu_b2.CFLAGS += -DSSP_VIC_SLOT=9
test_imu_b2.srcs += $(SRC_BOOZ)/booz2_imu_b2.c $(SRC_BOOZ_ARCH)/booz2_imu_b2_hw.c
test_imu_b2.CFLAGS += -DMAX1168_EOC_VIC_SLOT=8
test_imu_b2.CFLAGS += -DMAX1168_EOC_VIC_SLOT=11
test_imu_b2.srcs += $(SRC_BOOZ)/booz2_max1168.c $(SRC_BOOZ_ARCH)/booz2_max1168_hw.c
test_imu_b2.CFLAGS += -DFLOAT_T=float
test_imu_b2.srcs += $(SRC_BOOZ)/booz2_imu.c
@@ -426,7 +424,7 @@ test_mc.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_transpor
test_mc.CFLAGS += -DACTUATORS=\"actuators_buss_twi_blmc_hw.h\" -DUSE_BUSS_TWI_BLMC
test_mc.srcs += $(SRC_BOOZ_ARCH)/actuators_buss_twi_blmc_hw.c actuators.c
test_mc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150 -DI2C0_VIC_SLOT=10
test_mc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150
test_mc.srcs += i2c.c $(SRC_ARCH)/i2c_hw.c
@@ -450,7 +448,7 @@ test_buss_bldc.srcs += $(SRC_ARCH)/mcu_periph/uart_arch.c
test_buss_bldc.CFLAGS += -DDOWNLINK -DDOWNLINK_TRANSPORT=PprzTransport -DDOWNLINK_DEVICE=Uart1
test_buss_bldc.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_transport.c
test_buss_bldc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150 -DI2C0_VIC_SLOT=10
test_buss_bldc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150
test_buss_bldc.srcs += i2c.c $(SRC_ARCH)/i2c_hw.c
@@ -477,9 +475,8 @@ test_amc.srcs += $(SRC_FIRMWARE)/datalink.c
test_amc.CFLAGS += -DACTUATORS=\"actuators_asctec_twi_blmc_hw.h\"
test_amc.srcs += $(SRC_BOOZ_ARCH)/actuators_asctec_twi_blmc_hw.c actuators.c
test_amc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150 -DI2C0_VIC_SLOT=10
test_amc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150
test_amc.srcs += i2c.c $(SRC_ARCH)/i2c_hw.c
test_amc.CFLAGS += -DFLOAT_T=float
#-DBOOZ2_IMU_TYPE=\"booz2_imu_crista.h\"
@@ -496,7 +493,7 @@ test_mkk_bldc.srcs += $(SRC_BOOZ_TEST)/booz2_test_buss_bldc_hexa.c
test_mkk_bldc.CFLAGS += -DUSE_LED
test_mkk_bldc.CFLAGS += -DPERIODIC_FREQUENCY='512.' -DSYS_TIME_LED=1
test_mkk_bldc.srcs += mcu_periph/sys_time.c $(SRC_ARCH)/mcu_periph/sys_time_arch.c $(SRC_ARCH)/armVIC.c
test_mkk_bldc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150 -DI2C0_VIC_SLOT=10
test_mkk_bldc.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150
test_mkk_bldc.srcs += i2c.c $(SRC_ARCH)/i2c_hw.c
@@ -519,7 +516,7 @@ test_baro_24.srcs += $(SRC_ARCH)/mcu_periph/uart_arch.c
test_baro_24.CFLAGS += -DDOWNLINK -DDOWNLINK_TRANSPORT=PprzTransport -DDOWNLINK_DEVICE=Uart1
test_baro_24.srcs += subsystems/datalink/downlink.c subsystems/datalink/pprz_transport.c
test_baro_24.CFLAGS += -DUSE_I2C1 -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_VIC_SLOT=11 -DI2C1_BUF_LEN=16
test_baro_24.CFLAGS += -DUSE_I2C1 -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_BUF_LEN=16
test_baro_24.srcs += i2c.c $(SRC_ARCH)/i2c_hw.c
test_baro_24.srcs += $(SRC_BOOZ)/booz2_baro_24.c
conf/firmwares/subsystems/fixedwing/spi_slave_hs.makefile
-6
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@@ -3,12 +3,6 @@
#generic spi driver
$(TARGET).CFLAGS += -DUSE_SPI
ifeq ($(ARCH), lpc21)
$(TARGET).CFLAGS += -DSSP_VIC_SLOT=9
else ifeq ($(ARCH), stm32)
endif
ifeq ($(TARGET), sim)
else
conf/firmwares/subsystems/fixedwing/telemetry_w5100.makefile
-1
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@@ -17,7 +17,6 @@ ifeq ($(ARCH), lpc21)
# only an issue of setting the DRDY pin in w5100.c, which is stm32 specific
$(error Not implemented for the LCP21x yet.)
ap.CFLAGS += -DUSE_SPI1
ap.CFLAGS += -DSSP_VIC_SLOT=9
# default SPI device for W5100 is already SPI1
ap.CFLAGS += -DUSE_SPI_SLAVE0
ap.CFLAGS += -DW5100_SLAVE_IDX=0
conf/firmwares/subsystems/lisa_passthrough/imu_b2_v1.1.makefile
+2 -3
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@@ -49,9 +49,8 @@ imu_srcs += peripherals/ms2100.c
imu_srcs += $(SRC_ARCH)/peripherals/ms2100_arch.c
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DSSP_VIC_SLOT=9
imu_CFLAGS += -DMAX1168_EOC_VIC_SLOT=8
imu_CFLAGS += -DMS2100_DRDY_VIC_SLOT=11
imu_CFLAGS += -DMAX1168_EOC_VIC_SLOT=11
imu_CFLAGS += -DMS2100_DRDY_VIC_SLOT=12
else ifeq ($(ARCH), stm32)
imu_CFLAGS += -DUSE_SPI2
endif
conf/firmwares/subsystems/lisa_passthrough/imu_b2_v1.2.makefile
+2 -3
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@@ -49,10 +49,9 @@ imu_srcs += peripherals/hmc5843.c
imu_srcs += $(SRC_ARCH)/peripherals/hmc5843_arch.c
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DSSP_VIC_SLOT=9
imu_CFLAGS += -DMAX1168_EOC_VIC_SLOT=8
imu_CFLAGS += -DMAX1168_EOC_VIC_SLOT=11
#FIXME ms2100 not used on this imu
imu_CFLAGS += -DMS2100_DRDY_VIC_SLOT=11
imu_CFLAGS += -DMS2100_DRDY_VIC_SLOT=12
else ifeq ($(ARCH), stm32)
imu_CFLAGS += -DUSE_SPI2
imu_CFLAGS += -DUSE_I2C2
conf/firmwares/subsystems/rotorcraft/imu_crista.makefile
+1 -1
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@@ -70,7 +70,7 @@ imu_srcs += peripherals/ami601.c
imu_CFLAGS += -DUSE_I2C1
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_VIC_SLOT=12 -DI2C1_BUF_LEN=16
imu_CFLAGS += -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_BUF_LEN=16
else ifeq ($(ARCH), stm32)
#FIXME
endif
conf/firmwares/subsystems/rotorcraft/imu_crista_hmc5843.makefile
+1 -1
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@@ -71,7 +71,7 @@ imu_CFLAGS += -DUSE_HMC5843
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DUSE_I2C1
imu_CFLAGS += -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_VIC_SLOT=12 -DI2C1_BUF_LEN=16
imu_CFLAGS += -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_BUF_LEN=16
else ifeq ($(ARCH), stm32)
imu_CFLAGS += -DUSE_I2C2
endif
conf/firmwares/subsystems/shared/actuators_asctec.makefile
+1 -1
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@@ -4,7 +4,7 @@ ap.srcs += subsystems/actuators/actuators_asctec.c
ifeq ($(ARCH), lpc21)
ap.CFLAGS += -DACTUATORS_ASCTEC_DEVICE=i2c0
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150 -DI2C0_VIC_SLOT=10
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150
endif
ifeq ($(ARCH), stm32)
conf/firmwares/subsystems/shared/actuators_asctec_v2.makefile
+1 -1
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@@ -12,7 +12,7 @@ ap.srcs += subsystems/actuators/actuators_asctec.c
ifeq ($(ARCH), lpc21)
ap.CFLAGS += -DACTUATORS_ASCTEC_DEVICE=i2c0
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150 -DI2C0_VIC_SLOT=11
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=150 -DI2C0_SCLH=150
endif
ifeq ($(ARCH), stm32)
conf/firmwares/subsystems/shared/actuators_mkk.makefile
+1 -1
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@@ -32,7 +32,7 @@ MKK_I2C_SCL_TIME=150
endif
ap.CFLAGS += -DACTUATORS_MKK_DEVICE=i2c0
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=$(MKK_I2C_SCL_TIME) -DI2C0_SCLH=$(MKK_I2C_SCL_TIME) -DI2C0_VIC_SLOT=11
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=$(MKK_I2C_SCL_TIME) -DI2C0_SCLH=$(MKK_I2C_SCL_TIME)
else ifeq ($(ARCH), stm32)
ap.CFLAGS += -DACTUATORS_MKK_DEVICE=i2c1
conf/firmwares/subsystems/shared/actuators_skiron.makefile
+2 -2
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@@ -27,10 +27,10 @@ ap.srcs += subsystems/actuators/actuators_skiron.c
ifeq ($(ARCH), lpc21)
ap.CFLAGS += -DACTUATORS_SKIRON_DEVICE=i2c0
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=$(SKIRON_I2C_SCL_TIME) -DI2C0_SCLH=$(SKIRON_I2C_SCL_TIME) -DI2C0_VIC_SLOT=10
ap.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=$(SKIRON_I2C_SCL_TIME) -DI2C0_SCLH=$(SKIRON_I2C_SCL_TIME)
endif
# Simulator
nps.srcs += subsystems/actuators/actuators_skiron.c
nps.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=$(SKIRON_I2C_SCL_TIME) -DI2C0_SCLH=$(SKIRON_I2C_SCL_TIME) -DI2C0_VIC_SLOT=10 -DACTUATORS_SKIRON_DEVICE=i2c0
nps.CFLAGS += -DUSE_I2C0 -DI2C0_SCLL=$(SKIRON_I2C_SCL_TIME) -DI2C0_SCLH=$(SKIRON_I2C_SCL_TIME) -DACTUATORS_SKIRON_DEVICE=i2c0
conf/firmwares/subsystems/shared/imu_aspirin_v2.1.makefile
-1
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@@ -50,7 +50,6 @@ include $(CFG_SHARED)/spi.makefile
ifeq ($(ARCH), lpc21)
IMU_ASPIRIN_CFLAGS += -DUSE_SPI1
IMU_ASPIRIN_CFLAGS += -DSSP_VIC_SLOT=9
IMU_ASPIRIN_CFLAGS += -DUSE_SPI_SLAVE0
else ifeq ($(ARCH), stm32)
IMU_ASPIRIN_CFLAGS += -DUSE_SPI2
conf/firmwares/subsystems/shared/imu_b2_common.makefile
+1 -2
View File
@@ -50,8 +50,7 @@ include $(CFG_SHARED)/spi.makefile
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DUSE_SPI_SLAVE0
imu_CFLAGS += -DUSE_SPI1
imu_CFLAGS += -DSSP_VIC_SLOT=9
imu_CFLAGS += -DMAX1168_EOC_VIC_SLOT=8
imu_CFLAGS += -DMAX1168_EOC_VIC_SLOT=11
else ifeq ($(ARCH), stm32)
#FIXME: untested
imu_CFLAGS += -DUSE_SPI2 -DMAX1168_SPI_DEV=spi2
conf/firmwares/subsystems/shared/imu_b2_v1.0.makefile
+1 -1
View File
@@ -49,7 +49,7 @@ imu_CFLAGS += -DUSE_AMI601
imu_srcs += peripherals/ami601.c
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DUSE_I2C1 -DI2C1_SCLL=150 -DI2C1_SCLH=150 -DI2C1_VIC_SLOT=12
imu_CFLAGS += -DUSE_I2C1 -DI2C1_SCLL=150 -DI2C1_SCLH=150
else ifeq ($(ARCH), stm32)
#FIXME: untested
imu_CFLAGS += -DUSE_I2C2
conf/firmwares/subsystems/shared/imu_b2_v1.2.makefile
+1 -1
View File
@@ -44,7 +44,7 @@ imu_CFLAGS += -DIMU_B2_VERSION_1_2
ifeq ($(ARCH), lpc21)
imu_CFLAGS += -DIMU_B2_MAG_TYPE=IMU_B2_MAG_HMC58XX
imu_CFLAGS += -DHMC58XX_I2C_DEVICE=i2c1 -DUSE_I2C1 -DI2C1_VIC_SLOT=12
imu_CFLAGS += -DHMC58XX_I2C_DEVICE=i2c1 -DUSE_I2C1
imu_srcs += peripherals/hmc58xx.c
else ifeq ($(ARCH), stm32)
imu_CFLAGS += -DIMU_B2_MAG_TYPE=IMU_B2_MAG_HMC5843
sw/airborne/arch/lpc21/ADS8344.c
+8 -2
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@@ -79,6 +79,12 @@ uint16_t ADS8344_values[NB_CHANNELS];
static void SPI1_ISR(void) __attribute__((naked));
static uint8_t channel;
#warning "This driver should be updated to use the new SPI peripheral"
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
void ADS8344_init( void ) {
channel = 0;
ADS8344_available = FALSE;
@@ -94,8 +100,8 @@ void ADS8344_init( void ) {
/* initialize interrupt vector */
VICIntSelect &= ~VIC_BIT(VIC_SPI1); // SPI1 selected as IRQ
VICIntEnable = VIC_BIT(VIC_SPI1); // SPI1 interrupt enabled
VICVectCntl7 = VIC_ENABLE | VIC_SPI1;
VICVectAddr7 = (uint32_t)SPI1_ISR; // address of the ISR
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_CNTL(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; /* address of the ISR */
/* setup slave select */
/* configure SS pin */
sw/airborne/arch/lpc21/mcu_periph/i2c_arch.c
+2 -2
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@@ -196,7 +196,7 @@ __attribute__ ((always_inline)) static inline void I2cAutomaton(int32_t state, s
#endif
#ifndef I2C0_VIC_SLOT
#define I2C0_VIC_SLOT 9
#define I2C0_VIC_SLOT 8
#endif
@@ -279,7 +279,7 @@ void i2c0_hw_init ( void ) {
#endif
#ifndef I2C1_VIC_SLOT
#define I2C1_VIC_SLOT 11
#define I2C1_VIC_SLOT 9
#endif
sw/airborne/arch/lpc21/mcu_periph/spi_arch.h
-9
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@@ -35,13 +35,4 @@
#include "LPC21xx.h"
#include BOARD_CONFIG
// SSP is on SPI1 on lpc
#if defined USE_SSP & !USE_SPI1
#define USE_SP11 1
#endif
#if defined SSP_VIC_SLOT & !SPI1_VIC_SLOT
#define SPI1_VIC_SLOT SSP_VIC_SLOT
#endif
#endif /* SPI_ARCH_H */
sw/airborne/arch/lpc21/mcu_periph/spi_slave_hs_arch.c
+8 -2
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@@ -99,6 +99,12 @@ static void SSP_ISR(void) __attribute__((naked));
#define SSP_Read() SSPDR
#define SSP_Status() SSPSR
/** default initial settings */
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
void spi_init(void) {
/* setup pins for SSP (SCK, MISO, MOSI) */
@@ -114,8 +120,8 @@ void spi_init(void) {
/* initialize interrupt vector */
VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
_VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
// Enable SPI Slave
sw/airborne/arch/lpc21/modules/adcs/max11040_hw.c
+7 -2
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@@ -40,6 +40,11 @@ volatile uint8_t num_irqs = 0;
static void SSP_ISR(void) __attribute__((naked));
static void EXTINT_ISR(void) __attribute__((naked));
#warning "This driver should be updated to use the new SPI peripheral"
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
static void SSP_ISR(void) {
int i;
@@ -283,8 +288,8 @@ void max11040_hw_init( void ) {
/* initialize interrupt vector */
VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
_VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
/* *** configure DRDY pin*** */
sw/airborne/arch/lpc21/modules/display/lcd_dogm_hw.c
+7 -2
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@@ -48,6 +48,11 @@ static void SPI1_ISR(void) __attribute__((naked));
#define SSPCPSR_VAL 0x04
#endif
#warning "This driver should be updated to use the new SPI peripheral"
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
void lcd_spi_tx(uint8_t data) {
SpiClearRti();
@@ -74,8 +79,8 @@ void lcd_dogm_init_hw( void ) {
/* Configure interrupt vector for SPI */
VICIntSelect &= ~VIC_BIT(VIC_SPI1); /* SPI1 selected as IRQ */
VICIntEnable = VIC_BIT(VIC_SPI1); /* SPI1 interrupt enabled */
VICVectCntl7 = VIC_ENABLE | VIC_SPI1;
VICVectAddr7 = (uint32_t)SPI1_ISR; /* address of the ISR */
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_CNTL(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; /* address of the ISR */
}
void SPI1_ISR(void) {
sw/airborne/arch/lpc21/modules/sensors/mag_micromag_fw_hw.c
+7 -2
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@@ -15,6 +15,11 @@ volatile uint8_t micromag_cur_axe;
static void SSP_ISR(void) __attribute__((naked));
static void EXTINT_ISR(void) __attribute__((naked));
#warning "This driver should be updated to use the new SPI peripheral"
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
static void SSP_ISR(void) {
ISR_ENTRY();
@@ -50,8 +55,8 @@ void micromag_hw_init( void ) {
/* initialize interrupt vector */
VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
_VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
MmUnselect(); /* pin idles high */
/* configure SS pin */
sw/airborne/arch/lpc21/subsystems/actuators/servos_4015_hw.c
+5 -2
View File
@@ -39,15 +39,18 @@ uint16_t servos_values[_4015_NB_CHANNELS];
#define PWMIR_MRI_SERV0 PWMIR_MR5I
#define PWMIR_MRI_SERV1 PWMIR_MR2I
#ifndef PWM_VIC_SLOT
#define PWM_VIC_SLOT 3
#endif
void actuators_4015_init ( void ) {
/* PWM selected as IRQ */
VICIntSelect &= ~VIC_BIT(VIC_PWM);
/* PWM interrupt enabled */
VICIntEnable = VIC_BIT(VIC_PWM);
VICVectCntl3 = VIC_ENABLE | VIC_PWM;
_VIC_CNTL(PWM_VIC_SLOT) = VIC_ENABLE | VIC_PWM;
/* address of the ISR */
VICVectAddr3 = (uint32_t)PWM_ISR;
_VIC_ADDR(PWM_VIC_SLOT) = (uint32_t)PWM_ISR;
/* PW5 pin (P0.21) used for PWM */
IO0DIR |= _BV(SERV1_CLOCK_PIN);
IO1DIR |= _BV(SERV1_DATA_PIN) | _BV(SERV1_RESET_PIN);
sw/airborne/arch/lpc21/subsystems/actuators/servos_4015_hw_new.c
+5 -2
View File
@@ -39,15 +39,18 @@ uint16_t servos_values[_4015_NB_CHANNELS];
#define PWMIR_MRI_SERV0 PWMIR_MR5I
#define PWMIR_MRI_SERV1 PWMIR_MR2I
#ifndef PWM_VIC_SLOT
#define PWM_VIC_SLOT 3
#endif
void actuators_4015_init ( void ) {
/* PWM selected as IRQ */
VICIntSelect &= ~VIC_BIT(VIC_PWM);
/* PWM interrupt enabled */
VICIntEnable = VIC_BIT(VIC_PWM);
VICVectCntl3 = VIC_ENABLE | VIC_PWM;
_VIC_CNTL(PWM_VIC_SLOT) = VIC_ENABLE | VIC_PWM;
/* address of the ISR */
VICVectAddr3 = (uint32_t)PWM_ISR;
_VIC_ADDR(PWM_VIC_SLOT) = (uint32_t)PWM_ISR;
/* set clock, data and reset pins as output */
IO0DIR |= _BV(SERV0_CLOCK_PIN);
IO1DIR |= _BV(SERV0_DATA_PIN) | _BV(SERV0_RESET_PIN);
sw/airborne/arch/lpc21/subsystems/imu/imu_crista_arch.c
+4 -2
View File
@@ -53,6 +53,8 @@
static void SPI1_ISR(void) __attribute__((naked));
static uint8_t channel;
#warning "This driver should be updated to use the new SPI peripheral"
void imu_crista_arch_init(void) {
channel = 0;
@@ -67,8 +69,8 @@ void imu_crista_arch_init(void) {
/* initialize interrupt vector */
VICIntSelect &= ~VIC_BIT(VIC_SPI1); // SPI1 selected as IRQ
VICIntEnable = VIC_BIT(VIC_SPI1); // SPI1 interrupt enabled
VICVectCntl7 = VIC_ENABLE | VIC_SPI1;
VICVectAddr7 = (uint32_t)SPI1_ISR; // address of the ISR
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; // address of the ISR
/* setup slave select */
/* configure SS pin */
sw/airborne/arch/lpc21/usb_ser_hw.c
+6 -2
View File
@@ -62,6 +62,10 @@
#endif
#endif
#ifndef USB_VIC_SLOT
#define USB_VIC_SLOT 10
#endif
#define INT_IN_EP 0x81
#define BULK_OUT_EP 0x05
#define BULK_IN_EP 0x82
@@ -579,8 +583,8 @@ void VCOM_init(void) {
VICIntSelect &= ~VIC_BIT(VIC_USB); // select IRQ for USB
VICIntEnable = VIC_BIT(VIC_USB);
VICVectCntl10 = VIC_ENABLE | VIC_USB;
VICVectAddr10 = (uint32_t)USBIntHandler;
_VIC_CNTL(USB_VIC_SLOT) = VIC_ENABLE | VIC_USB;
_VIC_ADDR(USB_VIC_SLOT) = (uint32_t)USBIntHandler;
// connect to bus
USBHwConnect(TRUE);
sw/airborne/arch/lpc21/vic_slots.txt
+26
View File
@@ -0,0 +1,26 @@
VIC slots used for the LPC2148
define name slot (default) used for
------------------------------------------------------------------
TIMER0_VIC_SLOT 1 system timer
AD0_VIC_SLOT 2 adc_arch if USE_AD0
PWM_VIC_SLOT 3 PWM_ISR in servos_4015
AD1_VIC_SLOT 4 adc_arch if USE_AD1
UART0_VIC_SLOT 5 uart_arch, e.g. gps
UART1_VIC_SLOT 6 uart_arch, e.g. modem
SPI1_VIC_SLOT 7 SPI1 in mcu_periph/spi_arch.c or spi_slave_hs_arch.c (and some others not using the SPI peripheral yet..)
I2C0_VIC_SLOT 8 mcu_periph/i2c_arch.c
I2C1_VIC_SLOT 9 mcu_periph/i2c_arch.c
USB_VIC_SLOT 10 usb, e.g. telemetry_transparent_usb
no defaults, explicitly set in subsystems:
MAX1168_EOC_VIC_SLOT 11 imu_b2_v1.0, imu_b2_v1.1, imu_b2_v1.2
MS2100_DRDY_VIC_SLOT 12 ms2100 mag in imu_b2_v1.1
in modules:
hardcoded, no define 8 EXTINT in max3100 module
these seem to be outdated, should be updated to use the new spi driver:
MAX11040_DRDY_VIC_SLOT 12 max11040_hw.c
MICROMAG_DRDY_VIC_SLOT 12 micromag_hw.c
sw/airborne/arch/lpc21/vic_slots_fw.txt
-23
View File
@@ -1,23 +0,0 @@
VIC slots used for fixedwings with the LPC2148
define name slot (default) used for
------------------------------------------------------------------
TIMER0_VIC_SLOT 1 (1) system timer
AD0_VIC_SLOT 2 (2) was for adc battery (not needed anymore?)
hardcoded, no define 3 PWM_ISR in servos_4015
AD1_VIC_SLOT 4 (4) was for adc baro (not needed anymore?)
UART0_VIC_SLOT 5 (5) uart_arch, e.g. gps
UART1_VIC_SLOT 6 (6) uart_arch, e.g. modem
hardcoded, no define 7 SPI1 in mcu_periph/spi_arch.c, imu_crista_arch, max3100 module, baro_scp module, lcd_dogm module
MAX1168_EOC_VIC_SLOT 8 imu_b2_v1.0, imu_b2_v1.1, imu_b2_v1.2
hardcoded, no define 8 EXTINT in max3100 module
I2C0_VIC_SLOT ? (9) (9 is default in mcu_periph/i2c_arch.c)
SSP_VIC_SLOT 9 imu_b2_v1.0, imu_b2_v1.1, imu_b2_v1.2
MICROMAG_DRDY_VIC_SLOT 9 micromag
hardcoded, no define 10 usb, e.g. telemetry_transparent_usb
hardcoded, no define 11 EXTINT in baro_scp module
I2C1_VIC_SLOT ? (11) (11 is default in mcu_periph/i2c_arch.c)
I2C1_VIC_SLOT 12 ami601 in imu_b2_v1.0, imu_crista
MS2100_DRDY_VIC_SLOT 12 ms2100 mag in imu_b2_v1.1
MAX11040_DRDY_VIC_SLOT ? max11040 adc module
sw/airborne/arch/lpc21/vic_slots_rotorcrafts.txt
-20
View File
@@ -1,20 +0,0 @@
VIC slots used for rotorcrafts with the LPC2148
define name slot (default) used for
------------------------------------------------------------------
TIMER0_VIC_SLOT 1 (1) system timer
AD0_VIC_SLOT 2 (2) adc_arch if USE_AD0
AD1_VIC_SLOT 4 (4) adc_arch if USE_AD1
UART0_VIC_SLOT 5 (5) uart_arch, e.g. gps
UART1_VIC_SLOT 6 (6) uart_arch, e.g. modem
SPI1_VIC_SLOT 7 (7) SPI1 in mcu_periph/spi_arch.c, imu_crista_arch
MAX1168_EOC_VIC_SLOT 8 imu_b2_v1.0, imu_b2_v1.1, imu_b2_v1.2
SSP_VIC_SLOT 9 imu_b2_v1.0, imu_b2_v1.1, imu_b2_v1.2
hardcoded, no define 10 usb, e.g. telemetry_transparent_usb
I2C0_VIC_SLOT 11 (9) actuators_acstec, actuators_acstec_v2, actuators_mkk, (9 is default in mcu_periph/i2c_arch.c)
I2C1_VIC_SLOT 12 (11) ami601 in imu_b2_v1.0, imu_crista
MS2100_DRDY_VIC_SLOT 12 ms2100 mag in imu_b2_v1.1
MAX11040_DRDY_VIC_SLOT max11040_hw.c
MICROMAG_DRDY_VIC_SLOT micromag_hw.c
sw/airborne/booz/test/booz2_test_max1168.c
+4 -3
View File
@@ -108,6 +108,10 @@ static inline void main_event_task( void ) {
#define SSP_DisableRti() ClearBit(SSPIMSC, RTIM);
#define SSP_ClearRti() SetBit(SSPICR, RTIC);
#ifndef SSP_VIC_SLOT
#define SSP_VIC_SLOT 7
#endif
static void main_init_ssp(void) {
@@ -125,9 +129,6 @@ static void main_init_ssp(void) {
_VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
}
static void SSP_ISR(void) {
sw/airborne/booz/test/booz2_test_micromag.c
+3 -3
View File
@@ -138,6 +138,9 @@ static inline void main_event_task( void ) {
#define SSP_DisableRti() ClearBit(SSPIMSC, RTIM);
#define SSP_ClearRti() SetBit(SSPICR, RTIC);
#ifndef SSP_VIC_SLOT
#define SSP_VIC_SLOT 7
#endif
static void main_init_ssp(void) {
@@ -155,9 +158,6 @@ static void main_init_ssp(void) {
_VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
}
static void SSP_ISR(void) {
sw/airborne/modules/max3100/max3100_hw.c
+8 -2
View File
@@ -68,6 +68,12 @@ static void SPI1_ISR(void) __attribute__((naked));
#define SSPCPSR_VAL 0x04
#endif
#warning "This driver should be updated to use the new SPI peripheral"
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
void max3100_init( void ) {
max3100_status = MAX3100_STATUS_IDLE;
@@ -112,8 +118,8 @@ void max3100_init( void ) {
/* Configure interrupt vector for SPI */
VICIntSelect &= ~VIC_BIT(VIC_SPI1); /* SPI1 selected as IRQ */
VICIntEnable = VIC_BIT(VIC_SPI1); /* SPI1 interrupt enabled */
VICVectCntl7 = VIC_ENABLE | VIC_SPI1;
VICVectAddr7 = (uint32_t)SPI1_ISR; /* address of the ISR */
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_CNTL(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; /* address of the ISR */
/* Write configuration */
//Max3100TransmitConf(MAX3100_BAUD_RATE | MAX3100_BIT_NOT_TM);
sw/airborne/modules/sensors/baro_scp.c
+8 -2
View File
@@ -64,6 +64,12 @@ void baro_scp_periodic(void) {
#define ScpSelect() SetBit(SS_IOCLR,SS_PIN)
#define ScpUnselect() SetBit(SS_IOSET,SS_PIN)
#warning "This driver should be updated to use the new SPI peripheral"
#ifndef SPI1_VIC_SLOT
#define SPI1_VIC_SLOT 7
#endif
void baro_scp_init( void ) {
/* setup pins for SSP (SCK, MISO, MOSI) */
PINSEL1 |= 2 << 2 | 2 << 4 | 2 << 6;
@@ -77,8 +83,8 @@ void baro_scp_init( void ) {
/* initialize interrupt vector */
VICIntSelect &= ~VIC_BIT(VIC_SPI1); // SPI1 selected as IRQ
VICIntEnable = VIC_BIT(VIC_SPI1); // SPI1 interrupt enabled
VICVectCntl7 = VIC_ENABLE | VIC_SPI1;
VICVectAddr7 = (uint32_t)SPI1_ISR; // address of the ISR
_VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
_VIC_CNTL(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; /* address of the ISR */
/* configure SS pin */
SetBit(SS_IODIR, SS_PIN); /* pin is output */