Mirrors_Framework/paparazzi
1
0
Fork 0
mirror of https://github.com/paparazzi/paparazzi.git synced 2026-02-06 02:52:42 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

[uavcan] memory offset can lines (#3508)
Some checks failed
Issues due date / Add labels to issues (push) Has been cancelled
Details
Doxygen / build (push) Has been cancelled
Details

Browse Source 
* add memory offset

* try Fabien's changes

* convert last hardcoded can1 and remove test

* initialize can frame to zero
This commit is contained in:
NoahWe
2025-07-28 17:50:47 +02:00
committed by GitHub
parent 66ba4c9918
commit e46c1e74b5
1 changed files with 10 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
sw/airborne/arch/chibios/mcu_periph/can_arch.c
View File

@@ -26,6 +26,7 @@ struct can_arch_periph {
CANDriver* cand;
CANConfig cfg;
uint32_t can_baudrate;
uint16_t memory_offset;
void *thread_rx_wa;
size_t thread_rx_wa_size;
@@ -44,6 +45,7 @@ struct can_arch_periph can1_arch_s = {
.cand = &CAND1,
.cfg = {0},
.can_baudrate = 1000000U,
.memory_offset = 0,
.thread_rx_wa = can1_rx_wa,
.thread_rx_wa_size = sizeof(can1_rx_wa),
};
@@ -59,6 +61,7 @@ struct can_arch_periph can2_arch_s = {
.cand = &CAND2,
.cfg = {0},
.can_baudrate = 1000000U,
.memory_offset = (128*3),
.thread_rx_wa = can2_rx_wa,
.thread_rx_wa_size = sizeof(can2_rx_wa),
};
@@ -147,7 +150,7 @@ static void can_thd_rx(void* arg) {
}
int can_transmit_frame(struct pprzcan_frame* txframe, struct pprzaddr_can* addr) {
CANTxFrame frame;
CANTxFrame frame = {0};
frame.DLC = can_len_to_dlc(txframe->len);
if(txframe->can_id & CAN_FRAME_RTR) {
frame.common.RTR = 1;
@@ -186,18 +189,18 @@ static void can_start(struct can_periph* canp) {
#if defined(STM32_CAN_USE_FDCAN1) || defined(STM32_CAN_USE_FDCAN2)
// Configure the RAM
can1_arch_s.cfg.RXF0C = (32 << FDCAN_RXF0C_F0S_Pos) | (0 << FDCAN_RXF0C_F0SA_Pos);
can1_arch_s.cfg.RXF1C = (32 << FDCAN_RXF1C_F1S_Pos) | (128 << FDCAN_RXF1C_F1SA_Pos);
can1_arch_s.cfg.TXBC = (32 << FDCAN_TXBC_TFQS_Pos) | (256 << FDCAN_TXBC_TBSA_Pos);
can1_arch_s.cfg.TXESC = 0x000; // 8 Byte mode only (4 words per message)
can1_arch_s.cfg.RXESC = 0x000; // 8 Byte mode only (4 words per message)
cas->cfg.RXF0C = (32 << FDCAN_RXF0C_F0S_Pos) | ((cas->memory_offset+0) << FDCAN_RXF0C_F0SA_Pos);
cas->cfg.RXF1C = (32 << FDCAN_RXF1C_F1S_Pos) | ((cas->memory_offset+128) << FDCAN_RXF1C_F1SA_Pos);
cas->cfg.TXBC = (32 << FDCAN_TXBC_TFQS_Pos) | ((cas->memory_offset+256) << FDCAN_TXBC_TBSA_Pos);
cas->cfg.TXESC = 0x000; // 8 Byte mode only (4 words per message)
cas->cfg.RXESC = 0x000; // 8 Byte mode only (4 words per message)
#endif
if (!canConfigureIface(cas)) {
return;
}
canStart(cas->cand, &can1_arch_s.cfg);
canStart(cas->cand, &cas->cfg);
chThdCreateStatic(cas->thread_rx_wa, cas->thread_rx_wa_size,
NORMALPRIO + 8, can_thd_rx, canp);
}