[mcu_periph] gpio helper functions

also removed the old gpio1 that was used on lpc and fixedwing firmware

conf/firmwares/lisa_test_progs.makefile

@@ -67,6 +67,7 @@ COMMON_TEST_CFLAGS  = -I$(SRC_FIRMWARE) -I$(SRC_BOARD) -DPERIPHERALS_AUTO_INIT
 COMMON_TEST_CFLAGS += -DBOARD_CONFIG=$(BOARD_CFG)
 COMMON_TEST_SRCS    = $(SRC_AIRBORNE)/mcu.c            \
                       $(SRC_ARCH)/mcu_arch.c
+COMMON_TEST_SRCS   += $(SRC_ARCH)/mcu_periph/gpio_arch.c
 COMMON_TEST_CFLAGS += -DUSE_SYS_TIME
 ifneq ($(SYS_TIME_LED),none)
   COMMON_TEST_CFLAGS += -DSYS_TIME_LED=$(SYS_TIME_LED)

conf/firmwares/rotorcraft.makefile

@@ -64,6 +64,10 @@ ifeq ($(ARCH), lpc21)
 ap.srcs += $(SRC_ARCH)/armVIC.c
 endif
 
+ifeq ($(ARCH), stm32)
+ap.srcs += $(SRC_ARCH)/mcu_periph/gpio_arch.c
+endif
+
 #
 # LEDs
 #
@@ -73,7 +77,7 @@ ap.srcs += $(SRC_ARCH)/led_hw.c
 endif
 
 ifeq ($(BOARD)$(BOARD_TYPE), ardroneraw)
-ap.srcs   += $(SRC_BOARD)/gpio.c
+ap.srcs   += $(SRC_BOARD)/gpio_ardrone.c
 endif
 
 # frequency of main periodic

conf/firmwares/subsystems/fixedwing/autopilot.makefile

@@ -107,6 +107,7 @@ endif
 
 ifeq ($(ARCH), stm32)
   ns_srcs 		+= lisa/plug_sys.c
+  ns_srcs       += $(SRC_ARCH)/mcu_periph/gpio_arch.c
 endif
 
 

sw/airborne/arch/lpc21/gpio.c

@@ -1,3 +0,0 @@
-#include "gpio.h"
-
-bool_t gpio1_status;

sw/airborne/arch/lpc21/gpio.h

@@ -1,39 +0,0 @@
-#ifndef GPIO_H
-#define GPIO_H
-
-#include "std.h"
-#include "LPC21xx.h"
-
-extern bool_t gpio1_status;
-
-#define GPIO_1_BANK 0
-#define GPIO_1_PIN 7
-#define GPIO_1_PINSEL PINSEL0
-#define GPIO_1_PINSEL_BIT 14
-#define GPIO_1_PINSEL_VAL 0
-#define GPIO_1_DIR IO0DIR
-
-#define GpioOn1() { \
- gpio1_status = TRUE; \
- IO0SET = _BV(GPIO_1_PIN); \
-}
-
-#define GpioOff1() { \
- gpio1_status = FALSE; \
- IO0CLR = _BV(GPIO_1_PIN); \
-}
-
-#define GpioUpdate1() { \
- if (gpio1_status) \
-   IO0SET = _BV(GPIO_1_PIN); \
- else \
-   IO0CLR = _BV(GPIO_1_PIN); \
-}
-
-#define GpioInit() { \
-  GPIO_1_PINSEL |= GPIO_1_PINSEL_VAL << GPIO_1_PINSEL_BIT; \
-  GPIO_1_DIR |= _BV(GPIO_1_PIN); \
-  GpioOff1(); \
-}
-
-#endif /* GPIO_H */

sw/airborne/arch/lpc21/mcu_periph/gpio_arch.h

@@ -1,10 +1,55 @@
-#ifndef MY_GPIO_ARCH_H
-#define MY_GPIO_ARCH_H
+/*
+ * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
+ *
+ * This file is part of paparazzi.
+ *
+ * paparazzi is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * paparazzi is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with paparazzi; see the file COPYING.  If not, write to
+ * the Free Software Foundation, 59 Temple Place - Suite 330,
+ * Boston, MA 02111-1307, USA.
+ */
 
+/**
+ * @file arch/lpc21/mcu_periph/gpio_arch.h
+ *
+ * GPIO helper functions for LPC21xx.
+ */
 
-#define GPIO_ARCH_SET_SPI_CS_HIGH()					\
-{									\
+#ifndef GPIO_ARCH_H
+#define GPIO_ARCH_H
+
+#include "std.h"
+#include "LPC21xx.h"
+
+/**
+ * Set a gpio output to high level.
+ */
+static inline void gpio_output_high(uint32_t port, uint16_t pin) {
+  if (port == 0)
+    IO0SET = _BV(pin);
+  else if (port == 1)
+    IO1SET = _BV(pin);
+}
+
+/**
+ * Clear a gpio output to low level.
+ */
+static inline void gpio_output_low(uint32_t port, uint16_t pin) {
+  if (port == 0)
+    IO0CLR = _BV(pin);
+  else if (port == 1)
+    IO1CLR = _BV(pin);
 }
 
 
-#endif /* MY_GPIO_ARCH_H */
+#endif /* GPIO_ARCH_H */

sw/airborne/arch/sim/gpio.h

@@ -1,7 +0,0 @@
-#ifndef GPIO_H
-#define GPIO_H
-
-extern bool_t gpio1_status;
-
-#endif /* GPIO_H */
-

sw/airborne/arch/sim/jsbsim_hw.c

@@ -19,7 +19,6 @@
 uint8_t gps_nb_ovrn, link_fbw_fbw_nb_err, link_fbw_nb_err;
 //float alt_roll_pgain;
 //float roll_rate_pgain;
-//bool_t gpio1_status;
 uint16_t adc_generic_val1;
 uint16_t adc_generic_val2;
 //uint16_t ppm_pulses[ PPM_NB_PULSES ];

sw/airborne/arch/sim/sim_ap.c

@@ -41,7 +41,6 @@ bool_t launch;
 uint8_t gps_nb_ovrn, link_fbw_fbw_nb_err, link_fbw_nb_err;
 float alt_roll_pgain;
 float roll_rate_pgain;
-bool_t gpio1_status;
 uint16_t datalink_time = 0;
 
 

sw/airborne/arch/stm32/gpio.h

@@ -1,6 +0,0 @@
-#ifndef GPIO_H
-#define GPIO_H
-
-/* this is an empty header for now to make things build on stm32 */
-
-#endif /* GPIO_H */

sw/airborne/arch/stm32/mcu_periph/gpio_arch.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
+ *
+ * This file is part of paparazzi.
+ *
+ * paparazzi is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * paparazzi is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with paparazzi; see the file COPYING.  If not, write to
+ * the Free Software Foundation, 59 Temple Place - Suite 330,
+ * Boston, MA 02111-1307, USA.
+ */
+
+/**
+ * @file arch/stm32/mcu_periph/gpio_arch.c
+ * @ingroup stm32_arch
+ *
+ * GPIO helper functions for STM32F1 and STM32F4.
+ */
+
+#include "mcu_periph/gpio.h"
+
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/rcc.h>
+
+#ifdef STM32F1
+void gpio_enable_clock(uint32_t port) {
+  switch (port) {
+    case GPIOA:
+      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
+      break;
+    case GPIOB:
+      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
+      break;
+    case GPIOC:
+      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
+      break;
+    case GPIOD:
+      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPDEN);
+      break;
+    default:
+      break;
+  };
+}
+
+void gpio_setup_output(uint32_t port, uint16_t pin) {
+  gpio_enable_clock(port);
+  gpio_set_mode(port, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, pin);
+}
+
+void gpio_setup_input(uint32_t port, uint16_t pin) {
+  gpio_enable_clock(port);
+  gpio_set_mode(port, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, pin);
+}
+
+void gpio_setup_pin_af(uint32_t port, uint16_t pin, uint8_t af, bool_t is_output) {
+  gpio_enable_clock(port);
+  /* remap alternate function if needed */
+  if (af) {
+    rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
+    AFIO_MAPR |= af;
+  }
+  if (is_output)
+    gpio_set_mode(port, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, pin);
+  else
+    gpio_set_mode(port, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, pin);
+}
+
+#elif defined STM32F4
+void gpio_enable_clock(uint32_t port) {
+  switch (port) {
+    case GPIOA:
+      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN);
+      break;
+    case GPIOB:
+      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPBEN);
+      break;
+    case GPIOC:
+      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPCEN);
+      break;
+    case GPIOD:
+      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN);
+      break;
+    default:
+      break;
+  };
+}
+
+void gpio_setup_output(uint32_t port, uint16_t pin) {
+  gpio_enable_clock(port);
+  gpio_mode_setup(port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, pin);
+}
+
+void gpio_setup_input(uint32_t port, uint16_t pin) {
+  gpio_enable_clock(port);
+  gpio_mode_setup(port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, pin);
+}
+
+void gpio_setup_pin_af(uint32_t port, uint16_t pin, uint8_t af, bool_t is_output __attribute__ ((unused))) {
+  gpio_enable_clock(port);
+  gpio_mode_setup(port, GPIO_MODE_AF, GPIO_PUPD_NONE, pin);
+  gpio_set_af(port, af, pin);
+}
+#endif
+

sw/airborne/arch/stm32/mcu_periph/gpio_arch.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
  *
  * This file is part of paparazzi.
  *
@@ -17,29 +17,39 @@
  * along with paparazzi; see the file COPYING.  If not, write to
  * the Free Software Foundation, 59 Temple Place - Suite 330,
  * Boston, MA 02111-1307, USA.
- *
  */
 
 /**
  * @file arch/stm32/mcu_periph/gpio_arch.h
  * @ingroup stm32_arch
  *
- * Handling of GPIOs for STM32.
+ * GPIO helper functions for STM32F1 and STM32F4.
  */
 
-#ifndef MY_GPIO_ARCH_H
-#define MY_GPIO_ARCH_H
+#ifndef GPIO_ARCH_H
+#define GPIO_ARCH_H
 
-#include <libopencm3/stm32/f1/gpio.h>
-#include <libopencm3/stm32/f1/rcc.h>
+#include <libopencm3/stm32/gpio.h>
 
-#define GPIO_ARCH_SET_SPI_CS_HIGH()					\
-{									\
-  rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);        \
-  gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,                         \
-	        GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);                      \
-  gpio_set(GPIOB, GPIO12);                                              \
+/**
+ * Set a gpio output to high level.
+ */
+static inline void gpio_output_high(uint32_t port, uint16_t pin) {
+  gpio_set(port, pin);
 }
 
+/**
+ * Clear a gpio output to low level.
+ */
+static inline void gpio_output_low(uint32_t port, uint16_t pin) {
+  gpio_clear(port, pin);
+}
 
-#endif /* MY_GPIO_ARCH_H */
+/**
+ * Setup a gpio for input or output with alternate function.
+ */
+extern void gpio_setup_pin_af(uint32_t port, uint16_t pin, uint8_t af, bool_t is_output);
+
+extern void gpio_enable_clock(uint32_t port);
+
+#endif /* GPIO_ARCH_H */

sw/airborne/arch/stm32/mcu_periph/spi_arch.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2012 The Paparazzi Team
+ * Copyright (C) 2005-2013 The Paparazzi Team
  *
  * This file is part of paparazzi.
  *
@@ -56,9 +56,10 @@
 #include <libopencm3/stm32/rcc.h>
 #include <libopencm3/stm32/exti.h>
 #include <libopencm3/stm32/spi.h>
-#include <libopencm3/stm32/f1/dma.h>
+#include <libopencm3/stm32/dma.h>
 
 #include "mcu_periph/spi.h"
+#include "mcu_periph/gpio.h"
 
 #include BOARD_CONFIG
 
@@ -210,57 +211,33 @@ void spi_slave_unselect(uint8_t slave) {
 void spi_init_slaves(void) {
 
 #if USE_SPI_SLAVE0
-  rcc_peripheral_enable_clock(&RCC_APB2ENR,
-                              SPI_SELECT_SLAVE0_PERIPH | RCC_APB2ENR_AFIOEN);
+  gpio_setup_output(SPI_SELECT_SLAVE0_PORT, SPI_SELECT_SLAVE0_PIN);
   SpiSlaveUnselect(0);
-  gpio_set(SPI_SELECT_SLAVE0_PORT, SPI_SELECT_SLAVE0_PIN);
-  gpio_set_mode(SPI_SELECT_SLAVE0_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-                GPIO_CNF_OUTPUT_PUSHPULL, SPI_SELECT_SLAVE0_PIN);
 #endif
 
 #if USE_SPI_SLAVE1
-  rcc_peripheral_enable_clock(&RCC_APB2ENR,
-                              SPI_SELECT_SLAVE1_PERIPH | RCC_APB2ENR_AFIOEN);
+  gpio_setup_output(SPI_SELECT_SLAVE1_PORT, SPI_SELECT_SLAVE1_PIN);
   SpiSlaveUnselect(1);
-  gpio_set(SPI_SELECT_SLAVE1_PORT, SPI_SELECT_SLAVE1_PIN);
-  gpio_set_mode(SPI_SELECT_SLAVE1_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-                GPIO_CNF_OUTPUT_PUSHPULL, SPI_SELECT_SLAVE1_PIN);
 #endif
 
 #if USE_SPI_SLAVE2
-  rcc_peripheral_enable_clock(&RCC_APB2ENR,
-                              SPI_SELECT_SLAVE2_PERIPH | RCC_APB2ENR_AFIOEN);
+  gpio_setup_output(SPI_SELECT_SLAVE2_PORT, SPI_SELECT_SLAVE2_PIN);
   SpiSlaveUnselect(2);
-  gpio_set(SPI_SELECT_SLAVE2_PORT, SPI_SELECT_SLAVE2_PIN);
-  gpio_set_mode(SPI_SELECT_SLAVE2_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-                GPIO_CNF_OUTPUT_PUSHPULL, SPI_SELECT_SLAVE2_PIN);
 #endif
 
 #if USE_SPI_SLAVE3
-  rcc_peripheral_enable_clock(&RCC_APB2ENR,
-                              SPI_SELECT_SLAVE3_PERIPH | RCC_APB2ENR_AFIOEN);
+  gpio_setup_output(SPI_SELECT_SLAVE3_PORT, SPI_SELECT_SLAVE3_PIN);
   SpiSlaveUnselect(3);
-  gpio_set(SPI_SELECT_SLAVE3_PORT, SPI_SELECT_SLAVE3_PIN);
-  gpio_set_mode(SPI_SELECT_SLAVE3_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-                GPIO_CNF_OUTPUT_PUSHPULL, SPI_SELECT_SLAVE3_PIN);
 #endif
 
 #if USE_SPI_SLAVE4
-  rcc_peripheral_enable_clock(&RCC_APB2ENR,
-                              SPI_SELECT_SLAVE4_PERIPH | RCC_APB2ENR_AFIOEN);
+  gpio_setup_output(SPI_SELECT_SLAVE4_PORT, SPI_SELECT_SLAVE4_PIN);
   SpiSlaveUnselect(4);
-  gpio_set(SPI_SELECT_SLAVE4_PORT, SPI_SELECT_SLAVE4_PIN);
-  gpio_set_mode(SPI_SELECT_SLAVE4_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-                GPIO_CNF_OUTPUT_PUSHPULL, SPI_SELECT_SLAVE4_PIN);
 #endif
 
 #if USE_SPI_SLAVE5
-  rcc_peripheral_enable_clock(&RCC_APB2ENR,
-                              SPI_SELECT_SLAVE5_PERIPH | RCC_APB2ENR_AFIOEN);
+  gpio_setup_output(SPI_SELECT_SLAVE5_PORT, SPI_SELECT_SLAVE5_PIN);
   SpiSlaveUnselect(5);
-  gpio_set(SPI_SELECT_SLAVE5_PORT, SPI_SELECT_SLAVE5_PIN);
-  gpio_set_mode(SPI_SELECT_SLAVE5_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-                GPIO_CNF_OUTPUT_PUSHPULL, SPI_SELECT_SLAVE5_PIN);
 #endif
 }
 

sw/airborne/arch/stm32/mcu_periph/uart_arch.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2009 Antoine Drouin <poinix@gmail.com>
+ * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
  *
  * This file is part of paparazzi.
  *
@@ -27,6 +28,7 @@
  */
 
 #include "mcu_periph/uart.h"
+#include "mcu_periph/gpio.h"
 
 #include <libopencm3/stm32/gpio.h>
 #include <libopencm3/stm32/rcc.h>
@@ -156,57 +158,6 @@ static inline void usart_enable_irq(u8 IRQn) {
   nvic_enable_irq(IRQn);
 }
 
-/** Set RCC and GPIO mode
- */
-#ifdef STM32F1
-static inline void set_uart_pin(u32 gpioport, u16 gpio, u8 alt_func_remap, bool_t is_output) {
-  switch (gpioport) {
-    case GPIOA:
-      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
-      break;
-    case GPIOB:
-      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
-      break;
-    case GPIOC:
-      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
-      break;
-    case GPIOD:
-      rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPDEN);
-      break;
-    default:
-      break;
-  };
-  if (alt_func_remap) {
-    rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
-    AFIO_MAPR |= alt_func_remap;
-  }
-  if (is_output)
-    gpio_set_mode(gpioport, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, gpio);
-  else
-    gpio_set_mode(gpioport, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, gpio);
-}
-#elif defined STM32F4
-static inline void set_uart_pin(u32 gpioport, u16 gpio, u8 alt_func_num, bool_t foo __attribute__ ((unused))) {
-  switch (gpioport) {
-    case GPIOA:
-      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN);
-      break;
-    case GPIOB:
-      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPBEN);
-      break;
-    case GPIOC:
-      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPCEN);
-      break;
-    case GPIOD:
-      rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN);
-      break;
-    default:
-      break;
-  };
-  gpio_mode_setup(gpioport, GPIO_MODE_AF, GPIO_PUPD_NONE, gpio);
-  gpio_set_af(gpioport, alt_func_num, gpio);
-}
-#endif /* STM32F4 */
 
 #ifdef USE_UART1
 
@@ -231,10 +182,10 @@ void uart1_init( void ) {
   rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN);
 
 #if USE_UART1_TX
-  set_uart_pin(UART1_GPIO_PORT_TX, UART1_GPIO_TX, UART1_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART1_GPIO_PORT_TX, UART1_GPIO_TX, UART1_GPIO_AF, TRUE);
 #endif
 #if USE_UART1_RX
-  set_uart_pin(UART1_GPIO_PORT_RX, UART1_GPIO_RX, UART1_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART1_GPIO_PORT_RX, UART1_GPIO_RX, UART1_GPIO_AF, FALSE);
 #endif
 
   /* Enable USART interrupts in the interrupt controller */
@@ -243,8 +194,8 @@ void uart1_init( void ) {
 #if UART1_HW_FLOW_CONTROL
 #warning "USING UART1 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
   /* setup CTS and RTS gpios */
-  set_uart_pin(UART1_GPIO_PORT_CTS, UART1_GPIO_CTS, UART1_GPIO_AF, FALSE);
-  set_uart_pin(UART1_GPIO_PORT_RTS, UART1_GPIO_RTS, UART1_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART1_GPIO_PORT_CTS, UART1_GPIO_CTS, UART1_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART1_GPIO_PORT_RTS, UART1_GPIO_RTS, UART1_GPIO_AF, TRUE);
 #endif
 
   /* Configure USART1, enable hardware flow control*/
@@ -282,10 +233,10 @@ void uart2_init( void ) {
   rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
 
 #if USE_UART2_TX
-  set_uart_pin(UART2_GPIO_PORT_TX, UART2_GPIO_TX, UART2_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART2_GPIO_PORT_TX, UART2_GPIO_TX, UART2_GPIO_AF, TRUE);
 #endif
 #if USE_UART2_RX
-  set_uart_pin(UART2_GPIO_PORT_RX, UART2_GPIO_RX, UART2_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART2_GPIO_PORT_RX, UART2_GPIO_RX, UART2_GPIO_AF, FALSE);
 #endif
 
   /* Enable USART interrupts in the interrupt controller */
@@ -294,8 +245,8 @@ void uart2_init( void ) {
 #if UART2_HW_FLOW_CONTROL && defined(STM32F4)
 #warning "USING UART2 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
   /* setup CTS and RTS pins */
-  set_uart_pin(UART2_GPIO_PORT_CTS, UART2_GPIO_CTS, UART2_GPIO_AF, FALSE);
-  set_uart_pin(UART2_GPIO_PORT_RTS, UART2_GPIO_RTS, UART2_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART2_GPIO_PORT_CTS, UART2_GPIO_CTS, UART2_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART2_GPIO_PORT_RTS, UART2_GPIO_RTS, UART2_GPIO_AF, TRUE);
 #endif
 
   /* Configure USART Tx,Rx, and hardware flow control*/
@@ -333,10 +284,10 @@ void uart3_init( void ) {
   rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART3EN);
 
 #if USE_UART3_TX
-  set_uart_pin(UART3_GPIO_PORT_TX, UART3_GPIO_TX, UART3_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART3_GPIO_PORT_TX, UART3_GPIO_TX, UART3_GPIO_AF, TRUE);
 #endif
 #if USE_UART3_RX
-  set_uart_pin(UART3_GPIO_PORT_RX, UART3_GPIO_RX, UART3_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART3_GPIO_PORT_RX, UART3_GPIO_RX, UART3_GPIO_AF, FALSE);
 #endif
 
   /* Enable USART interrupts in the interrupt controller */
@@ -345,8 +296,8 @@ void uart3_init( void ) {
 #if UART3_HW_FLOW_CONTROL && defined(STM32F4)
 #warning "USING UART3 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
   /* setup CTS and RTS pins */
-  set_uart_pin(UART3_GPIO_PORT_CTS, UART3_GPIO_CTS, UART3_GPIO_AF, FALSE);
-  set_uart_pin(UART3_GPIO_PORT_RTS, UART3_GPIO_RTS, UART3_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART3_GPIO_PORT_CTS, UART3_GPIO_CTS, UART3_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART3_GPIO_PORT_RTS, UART3_GPIO_RTS, UART3_GPIO_AF, TRUE);
 #endif
 
   /* Configure USART Tx,Rx, and hardware flow control*/
@@ -380,10 +331,10 @@ void uart4_init( void ) {
   rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_UART4EN);
 
 #if USE_UART4_TX
-  set_uart_pin(UART4_GPIO_PORT_TX, UART4_GPIO_TX, UART4_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART4_GPIO_PORT_TX, UART4_GPIO_TX, UART4_GPIO_AF, TRUE);
 #endif
 #if USE_UART4_RX
-  set_uart_pin(UART4_GPIO_PORT_RX, UART4_GPIO_RX, UART4_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART4_GPIO_PORT_RX, UART4_GPIO_RX, UART4_GPIO_AF, FALSE);
 #endif
 
   /* Enable USART interrupts in the interrupt controller */
@@ -418,10 +369,10 @@ void uart5_init( void ) {
   rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_UART5EN);
 
 #if USE_UART5_TX
-  set_uart_pin(UART5_GPIO_PORT_TX, UART5_GPIO_TX, UART5_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART5_GPIO_PORT_TX, UART5_GPIO_TX, UART5_GPIO_AF, TRUE);
 #endif
 #if USE_UART5_RX
-  set_uart_pin(UART5_GPIO_PORT_RX, UART5_GPIO_RX, UART5_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART5_GPIO_PORT_RX, UART5_GPIO_RX, UART5_GPIO_AF, FALSE);
 #endif
 
   /* Enable USART interrupts in the interrupt controller */
@@ -461,10 +412,10 @@ void uart6_init( void ) {
 
   /* init RCC and GPIOs */
 #if USE_UART6_TX
-  set_uart_pin(UART6_GPIO_PORT_TX, UART6_GPIO_TX, UART6_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART6_GPIO_PORT_TX, UART6_GPIO_TX, UART6_GPIO_AF, TRUE);
 #endif
 #if USE_UART6_RX
-  set_uart_pin(UART6_GPIO_PORT_RX, UART6_GPIO_RX, UART6_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART6_GPIO_PORT_RX, UART6_GPIO_RX, UART6_GPIO_AF, FALSE);
 #endif
 
   /* Enable USART interrupts in the interrupt controller */
@@ -473,8 +424,8 @@ void uart6_init( void ) {
 #if UART6_HW_FLOW_CONTROL
 #warning "USING UART6 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
   /* setup CTS and RTS pins */
-  set_uart_pin(UART6_GPIO_PORT_CTS, UART6_GPIO_CTS, UART6_GPIO_AF, FALSE);
-  set_uart_pin(UART6_GPIO_PORT_RTS, UART6_GPIO_RTS, UART6_GPIO_AF, TRUE);
+  gpio_setup_pin_af(UART6_GPIO_PORT_CTS, UART6_GPIO_CTS, UART6_GPIO_AF, FALSE);
+  gpio_setup_pin_af(UART6_GPIO_PORT_RTS, UART6_GPIO_RTS, UART6_GPIO_AF, TRUE);
 #endif
 
   /* Configure USART Tx,Rx and hardware flow control*/

sw/airborne/boards/apogee_0.99.h

@@ -150,27 +150,21 @@
 
 
 /* SPI slave pin declaration */
-//#define SPI_SELECT_SLAVE0_PERIPH RCC_APB2ENR_IOPAEN
 //#define SPI_SELECT_SLAVE0_PORT GPIOA
 //#define SPI_SELECT_SLAVE0_PIN GPIO15
 //
-//#define SPI_SELECT_SLAVE1_PERIPH RCC_APB2ENR_IOPAEN
 //#define SPI_SELECT_SLAVE1_PORT GPIOA
 //#define SPI_SELECT_SLAVE1_PIN GPIO4
 
-#define SPI_SELECT_SLAVE2_PERIPH RCC_AHB1ENR_IOPBEN
 #define SPI_SELECT_SLAVE2_PORT GPIOB
 #define SPI_SELECT_SLAVE2_PIN GPIO12
 
-//#define SPI_SELECT_SLAVE3_PERIPH RCC_APB2ENR_IOPCEN
 //#define SPI_SELECT_SLAVE3_PORT GPIOC
 //#define SPI_SELECT_SLAVE3_PIN GPIO13
 //
-//#define SPI_SELECT_SLAVE4_PERIPH RCC_APB2ENR_IOPCEN
 //#define SPI_SELECT_SLAVE4_PORT GPIOC
 //#define SPI_SELECT_SLAVE4_PIN GPIO12
 //
-//#define SPI_SELECT_SLAVE5_PERIPH RCC_APB2ENR_IOPCEN
 //#define SPI_SELECT_SLAVE5_PORT GPIOC
 //#define SPI_SELECT_SLAVE5_PIN GPIO4
 

sw/airborne/boards/ardrone/actuators_ardrone2_raw.c

@@ -30,7 +30,7 @@
 
 #include "subsystems/actuators.h"
 #include "actuators_ardrone2_raw.h"
-#include "gpio.h"
+#include "gpio_ardrone.h"
 
 #include <stdio.h>   /* Standard input/output definitions */
 #include <string.h>  /* String function definitions */

sw/airborne/boards/ardrone/gpio_ardrone.c

@@ -18,13 +18,13 @@
  */
 
 /**
- * @file boards/ardrone/gpio.c
+ * @file boards/ardrone/gpio_ardrone.c
  * ardrone GPIO driver
  */
 
 #include <stdio.h>
 #include <stdlib.h>
-#include "gpio.h"
+#include "gpio_ardrone.h"
 
 //val=0 -> set gpio output lo
 //val=1 -> set gpio output hi

sw/airborne/boards/ardrone/gpio_ardrone.h

@@ -18,16 +18,16 @@
  */
 
 /**
- * @file boards/ardrone/gpio.h
+ * @file boards/ardrone/gpio_ardrone.h
  * ardrone GPIO driver
  */
 
-#ifndef GPIO_H
-#define GPIO_H
+#ifndef GPIO_ARDRONE_H
+#define GPIO_ARDRONE_H
 
 //val=0 -> set gpio output lo
 //val=1 -> set gpio output hi
 //val=-1 -> set gpio as input (output hi-Z)
 int gpio_set(int nr,int val);
 
-#endif /* GPIO_H */
+#endif /* GPIO_ARDRONE_H */

sw/airborne/boards/lisa_m_common.h

@@ -3,27 +3,21 @@
 
 /* SPI slave mapping */
 
-#define SPI_SELECT_SLAVE0_PERIPH RCC_APB2ENR_IOPAEN
 #define SPI_SELECT_SLAVE0_PORT GPIOA
 #define SPI_SELECT_SLAVE0_PIN GPIO15
 
-#define SPI_SELECT_SLAVE1_PERIPH RCC_APB2ENR_IOPAEN
 #define SPI_SELECT_SLAVE1_PORT GPIOA
 #define SPI_SELECT_SLAVE1_PIN GPIO4
 
-#define SPI_SELECT_SLAVE2_PERIPH RCC_APB2ENR_IOPBEN
 #define SPI_SELECT_SLAVE2_PORT GPIOB
 #define SPI_SELECT_SLAVE2_PIN GPIO12
 
-#define SPI_SELECT_SLAVE3_PERIPH RCC_APB2ENR_IOPCEN
 #define SPI_SELECT_SLAVE3_PORT GPIOC
 #define SPI_SELECT_SLAVE3_PIN GPIO13
 
-#define SPI_SELECT_SLAVE4_PERIPH RCC_APB2ENR_IOPCEN
 #define SPI_SELECT_SLAVE4_PORT GPIOC
 #define SPI_SELECT_SLAVE4_PIN GPIO12
 
-#define SPI_SELECT_SLAVE5_PERIPH RCC_APB2ENR_IOPCEN
 #define SPI_SELECT_SLAVE5_PORT GPIOC
 #define SPI_SELECT_SLAVE5_PIN GPIO4
 

sw/airborne/firmwares/fixedwing/main_ap.c

@@ -82,7 +82,6 @@
 #include "rc_settings.h"
 #endif
 
-#include "gpio.h"
 #include "led.h"
 
 /* if PRINT_CONFIG is defined, print some config options */
@@ -161,10 +160,6 @@ void init_ap( void ) {
   gps_init();
 #endif
 
-#ifdef USE_GPIO
-  GpioInit();
-#endif
-
 #if USE_IMU
   imu_init();
 #endif
@@ -604,9 +599,6 @@ void monitor_task( void ) {
     DOWNLINK_SEND_TAKEOFF(DefaultChannel, DefaultDevice, &time_sec);
   }
 
-#ifdef USE_GPIO
-   GpioUpdate1();
-#endif
 }
 
 

sw/airborne/mcu_periph/gpio.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
+ *
+ * This file is part of paparazzi.
+ *
+ * paparazzi is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * paparazzi is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with paparazzi; see the file COPYING.  If not, write to
+ * the Free Software Foundation, 59 Temple Place - Suite 330,
+ * Boston, MA 02111-1307, USA.
+ */
+
+/**
+ * @file mcu_periph/gpio.h
+ *
+ * Some architecture independent helper functions for GPIOs.
+ */
+
+#include "std.h"
+#include "mcu_periph/gpio_arch.h"
+
+/**
+ * Setup gpio pin as generic output.
+ */
+extern void gpio_setup_output(uint32_t port, uint16_t pin);
+
+/**
+ * Setup a gpio pin as generic input.
+ */
+extern void gpio_setup_input(uint32_t port, uint16_t pin);
+

sw/airborne/subsystems/imu/imu_aspirin_i2c.c

@@ -30,7 +30,7 @@
 #include "mcu_periph/i2c.h"
 
 // Set SPI_CS High to enable I2C mode of ADXL345
-#include "mcu_periph/gpio_arch.h"
+#include "mcu_periph/gpio.h"
 
 
 /* i2c default suitable for Lisa */
@@ -94,7 +94,10 @@ void imu_impl_init(void)
   //imu_aspirin.acc_adxl.config.drdy_int_enable = TRUE;
 
   // With CS tied high to VDD I/O, the ADXL345 is in I2C mode
-  GPIO_ARCH_SET_SPI_CS_HIGH();
+#ifdef ASPIRIN_I2C_CS_PORT
+  gpio_setup_output(ASPIRIN_I2C_CS_PORT, ASPIRIN_I2C_CS_PIN);
+  gpio_output_high(ASPIRIN_I2C_CS_PORT, ASPIRIN_I2C_CS_PIN);
+#endif
 
   /* Gyro configuration and initalization */
   itg3200_init(&imu_aspirin.gyro_itg, &(ASPIRIN_I2C_DEV), ITG3200_ADDR);