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Cleaning up the stm32 spi periph driver.

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This commit is contained in:
Piotr Esden-Tempski
2012-03-14 21:21:05 -07:00
parent cc4a1548fb
commit b92337f266
1 changed files with 0 additions and 53 deletions
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sw/airborne/arch/stm32/mcu_periph/spi_arch.c
-53
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@@ -79,13 +79,6 @@ void spi_init(void) {
spi_arch_int_enable();
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO6);
gpio_set(GPIOC, GPIO6);
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO7);
gpio_set(GPIOC, GPIO7);
}
/*
@@ -109,8 +102,6 @@ struct spi_transaction* slave0;
void spi_rw(struct spi_transaction * _trans)
{
gpio_toggle(GPIOC, GPIO6);
// Store local copy to notify of the results
slave0 = _trans;
slave0->status = SPITransRunning;
@@ -132,24 +123,6 @@ void spi_rw(struct spi_transaction * _trans)
//dma_set_mode(DMA1, DMA_CHANNEL4, DMA_???_NORMAL);
dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH);
/*
DMA_DeInit(DMA1_Channel4);
DMA_InitTypeDef DMA_initStructure_4 = {
.DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
.DMA_MemoryBaseAddr = (uint32_t) slave0->miso_buf,
.DMA_DIR = DMA_DIR_PeripheralSRC,
.DMA_BufferSize = slave0->length,
.DMA_PeripheralInc = DMA_PeripheralInc_Disable,
.DMA_MemoryInc = DMA_MemoryInc_Enable,
.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
.DMA_Mode = DMA_Mode_Normal,
.DMA_Priority = DMA_Priority_VeryHigh,
.DMA_M2M = DMA_M2M_Disable
};
DMA_Init(DMA1_Channel4, &DMA_initStructure_4);
*/
// SPI2_Tx_DMA_Channel configuration ------------------------------------
dma_channel_reset(DMA1, DMA_CHANNEL5);
dma_set_peripheral_address(DMA1, DMA_CHANNEL5, (u32)&SPI2_DR);
@@ -163,49 +136,24 @@ void spi_rw(struct spi_transaction * _trans)
//dma_set_mode(DMA1, DMA_CHANNEL5, DMA_???_NORMAL);
dma_set_priority(DMA1, DMA_CHANNEL5, DMA_CCR_PL_MEDIUM);
/*
DMA_DeInit(DMA1_Channel5);
DMA_InitTypeDef DMA_initStructure_5 = {
.DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
.DMA_MemoryBaseAddr = (uint32_t) slave0->mosi_buf,
.DMA_DIR = DMA_DIR_PeripheralDST,
.DMA_BufferSize = slave0->length,
.DMA_PeripheralInc = DMA_PeripheralInc_Disable,
.DMA_MemoryInc = DMA_MemoryInc_Enable,
.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
.DMA_Mode = DMA_Mode_Normal,
.DMA_Priority = DMA_Priority_Medium,
.DMA_M2M = DMA_M2M_Disable
};
DMA_Init(DMA1_Channel5, &DMA_initStructure_5);
*/
// Enable DMA1 Channel4
dma_enable_channel(DMA1, DMA_CHANNEL4);
//DMA_Cmd(DMA1_Channel4, ENABLE);
// Enable SPI_2 Rx request
spi_enable_rx_dma(SPI2);
//SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
// Enable DMA1 Channel5
dma_enable_channel(DMA1, DMA_CHANNEL5);
//DMA_Cmd(DMA1_Channel5, ENABLE);
// Enable SPI_2 Tx request
spi_enable_tx_dma(SPI2);
//SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
// Enable DMA1 Channel4 Transfer Complete interrupt
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4);
//DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
//gpio_set(GPIOC, GPIO6);
}
// Accel end of DMA transferred
void dma1_channel4_isr(void)
{
gpio_toggle(GPIOC, GPIO7);
Spi2Slave0Unselect();
@@ -231,7 +179,6 @@ void dma1_channel4_isr(void)
slave0->status = SPITransSuccess;
*(slave0->ready) = 1;
//gpio_set(GPIOC, GPIO7);
}