SPI transaction struct

conf/airframes/CDW/LisaAspirin2.xml

@@ -222,7 +222,7 @@
 
   <firmware name="fixedwing">
 
-    <target name="ap" board="lisa_m_1.0">
+    <target name="ap" board="lisa_l_1.0">
       <define name="STRONG_WIND"/>
       <define name="WIND_INFO"/>
       <define name="WIND_INFO_RET"/>

sw/airborne/arch/stm32/mcu_periph/spi_arch.c

@@ -101,19 +101,23 @@ void spi_clear_rx_buf(void) {
 }
 */
 
+struct spi_transaction* slave0;
 
-
-void spi_rw(volatile uint8_t* _send, volatile uint8_t* _read, volatile int _len) 
+void spi_rw(struct spi_transaction  * _trans) 
 {
-   Spi2Slave0Select();
+  // Store local copy to notify of the results
+  slave0 = _trans;
+  slave0->status = SPITransRunning;
+
+  Spi2Slave0Select();
 
   // SPI2_Rx_DMA_Channel configuration ------------------------------------
   DMA_DeInit(DMA1_Channel4);
   DMA_InitTypeDef DMA_initStructure_4 = {
     .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
-    .DMA_MemoryBaseAddr = (uint32_t)_read,
+    .DMA_MemoryBaseAddr = (uint32_t) slave0->miso_buf,
     .DMA_DIR = DMA_DIR_PeripheralSRC,
-    .DMA_BufferSize = _len,
+    .DMA_BufferSize = slave0->length,
     .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
     .DMA_MemoryInc = DMA_MemoryInc_Enable,
     .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
@@ -128,9 +132,9 @@ void spi_rw(volatile uint8_t* _send, volatile uint8_t* _read, volatile int _len)
   DMA_DeInit(DMA1_Channel5);
   DMA_InitTypeDef DMA_initStructure_5 = {
     .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
-    .DMA_MemoryBaseAddr = (uint32_t)_send,
+    .DMA_MemoryBaseAddr = (uint32_t) slave0->mosi_buf,
     .DMA_DIR = DMA_DIR_PeripheralDST,
-    .DMA_BufferSize = _len,
+    .DMA_BufferSize = slave0->length,
     .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
     .DMA_MemoryInc = DMA_MemoryInc_Enable,
     .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
@@ -179,6 +183,7 @@ void dma1_c4_irq_handler(void)
   DMA_Cmd(DMA1_Channel4, DISABLE);
   DMA_Cmd(DMA1_Channel5, DISABLE);
 
+  slave0->status = SPITransSuccess;
 }
 
 

sw/airborne/arch/stm32/mcu_periph/spi_arch.h

@@ -35,7 +35,7 @@ extern void spi_arch_int_enable(void);
 extern void spi_arch_int_disable(void);
 
 extern void spi_clear_rx_buf(void);
-void spi_rw(volatile uint8_t* _send, volatile uint8_t* _read, volatile int _len);
+void spi_rw(struct spi_transaction  * _trans);
 
 
 /*

sw/airborne/mcu_periph/spi.h

@@ -32,8 +32,24 @@
 #ifdef USE_SPI
 
 #include "std.h"
+
+enum SPITransactionStatus {
+  SPITransPending,
+  SPITransRunning,
+  SPITransSuccess,
+  SPITransFailed
+};
+
+struct spi_transaction {
+  volatile uint8_t* mosi_buf;
+  volatile uint8_t* miso_buf;
+  uint8_t length;
+  volatile enum SPITransactionStatus status;
+};
+
 #include "mcu_periph/spi_arch.h"
 
+
 extern uint8_t* spi_buffer_input;
 extern uint8_t* spi_buffer_output;
 extern uint8_t spi_buffer_length;

sw/airborne/subsystems/imu/imu_aspirin2.c

@@ -10,6 +10,8 @@
 
 struct ImuAspirin2 imu_aspirin2;
 
+struct spi_transaction aspirin2_mpu60x0;
+
 /*
 
 // initialize peripherals
@@ -24,25 +26,23 @@ void imu_impl_init(void) {
   imu_aspirin2.status = Aspirin2StatusUninit;
   imu_aspirin2.imu_available = FALSE;
 
+  aspirin2_mpu60x0.mosi_buf = imu_aspirin2.imu_tx_buf;
+  aspirin2_mpu60x0.miso_buf = imu_aspirin2.imu_rx_buf;
+  aspirin2_mpu60x0.length = 2;
+
 //  imu_aspirin2_arch_init();
 //  spi_arch_int_enable();
 
-//  LED_TOGGLE(2);
-  LED_TOGGLE(3);
 }
 
 
 void imu_periodic(void) 
 {
 
-//  LED_TOGGLE(2);
-//  LED_TOGGLE(3);
-
-  imu_aspirin2.imu_len = 2;
   imu_aspirin2.imu_tx_buf[0] = MPU60X0_REG_WHO_AM_I + 0x80;
   imu_aspirin2.imu_tx_buf[1] = 0x00;
 
-  spi_rw(imu_aspirin2.imu_tx_buf, imu_aspirin2.imu_rx_buf, imu_aspirin2.imu_len);
+  spi_rw(&aspirin2_mpu60x0);
 
 /*
   hmc5843_periodic();

sw/airborne/subsystems/imu/imu_aspirin2.h

@@ -66,11 +66,12 @@ struct ImuAspirin2 {
   volatile uint8_t imu_available;
   volatile uint8_t imu_tx_buf[64];
   volatile uint8_t imu_rx_buf[64];
-  volatile uint8_t imu_len;
   uint32_t time_since_last_reading;
 };
 
 extern struct ImuAspirin2 imu_aspirin2;
+
+
 #define ASPIRIN2_TIMEOUT 3
 /*