zhangyu117 4e40393cc4 arch/tricore: record trapinfo for coredump ...

use global var record trap type and reason info for coredump

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>

2026-01-15 16:09:13 -03:00

..

arm

arch/arm/src/samv7/Kconfig: fix incorrect SAMV7_EMAC0_RMII dependency

2026-01-15 16:39:14 +01:00

arm64

barrier: add UP_RMB UP_WMB

2025-12-22 10:22:06 -03:00

avr

nuttx/arch: merge tickless and tick process

2026-01-12 16:20:42 +08:00

ceva

barrier: add UP_RMB UP_WMB

2025-12-22 10:22:06 -03:00

dummy

…

hc

…

mips

sched:use tcb_s inside of task_tcb_s , remove all cast

2025-12-22 17:55:45 +08:00

misoc

…

or1k

…

renesas

…

risc-v

nuttx/arch: merge tickless and tick process

2026-01-12 16:20:42 +08:00

sim

libcxx: porting libcxx test.

2026-01-15 13:40:42 -03:00

sparc

nuttx/arch: merge tickless and tick process

2026-01-12 16:20:42 +08:00

tricore

arch/tricore: record trapinfo for coredump

2026-01-15 16:09:13 -03:00

x86

…

x86_64

barrier: add UP_RMB UP_WMB

2025-12-22 10:22:06 -03:00

xtensa

nuttx/arch: merge tickless and tick process

2026-01-12 16:20:42 +08:00

z16

…

z80

…

CMakeLists.txt

…

Kconfig

arch/tricore: upcsa/lowcsa process && dumpinfo

2026-01-15 16:09:13 -03:00