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barrier: add UP_RMB UP_WMB

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This commit added linux-style UP_RMB() and UP_WMB().

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
2025-09-18 08:48:05 +08:00
committed by Alan C. Assis
parent 7d01d8aab5
commit c55954d56c
14 changed files with 93 additions and 47 deletions
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arch/arm/include/arm/barriers.h
+6 -6
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@@ -31,12 +31,12 @@
/* ARM memory barriers */
#define arm_dsb() __asm__ __volatile__ ("dsb " : : : "memory")
#define arm_isb() __asm__ __volatile__ ("isb " : : : "memory")
#define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory")
#define arm_mb() __asm__ __volatile__ ("" : : : "memory")
#define UP_DSB() arm_dsb()
#define UP_ISB() arm_isb()
#define UP_DMB() arm_dmb()
#define UP_DSB() arm_mb()
#define UP_ISB() arm_mb()
#define UP_DMB() arm_mb()
#define UP_RMB() arm_mb()
#define UP_WMB() arm_mb()
#endif /* __ARCH_ARM_INCLUDE_ARM_BARRIERS_H */
arch/arm/include/armv6-m/barriers.h
+5 -1
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@@ -35,10 +35,14 @@
#define arm_dsb() __asm__ __volatile__ ("dsb " : : : "memory")
#define arm_isb() __asm__ __volatile__ ("isb " : : : "memory")
#define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory")
#define arm_dmb() __asm__ __volatile__ ("dmb" : : : "memory")
#define arm_rmb() __asm__ __volatile__ ("dmb ish" : : : "memory")
#define arm_wmb() __asm__ __volatile__ ("dmb ish" : : : "memory")
#define UP_DSB() arm_dsb()
#define UP_ISB() arm_isb()
#define UP_DMB() arm_dmb()
#define UP_RMB() arm_rmb()
#define UP_WMB() arm_wmb()
#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H */
arch/arm/include/armv7-a/barriers.h
+4
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@@ -40,7 +40,11 @@
#define arm_sev() __asm__ __volatile__ ("sev\n")
#define UP_DSB() arm_dsb(15)
#define UP_DMB() arm_dmb(15)
#define UP_RMB() arm_dmb(3)
#define UP_WMB() arm_dmb(2)
#define UP_ISB() arm_isb()
#define UP_NOP() arm_nop()
#define UP_SEV() arm_sev()
arch/arm/include/armv7-m/barriers.h
+4
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@@ -36,9 +36,13 @@
#define arm_dsb() __asm__ __volatile__ ("dsb " : : : "memory")
#define arm_isb() __asm__ __volatile__ ("isb " : : : "memory")
#define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory")
#define arm_rmb() __asm__ __volatile__ ("dmb ish" : : : "memory")
#define arm_wmb() __asm__ __volatile__ ("dmb ish" : : : "memory")
#define UP_DSB() arm_dsb()
#define UP_ISB() arm_isb()
#define UP_DMB() arm_dmb()
#define UP_RMB() arm_rmb()
#define UP_WMB() arm_wmb()
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H */
arch/arm/include/armv7-r/barriers.h
+6
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@@ -35,12 +35,18 @@
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define arm_rmb() __asm__ __volatile__ ("dmb ishld" : : : "memory")
#define arm_wmb() __asm__ __volatile__ ("dmb ishst" : : : "memory")
#define arm_isb() __asm__ __volatile__ ("isb " : : : "memory")
#define arm_nop() __asm__ __volatile__ ("nop\n")
#define arm_sev() __asm__ __volatile__ ("sev\n")
#define UP_DSB() arm_dsb(15)
#define UP_DMB() arm_dmb(15)
#define UP_RMB() arm_rmb()
#define UP_WMB() arm_wmb()
#define UP_ISB() arm_isb()
#define UP_NOP() arm_nop()
#define UP_SEV() arm_sev()
arch/arm/include/armv8-m/barriers.h
+6
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@@ -35,10 +35,16 @@
#define arm_isb() __asm__ __volatile__ ("isb " : : : "memory")
#define arm_dmb() __asm__ __volatile__ ("dmb " : : : "memory")
#define arm_rmb() __asm__ __volatile__ ("dmb ishld" : : : "memory")
#define arm_wmb() __asm__ __volatile__ ("dmb ishst" : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define UP_ISB() arm_isb()
#define UP_DMB() arm_dmb()
#define UP_RMB() arm_rmb()
#define UP_WMB() arm_wmb()
#define UP_DSB() arm_dsb(15)
#endif /* __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H */
arch/arm/include/armv8-r/barriers.h
+6
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@@ -35,12 +35,18 @@
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define arm_rmb() __asm__ __volatile__ ("dmb ishld" : : : "memory")
#define arm_wmb() __asm__ __volatile__ ("dmb ishst" : : : "memory")
#define arm_isb() __asm__ __volatile__ ("isb " : : : "memory")
#define arm_nop() __asm__ __volatile__ ("nop\n")
#define arm_sev() __asm__ __volatile__ ("sev\n")
#define UP_DSB() arm_dsb(15)
#define UP_DMB() arm_dmb(15)
#define UP_RMB() arm_rmb()
#define UP_WMB() arm_wmb()
#define UP_ISB() arm_isb()
#define UP_NOP() arm_nop()
#define UP_SEV() arm_sev()
arch/arm64/include/barriers.h
+4 -3
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@@ -37,14 +37,15 @@
* ARM DDI 0487E.a C6.2.81
*/
#define UP_DSB() __asm__ volatile ("dsb sy" : : : "memory");
#define UP_DSB() asm volatile ("dsb sy" : : : "memory");
#define UP_DMB() asm volatile ("dmb sy" : : : "memory")
#define UP_RMB() asm volatile ("dmb ishld" : : : "memory")
#define UP_WMB() asm volatile ("dmb ishst" : : : "memory")
/* See Arm® Architecture Reference Manual
* ARM DDI 0487E.a C6.2.79
*/
#define UP_DMB() __asm__ volatile ("dmb sy" : : : "memory");
/* See Arm® Architecture Reference Manual
* ARM DDI 0487E.a C6.2.96
*/
arch/ceva/include/barriers.h
+2
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@@ -37,6 +37,8 @@
#define UP_DSB() up_dsb()
#define UP_DMB() up_dmb()
#define UP_RMB() up_dmb()
#define UP_WMB() up_dmb()
#endif /* __ARCH_CEVA_INCLUDE_BARRIERS_H */
arch/risc-v/include/barriers.h
+3 -1
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@@ -29,7 +29,9 @@
/* UP_DMB() is used to flush local data caches (memory) */
#define UP_DMB() __FENCE(rw, rw)
#define UP_DMB() __FENCE(rw, rw)
#define UP_RMB() __FENCE(r, r)
#define UP_WMB() __FENCE(w, w)
/* UP_DSB() is a full memory barrier */
arch/tricore/include/barriers.h
+4 -1
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@@ -22,7 +22,10 @@
#define __ARCH_TRICORE_INCLUDE_BARRIERS_H
#define UP_DSB() __dsync()
#define UP_DMB() __asm("":::"memory")
#define UP_DMB() asm volatile ("" : : : "memory")
#define UP_RMB() asm volatile ("" : : : "memory")
#define UP_WMB() asm volatile ("" : : : "memory")
#define UP_ISB() __isync()
#endif /* __ARCH_TRICORE_INCLUDE_BARRIERS_H */
arch/x86_64/include/barriers.h
+3 -1
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@@ -26,6 +26,8 @@
****************************************************************************/
#define UP_DSB() __asm__ __volatile__ ("mfence")
#define UP_DMB() __asm__ __volatile__ ("mfence")
#define UP_DMB() __asm__ __volatile__ ("mfence" ::: "memory")
#define UP_RMB() __asm__ __volatile__ ("lfence" ::: "memory")
#define UP_WMB() __asm__ __volatile__ ("sfence" ::: "memory")
#endif /* __ARCH_X86_64_INCLUDE_BARRIERS_H */
include/nuttx/arch.h
+40
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@@ -99,6 +99,46 @@
#define DEBUGPOINT_BREAKPOINT 0x04
#define DEBUGPOINT_STEPPOINT 0x05
/* Memory barriers may be provided in arch/spinlock.h
*
* DMB - Data memory barrier. Assures writes are completed to memory.
* DSB - Data synchronization barrier.
*/
#if !defined(UP_DMB)
# define UP_DMB()
#endif
#if !defined(UP_RMB)
# define UP_RMB()
#endif
#if !defined(UP_WMB)
# define UP_WMB()
#endif
#if !defined(UP_DSB)
# define UP_DSB()
#endif
#if !defined(UP_WFE)
# define UP_WFE()
#endif
#if !defined(UP_SEV)
# define UP_SEV()
#endif
#ifdef CONFIG_SMP
# define SMP_MB() UP_DMB()
# define SMP_RMB() UP_RMB()
# define SMP_WMB() UP_WMB()
#else /* !CONFIG_SMP */
# define SMP_MB() asm volatile ("" : : : "memory")
# define SMP_RMB() asm volatile ("" : : : "memory")
# define SMP_WMB() asm volatile ("" : : : "memory")
#endif
/****************************************************************************
* Name: up_cpu_index
*
include/nuttx/spinlock.h
-34
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@@ -50,40 +50,6 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory barriers may be provided in arch/spinlock.h
*
* DMB - Data memory barrier. Assures writes are completed to memory.
* DSB - Data synchronization barrier.
*/
#undef __SP_UNLOCK_FUNCTION
#if !defined(UP_DMB)
# define UP_DMB()
#else
# define __SP_UNLOCK_FUNCTION 1
#endif
#if !defined(UP_DSB)
# define UP_DSB()
#endif
#if !defined(UP_WFE)
# define UP_WFE()
#endif
#if !defined(UP_SEV)
# define UP_SEV()
#endif
#if !defined(__SP_UNLOCK_FUNCTION) && (defined(CONFIG_TICKET_SPINLOCK) || \
defined(CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS))
# define __SP_UNLOCK_FUNCTION 1
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/