Prep for 4.14 release

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2296 42af7a65-404d-4744-a932-0658087f49c3
Fix a problem with TX status on resume from stall
2025-12-11 21:20:26 +08:00 · 2009-12-02 17:38:15 +00:00 · 2009-12-01 21:14:56 +00:00 · 2009-12-01 15:28:33 +00:00 · 2009-12-01 00:33:58 +00:00 · 2009-11-30 16:19:31 +00:00
82 changed files with 12312 additions and 808 deletions
--- a/126
+++ b/126
@@ -10,7 +10,7 @@
 	  for C5471
 	* Added fgets() and gets() logic; verified c5471 console read.
 	* Corrected error in reading from the C5471 serial port:
-          Improper use of semaphore can cause deadlock.
+	  Improper use of semaphore can cause deadlock.
 	* Fixed an error in the memory cleanup:  The idle task
 	  cannot take sempahores (because it must always be ready
 	  to run).
@@ -28,7 +28,7 @@
 	* Added strtok() and strtok_r()
 	* Added a simple shell called nsh (see examples/nsh).
 	* Platform support for 8052 is complete but not stable
-	  when the timer interrupt is enabled.  Seems to be an
+	  when the timer interrupt is enabled.	Seems to be an
 	  issue when SP enters indirect address space.
 	* Documentation updates

@@ -42,7 +42,7 @@
 	  Can't do this; the caller must be able to wait for access
 	  to memory.
 	* Fixed bugs associated with debug output:
-          Cannot do dbg() in middle of context switch logic.
+		  Cannot do dbg() in middle of context switch logic.
 	  because it may require use of semaphores and cause
 	  additional context switches. lldbg() is safe.
 	* Interrupt must be disabled throughout all context switches.
@@ -51,8 +51,8 @@
 	  serial.h defines the interface.
 	* Fixed mq_receive() and mq_send() -- bad memcpy()
 	* Fixed C5471 signal deliver logic: use of dbg() and
-          other actions by use signal handler can alter errno.
-          need to protect errno during signal handling.
+		  other actions by use signal handler can alter errno.
+		  need to protect errno during signal handling.
 	* Fixed uninitialized variable in filesystem that could
 	  cause various problems
 	* Added a test for roundrobin scheduler.
@@ -206,7 +206,7 @@
 	* Adding socket(), bind(), connect()
 	* Added snprintf()
 	* Added send() and sendto(); integrate write() and close() with socket descriptors.
-        * Added recv() and recvfrom().
+	* Added recv() and recvfrom().
 	* Added getsockopt() and setsockopt()
 	* Documentation updated to address socket interfaces.
 	* Implemented receive timeouts via setsockopt(SO_RCVTIMEO).
@@ -308,7 +308,7 @@
 	  interrupt architecture (like the Z16F)
 	* Added a "dumb" serial console driver to simplify OS bringup
 	* Corrected a bug that caused the errno value of one task to be clobbered
-	  when a different task exits.  Effects all architectures.
+	  when a different task exits.	Effects all architectures.

 0.3.8 2008-02-10 Gregory Nutt <spudmonkey@racsa.co.cr>

@@ -317,16 +317,16 @@
 	* 'errno' is now defined to be *get_errno_ptr() with no name conflicts
 	* Added lseek() and fseek()
 	* Integrated Pascal interpreter test case on the simulation platform.  Needs
-          pascal-0.1.1.
+		  pascal-0.1.1.
 	* Add Pascal test case on the z16f platform.  Needs pascal-0.1.2 (does not
-          yet work due to some tool issues).
+		  yet work due to some tool issues).
 	* C buffered I/O fixes:
 	  - Fix fflush() return value,
 	  - Add correct fflush behavior when the FILE argument is null.
 	  - Add logic to a correctly handle read/write access on the same FILE
 	  - fseek() flushes read/write data when before moving the file pointer
 	  - When read data is flushed, reposition the file pointer to account for
-	    buffered, but unread data
+		buffered, but unread data
 	* Pascal P-Code files are now standardized to big-endian for portability
 	* Fix a build problem with z80 and SDCC 2.7.0 (format of a map file changed)
 	  (see bug 1887170)
@@ -384,7 +384,7 @@
 	* Fixed error in dup and dup2: Must call open/close methods in fs/driver so that
 	  driver can correctly maintain open reference counts.
 	* Same issue on closing file descriptors in exit()
-	* Fixed in error in stdio flush logic.  Needed ssize_t vs size_t for error
+	* Fixed in error in stdio flush logic.	Needed ssize_t vs size_t for error
 	  check.
 	* Moved all FAT related files from fs to fs/fat
 	* Implemented mkfatfs(), a non-standard API to create a FAT filesystem on a
@@ -514,7 +514,7 @@
 	* Added USB storage class device side driver (BBB)
 	* Fixed a bug in the LPC214x USB driver: It was not properly handling request buffers
 	  larger then the endpoint's max packet (DM320 driver also fixed, untested)
-	* Added logic to the USB device interface:  A bit is needed to force the driver to
+	* Added logic to the USB device interface:	A bit is needed to force the driver to
 	  to terminate an IN transfer with a short packet (zero-length if necessary).
 	* Fix an error in the NXP LPC214x USB device driver that was causing corruption of
 	  the request queue (M320 driver also fixed, untested)
@@ -543,24 +543,24 @@
 	  CMON debugger.  At any rate, I have exhausted all of the energy that I am willing to put
 	  into this cool old processor for the time being.
 	* Renamed configuration item CONFIG_PROC_STACK_SIZE as CONFIG_IDLETHREAD_STACKSIZE:  It now
-	  only controls the size of the stack for the IDLE thread.  Added CONFIG_USERMAIN_STACKSIZE:
+	  only controls the size of the stack for the IDLE thread.	Added CONFIG_USERMAIN_STACKSIZE:
 	  This is the size of stack used with the user_start() thread is created.  The two stacks
 	  no longer have to be the same.
 	* Add a loop device that converts a file into a block device.
 	* Each NSH command can not be disabled through a configuration setting. All of these
 	 settings make the configuration of NSH potentially complex but also allow it to squeeze
 	  into very small memory footprints.
-	* Added a block to character (BCH) driver.  This is kind of the reverse of the loop
+	* Added a block to character (BCH) driver.	This is kind of the reverse of the loop
 	  device; it allows you access a block device like a character device.
 	* Added strcasecmp() and strncasecmp()
 	* NSH: Added the 'dd' command
 	* NSH: Added the 'losetup' command
-	* Fixed a FAT bug:  After recent changes, it would mount a (invalid) FAT file system
+	* Fixed a FAT bug:	After recent changes, it would mount a (invalid) FAT file system
 	  even if the medium is not formatted!
 	* Corrected two important errors in FAT lseek implementation: (1) the sectors-per-cluster
 	  value was being reset to "1" and (2) important lseek logic was omitted when the seek
 	  position was zero.
-	* Fixed a bug in getopt().  It would fail if on certain combinations of terminal argument
+	* Fixed a bug in getopt().	It would fail if on certain combinations of terminal argument
 	  types.

 0.3.19 2008-11-26 Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -574,7 +574,7 @@
 	* Implement poll() and select() support for TCP/IP sockets
 	* Fixed an important bug in the TCP/IP buffering logic.  When TCP/IP read-ahead is enabled
 	  and not recv() is in-place when a TCP/IP packet is received, the packet is placed into
-	  a read-ahead buffer.  However, the old contents of the read-ahead buffer were not being
+	  a read-ahead buffer.	However, the old contents of the read-ahead buffer were not being
 	  cleared and old data would contaminate the newly received buffer.
 	* Implemented support for connection backlog.  The size of the backlog is specified by the
 	  second argument of the standard listen() API.  Hooks are provided to support poll()/select()
@@ -617,15 +617,15 @@
 	  the target cannot be built because the GNU m16c-elf-ld link fails with 
 	  the following message:

-	    m32c-elf-ld: BFD (GNU Binutils) 2.19 assertion fail /home/Owner/projects/nuttx/buildroot/toolchain_build_m32c/binutils-2.19/bfd/elf32-m32c.c:482
+		m32c-elf-ld: BFD (GNU Binutils) 2.19 assertion fail /home/Owner/projects/nuttx/buildroot/toolchain_build_m32c/binutils-2.19/bfd/elf32-m32c.c:482

 	  Where the reference line is:

-	    /* If the symbol is out of range for a 16-bit address,
-	       we must have allocated a plt entry.  */
-	     BFD_ASSERT (*plt_offset != (bfd_vma) -1);
+		/* If the symbol is out of range for a 16-bit address,
+		   we must have allocated a plt entry.	*/
+		 BFD_ASSERT (*plt_offset != (bfd_vma) -1);

-	  No workaround is known at this time.  This is a show stopper for M16C.
+	  No workaround is known at this time.	This is a show stopper for M16C.

 	* eZ80Acclaim!: Fix interrupt vectors positioning; they were being positioned
 	  wrong by 64 bytes (Kevin Franzen).
@@ -633,7 +633,7 @@
 	   context save and restore (Kevin Franzen).
 	* eZ80Acclaim!: Corrected vector intialization logic (Kevin Franzen).
 	* eZ80Acclaim!: Corrected overflow problem in the calculation of UART baud rate
-	    divisor, the system timer divisor, and the EMAC poll timer.
+		divisor, the system timer divisor, and the EMAC poll timer.
 	* eZ80Acclaim!: Fixed GPIO pin configuration get serial output
 	* eZ80Acclaim!: Correct stack overflow in ostest example configuration
 	* eZ80Acclaim!: Fixed restoration of interrupts state on interrupt level context swith.
@@ -648,9 +648,9 @@
 	* eZ80Acclaim!: Added and verified a NuttShell (NSH) configuration.
 	* eZ80Acclaim!: Correct endian-ness; defconfig files said BIG endian.
 	* Restructured parts of the uIP port for correct compilation with ZDS-II
-	* eZ80Acclaim!: Complete basic integration of the eZ80F91 EMAC driver.  The
+	* eZ80Acclaim!: Complete basic integration of the eZ80F91 EMAC driver.	The
 	  driver is basically functional and should mature prior to the 0.4.3 release.
-	* Implemented priority inheritance logic for POSIX semaphores.  Because the pthread
+	* Implemented priority inheritance logic for POSIX semaphores.	Because the pthread
 	  mutexes are built on semaphores, they will have this property as well.

 0.4.4 2009-03-29 Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -678,7 +678,7 @@
 	* examples/sendmail: A simple sendmail example (untested -- see NOTE)

 	NOTE: Features related to wget and sendmail are not tested on the target platform
-	in this release and, hence, most likely have problems.  I don't have the correct network
+	in this release and, hence, most likely have problems.	I don't have the correct network
 	network setup to perform that testing now (I'm in a hotel).

 0.4.5 2009-04-19 Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -756,19 +756,19 @@

 	* lib/lib_*stream.c: Extend internal stream logic to support incoming streams.
 	* arch/arm/src/str71x: Serial output is now correct and timer interrupts are
-	  working.  The test at configs/olimex-strp711/ostest passes.  This means that
+	  working.	The test at configs/olimex-strp711/ostest passes.  This means that
 	  the basic STR-P711 port is complete.
 	* configs/olimex-strp711/nsh:  Add and verifed a NuttShell (NSH) configuration
 	  for the STR-P711.
-	* arch/arm/str71x/str71x_serial.c:  The STR711 interrupt driven serial driver
+	* arch/arm/str71x/str71x_serial.c:	The STR711 interrupt driven serial driver
 	  finally works after some extradinary measures to handle missed interrupts.
 	  NSH is fully functional on the Olimex STR-P711 board.
 	* example/nsh: Moved architecture specific files from NSH directory to board-
 	  specific directories.
 	* config/olimex-strp711/src/up_nsh.c:  Add an NSH board specific directory for
 	  for the Olimex STR7P11 board.
-	* Fixed build of LM3X6918 using the CodeSourcery Windows native toolchain.  There
-	  were lots of issues with Cygwin paths and Cygwin symbolic links.  These changes
+	* Fixed build of LM3X6918 using the CodeSourcery Windows native toolchain.	There
+	  were lots of issues with Cygwin paths and Cygwin symbolic links.	These changes
 	  may work with the devarmKIT as well, but that remains untested.
 	* The NXP LPC2148 and STR711 targets can now also be built using the CodeSourcery
 	  or devkitARM Windows native toolchains.
@@ -795,7 +795,7 @@
 	  include paths for Cygwin-based GCC were being converted to windows
 	  native paths.  That causes many problems -- breaking dependencies
 	  for one.
-	* Fixed an important bug in ROMFS.  The initial XIP offset was set
+	* Fixed an important bug in ROMFS.	The initial XIP offset was set
 	  incorrectly so if sector zero was read first, there was a bad read.
 	  I don't know how it worked before.
 	* arch/arm/src/common/up_use_stack.c.  Fixed a fatal stack setup error.
@@ -811,13 +811,13 @@
 	* sched/: Added gettimeofday().  This implementation is simply a thin
 	  wrapper around clock_gettimer().
 	* lib/: Add gmtime(), localtime(), and strftime()
-	* binfmt/: Add exec().  This is just a wrapper that executes both
+	* binfmt/: Add exec().	This is just a wrapper that executes both
 	  load_ and exec_module() in a more familiar manner.  It is not consistent
 	  with more standard exec() functions, however, because (1) it returns
 	  and (2) it requires symbol table arguments.
 	* lib/: Add fileno()
 	* examples/ostest: Several of the tests used a big, hard-coded stack size
-	  when creating test threads (16Kb stacksize).  The stack size should
+	  when creating test threads (16Kb stacksize).	The stack size should
 	  be controlled by the .config file or the OSTest won't work on platforms
 	  with memory constraints.
 	* netutils/thttpd: An initial port of Jeff Poskanzer's THTTPD HTTP server.
@@ -834,7 +834,7 @@
 	  connection backlog is enabled.
 	* fs/fs_fcntl.c and net/net_vfcntl.c: Minimal support provided for fcntl().
 	  It can, at least, be used to mark sockets as blocking or non-blocking.
-	* net/net_close.c: Fix bug in close().  If reference count not set to zero
+	* net/net_close.c: Fix bug in close().	If reference count not set to zero
 	  then uip_tcpfree() will assert when DEBUG is enabled.
 	* net/accept.c: Fix bug in accept().  The logic expected parts of the
 	  return address structure to be initialized or it would return an error.
@@ -856,11 +856,11 @@
 	  extra two bytes of length cause the driver to sometimes read one too many
 	  words from the received FIFO (corrupting the next queued receive packet,
 	  if any).
-	* net/net_poll.c and net/uip/uip_tcpbacklog.c.  Fixed an important race condition
+	* net/net_poll.c and net/uip/uip_tcpbacklog.c.	Fixed an important race condition
 	  bug in polling for connections.  The logic worked if the poll was inplace
 	  before the connection was received; but the poll failed to awaken if the
 	  connection was already pending in the backlog when poll() was called.
-	* net/net_close.c.  Fixed another important TCP/IP race condition bug:  If
+	* net/net_close.c.	Fixed another important TCP/IP race condition bug:	If
 	  the host closes the TCP connection just before the target calls close(), then
 	  the close operation may hang indefinitely!
 	* net/net_tcppoll.c.  Removed an unnecessary check for outstanding, un-ACKed
@@ -869,14 +869,14 @@
 	* Add DEBUG configuration option to enable debug console output without disabling
 	  optimization (and vice versa)
 	* Changed lots of occurrents of debug macro dbg() to lldbg().  dbg() uses
-	  stdout to output debug data.  That works fine unless (1) the dbg() macro
+	  stdout to output debug data.	That works fine unless (1) the dbg() macro
 	  is interrupt logic and the interrupted task has redirected stdout!  Most
 	  changes were in uIP.
 	* net/uip/uip_tcpinput.c.  Connection reference count was not being set correctly
 	  when a socket is created by accepting a new connection.  Since the reference
 	  count is bad, such sockets are not successfully duplicated when being passed
 	  to new tasks.
-	* net/net_clone.c.  Similarly, after a socket is cloned, its reference count
+	* net/net_clone.c.	Similarly, after a socket is cloned, its reference count
 	  was not being initialized.
 	* lib/lib_strstr.c.  Improperly incremented pointer could cause comparison
 	  failures.
@@ -889,7 +889,7 @@
 	* net/net_close.c and net/net_sockets.c.  Sockets were not being closed
 	  when a task exits.  If many server tasks are created and exit without closing
 	  sockets (such as with CGI tasks), then eventually, you will run out of sockets.
-	* netutils/thttpd.  Basic functionality of THTTPD is complete.  This includes
+	* netutils/thttpd.	Basic functionality of THTTPD is complete.	This includes
 	  serving up files from a file system and executing NXFLAT-based CGI programs
 	  and pipe the stdout back to the HTTP client.

@@ -907,7 +907,7 @@
 	* configs/stm3210e-eval/src/stm32102e-internal.h.  Fix on-board LED GPIO definitions.
 	* arch/arm/src/stm32/src/stm32/stm32_dma.c.  Added DMA channel support for the STM32
 	* arch/arm/src/stm32/src/stm32/stm32_spi.c.  Added a DMA-based SPI driver for the STM32.
-	* arch/arm/src/stm32/src/stm32/stm32_serial.c.  Finished interrupt-drivent,
+	* arch/arm/src/stm32/src/stm32/stm32_serial.c.	Finished interrupt-drivent,
 	  USART console driver.  This makes NSH work perfectly.
 	* Things left to do for the STM32 deferred to the 0.4.13 release:  USB device driver,
 	  LCD driver and NX bringup on the eval board's display and MicroSD support.  An SPI
@@ -915,17 +915,17 @@

 0.4.13 2009-11-04 Gregory Nutt <spudmonkey@racsa.co.cr>

-	* include/nuttx/mtd.h.  Added a simple interface definition to support some
+	* include/nuttx/mtd.h.	Added a simple interface definition to support some
 	  FLASH, EEPROM, NVRAM, etc. devices.
 	* driver/mtd/m25px.c.  Added a driver for SPI based FLASH parts M25P64 and M25P128.
-	* configs/stm3210e-eval/usbserial.  Add a USB serial configuration for the STM32.
+	* configs/stm3210e-eval/usbserial.	Add a USB serial configuration for the STM32.
 	  Depends on the STM32 USB driver.
-	* arch/arm/src/cortexm3/up_switchcontext.S & up_svccall.c.  Made an improvement
+	* arch/arm/src/cortexm3/up_switchcontext.S & up_svccall.c.	Made an improvement
 	  to context switching.  There are two types of context switches:  interrupt
 	  context switches and background/user context switches.  This change should
 	  improve the performance of those background/user context switches by a factor
 	  of about two.
-	* arch/arm/src/stm32/ - fix several typos in the serial logic.  It turns out
+	* arch/arm/src/stm32/ - fix several typos in the serial logic.	It turns out
 	  that these typose don't make any difference as long as you use only one
 	  serial port and all uarts are configured the same.  But the typos are bugs
 	  waiting to happen in any other configuration.
@@ -939,11 +939,45 @@
 	  On some boards (none of mine), the HSE (high speed external clock) delay
 	  loop times out if the optimization level is high. The STM32 then falls
 	  back to the HSI (internal clock), and the system clock is too slow by a
-	  factor of 11.1%.  This was fixed by simply add the volatile storage class
+	  factor of 11.1%.	This was fixed by simply add the volatile storage class
 	  to the timeout loop counter
 	* arch/arm/src/stm32/stm32_irq.c - Fixed a critical bug in the interrupt
 	  control logic.  The wrong register was being used for interrupts in a
 	  certain range.  Worked fine until you try to use an interrupt in that
 	  range!

-0.4.14 2009-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+4.14 2009-12-02 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* arch/arm/src/stm32/stm32_gpio.c - Add support for configure an input GPIO
+	  to generate an EXTI interrupt.
+	* config/stm3210e-eval/src/up_buttons.c - Add support for on-board buttons.
+	* include/nuttx/rwbuffer.h -- Add generic support for read-ahead buffering
+	  and write buffering that can be used in any block driver.
+	* include/nuttx/wqueue.h -- Added a generic worker thread that can used to
+	  defer processing from an interrupt to a task.
+	* include/nuttx/sdio.h -- Defines a generic SD/SDIO interface can can be
+	  bound to a MMC/SD driver to provide SDIO-based MMC/SD support.
+	* drivers/mmcsd/mmcsd_sdio.c -- Provides a an SDIO-based MMC/SD driver.
+	* arch/arm/src/stm32/stm32_sdio.c -- Provides an STM32 implementation of
+	  the SDIO interface defined in include/nuttx/sdio.h.
+	* fs/fs_mount.c -- Correct error handling logic.  If the bind() method
+	  fails, then a reserved node is left in the tree.	This causes subsequent
+	  attempts to mount at the location to fail (reporting that the node
+	  already exists).	This is a problem for block drivers for removable
+	  media: The bind method could fail repeatedly until media is inserted.
+	* arch/arm/src/stm32/chip.h & stm32_dma.c -- Fixed several definitions
+	  that can cause compilation errors when DMA2 is enabled.
+	* arch/arm/src/stm32/stm32_dma.c - Integrated and debugged STM32 DMA
+	  functionality that was added in 0.4.12.
+	* configs/stm3210e-eval/usbstorage - Add a configuration to exercise
+	  the STM32 with the USB mass storage device class example
+	  (examples/usbstorage).
+	* configs/mcu123-lpc214x/up_usbstrg - Move LPC-specific code from
+	  examples/usbstorage to configs/mcu123-lpc214x.
+	* configs/stm321e-eval/up_usbstrg - Add STM32-specific logic for the
+	  examples/usbstorage test.
+	* arch/arm/src/stm32/stm32_usbdev.c - Fix bugs in STM32 USB device-side
+	  driver:  (1) Need to disconnect after reset received, (2) Status setup
+	  to recover from stall on TX endpoint.
+
+2010.1 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
--- a/Documentation/NuttX.html
+++ b/Documentation/NuttX.html
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: October 30, 2009</p>
+      <p>Last Updated: December 2, 2009</p>
    </td>
  </tr>
 </table>
@@ -729,10 +729,10 @@
  </tr>
 </table>

-<p><b>nuttx-0.4.12</b>.
+<p><b>nuttx-4.14</b>.

 <p>
-  This 45<sup>th</sup> release of NuttX was made on November 4, 2009 and is available for download from the
+  This 46<sup>th</sup> release of NuttX was made on December 2, 2009 and is available for download from the
  <a href="http://sourceforge.net/project/showfiles.php?group_id=189573">SourceForge</a> website.
  The change log associated with the release is available <a href="#currentrelease">here</a>.
  Unreleased changes after this release are available in CVS.
@@ -740,35 +740,48 @@
 </p>
 <p>
  The release extends the support for the STMicro STM32 microcontroller.
-  Minimul support for the STM3210E-EVAL development board based around the STM32F103ZET6
-  MCU was released in NuttX-0.4.12.
-  This release adds:
+  Minimal support for the STM3210E-EVAL development board based around the STM32F103ZET6
+  MCU was released in NuttX-0.4.12 and extended in Nuttx-0.4.13 to include initial USB support.
+  This completes the STM32F103ZET6 support and adds:
+</p>
+<p>
+  New Generic RTOS Features:
  <ul>
-	<li>A simple interface definition to support some FLASH, EEPROM, NVRAM, etc. devices.</li>
-    <li>Verified SPI operation using driver for SPI based FLASH parts M25P64 and M25P128.</li>
-    <li>Improved Cortex-M3 context switching.
-      This should improve context switching performance be 2x in certain cases.</li>
-    <li>Added a USB device-side driver for the STM32.
-      This is an early release of a very complex driver; some bugs are expected.</li> 
-    <li>The USB driver has been verified against the USB serial device class driver.
-	  There is at least one known outstanding issue (see the full bug description in
-	  the TODO list).</li>
+	<li>Added generic support that can be included in any block driver to provide
+	    read-ahead buffering and write buffering for improved driver performance.</li>
+    <li>Added a generic worker thread that can used to defer processing from an
+	    interrupt to a task.</li>
+    <li>Defined a generic SD/SDIO interface can can be bound to a MMC/SD or SDIO
+	    driver to orovide SDIO support.</li>
+    <li>Implemented a an SDIO-based MMC/SD driver using this new SDIO interface</li> 
  </ul>
 </p>
 <p>
-  This release also corrects some important bugs in the early STM32 release:
+  New STM32-specific Features:
  <ul>
-    <li>Fixed several errors the prevented operation of NuttX on an STM32 development
-	  board using USART2 as the serial console.</li>
-    <li>Fixed and optimization-dependent race condition in the clock initialization.</li>
-    <li>Fixed a critical bug in the interrupt control logic that could cause interrupt
-	  operations to failed used for interrupts in a certain range.</li>
+	<li>Add support to configure an STM32 input GPIO to generate an EXTI interrupt.</li>
+    <li>Added support for buttons on the STM3210E-EVAL board.</li>
+    <li>Implemented an STM32 version of the common the SDIO interface.</li>
+    <li>Added a configuration to exercise the STM32 with the USB mass storage
+	    device class example.</li> 
  </ul>
+</p>
 <p>
+  This release also corrects some important bugs in the earlier STM32 releases:
+  <ul>
+	<li>Correct error handling in the mount() logic.</li>
+    <li> Fixed several STM32 DMA-related issues. Integrated and debugged STM32 DMA
+	    functionality that was added in 0.4.12.</li>
+    <li>Fixed several bugs in the STM32 USB device-side driver.</li>
+  </ul>
+</p>
 <p>
-  DMA and external memory support are included in the 0.4.13 release, but is not yet tested.
-  This basic STM32 port will be further extended in the 0.4.14 NuttX release to include
-  MicroSD support and verified USB mass storage class support.
+  NOTE:  This version, 4.14, is equivalent to what would have been called 0.4.14
+  to follow 0.4.13.  The zero has been eliminated from the front of the version
+  number to avoid confusion about the state of development:  Some have interpreted
+  the leading zero to mean that the code is in some way unstable.  That was not
+  the intent.  Beginning in January 2010, I will switch to the 2010.nn versioning
+  as many others have done to avoid such confusion.
 </p>

 <table width ="100%">
@@ -990,12 +1003,10 @@
        <b>STATUS:</b>
        The basic STM32 port was released in NuttX version 0.4.12. The basic port includes boot-up
        logic, interrupt driven serial console, and system timer interrupts.
-        The 0.4.13 release added support for SPI, serial FLASH, and USB device.
+        The 0.4.13 release added support for SPI, serial FLASH, and USB device.;
+        The 4.14 release added support for buttons and SDIO-based MMC/SD and verifed DMA support.
        Verified configurations are available for NuttX OS test, the NuttShell (NSH) example,
-        and a USB serial device class.
-        DMA and external memory support are included in the 0.4.13 release, but is not yet tested.
-        This basic STM32 port will be further extended in the 0.4.14 NuttX release to include
-        MicroSD support and verified USB mass storage class support.
+        the USB serial device class, and the USB mass storage device class example.
      </p>
      <p>
        <b>Development Environments:</b>
@@ -1534,38 +1545,39 @@ Other memory:
 </table>

 <ul><pre>
-nuttx-0.4.13 2009-11-04 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
+nuttx-4.14 2009-12-02 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

-	* include/nuttx/mtd.h.  Added a simple interface definition to support some
-	  FLASH, EEPROM, NVRAM, etc. devices.
-	* driver/mtd/m25px.c.  Added a driver for SPI based FLASH parts M25P64 and M25P128.
-	* configs/stm3210e-eval/usbserial.  Add a USB serial configuration for the STM32.
-	  Depends on the STM32 USB driver.
-	* arch/arm/src/cortexm3/up_switchcontext.S & up_svccall.c.  Made an improvement
-	  to context switching.  There are two types of context switches:  interrupt
-	  context switches and background/user context switches.  This change should
-	  improve the performance of those background/user context switches by a factor
-	  of about two.
-	* arch/arm/src/stm32/ - fix several typos in the serial logic.  It turns out
-	  that these typose don't make any difference as long as you use only one
-	  serial port and all uarts are configured the same.  But the typos are bugs
-	  waiting to happen in any other configuration.
-	* arch/arm/src/stm32/ - You have to configure CTS/RTS function pins for USART
-	  2 and USART 3 even if you are not using flow control.
-	* arch/arm/src/stm32/stm32_usbdev.c - Added a USB device-side driver for the
-	  STM32.  NOTE: This is an early release of the USB driver.  There is at least
-	  one known issue. The examples/usbserial test only executes correctly under
-	  certain conditions (see the full bug description in the TODO list).
-	* arch/arm/src/stm32/stm32_rcc.c - Fixed an error in clock initialization.
-	  On some boards (none of mine), the HSE (high speed external clock) delay
-	  loop times out if the optimization level is high. The STM32 then falls
-	  back to the HSI (internal clock), and the system clock is too slow by a
-	  factor of 11.1%.  This was fixed by simply add the volatile storage class
-	  to the timeout loop counter
-	* arch/arm/src/stm32/stm32_irq.c - Fixed a critical bug in the interrupt
-	  control logic.  The wrong register was being used for interrupts in a
-	  certain range.  Worked fine until you try to use an interrupt in that
-	  range!
+	* arch/arm/src/stm32/stm32_gpio.c - Add support for configure an input GPIO
+	  to generate an EXTI interrupt.
+	* config/stm3210e-eval/src/up_buttons.c - Add support for on-board buttons.
+	* include/nuttx/rwbuffer.h -- Add generic support for read-ahead buffering
+	  and write buffering that can be used in any block driver.
+	* include/nuttx/wqueue.h -- Added a generic worker thread that can used to
+	  defer processing from an interrupt to a task.
+	* include/nuttx/sdio.h -- Defines a generic SD/SDIO interface can can be
+	  bound to a MMC/SD driver to provide SDIO-based MMC/SD support.
+	* drivers/mmcsd/mmcsd_sdio.c -- Provides a an SDIO-based MMC/SD driver.
+	* arch/arm/src/stm32/stm32_sdio.c -- Provides an STM32 implementation of
+	  the SDIO interface defined in include/nuttx/sdio.h.
+	* fs/fs_mount.c -- Correct error handling logic.  If the bind() method
+	  fails, then a reserved node is left in the tree.  This causes subsequent
+	  attempts to mount at the location to fail (reporting that the node
+	  already exists).  This is a problem for block drivers for removable
+	  media: The bind method could fail repeatedly until media is inserted.
+	* arch/arm/src/stm32/chip.h & stm32_dma.c -- Fixed several definitions
+	  that can cause compilation errors when DMA2 is enabled.
+	* arch/arm/src/stm32/stm32_dma.c - Integrated and debugged STM32 DMA
+	  functionality that was added in 0.4.12.
+	* configs/stm3210e-eval/usbstorage - Add a configuration to exercise
+	  the STM32 with the USB mass storage device class example
+	  (examples/usbstorage).
+	* configs/mcu123-lpc214x/up_usbstrg - Move LPC-specific code from
+	  examples/usbstorage to configs/mcu123-lpc214x.
+	* configs/stm321e-eval/up_usbstrg - Add STM32-specific logic for the
+	  examples/usbstorage test.
+	* arch/arm/src/stm32/stm32_usbdev.c - Fix bugs in STM32 USB device-side
+	  driver:  (1) Need to disconnect after reset received, (2) Status setup
+	  to recover from stall on TX endpoint.

 pascal-0.1.2 2008-02-10 Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

@@ -1594,11 +1606,11 @@ buildroot-0.1.7 2009-06-26 &lt;spudmonkey@racsa.co.cr&gt;
 </table>

 <ul><pre>
-nuttx-0.4.14 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
+nuttx-2010.1 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

-pascal-0.1.3 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
+pascal-2010.1 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

-buildroot-0.1.8 2009-xx-xx &lt;spudmonkey@racsa.co.cr&gt;
+buildroot-2010.1 2010-xx-xx &lt;spudmonkey@racsa.co.cr&gt;
 </pre></ul>

 <table width ="100%">
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -12,7 +12,7 @@
      <h1><big><font color="#3c34ec">
        <i>NuttX RTOS Porting Guide</i>
      </font></big></h1>
-      <p>Last Updated: September 15, 2009</p>
+      <p>Last Updated: November 17, 2009</p>
    </td>
  </tr>
 </table>
@@ -2124,12 +2124,40 @@ extern void up_ledoff(int led);
    <code>CONFIG_SDCLONE_DISABLE</code>: Disable cloning of all socket
    desciptors by task_create() when a new task is started.
    If set, all sockets will appear to be closed in the new task.
-  </li>: 
+  </li>
  <li>
    <code>CONFIG_NXFLAT</code>: Enable support for the NXFLAT binary format.
    This format will support execution of NuttX binaries located
    in a ROMFS filesystem (see <code>examples/nxflat</code>).
  </li>
+  <li>
+    <code>CONFIG_SCHED_WORKQUEUE</code>: Create a dedicated "worker" thread to
+    handle delayed processing from interrupt handlers.  This feature
+    is required for some drivers but, if there are not complaints,
+    can be safely disabled.  The worker thread also performs
+    garbage collection -- completing any delayed memory deallocations
+    from interrupt handlers.  If the worker thread is disabled,
+    then that clean will be performed by the IDLE thread instead
+    (which runs at the lowest of priority and may not be appropriate
+    if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+    is enabled, then the following options can also be used:
+  </li>
+  <li>
+    <code>CONFIG_SCHED_WORKPRIORITY</code>: The execution priority of the worker
+    thread.  Default: 50
+  </li>
+  <li>
+    <code>CONFIG_SCHED_WORKPERIOD</code>: How often the worker thread checks for
+    work in units of microseconds.  Default: 50*1000 (50 MS).
+  </li>
+  <li>
+    <code>CONFIG_SCHED_WORKSTACKSIZE</code>: The stack size allocated for the worker
+    thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+  </li>
+  <li>
+    <code>CONFIG_SIG_SIGWORK</code>: The signal number that will be used to wake-up
+    the worker thread.  Default: 4
+  </li>
 </ul>

 <p>
@@ -2260,6 +2288,25 @@ extern void up_ledoff(int led);
  </li>
 </ul>

+<h2>SDIO-based MMC/SD driver</h2>
+<ul>
+  <li>
+    <code>CONFIG_FS_READAHEAD</code>: Enable read-ahead buffering
+  </li>
+  <li>
+    <code>CONFIG_FS_WRITEBUFFER</code>: Enable write buffering
+  </li>
+  <li>
+    <code>CONFIG_SDIO_DMA</code>: SDIO driver supports DMA
+  </li>
+  <li>
+    <code>CONFIG_MMCSD_MMCSUPPORT</code>: Enable support for MMC cards
+  </li>
+  <li>
+    <code>CONFIG_MMCSD_HAVECARDDETECT</code>: SDIO driver card detection is 100% accurate
+  </li>
+</ul>
+
 <h2>Network Support</h2>
 <h3>TCP/IP and UDP support via uIP</h2>
 <ul>
--- a/README.txt
+++ b/README.txt
@@ -1,10 +1,25 @@
 README
 ^^^^^^

+  o Installation
  o Configuring NuttX
  o Building NuttX
  o Documentation

+INSTALLATION
+^^^^^^^^^^^^
+
+Download and unpack the NuttX tarball.  If you are reading this, then you
+have probably already done that.  After unpacking, you will end up with a
+directory called nuttx-version (where version is the NuttX version number).
+You might want to rename that directory nuttx to match the various instructions
+in the documentation and some scripts in the source tree.
+
+That nuttx build directory should reside in a path that contains no spaces
+in the higher level directory names.  For example, under Cygwin, your home
+directory might be formed from your first and last names like: "/home/First Last".
+That will cause strange errors when the make system tries to build.
+
 CONFIGURING NUTTX
 ^^^^^^^^^^^^^^^^^

--- a/46
+++ b/46
@@ -1007,7 +1007,7 @@ nuttx-0.4.13
 ^^^^^^^^^^^^

 This is the 45th release of NuttX.  The release extends the support for the STMicro
-STM32 microcontroller.  Minimul support for the STM3210E-EVAL development board based
+STM32 microcontroller.  Minimal support for the STM3210E-EVAL development board based
 around the STM32F103ZET6 MCU was released in NuttX-0.4.12.  This release adds:

 	* A simple interface definition to support some FLASH, EEPROM, NVRAM, etc. devices.
@@ -1029,3 +1029,47 @@ This release also corrects some important bugs in the early STM32 release:
 	  operations to failed used for interrupts in a certain range.

 This tarball contains a complete CVS snapshot from November 4, 2009
+
+nuttx-4.14
+^^^^^^^^^^
+
+This is the 46th release of NuttX.  The release extends the support for the STMicro
+STM32 microcontroller.  Minimal support for the STM3210E-EVAL development board based
+around the STM32F103ZET6 MCU was released in NuttX-0.4.12 and extended in Nuttx-0.4.13
+to include initial USB support.  This completes the STM32F103ZET6 and adds:
+
+New Generic RTOS Features:
+
+	* Added generic support that can be included in any block driver to provide
+	  read-ahead buffering and write buffering for improved driver performance.
+	* Added a generic worker thread that can used to defer processing from an
+	  interrupt to a task.
+	* Defined a generic SD/SDIO interface can can be bound to a MMC/SD or SDIO
+	  driver to orovide SDIO support.
+	* Implemented a an SDIO-based MMC/SD driver using this new SDIO interface
+
+New STM32 Features:
+
+	* Add support to configure an STM32 input GPIO to generate an EXTI interrupt.
+	* Added support for buttons on the STM3210E-EVAL board.
+	* Implemented an STM32 version of the common the SDIO interface.
+	* Added a configuration to exercise the STM32 with the USB mass storage
+	  device class example.
+
+This release also corrects some important bugs in the early STM32 release:
+
+	* Correct error handling in the mount() logic.
+	* Fixed several STM32 DMA-related issues. Integrated and debugged STM32 DMA
+	  functionality that was added in 0.4.12.
+	* Fixed several bugs in the STM32 USB device-side driver.
+
+NOTE:  This version, 4.14, is equivalent to what would have been called 0.4.14
+to follow 0.4.13.  The zero has been eliminated from the front of the version
+number to avoid confusion about the state of development:  Some have interpreted
+the leading zero to mean that the code is in some way unstable.  That was not
+the intent.  Beginning in January 2010, I will switch to the 2010.nn versioning
+as many others have done to avoid such confusion.
+
+This tarball contains a complete CVS snapshot from December 2, 2009
+
+
--- a/26
+++ b/26
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated November 4, 2009)
+NuttX TODO List (Last updated November 29, 2009)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

  (5)  Task/Scheduler (sched/)
@@ -645,18 +645,10 @@ o ARM/LM3S6918 (arch/arm/src/lm3s/)
 o ARM/STM32 (arch/arm/src/stm32/)
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

-  Description: DMA subsystem is untested.
-  Status:      Open
-  Priority:    Low -- for now
-
  Description: NOR Flash driver and FTL layer to support a file system.
  Status:      Open
  Priority:    Low

-  Description: MMC/SD SDIO driver needed.
-  Status:      Open
-  Priority:    Medium
-
  Description  A USB device-side driver is in place but not well tested.  At
               present, the examples/usbserial test sometimes fails.  The situation
               that causes the failure is:
@@ -679,9 +671,23 @@ o ARM/STM32 (arch/arm/src/stm32/)
  Priority:    Medium-High
  
  Description: FSMC external memory support is untested
-  Status:      Opon
+  Status:      Open
  Priority:    Low

+  Description: DMA logic needs to be extended.  DMA2, Channel 5, will not work
+               because the DMA2 channels 4 & 5 share the same interrupt.
+  Status:      Open
+  Priority:    Low until someone needs DMA1, Channel 5 (ADC3, UART4_TX, TIM5_CH1, or
+               TIM8_CH2).
+
+  Desription:  I am unable to access a 2Gb SanDisk microSD card (in adaptor) on the
+               the STM3210E-EVAL board.  The card reports that it is a SDV1.x card
+               with a 1Kb block size, but the CMD16 to set the block length to
+               1024 fails.
+  Status:      Open
+  Priority:    Uncertain.  I don't this is a bug, I think I just don't understand
+               how to work with this type of SD card.
+
 o pjrc-8052 / MCS51 (arch/pjrc-8051/)
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -124,6 +124,19 @@ void up_initialize(void)

  up_irqinitialize();

+  /* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
+   * brought into the build
+   */
+
+#ifdef CONFIG_ARCH_DMA
+#ifdef CONFIG_HAVE_WEAKFUNCTIONS
+  if (up_dmainitialize)
+#endif
+    {
+      up_dmainitialize();
+    }
+#endif
+
  /* Initialize the system timer interrupt */

 #if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -156,6 +156,9 @@ extern void up_boot(void);
 extern void up_copystate(uint32 *dest, uint32 *src);
 extern void up_decodeirq(uint32 *regs);
 extern void up_irqinitialize(void);
+#ifdef CONFIG_ARCH_DMA
+extern void weak_function up_dmainitialize(void);
+#endif
 extern int  up_saveusercontext(uint32 *saveregs);
 extern void up_fullcontextrestore(uint32 *restoreregs) __attribute__ ((noreturn));
 extern void up_switchcontext(uint32 *saveregs, uint32 *restoreregs);
--- a/arch/arm/src/lpc214x/lpc214x_usbdev.c
+++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * arch/arm/src/lpc214x/lpc214x_usbdev.c
 *
- *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 *
 * Redistribution and use in source and binary forms, with or without
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -47,5 +47,5 @@ CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 CHIP_ASRCS	= 
 CHIP_CSRCS	= stm32_start.c stm32_rcc.c stm32_gpio.c stm32_irq.c \
 		  stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
-		  stm32_spi.c stm32_usbdev.c
+		  stm32_spi.c stm32_usbdev.c stm32_sdio.c

--- a/arch/arm/src/stm32/chip.h
+++ b/arch/arm/src/stm32/chip.h
@@ -57,11 +57,12 @@
 #  define STM32_NATIM                   1   /* One advanced timers TIM1 */
 #  define STM32_NGTIM                   4   /* General timers TIM2,3,4,5 */
 #  define STM32 NBTIM                   0   /* No basic timers */
+#  define STM32_NDMA                    2   /* DMA1-2 */
 #  define STM32_NSPI                    2   /* SPI1-2 */
 #  define STM32_NUSART                  3   /* USART1-3 */
 #  define STM32_NI2C                    2   /* I2C1-2 */
 #  define STM32_NCAN                    1   /* bxCAN1 */
-#  define STM32_NSDIO                   1   /* 1 */
+#  define STM32_NSDIO                   1   /* SDIO */
 #  define STM32_NGPIO                   112 /* GPIOA-G */
 #  define STM32_NADC                    1   /* ADC1 */
 #  define STM32_NDAC                    0   /* No DAC */
--- a/arch/arm/src/stm32/stm32_dma.c
+++ b/arch/arm/src/stm32/stm32_dma.c
@@ -44,9 +44,12 @@
 #include <debug.h>
 #include <errno.h>

+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
 #include <arch/irq.h>

 #include "up_arch.h"
+#include "up_internal.h"
 #include "os_internal.h"
 #include "chip.h"
 #include "stm32_dma.h"
@@ -64,6 +67,10 @@
 #  define DMA_NCHANNELS  DMA1_NCHANNELS
 #endif

+#ifndef CONFIG_DMA_PRI
+#  define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
+#endif
+
 /* Convert the DMA channel base address to the DMA register block address */
 
 #define DMA_BASE(ch)     (ch & 0xfffffc00)
@@ -76,7 +83,7 @@

 struct stm32_dma_s
 {
-  ubyte          chan;     /* DMA channel number */
+  ubyte          chan;     /* DMA channel number (0-6) */
  ubyte          irq;      /* DMA channel IRQ number */
  sem_t          sem;      /* Used to wait for DMA channel to become available */
  uint32         base;     /* DMA register channel base address */
@@ -93,64 +100,72 @@ struct stm32_dma_s
 static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
 {
  {
-	.chan     = STM32_DMA1_CHAN1,
-	.irq      = STM32_IRQ_DMA1CH1,
+    .chan     = 0,
+    .irq      = STM32_IRQ_DMA1CH1,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
  },
  {
-	.chan     = STM32_DMA1_CHAN2,
-	.irq      = STM32_IRQ_DMA1CH2,
+    .chan     = 1,
+    .irq      = STM32_IRQ_DMA1CH2,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
  },
  {
-	.chan     = STM32_DMA1_CHAN3,
-	.irq      = STM32_IRQ_DMA1CH3,
+    .chan     = 2,
+    .irq      = STM32_IRQ_DMA1CH3,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
  },
  {
-	.chan     = STM32_DMA1_CHAN4,
-	.irq      = STM32_IRQ_DMA1CH4,
+    .chan     = 3,
+    .irq      = STM32_IRQ_DMA1CH4,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
  },
  {
-	.chan     = STM32_DMA1_CHAN5,
-	.irq      = STM32_IRQ_DMA1CH5,
+    .chan     = 4,
+    .irq      = STM32_IRQ_DMA1CH5,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
  },
  {
-	.chan     = STM32_DMA1_CHAN6,
-	.irq      = STM32_IRQ_DMA1CH6,
+    .chan     = 5,
+    .irq      = STM32_IRQ_DMA1CH6,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
  },
  {
-	.chan     = STM32_DMA1_CHAN7,
-	.irq      = STM32_IRQ_DMA1CH7,
+    .chan     = 6,
+    .irq      = STM32_IRQ_DMA1CH7,
    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
  },
 #if STM32_NDMA > 1
  {
-	.chan     = STM32_DMA2_CHAN1,
-	.irq      = STM32_IRQ_DMA2CH1,
+    .chan     = 0,
+    .irq      = STM32_IRQ_DMA2CH1,
    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
  },
  {
-	.chan     = STM32_DMA2_CHAN2,
-	.irq      = STM32_IRQ_DMA2CH2,
+    .chan     = 1,
+    .irq      = STM32_IRQ_DMA2CH2,
    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
  },
  {
-	.chan     = STM32_DMA2_CHAN3,
-	.irq      = STM32_IRQ_DMA2CH3,
+    .chan     = 2,
+    .irq      = STM32_IRQ_DMA2CH3,
    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
  },
  {
-	.chan     = STM32_DMA2_CHAN4,
-	.irq      = STM32_IRQ_DMA2CH4,
+    .chan     = 3,
+#ifdef CONFIG_STM32_CONNECTIVITY_LINE
+    .irq      = STM32_IRQ_DMA2CH4,
+#else
+    .irq      = STM32_IRQ_DMA2CH45,
+#endif
    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
  },
  {
-	.chan     = STM32_DMA2_CHAN5,
-	.irq      = STM32_IRQ_DMA2CH5,
+    .chan     = 4,
+#ifdef CONFIG_STM32_CONNECTIVITY_LINE
+    .irq      = STM32_IRQ_DMA2CH5,
+#else
+    .irq      = STM32_IRQ_DMA2CH45,
+#endif
    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
  },
 #endif
@@ -219,6 +234,33 @@ static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach)
  (void)sem_post(&dmach->sem);
 }

+/************************************************************************************
+ * Name: stm32_dmachandisable
+ *
+ * Description:
+ *  Disable the DMA channel
+ *
+ ************************************************************************************/
+
+static void stm32_dmachandisable(struct stm32_dma_s *dmach)
+{
+  uint32 regval;
+
+  /* Disable all interrupts at the DMA controller */
+
+  regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
+  regval &= ~DMA_CCR_ALLINTS;
+
+  /* Disable the DMA channel */
+
+  regval &= ~DMA_CCR_EN;
+  dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
+
+  /* Clear pending channel interrupts */
+
+  dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan));
+}
+
 /************************************************************************************
 * Name: stm32_dmainterrupt
 *
@@ -231,40 +273,44 @@ static int stm32_dmainterrupt(int irq, void *context)
 {
  struct stm32_dma_s *dmach;
  uint32 isr;
-  int chan;
+  int chndx;

  /* Get the channel structure from the interrupt number */

  if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
    {
-      chan = irq - STM32_IRQ_DMA1CH1;
+      chndx = irq - STM32_IRQ_DMA1CH1;
    }
  else
 #if STM32_NDMA > 1
+#ifdef CONFIG_STM32_CONNECTIVITY_LINE
  if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
+#else
+  if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
+#endif
    {
-      chan = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
+      chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
    }
  else
 #endif
    {
      PANIC(OSERR_INTERNAL);
    }
-  dmach = &g_dma[chan];
+  dmach = &g_dma[chndx];

-  /* Get the interrupt status (for this channel only) */
+  /* Get the interrupt status (for this channel only) -- not currently used */

-  isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & ~DMA_ISR_CHAN_MASK(chan);
+  isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);

-  /* Clear pending interrupts (for this channel only) */
+  /* Disable the DMA channel */

-  dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
+  stm32_dmachandisable(dmach);

  /* Invoke the callback */

  if (dmach->callback)
    {
-      dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(chan), dmach->arg);
+      dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), dmach->arg);
    }
  return OK;
 }
@@ -284,16 +330,33 @@ static int stm32_dmainterrupt(int irq, void *context)
 *
 ****************************************************************************/

-void weak_function stm32_dmainitialize(void)
+void weak_function up_dmainitialize(void)
 {
-  int chan;
+  struct stm32_dma_s *dmach;
+  int chndx;

-  /* Attach DMA interrupt vectors */
+  /* Initialize each DMA channel */

-  for (chan = 0; chan < DMA_NCHANNELS; chan++)
+  for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
    {
-      sem_init(&g_dma[chan].sem, 0, 1);	
-      irq_attach(g_dma[chan].irq, stm32_dmainterrupt);
+      dmach = &g_dma[chndx];
+      sem_init(&dmach->sem, 0, 1);
+
+      /* Attach DMA interrupt vectors */
+
+      (void)irq_attach(dmach->irq, stm32_dmainterrupt);
+
+      /* Disable the DMA channel */
+
+      stm32_dmachandisable(dmach);
+
+      /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
+
+      up_enable_irq(dmach->irq);
+ 
+      /* Set the interrrupt priority */
+
+      up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI);
    }
 }

@@ -302,7 +365,7 @@ void weak_function stm32_dmainitialize(void)
 *
 * Description:
 *   Allocate a DMA channel.  This function gives the caller mutually
- *   exclusive access to the DMA channel specified by the 'chan' argument.
+ *   exclusive access to the DMA channel specified by the 'chndx' argument.
 *   DMA channels are shared on the STM32:  Devices sharing the same DMA
 *   channel cannot do DMA concurrently!  See the DMACHAN_* definitions in
 *   stm32_dma.h.
@@ -318,8 +381,8 @@ void weak_function stm32_dmainitialize(void)
 *   version.  Feel free to do that if that is what you need.
 *
 * Returned Value:
- *   Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
- *   void* DMA channel handle.  (If 'chan' is invalid, the function will
+ *   Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL,
+ *   void* DMA channel handle.  (If 'chndx' is invalid, the function will
 *   assert if debug is enabled or do something ignorant otherwise).
 *
 * Assumptions:
@@ -329,11 +392,11 @@ void weak_function stm32_dmainitialize(void)
 *
 ****************************************************************************/

-DMA_HANDLE stm32_dmachannel(int chan)
+DMA_HANDLE stm32_dmachannel(int chndx)
 {
-  struct stm32_dma_s *dmach = &g_dma[chan];
+  struct stm32_dma_s *dmach = &g_dma[chndx];

-  DEBUGASSERT(chan < DMA_NCHANNELS);
+  DEBUGASSERT(chndx < DMA_NCHANNELS);

  /* Get exclusive access to the DMA channel -- OR wait until the channel
   * is available if it is currently being used by another driver
@@ -414,7 +477,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, size_t ntrans
   * half and/or full transfer in the DMA_CCRx register.
   */

-  regval  = dmachan_gettreg(dmach, STM32_DMACHAN_CCR_OFFSET);
+  regval  = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
  regval &= ~(DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
              DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
  ccr    &=  (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
@@ -453,7 +516,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, boole
   * peripheral connected on the channel.
   */

-  ccr  = dmachan_gettreg(dmach, STM32_DMACHAN_CCR_OFFSET);
+  ccr  = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
  ccr |= DMA_CCR_EN;

  /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
@@ -466,3 +529,77 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, boole
  ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
  dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
 }
+
+/****************************************************************************
+ * Name: stm32_dmastop
+ *
+ * Description:
+ *   Cancel the DMA.  After stm32_dmastop() is called, the DMA channel is
+ *   reset and stm32_dmasetup() must be called before stm32_dmastart() can be
+ *   called again
+ *
+ * Assumptions:
+ *   - DMA handle allocated by stm32_dmachannel()
+ *
+ ****************************************************************************/
+
+void stm32_dmastop(DMA_HANDLE handle)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+  stm32_dmachandisable(dmach);
+}
+
+/****************************************************************************
+ * Name: stm32_dmasample
+ *
+ * Description:
+ *   Sample DMA register contents
+ *
+ * Assumptions:
+ *   - DMA handle allocated by stm32_dmachannel()
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+  irqstate_t flags;
+
+  flags       = irqsave();
+  regs->isr   = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET);
+  regs->ccr   = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
+  regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
+  regs->cpar  = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET);
+  regs->cmar  = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET);
+  irqrestore(flags);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_dmadump
+ *
+ * Description:
+ *   Dump previously sampled DMA register contents
+ *
+ * Assumptions:
+ *   - DMA handle allocated by stm32_dmachannel()
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
+                   const char *msg)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+  uint32 dmabase = DMA_BASE(dmach->base);
+
+  dmadbg("DMA Registers: %s\n", msg);
+  dmadbg("   ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
+  dmadbg("    CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
+  dmadbg("  CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
+  dmadbg("   CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
+  dmadbg("   CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
+}
+#endif
+
--- a/arch/arm/src/stm32/stm32_dma.h
+++ b/arch/arm/src/stm32/stm32_dma.h
@@ -229,6 +229,7 @@
 #define DMA_IFCR_CHAN6_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN6_SHIFT)
 #define DMA_IFCR_CHAN7_SHIFT      (24)      /* Bits 27-24:  DMA Channel 7 interrupt flag clear */
 #define DMA_IFCR_CHAN7_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN7_SHIFT)
+#define DMA_IFCR_ALLCHANNELS      (0x0fffffff)

 #define DMA_IFCR_CGIF(n)          (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
 #define DMA_IFCR_CTCIF(n)         (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
@@ -263,6 +264,8 @@
 #define DMA_CCR_TCIE              (1 << 1)  /* Bit 1: Transfer complete interrupt enable */
 #define DMA_CCR_EN                (1 << 0)  /* Bit 0: Channel enable */

+#define DMA_CCR_ALLINTS           (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
+
 /* DMA channel number of data register */

 #define DMA_CNDTR_NDT_SHIFT       (0)       /* Bits 15-0: Number of data to Transfer */
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -203,9 +203,24 @@ int stm32_configgpio(uint32 cfgset)
        }
      else
        {
-          /* It is an input pin... If it is pull-down or pull up,
-           * then we need to set the ODR appropriately for that
-           * function.
+          /* It is an input pin... Should it configured as an EXTI interrupt? */
+
+          if ((cfgset & GPIO_EXTI) != 0)
+            {
+               int shift;
+
+               /* Yes.. Set the bits in the EXTI CR register */
+
+               regaddr = STM32_AFIO_EXTICR(pin);
+               regval  = getreg32(regaddr);
+               shift   = AFIO_EXTICR_EXTI_SHIFT(pin);
+               regval &= ~(AFIO_EXTICR_PORT_MASK << shift);
+               regval |= (((uint32)port) << shift);
+               putreg32(regval, regaddr);
+            }
+
+          /* If it is pull-down or pull up, then we need to set the ODR
+           * appropriately for that function.
           */
        
          if ((cfgset & GPIO_CNF_MASK) == GPIO_CNF_INPULLUP)
--- a/arch/arm/src/stm32/stm32_gpio.h
+++ b/arch/arm/src/stm32/stm32_gpio.h
@@ -62,6 +62,7 @@

 #define STM32_AFIO_EVCR_OFFSET       0x0000  /* Event control register */
 #define STM32_AFIO_MAPR_OFFSET       0x0004  /* AF remap and debug I/O configuration register */
+#define STM32_AFIO_EXTICR_OFFSET(p)  (0x0008 + ((p) >> 2))
 #define STM32_AFIO_EXTICR1_OFFSET    0x0008  /* External interrupt configuration register 1 */
 #define STM32_AFIO_EXTICR2_OFFSET    0x000c  /* External interrupt configuration register 2 */
 #define STM32_AFIO_EXTICR3_OFFSET    0x0010  /* External interrupt configuration register 3 */
@@ -141,6 +142,7 @@

 #define STM32_AFIO_EVCR              (STM32_AFIO_BASE+STM32_AFIO_EVCR_OFFSET)
 #define STM32_AFIO_MAPR              (STM32_AFIO_BASE+STM32_AFIO_MAPR_OFFSET)
+#define STM32_AFIO_EXTICR(p)         (STM32_AFIO_BASE+STM32_AFIO_EXTICR_OFFSET(p))
 #define STM32_AFIO_EXTICR1           (STM32_AFIO_BASE+STM32_AFIO_EXTICR1_OFFSET)
 #define STM32_AFIO_EXTICR2           (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
 #define STM32_AFIO_EXTICR3           (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
@@ -312,53 +314,59 @@

 /* External interrupt configuration register 1 */

+#define AFIO_EXTICR_PORT_MASK        (0x0f)
+#define AFIO_EXTICR_EXTI_SHIFT(g)    (((g) & 3) << 2)
+#define AFIO_EXTICR_EXTI_MASK(g)     (AFIO_EXTICR_PORT_MASK << (AFIO_EXTICR_EXTI_SHIFT(g)))
+
 #define AFIO_EXTICR1_EXTI0_SHIFT     (0)       /* Bits 3-0: EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI0_MASK      (0x0f << AFIO_EXTICR1_EXTI0_SHIFT)
+#define AFIO_EXTICR1_EXTI0_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI0_SHIFT)
 #define AFIO_EXTICR1_EXTI1_SHIFT     (4)       /* Bits 7-4: EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI1_MASK      (0x0f << AFIO_EXTICR1_EXTI1_SHIFT)
+#define AFIO_EXTICR1_EXTI1_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI1_SHIFT)
 #define AFIO_EXTICR1_EXTI2_SHIFT     (8)       /* Bits 11-8: EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI2_MASK      (0x0f << AFIO_EXTICR1_EXTI2_SHIFT)
+#define AFIO_EXTICR1_EXTI2_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI2_SHIFT)
 #define AFIO_EXTICR1_EXTI3_SHIFT     (12)      /* Bits 15-12: EXTI 3 configuration */
-#define AFIO_EXTICR1_EXTI3_MASK      (0x0f << AFIO_EXTICR1_EXTI3_SHIFT)
+#define AFIO_EXTICR1_EXTI3_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI3_SHIFT)

 #define AFIO_EXTICR_PORTA            (0)       /* 0000: PA[x] pin */
 #define AFIO_EXTICR_PORTB            (1)       /* 0001: PB[x] pin */
 #define AFIO_EXTICR_PORTC            (2)       /* 0010: PC[x] pin */
 #define AFIO_EXTICR_PORTD            (3)       /* 0011: PD[x] pin */
 #define AFIO_EXTICR_PORTE            (4)       /* 0100: PE[x] pin */
+#define AFIO_EXTICR_PORTF            (5)       /* 0101: PF[x] pin */
+#define AFIO_EXTICR_PORTG            (6)       /* 0110: PG[x] pin */

 /* External interrupt configuration register 2 */

 #define AFIO_EXTICR2_EXTI4_SHIFT     (0)       /* Bits 3-0: EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI4_MASK      (0x0f << AFIO_EXTICR2_EXTI4_SHIFT)
+#define AFIO_EXTICR2_EXTI4_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI4_SHIFT)
 #define AFIO_EXTICR2_EXTI5_SHIFT     (4)       /* Bits 7-4: EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI5_MASK      (0x0f << AFIO_EXTICR2_EXTI5_SHIFT)
+#define AFIO_EXTICR2_EXTI5_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI5_SHIFT)
 #define AFIO_EXTICR2_EXTI6_SHIFT     (8)       /* Bits 11-8: EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI6_MASK      (0x0f << AFIO_EXTICR2_EXTI6_SHIFT)
+#define AFIO_EXTICR2_EXTI6_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI6_SHIFT)
 #define AFIO_EXTICR2_EXTI7_SHIFT     (12)      /* Bits 15-12: EXTI 7 configuration */
-#define AFIO_EXTICR2_EXTI7_MASK      (0x0f << AFIO_EXTICR2_EXTI7_SHIFT)
+#define AFIO_EXTICR2_EXTI7_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI7_SHIFT)

 /* External interrupt configuration register 3 */

 #define AFIO_EXTICR3_EXTI8_SHIFT     (0)       /* Bits 3-0: EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI8_MASK      (0x0f << AFIO_EXTICR3_EXTI8_SHIFT)
+#define AFIO_EXTICR3_EXTI8_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI8_SHIFT)
 #define AFIO_EXTICR3_EXTI9_SHIFT     (4)       /* Bits 7-4: EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI9_MASK      (0x0f << AFIO_EXTICR3_EXTI9_SHIFT)
+#define AFIO_EXTICR3_EXTI9_MASK      (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI9_SHIFT)
 #define AFIO_EXTICR3_EXTI10_SHIFT    (8)       /* Bits 11-8: EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI10_MASK     (0x0f << AFIO_EXTICR3_EXTI10_SHIFT)
+#define AFIO_EXTICR3_EXTI10_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI10_SHIFT)
 #define AFIO_EXTICR3_EXTI11_SHIFT    (12)      /* Bits 15-12: EXTI 11 configuration */
-#define AFIO_EXTICR3_EXTI11_MASK     (0x0f << AFIO_EXTICR3_EXTI11_SHIFT)
+#define AFIO_EXTICR3_EXTI11_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI11_SHIFT)

 /* External interrupt configuration register 4 */

 #define AFIO_EXTICR4_EXTI12_SHIFT    (0)       /* Bits 3-0: EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI12_MASK     (0x0f << AFIO_EXTICR4_EXTI12_SHIFT)
+#define AFIO_EXTICR4_EXTI12_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI12_SHIFT)
 #define AFIO_EXTICR4_EXTI13_SHIFT    (4)       /* Bits 7-4: EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI13_MASK     (0x0f << AFIO_EXTICR4_EXTI13_SHIFT)
+#define AFIO_EXTICR4_EXTI13_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI13_SHIFT)
 #define AFIO_EXTICR4_EXTI14_SHIFT    (8)       /* Bits 11-8: EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI14_MASK     (0x0f << AFIO_EXTICR4_EXTI14_SHIFT)
+#define AFIO_EXTICR4_EXTI14_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI14_SHIFT)
 #define AFIO_EXTICR4_EXTI15_SHIFT    (12)      /* Bits 15-12: EXTI 15 configuration */
-#define AFIO_EXTICR4_EXTI15_MASK     (0x0f << AFIO_EXTICR4_EXTI15_SHIFT)
+#define AFIO_EXTICR4_EXTI15_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)

 /************************************************************************************
 * Public Types
--- a/arch/arm/src/stm32/stm32_internal.h
+++ b/arch/arm/src/stm32/stm32_internal.h
--- a/arch/arm/src/stm32/stm32_memorymap.h
+++ b/arch/arm/src/stm32/stm32_memorymap.h
@@ -53,6 +53,7 @@
 #define STM32_FLASH_BASE     0x08000000     /* 0x08000000 - Up to 512Kb */
 #define STM32_SRAM_BASE      0x20000000     /* 0x20000000 - 64Kb SRAM */
 #define STM32_SRAMBB_BASE    0x22000000
+#define STM32_PERIPH_BASE    0x40000000

 /* Register Base Address ************************************************************/

@@ -110,7 +111,7 @@
                                            /* 0x40014000 - 0x40017fff: Reserved */
 /* AHB bus */

-#define STM32_SDIO_BASE     0x40020000     /* 0x40018000 - 0x400183ff: SDIO  */
+#define STM32_SDIO_BASE     0x40018000     /* 0x40018000 - 0x400183ff: SDIO  */
                                           /* 0x40018400 - 0x40017fff: Reserved */
 #define STM32_DMA1_BASE     0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
 #define STM32_DMA2_BASE     0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
--- a/arch/arm/src/stm32/stm32_sdio.c
+++ b/arch/arm/src/stm32/stm32_sdio.c
--- a/arch/arm/src/stm32/stm32_sdio.h
+++ b/arch/arm/src/stm32/stm32_sdio.h
@@ -0,0 +1,311 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_sdio.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_SDIO_H
+#define __ARCH_ARM_SRC_STM32_STM32_SDIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+#include "stm32_memorymap.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SDIO_POWER_OFFSET   0x0000 /* SDIO power control register */
+#define STM32_SDIO_CLKCR_OFFSET   0x0004 /* SDI clock control register */
+#define STM32_SDIO_ARG_OFFSET     0x0008 /* SDIO argument register */
+#define STM32_SDIO_CMD_OFFSET     0x000c /* SDIO command register */
+#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */
+#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n))
+#define STM32_SDIO_RESP1_OFFSET   0x0014 /* SDIO response 1 register */
+#define STM32_SDIO_RESP2_OFFSET   0x0018 /* SDIO response 2 register */
+#define STM32_SDIO_RESP3_OFFSET   0x001c /* SDIO response 3 register */
+#define STM32_SDIO_RESP4_OFFSET   0x0020 /* SDIO response 4 register */
+#define STM32_SDIO_DTIMER_OFFSET  0x0024 /* SDIO data timer register */
+#define STM32_SDIO_DLEN_OFFSET    0x0028 /* SDIO data length register */
+#define STM32_SDIO_DCTRL_OFFSET   0x002c /* SDIO data control register */
+#define STM32_SDIO_DCOUNT_OFFSET  0x0030 /* SDIO data counter register */
+#define STM32_SDIO_STA_OFFSET     0x0034 /* SDIO status register */
+#define STM32_SDIO_ICR_OFFSET     0x0038 /* SDIO interrupt clear register */
+#define STM32_SDIO_MASK_OFFSET    0x003c /* SDIO mask register */
+#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */
+#define STM32_SDIO_FIFO_OFFSET    0x0080 /* SDIO data FIFO register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_SDIO_POWER          (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET)
+#define STM32_SDIO_CLKCR          (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET)
+#define STM32_SDIO_ARG            (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET)
+#define STM32_SDIO_CMD            (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET)
+#define STM32_SDIO_RESPCMD        (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET)
+#define STM32_SDIO_RESP(n)        (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n))
+#define STM32_SDIO_RESP1          (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET)
+#define STM32_SDIO_RESP2          (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET)
+#define STM32_SDIO_RESP3          (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET)
+#define STM32_SDIO_RESP4          (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET)
+#define STM32_SDIO_DTIMER         (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET)
+#define STM32_SDIO_DLEN           (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET)
+#define STM32_SDIO_DCTRL          (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET)
+#define STM32_SDIO_DCOUNT         (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET)
+#define STM32_SDIO_STA            (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET)
+#define STM32_SDIO_ICR            (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET)
+#define STM32_SDIO_MASK           (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET)
+#define STM32_SDIO_FIFOCNT        (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET)
+#define STM32_SDIO_FIFO           (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET)
+
+/* Bit-band (BB) base addresses ****************************************************/
+
+#define STM32_SDIO_OFFSET         (STM32_SDIO_BASE-STM32_PERIPH_BASE)
+
+#define STM32_SDIO_POWER_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5))
+#define STM32_SDIO_CLKCR_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5))
+#define STM32_SDIO_ARG_BB         (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5))
+#define STM32_SDIO_CMD_BB         (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5))
+#define STM32_SDIO_RESPCMD_BB     (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5))
+#define STM32_SDIO_RESP_BB(n)     (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5))
+#define STM32_SDIO_RESP1_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5))
+#define STM32_SDIO_RESP2_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5))
+#define STM32_SDIO_RESP3_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5))
+#define STM32_SDIO_RESP4_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5))
+#define STM32_SDIO_DTIMER_BB      (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5))
+#define STM32_SDIO_DLEN_BB        (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5))
+#define STM32_SDIO_DCTRL_BB       (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5))
+#define STM32_SDIO_DCOUNT_BB      (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5))
+#define STM32_SDIO_STA_BB         (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5))
+#define STM32_SDIO_ICR_BB         (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5))
+#define STM32_SDIO_MASK_BB        (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5))
+#define STM32_SDIO_FIFOCNT_BB     (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5))
+#define STM32_SDIO_FIFO_BB        (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5))
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define SDIO_POWER_PWRCTRL_SHIFT       (0)       /* Bits 0-1: Power supply control bits */
+#define SDIO_POWER_PWRCTRL_MASK        (3 << SDIO_POWER_PWRCTRL_SHIFT)
+#  define SDIO_POWER_PWRCTRL_OFF       (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
+#  define SDIO_POWER_PWRCTRL_PWRUP     (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
+#  define SDIO_POWER_PWRCTRL_ON        (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
+
+#define SDIO_POWER_RESET               (0)       /* Reset value */
+
+#define SDIO_CLKCR_CLKDIV_SHIFT        (0)       /* Bits 7-0: Clock divide factor */
+#define SDIO_CLKCR_CLKDIV_MASK         (0xff << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_CLKCR_CLKEN               (1 << 8)  /* Bit 8: Clock enable bit */
+#define SDIO_CLKCR_PWRSAV              (1 << 9)  /* Bit 9: Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS              (1 << 10) /* Bit 10: Clock divider bypass enable bit */
+#define SDIO_CLKCR_WIDBUS_SHIFT        (11)      /* Bits 12-11: Wide bus mode enable bits */
+#define SDIO_CLKCR_WIDBUS_MASK         (3 << SDIO_CLKCR_WIDBUS_SHIFT)
+#  define SDIO_CLKCR_WIDBUS_D1         (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */
+#  define SDIO_CLKCR_WIDBUS_D4         (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */
+#  define SDIO_CLKCR_WIDBUS_D8         (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */
+#define SDIO_CLKCR_NEGEDGE             (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN             (1 << 14) /* Bit 14: HW Flow Control enable */
+
+#define SDIO_CLKCR_RESET               (0)       /* Reset value */
+#define SDIO_ARG_RESET                 (0)       /* Reset value */
+
+#define SDIO_CLKCR_CLKEN_BB            (STM32_SDIO_CLKCR_BB + (8 * 4))
+#define SDIO_CLKCR_PWRSAV_BB           (STM32_SDIO_CLKCR_BB + (9 * 4))
+#define SDIO_CLKCR_BYPASS_BB           (STM32_SDIO_CLKCR_BB + (10 * 4))
+#define SDIO_CLKCR_NEGEDGE_BB          (STM32_SDIO_CLKCR_BB + (13 * 4))
+#define SDIO_CLKCR_HWFC_EN_BB          (STM32_SDIO_CLKCR_BB + (14 * 4))
+
+#define SDIO_CMD_CMDINDEX_SHIFT        (0)
+#define SDIO_CMD_CMDINDEX_MASK         (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
+#define SDIO_CMD_WAITRESP_SHIFT        (6)       /* Bits 7-6: Wait for response bits */
+#define SDIO_CMD_WAITRESP_MASK         (3 << SDIO_CMD_WAITRESP_SHIFT)
+#  define SDIO_CMD_NORESPONSE          (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
+#  define SDIO_CMD_SHORTRESPONSE       (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */
+#  define SDIO_CMD_LONGRESPONSE        (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */
+#define SDIO_CMD_WAITINT               (1 << 8)  /* Bit 8: CPSM waits for interrupt request */
+#define SDIO_CMD_WAITPEND              (1 << 9)  /* Bit 9: CPSM Waits for ends of data transfer */
+#define SDIO_CMD_CPSMEN                (1 << 10) /* Bit 10: Command path state machine enable */
+#define SDIO_CMD_SUSPEND               (1 << 11) /* Bit 11: SD I/O suspend command */
+#define SDIO_CMD_ENDCMD                (1 << 12) /* Bit 12: Enable CMD completion */
+#define SDIO_CMD_NIEN                  (1 << 13) /* Bit 13: not Interrupt Enable */
+#define SDIO_CMD_ATACMD                (1 << 14) /* Bit 14: CE-ATA command */
+
+#define SDIO_CMD_RESET                 (0)       /* Reset value */
+
+#define SDIO_CMD_WAITINT_BB            (STM32_SDIO_CMD_BB + (8 * 4))
+#define SDIO_CMD_WAITPEND_BB           (STM32_SDIO_CMD_BB + (9 * 4))
+#define SDIO_CMD_CPSMEN_BB             (STM32_SDIO_CMD_BB + (10 * 4))
+#define SDIO_CMD_SUSPEND_BB            (STM32_SDIO_CMD_BB + (11 * 4))
+#define SDIO_CMD_ENCMD_BB              (STM32_SDIO_CMD_BB + (12 * 4))
+#define SDIO_CMD_NIEN_BB               (STM32_SDIO_CMD_BB + (13 * 4))
+#define SDIO_CMD_ATACMD_BB             (STM32_SDIO_CMD_BB + (14 * 4))
+
+#define SDIO_RESPCMD_SHIFT             (0)
+#define SDIO_RESPCMD_MASK              (0x3f << SDIO_RESPCMD_SHIFT)
+
+#define SDIO_DTIMER_RESET              (0)       /* Reset value */
+
+#define SDIO_DLEN_SHIFT                (0)
+#define SDIO_DLEN_MASK                 (0x01ffffff << SDIO_DLEN_SHIFT)
+
+#define SDIO_DLEN_RESET                (0)       /* Reset value */
+
+#define SDIO_DCTRL_DTEN                (1 << 0)  /* Bit 0: Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR               (1 << 1)  /* Bit 1: Data transfer direction */
+#define SDIO_DCTRL_DTMODE              (1 << 2)  /* Bit 2: Data transfer mode */
+#define SDIO_DCTRL_DMAEN               (1 << 3)  /* Bit 3: DMA enable bit */
+#define SDIO_DCTRL_DBLOCKSIZE_SHIFT    (4)       /* Bits 7-4: Data block size */
+#define SDIO_DCTRL_DBLOCKSIZE_MASK     (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_1BYTE             (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_2BYTES            (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_4BYTES            (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_8BYTES            (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_16BYTES           (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_32BYTES           (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_64BYTES           (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_128BYTES          (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_256BYTES          (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_512BYTES          (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_1KBYTE            (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_2KBYTES           (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_4KBYTES           (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_8KBYTES           (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#  define SDIO_DCTRL_16KBYTES          (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_RWSTART             (1 << 8)  /* Bit 8: Read wait start */
+#define SDIO_DCTRL_RWSTOP              (1 << 9)  /* Bit 9: Read wait stop */
+#define SDIO_DCTRL_RWMOD               (1 << 10) /* Bit 10: Read wait mode */
+#define SDIO_DCTRL_SDIOEN              (1 << 11) /* Bit 11: SD I/O enable functions */
+
+#define SDIO_DCTRL_RESET               (0)       /* Reset value */
+
+#define SDIO_DCTRL_DTEN_BB             (STM32_SDIO_DCTRL_BB + (0 * 4))
+#define SDIO_DCTRL_DTDIR_BB            (STM32_SDIO_DCTRL_BB + (1 * 4))
+#define SDIO_DCTRL_DTMODE_BB           (STM32_SDIO_DCTRL_BB + (2 * 4))
+#define SDIO_DCTRL_DMAEN_BB            (STM32_SDIO_DCTRL_BB + (3 * 4))
+#define SDIO_DCTRL_RWSTART_BB          (STM32_SDIO_DCTRL_BB + (8 * 4))
+#define SDIO_DCTRL_RWSTOP_BB           (STM32_SDIO_DCTRL_BB + (9 * 4))
+#define SDIO_DCTRL_RWMOD_BB            (STM32_SDIO_DCTRL_BB + (10 * 4))
+#define SDIO_DCTRL_SDIOEN_BB           (STM32_SDIO_DCTRL_BB + (11 * 4))
+
+#define SDIO_DATACOUNT_SHIFT           (0)
+#define SDIO_DATACOUNT_MASK            (0x01ffffff << SDIO_DATACOUNT_SHIFT)
+
+#define SDIO_STA_CCRCFAIL              (1 << 0)  /* Bit 0: Command response CRC fail */
+#define SDIO_STA_DCRCFAIL              (1 << 1)  /* Bit 1: Data block CRC fail */
+#define SDIO_STA_CTIMEOUT              (1 << 2)  /* Bit 2: Command response timeout */
+#define SDIO_STA_DTIMEOUT              (1 << 3)  /* Bit 3: Data timeout */
+#define SDIO_STA_TXUNDERR              (1 << 4)  /* Bit 4: Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR               (1 << 5)  /* Bit 5: Received FIFO overrun error */
+#define SDIO_STA_CMDREND               (1 << 6)  /* Bit 6: Command response received  */
+#define SDIO_STA_CMDSENT               (1 << 7)  /* Bit 7: Command sent  */
+#define SDIO_STA_DATAEND               (1 << 8)  /* Bit 8: Data end */
+#define SDIO_STA_STBITERR              (1 << 9)  /* Bit 9: Start bit not detected  */
+#define SDIO_STA_DBCKEND               (1 << 10) /* Bit 10: Data block sent/received  */
+#define SDIO_STA_CMDACT                (1 << 11) /* Bit 11: Command transfer in progress */
+#define SDIO_STA_TXACT                 (1 << 12) /* Bit 12: Data transmit in progress */
+#define SDIO_STA_RXACT                 (1 << 13) /* Bit 13: Data receive in progress */
+#define SDIO_STA_TXFIFOHE              (1 << 14) /* Bit 14: Transmit FIFO half empty */
+#define SDIO_STA_RXFIFOHF              (1 << 15) /* Bit 15: Receive FIFO half full */
+#define SDIO_STA_TXFIFOF               (1 << 16) /* Bit 16: Transmit FIFO full */
+#define SDIO_STA_RXFIFOF               (1 << 17) /* Bit 17: Receive FIFO full */
+#define SDIO_STA_TXFIFOE               (1 << 18) /* Bit 18: Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE               (1 << 19) /* Bit 19: Receive FIFO empty */
+#define SDIO_STA_TXDAVL                (1 << 20) /* Bit 20: Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL                (1 << 21) /* Bit 21: Data available in receive FIFO */
+#define SDIO_STA_SDIOIT                (1 << 22) /* Bit 22: SDIO interrupt received */
+#define SDIO_STA_CEATAEND              (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
+
+#define SDIO_ICR_CCRCFAILC             (1 << 0)  /* Bit 0: CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC             (1 << 1)  /* Bit 1: DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC             (1 << 2)  /* Bit 2: CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC             (1 << 3)  /* Bit 3: DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC             (1 << 4)  /* Bit 4: TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC              (1 << 5)  /* Bit 5: RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC              (1 << 6)  /* Bit 6: CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC              (1 << 7)  /* Bit 7: CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC              (1 << 8)  /* Bit 8: DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC             (1 << 9)  /* Bit 9: STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC              (1 << 10) /* Bit 10: DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC               (1 << 22) /* Bit 22: SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC             (1 << 23) /* Bit 23: CEATAEND flag clear bit */
+
+#define SDIO_ICR_RESET                 0x00c007ff
+#define SDIO_ICR_STATICFLAGS           0x000005ff
+
+#define SDIO_MASK_CCRCFAILIE           (1 << 0)  /* Bit 0: Command CRC fail interrupt enable */
+#define SDIO_MASK_DCRCFAILIE           (1 << 1)  /* Bit 1: Data CRC fail interrupt enable */
+#define SDIO_MASK_CTIMEOUTIE           (1 << 2)  /* Bit 2: Command timeout interrupt enable */
+#define SDIO_MASK_DTIMEOUTIE           (1 << 3)  /* Bit 3: Data timeout interrupt enable */
+#define SDIO_MASK_TXUNDERRIE           (1 << 4)  /* Bit 4: Tx FIFO underrun error interrupt enable */
+#define SDIO_MASK_RXOVERRIE            (1 << 5)  /* Bit 5: Rx FIFO overrun error interrupt enable */
+#define SDIO_MASK_CMDRENDIE            (1 << 6)  /* Bit 6: Command response received interrupt enable */
+#define SDIO_MASK_CMDSENTIE            (1 << 7)  /* Bit 7: Command sent interrupt enable */
+#define SDIO_MASK_DATAENDIE            (1 << 8)  /* Bit 8: Data end interrupt enable */
+#define SDIO_MASK_STBITERRIE           (1 << 9)  /* Bit 9: Start bit error interrupt enable */
+#define SDIO_MASK_DBCKENDIE            (1 << 10) /* Bit 10: Data block end interrupt enable */
+#define SDIO_MASK_CMDACTIE             (1 << 11) /* Bit 11: Command acting interrupt enable */
+#define SDIO_MASK_TXACTIE              (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
+#define SDIO_MASK_RXACTIE              (1 << 13) /* Bit 13: Data receive acting interrupt enable */
+#define SDIO_MASK_TXFIFOHEIE           (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
+#define SDIO_MASK_RXFIFOHFIE           (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
+#define SDIO_MASK_TXFIFOFIE            (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
+#define SDIO_MASK_RXFIFOFIE            (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
+#define SDIO_MASK_TXFIFOEIE            (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
+#define SDIO_MASK_RXFIFOEIE            (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
+#define SDIO_MASK_TXDAVLIE             (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
+#define SDIO_MASK_RXDAVLIE             (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
+#define SDIO_MASK_SDIOITIE             (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
+#define SDIO_MASK_CEATAENDIE           (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
+
+#define SDIO_MASK_RESET                (0)
+
+#define SDIO_FIFOCNT_SHIFT             (0)
+#define SDIO_FIFOCNT_MASK              (0x01ffffff << SDIO_FIFOCNT_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_SDIO_H */
--- a/arch/arm/src/stm32/stm32_usbdev.c
+++ b/arch/arm/src/stm32/stm32_usbdev.c
@@ -418,6 +418,7 @@ static int    stm32_wrrequest(struct stm32_usbdev_s *priv,
                struct stm32_ep_s *privep);
 static int    stm32_rdrequest(struct stm32_usbdev_s *priv,
                struct stm32_ep_s *privep);
+static void   stm32_cancelrequests(struct stm32_ep_s *privep);

 /* Interrupt level processing ***********************************************/

@@ -698,7 +699,8 @@ static inline uint16 stm32_geteptxaddr(ubyte epno)
 static void stm32_seteprxcount(ubyte epno, uint16 count) 
 {
  volatile uint32 *epaddr = (uint32*)STM32_USB_COUNT_RX(epno);
-  uint16  nblocks;
+  uint32 rxcount = 0;
+  uint16 nblocks;

  /* The upper bits of the RX COUNT value contain the size of allocated
   * RX buffer.  This is based on a block size of 2 or 32:
@@ -724,16 +726,17 @@ static void stm32_seteprxcount(ubyte epno, uint16 count)

      nblocks = (count >> 5) - 1 ;
      DEBUGASSERT(nblocks <= 0x0f);
-      *epaddr = (uint32)((nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE);
+      rxcount = (uint32)((nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT) | USB_COUNT_RX_BL_SIZE);
    }
-  else
+  else if (count > 0)
    {
      /* Blocks of 2 (with 1 meaning one block of 2) */

      nblocks = (count + 1) >> 1;
      DEBUGASSERT(nblocks > 0 && nblocks < 0x1f);
-      *epaddr = (uint32)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT);
+      rxcount = (uint32)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT);
    }
+  *epaddr = rxcount;
 } 

 /****************************************************************************
@@ -1218,7 +1221,7 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
  if (!privreq)
    {
      /* There is no TX transfer in progress and no new pending TX
-       * requests to send... STALL the TX status.
+       * requests to send.
       */

      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0);
@@ -2225,12 +2228,10 @@ static int stm32_lpinterrupt(int irq, void *context)

  if ((istr & USB_ISTR_RESET) != 0)
    {
-      /* Wakeup interrupt received. Clear the WKUP interrupt status. The cause of
-       * the wakeup is indicated in the FNR register
-       */
+      /* Reset interrupt received. Clear the RESET interrupt status. */

      stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR);
-      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), stm32_getreg(STM32_USB_FNR));
+      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr);

      /* Restore our power-up state and exit now because istr is no longer
       * valid.
@@ -2246,10 +2247,12 @@ static int stm32_lpinterrupt(int irq, void *context)

  if ((istr & USB_ISTR_WKUP & priv->imask) != 0)
    {
-      /* Wakeup interrupt received. Clear the WKUP interrupt status. */
+      /* Wakeup interrupt received. Clear the WKUP interrupt status.  The
+       * cause of the resume is indicated in the FNR register
+       */

      stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR);
-      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), 0);
+      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), stm32_getreg(STM32_USB_FNR));

      /* Perform the wakeup action */

@@ -2949,11 +2952,12 @@ static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume)

              /* Restart any queued write requests */

-              if (!stm32_rqempty(privep))
-                {
-                  (void)stm32_wrrequest(priv, privep);
-                  stm32_seteptxstatus(epno, USB_EPR_STATTX_VALID);
-                }
+              priv->txstatus = USB_EPR_STATTX_NAK;
+              (void)stm32_wrrequest(priv, privep);
+
+              /* Set the new TX status */
+
+              stm32_seteptxstatus(epno, priv->txstatus);
            }
        }
      else
@@ -2972,6 +2976,8 @@ static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume)
                {
                  stm32_clrrxdtog(epno);
                }
+
+              priv->rxstatus = USB_EPR_STATRX_VALID;
              stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID);
            }
        }  
@@ -2988,12 +2994,14 @@ static int stm32_epstall(struct usbdev_ep_s *ep, boolean resume)
        {
          /* IN endpoint */ 

+          priv->txstatus = USB_EPR_STATTX_STALL;
          stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL);
        }
      else
        {
          /* OUT endpoint */ 

+          priv->rxstatus = USB_EPR_STATRX_STALL;
          stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL);
        }
    }
@@ -3214,6 +3222,12 @@ static void stm32_reset(struct stm32_usbdev_s *priv)

  stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR);

+  /* Tell the class driver that we are disconnected.  The class driver
+   * should then accept any new configurations.
+   */
+
+  CLASS_DISCONNECT(priv->driver, &priv->usbdev);
+
  /* Reset the device state structure */

  priv->devstate  = DEVSTATE_IDLE;
@@ -3226,7 +3240,13 @@ static void stm32_reset(struct stm32_usbdev_s *priv)
    {
      struct stm32_ep_s *privep = &priv->eplist[epno];

-      /* Cancel any queue requests */
+      /* Cancel any queued requests.  Since they are canceled
+       * with status -ESHUTDOWN, then will not be requeued
+       * until the configuration is reset.  NOTE:  This should
+       * not be necessary... the CLASS_DISCONNECT above should
+       * result in the class implementation calling stm32_epdisable
+       * for each of its configured endpoints.
+       */

      stm32_cancelrequests(privep);

--- a/arch/arm/src/stm32/stm32f103ze_pinmap.h
+++ b/arch/arm/src/stm32/stm32f103ze_pinmap.h
--- a/configs/README.txt
+++ b/configs/README.txt
@@ -243,6 +243,24 @@ defconfig -- This is a configuration file similar to the Linux
 		CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
 		  This format will support execution of NuttX binaries located
 		  in a ROMFS filesystem (see examples/nxflat).
+		CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+		  handle delayed processing from interrupt handlers.  This feature
+		  is required for some drivers but, if there are not complaints,
+		  can be safely disabled.  The worker thread also performs
+		  garbage collection -- completing any delayed memory deallocations
+		  from interrupt handlers.  If the worker thread is disabled,
+		  then that clean will be performed by the IDLE thread instead
+		  (which runs at the lowest of priority and may not be appropriate
+		  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+		  is enabled, then the following options can also be used:
+		CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+		  thread.  Default: 50
+		CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+		  work in units of microseconds.  Default: 50*1000 (50 MS).
+		CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+		  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+		CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+		  the worker thread.  Default: 4

 	The following can be used to disable categories of APIs supported
 	by the OS.  If the compiler supports weak functions, then it
@@ -315,6 +333,14 @@ defconfig -- This is a configuration file similar to the Linux
 		CONFIG_MMCSD_SPICLOCK - Maximum SPI clock to drive MMC/SD card.
 		  Default is 20MHz.

+	SDIO-based MMC/SD driver
+		CONFIG_FS_READAHEAD - Enable read-ahead buffering
+		CONFIG_FS_WRITEBUFFER - Enable write buffering
+		CONFIG_SDIO_DMA - SDIO driver supports DMA
+		CONFIG_MMCSD_MMCSUPPORT - Enable support for MMC cards
+		CONFIG_MMCSD_HAVECARDDETECT - SDIO driver card detection is
+		  100% accurate
+
 	TCP/IP and UDP support via uIP
 		CONFIG_NET - Enable or disable all network features
 		CONFIG_NET_IPv6 - Build in support for IPv6
--- a/configs/mcu123-lpc214x/src/Makefile
+++ b/configs/mcu123-lpc214x/src/Makefile
@@ -51,6 +51,10 @@ CSRCS		= up_spi.c up_leds.c
 ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
 CSRCS		+= up_nsh.c
 endif
+ifeq ($(CONFIG_EXAMPLE),usbstorage)
+CSRCS		+= up_usbstrg.c
+endif
+
 COBJS		= $(CSRCS:.c=$(OBJEXT))

 SRCS		= $(ASRCS) $(CSRCS)
--- a/configs/mcu123-lpc214x/src/up_usbstrg.c
+++ b/configs/mcu123-lpc214x/src/up_usbstrg.c
@@ -1,7 +1,7 @@
 /****************************************************************************
- * examples/usbstorage/usbstrg_lpc214x.c
+ * configs/mcu123-lpc214x/src/up_usbstrg.c
 *
- *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 *
 * Configure and register the LPC214x MMC/SD SPI block driver.
@@ -49,14 +49,16 @@
 #include <nuttx/spi.h>
 #include <nuttx/mmcsd.h>

-#include "usbstrg.h"
-
 /****************************************************************************
 * Pre-Processor Definitions
 ****************************************************************************/

 /* Configuration ************************************************************/

+#ifndef CONFIG_EXAMPLES_USBSTRG_DEVMINOR1
+#  define CONFIG_EXAMPLES_USBSTRG_DEVMINOR1 0
+#endif
+
 /* PORT and SLOT number probably depend on the board configuration */

 #ifdef CONFIG_ARCH_BOARD_MCU123
@@ -69,6 +71,27 @@
 #  error "Unrecognized LPC214x board"
 #endif

+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) lib_lowprintf(__VA_ARGS__)
+#    define msgflush()
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#    define msgflush() fflush(stdout)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message lib_lowprintf
+#    define msgflush()
+#  else
+#    define message printf
+#    define msgflush() fflush(stdout)
+#  endif
+#endif
+
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
--- a/configs/stm3210e-eval/README.txt
+++ b/configs/stm3210e-eval/README.txt
@@ -382,6 +382,12 @@ STM3210E-EVAL-specific Configuration Options
 	CONFIG_STM32_SPI_DMA - Use DMA to improve SPI transfer performance.
 	  Cannot be used with CONFIG_STM32_SPI_INTERRUPT.

+	CONFIG_SDIO_DMA - Support DMA data transfers.  Requires CONFIG_STM32_SDIO
+	  and CONFIG_STM32_DMA2.
+	CONFIG_SDIO_PRI - Select SDIO interrupt prority.  Default: 128
+	CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. 
+	  Default:  Medium
+
 Configurations
 ^^^^^^^^^^^^^^

@@ -412,3 +418,14 @@ Where <subdir> is one of the following:
    This configuration directory exercises the USB serial class
    driver at examples/usbserial.  See examples/README.txt for
    more information.
+
+  usbstorage:
+    This configuration directory exercises the USB mass storage
+    class driver at examples/usbstorage.  See examples/README.txt for
+    more information.
+
+    NOTE: The default usbstorage configuration exports a read-only
+    file system.  That is due to logic in include/nuttx/config.h that
+    is, perhaps, a little too clever and if there is no write-able
+    file systrem in the configuration, it forces read-only block
+    drivers to save space.
--- a/configs/stm3210e-eval/RIDE/defconfig
+++ b/configs/stm3210e-eval/RIDE/defconfig
@@ -60,12 +60,14 @@
 # CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
 # CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
 # CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
 # CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
 #   cause a 100 second delay during boot-up.  This 100 second delay
 #   serves no purpose other than it allows you to calibrate
 #   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
 #   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
 #   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
 #
 CONFIG_ARCH=arm
 CONFIG_ARCH_ARM=y
@@ -83,7 +85,9 @@ CONFIG_ARCH_INTERRUPTSTACK=n
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_BOOTLOADER=n
 CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_BUTTONS=n
 CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=n

 #
 # Identify toolchain
@@ -292,6 +296,24 @@ CONFIG_HAVE_LIBM=n
 # CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
 #  This format will support execution of NuttX binaries located
 #  in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
 #
 CONFIG_EXAMPLE=null
 CONFIG_DEBUG=n
@@ -318,6 +340,11 @@ CONFIG_FDCLONE_DISABLE=n
 CONFIG_FDCLONE_STDIO=n
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_NXFLAT=n
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4

 #
 # The following can be used to disable categories of
@@ -442,6 +469,31 @@ CONFIG_MMCSD_NSLOTS=1
 CONFIG_MMCSD_READONLY=n
 CONFIG_MMCSD_SPICLOCK=12500000

+#
+# Block driver buffering
+#
+# CONFIG_FS_READAHEAD
+#   Enable read-ahead buffering
+# CONFIG_FS_WRITEBUFFER
+#   Enable write buffering
+#
+CONFIG_FS_READAHEAD=n
+CONFIG_FS_WRITEBUFFER=n
+
+#
+# SDIO-based MMC/SD driver
+#
+# CONFIG_SDIO_DMA
+#   SDIO driver supports DMA
+# CONFIG_MMCSD_MMCSUPPORT
+#   Enable support for MMC cards
+# CONFIG_MMCSD_HAVECARDDETECT
+#   SDIO driver card detection is 100% accurate
+#
+CONFIG_SDIO_DMA=n
+CONFIG_MMCSD_MMCSUPPORT=n
+CONFIG_MMCSD_HAVECARDDETECT=n
+
 #
 # TCP/IP and UDP support via uIP
 # CONFIG_NET - Enable or disable all network features
@@ -561,7 +613,6 @@ CONFIG_USBSER_VENDORSTR="Nuttx"
 CONFIG_USBSER_PRODUCTSTR="USBdev Serial"
 CONFIG_USBSER_RXBUFSIZE=512
 CONFIG_USBSER_TXBUFSIZE=512
-CONFIG_NXFLAT=n

 #
 # USB Storage Device Configuration
--- a/configs/stm3210e-eval/include/board.h
+++ b/configs/stm3210e-eval/include/board.h
@@ -41,10 +41,12 @@
 * Included Files
 ************************************************************************************/

+#include <nuttx/config.h>
 #ifndef __ASSEMBLY__
 # include <sys/types.h>
 #endif
 #include "stm32_rcc.h"
+#include "stm32_sdio.h"
 #include "stm32_internal.h"

 /************************************************************************************
@@ -89,6 +91,36 @@

 #define STM32_CFGR_USBPRE      0

+/* SDIO dividers.  Note that slower clocking is required when DMA is disabled 
+ * in order to avoid RX overrun/TX underrun errors due to delayed responses
+ * to service FIFOs in interrupt driven mode.  These values have not been
+ * tuned!!!
+ *
+ * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
+ */
+  
+#define SDIO_INIT_CLKDIV       (178 << SDIO_CLKCR_CLKDIV_SHIFT)
+
+/* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
+ * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_MMCXFR_CLKDIV   (2 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#else
+#  define SDIO_MMCXFR_CLKDIV   (3 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#endif
+
+/* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
+ * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_SDXFR_CLKDIV    (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#else
+#  define SDIO_SDXFR_CLKDIV    (3 << SDIO_CLKCR_CLKDIV_SHIFT)
+#endif
+
 /* LED definitions ******************************************************************/

 /* The STM3210E-EVAL board has 4 LEDs that we will encode as: */
@@ -102,12 +134,51 @@
 #define LED_ASSERTION     6  /* LED1 + LED2 + LED3 */
 #define LED_PANIC         7  /* N/C  + N/C  + N/C + LED4 */

+/* The STM3210E-EVAL supports several buttons
+ *
+ * Reset           -- Connected to NRST
+ * Wakeup          -- Connected to PA.0
+ * Tamper          -- Connected to PC.13
+ * Key             -- Connected to PG.8
+ *
+ * And a Joystick
+ *
+ * Joystick center -- Connected to PG.7
+ * Joystick down   -- Connected to PD.3
+ * Joystick left   -- Connected to PG.14
+ * Joystick right  -- Connected to PG.13
+ * Joystick up     -- Connected to PG.15
+ */
+
+#define BUTTON_WAKEUP  (1 << 0)
+#define BUTTON_TAMPER  (1 << 1)
+#define BUTTON_KEY     (1 << 2)
+
+#define JOYSTICK_SEL   (1 << 3)
+#define JOYSTICK_DOWN  (1 << 4)
+#define JOYSTICK_LEFT  (1 << 5)
+#define JOYSTICK_RIGHT (1 << 6)
+#define JOYSTICK_UP    (1 << 7)
+
+#define NUM_BUTTONS     8
+
 /************************************************************************************
- * Public Function Prototypes
+ * Public Data
 ************************************************************************************/

 #ifndef __ASSEMBLY__

+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
 /************************************************************************************
 * Name: stm32_boardinitialize
 *
@@ -118,7 +189,28 @@
 *
 ************************************************************************************/

-extern void stm32_boardinitialize(void);
+EXTERN void stm32_boardinitialize(void);
+
+/************************************************************************************
+ * Button support.
+ *
+ * Description:
+ *   up_buttoninit() must be called to initialize button resources.  After that,
+ *   up_buttons() may be called to collect the state of all buttons.  up_buttons()
+ *   returns an 8-bit bit set with each bit associated with a button.  See the
+ *   BUTTON_* and JOYSTICK_* definitions above for the meaning of each bit.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_BUTTONS
+EXTERN void up_buttoninit(void);
+EXTERN ubyte up_buttons(void);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif

 #endif /* __ASSEMBLY__ */
 #endif  /* __ARCH_BOARD_BOARD_H */
--- a/configs/stm3210e-eval/nsh/defconfig
+++ b/configs/stm3210e-eval/nsh/defconfig
@@ -60,12 +60,14 @@
 # CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
 # CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
 # CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
 # CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
 #   cause a 100 second delay during boot-up.  This 100 second delay
 #   serves no purpose other than it allows you to calibrate
 #   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
 #   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
 #   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
 #
 CONFIG_ARCH=arm
 CONFIG_ARCH_ARM=y
@@ -83,7 +85,9 @@ CONFIG_ARCH_INTERRUPTSTACK=n
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_BOOTLOADER=n
 CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_BUTTONS=n
 CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=y

 #
 # Identify toolchain and linker options
@@ -99,10 +103,10 @@ CONFIG_STM32_DFU=y
 # Individual subsystems can be enabled:
 # AHB: 
 CONFIG_STM32_DMA1=n
-CONFIG_STM32_DMA2=n
+CONFIG_STM32_DMA2=y
 CONFIG_STM32_CRC=n
 CONFIG_STM32_FSMC=y
-CONFIG_STM32_SDIO=n
+CONFIG_STM32_SDIO=y
 # APB1:
 CONFIG_STM32_TIM2=n
 CONFIG_STM32_TIM3=n
@@ -302,6 +306,24 @@ CONFIG_HAVE_LIBM=n
 # CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
 #  This format will support execution of NuttX binaries located
 #  in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
 #
 CONFIG_EXAMPLE=nsh
 CONFIG_DEBUG=n
@@ -327,6 +349,11 @@ CONFIG_FDCLONE_DISABLE=n
 CONFIG_FDCLONE_STDIO=n
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_NXFLAT=n
+CONFIG_SCHED_WORKQUEUE=y
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4

 #
 # The following can be used to disable categories of
@@ -451,6 +478,31 @@ CONFIG_MMCSD_NSLOTS=1
 CONFIG_MMCSD_READONLY=n
 CONFIG_MMCSD_SPICLOCK=12500000

+#
+# Block driver buffering
+#
+# CONFIG_FS_READAHEAD
+#   Enable read-ahead buffering
+# CONFIG_FS_WRITEBUFFER
+#   Enable write buffering
+#
+CONFIG_FS_READAHEAD=n
+CONFIG_FS_WRITEBUFFER=n
+
+#
+# SDIO-based MMC/SD driver
+#
+# CONFIG_SDIO_DMA
+#   SDIO driver supports DMA
+# CONFIG_MMCSD_MMCSUPPORT
+#   Enable support for MMC cards
+# CONFIG_MMCSD_HAVECARDDETECT
+#   SDIO driver card detection is 100% accurate
+#
+CONFIG_SDIO_DMA=y
+CONFIG_MMCSD_MMCSUPPORT=n
+CONFIG_MMCSD_HAVECARDDETECT=n
+
 #
 # TCP/IP and UDP support via uIP
 # CONFIG_NET - Enable or disable all network features
@@ -570,7 +622,6 @@ CONFIG_USBSER_VENDORSTR="Nuttx"
 CONFIG_USBSER_PRODUCTSTR="USBdev Serial"
 CONFIG_USBSER_RXBUFSIZE=512
 CONFIG_USBSER_TXBUFSIZE=512
-CONFIG_NXFLAT=n

 #
 # USB Storage Device Configuration
--- a/configs/stm3210e-eval/ostest/defconfig
+++ b/configs/stm3210e-eval/ostest/defconfig
@@ -60,12 +60,14 @@
 # CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
 # CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
 # CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
 # CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
 #   cause a 100 second delay during boot-up.  This 100 second delay
 #   serves no purpose other than it allows you to calibrate
 #   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
 #   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
 #   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
 #
 CONFIG_ARCH=arm
 CONFIG_ARCH_ARM=y
@@ -83,7 +85,9 @@ CONFIG_ARCH_INTERRUPTSTACK=n
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_BOOTLOADER=n
 CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_BUTTONS=n
 CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=n

 #
 # Identify toolchain and linker options
@@ -304,6 +308,24 @@ CONFIG_HAVE_LIBM=n
 # CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
 #  This format will support execution of NuttX binaries located
 #  in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
 #
 CONFIG_EXAMPLE=ostest
 CONFIG_DEBUG=n
@@ -329,6 +351,11 @@ CONFIG_FDCLONE_DISABLE=n
 CONFIG_FDCLONE_STDIO=n
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_NXFLAT=n
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4

 #
 # The following can be used to disable categories of
@@ -453,6 +480,31 @@ CONFIG_MMCSD_NSLOTS=1
 CONFIG_MMCSD_READONLY=n
 CONFIG_MMCSD_SPICLOCK=12500000

+#
+# Block driver buffering
+#
+# CONFIG_FS_READAHEAD
+#   Enable read-ahead buffering
+# CONFIG_FS_WRITEBUFFER
+#   Enable write buffering
+#
+CONFIG_FS_READAHEAD=n
+CONFIG_FS_WRITEBUFFER=n
+
+#
+# SDIO-based MMC/SD driver
+#
+# CONFIG_SDIO_DMA
+#   SDIO driver supports DMA
+# CONFIG_MMCSD_MMCSUPPORT
+#   Enable support for MMC cards
+# CONFIG_MMCSD_HAVECARDDETECT
+#   SDIO driver card detection is 100% accurate
+#
+CONFIG_SDIO_DMA=n
+CONFIG_MMCSD_MMCSUPPORT=n
+CONFIG_MMCSD_HAVECARDDETECT=n
+
 #
 # TCP/IP and UDP support via uIP
 # CONFIG_NET - Enable or disable all network features
@@ -572,7 +624,6 @@ CONFIG_USBSER_VENDORSTR="Nuttx"
 CONFIG_USBSER_PRODUCTSTR="USBdev Serial"
 CONFIG_USBSER_RXBUFSIZE=512
 CONFIG_USBSER_TXBUFSIZE=512
-CONFIG_NXFLAT=n

 #
 # USB Storage Device Configuration
--- a/configs/stm3210e-eval/src/Makefile
+++ b/configs/stm3210e-eval/src/Makefile
@@ -39,11 +39,16 @@ CFLAGS		+= -I$(TOPDIR)/sched

 ASRCS		= 
 AOBJS		= $(ASRCS:.S=$(OBJEXT))
-CSRCS		= up_boot.c up_leds.c up_spi.c up_usbdev.c up_extcontext.c \
-		  up_selectnor.c up_deselectnor.c up_selectsram.c up_deselectsram.c
+
+CSRCS		= up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c \
+			  up_extcontext.c up_selectnor.c up_deselectnor.c \
+			  up_selectsram.c up_deselectsram.c
 ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
 CSRCS		+= up_nsh.c
 endif
+ifeq ($(CONFIG_EXAMPLE),usbstorage)
+CSRCS		+= up_usbstrg.c
+endif
 COBJS		= $(CSRCS:.c=$(OBJEXT))

 SRCS		= $(ASRCS) $(CSRCS)
--- a/configs/stm3210e-eval/src/stm3210e-internal.h
+++ b/configs/stm3210e-eval/src/stm3210e-internal.h
@@ -72,7 +72,26 @@
 #define GPIO_LED3       (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
                         GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN8)
 #define GPIO_LED4       (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
-                         GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN9)
+                         GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN9)
+
+/* BUTTONS -- NOTE that some have EXTI interrupts configured */
+
+#define GPIO_BTN_WAKEUP (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_PORTA|GPIO_PIN0)
+#define GPIO_BTN_TAMPER (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_PORTA|GPIO_PIN0)
+#define GPIO_BTN_KEY    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_EXTI|GPIO_PORTG|GPIO_PIN8)
+#define GPIO_JOY_KEY    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_EXTI|GPIO_PORTG|GPIO_PIN7)
+#define GPIO_JOY_DOWN   (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_EXTI|GPIO_PORTD|GPIO_PIN3)
+#define GPIO_JOY_LEFT   (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_EXTI|GPIO_PORTG|GPIO_PIN14)
+#define GPIO_JOY_RIGHT  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_EXTI|GPIO_PORTG|GPIO_PIN13)
+#define GPIO_JOY_UP     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\
+                         GPIO_EXTI|GPIO_PORTG|GPIO_PIN15)

 /* SPI FLASH chip select:  PA.4 */

--- a/configs/stm3210e-eval/src/up_boot.c
+++ b/configs/stm3210e-eval/src/up_boot.c
@@ -71,18 +71,7 @@
 ************************************************************************************/

 void stm32_boardinitialize(void)
-{
-  /* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
-   * brought into the build
-   */
-
-#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
-  if (stm32_dmainitialize)
-    {
-      stm32_dmainitialize();
-    }
-#endif
-
+{
  /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
   * stm32_spiinitialize() has been brought into the link.
   */
@@ -93,18 +82,18 @@ void stm32_boardinitialize(void)
      stm32_spiinitialize();
    }
 #endif
-
-   /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not
-    * disabled, and 3) the weak function stm32_usbinitialize() has been brought
-    * into the build.
-    */
-
-#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
+
+   /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not
+    * disabled, and 3) the weak function stm32_usbinitialize() has been brought
+    * into the build.
+    */
+
+#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
  if (stm32_usbinitialize)
    {
      stm32_usbinitialize();
    }
-#endif
+#endif

  /* Configure on-board LEDs if LED support has been selected. */

--- a/configs/stm3210e-eval/src/up_buttons.c
+++ b/configs/stm3210e-eval/src/up_buttons.c
@@ -0,0 +1,112 @@
+/****************************************************************************
+ * configs/stm3210e-eval/src/up_leds.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <arch/board/board.h>
+#include "stm3210e-internal.h"
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const uint16 g_buttons[NUM_BUTTONS] =
+{
+  GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_KEY,   GPIO_JOY_KEY,
+  GPIO_JOY_DOWN,   GPIO_JOY_LEFT,   GPIO_JOY_RIGHT, GPIO_JOY_UP
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_buttoninit
+ ****************************************************************************/
+
+void up_buttoninit(void)
+{
+  int i;
+
+  /* Configure the GPIO pins as inputs.  NOTE that EXTI interrupts are 
+   * configured for some pins but NOT used in this file
+   */
+
+  for (i = 0; i < NUM_BUTTONS; i++)
+    {
+      stm32_configgpio(g_buttons[i]);
+    }
+}
+
+/****************************************************************************
+ * Name: up_buttons
+ ****************************************************************************/
+
+ubyte up_buttons(void)
+{
+  ubyte ret = 0;
+  int i;
+
+  /* Check that state of each key */
+
+  for (i = 0; i < NUM_BUTTONS; i++)
+    {
+       /* A LOW value means that the key is pressed */
+
+       if (!stm32_gpioread(g_buttons[i]))
+         {
+           ret |= (1 << i);
+         }
+    }
+
+  return ret;
+}
+
+#endif /* CONFIG_ARCH_BUTTONS */
--- a/configs/stm3210e-eval/src/up_nsh.c
+++ b/configs/stm3210e-eval/src/up_nsh.c
@@ -49,7 +49,13 @@
 #  include <nuttx/spi.h>
 #  include <nuttx/mtd.h>
 #endif
-#include <nuttx/mmcsd.h>
+
+#ifdef CONFIG_STM32_SDIO
+#  include <nuttx/sdio.h>
+#  include <nuttx/mmcsd.h>
+#endif
+
+#include "stm32_internal.h"

 /****************************************************************************
 * Pre-Processor Definitions
@@ -63,20 +69,34 @@

 /* PORT and SLOT number probably depend on the board configuration */

+#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL
+#  define CONFIG_EXAMPLES_NSH_HAVEUSBDEV 1
+#  define CONFIG_EXAMPLES_NSH_HAVEMMCSD  1
+#  if defined(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO) && CONFIG_EXAMPLES_NSH_MMCSDSLOTNO != 0
+#    error "Only one MMC/SD slot"
+#    undef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
+#  endif
+#  ifndef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
+#    define CONFIG_EXAMPLES_NSH_MMCSDSLOTNO 0
+#  endif
+#else
+   /* Add configuration for new STM32 boards here */
+#  error "Unrecognized STM32 board"
+#  undef CONFIG_EXAMPLES_NSH_HAVEUSBDEV
+#  undef CONFIG_EXAMPLES_NSH_HAVEMMCSD
+#endif
+
 /* Can't support USB features if USB is not enabled */

 #ifndef CONFIG_USBDEV
 #  undef CONFIG_EXAMPLES_NSH_HAVEUSBDEV
 #endif

-#if defined(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO) && CONFIG_EXAMPLES_NSH_MMCSDSLOTNO != 0
-#  error "Only one MMC/SD slot"
-#  undef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
-#endif
+/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support
+ * is not enabled.
+ */

-/* Can't support MMC/SD features if mountpoints are disabled */
-
-#if defined(CONFIG_DISABLE_MOUNTPOINT)
+#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO)
 #  undef CONFIG_EXAMPLES_NSH_HAVEMMCSD
 #endif

@@ -118,6 +138,10 @@ int nsh_archinitialize(void)
  FAR struct spi_dev_s *spi;
  FAR struct mtd_dev_s *mtd;
 #endif
+#ifdef CONFIG_EXAMPLES_NSH_HAVEMMCSD
+  FAR struct sdio_dev_s *sdio;
+  int ret;
+#endif

  /* Configure SPI-based devices */

@@ -147,13 +171,43 @@ int nsh_archinitialize(void)
 #endif

  /* Create the SPI FLASH MTD instance */
-
-  /* Here we will eventually need to
-   * 1. Get the SDIO interface instance, and 
-   * 2. Bind it to the MMC/SD driver (slot CONFIG_EXAMPLES_NSH_MMCSDSLOTNO,
-   *    CONFIG_EXAMPLES_NSH_MMCSDMINOR).
+  /* The M25Pxx is not a give media to implement a file system..
+   * its block sizes are too large
   */

-#warning "Missing MMC/SD device configuration"
+  /* Mount the SDIO-based MMC/SD block driver */
+
+#ifdef CONFIG_EXAMPLES_NSH_HAVEMMCSD
+  /* First, get an instance of the SDIO interface */
+
+  message("nsh_archinitialize: Initializing SDIO slot %d\n",
+          CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
+  sdio = sdio_initialize(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
+  if (!sdio)
+    {
+      message("nsh_archinitialize: Failed to initialize SDIO slot %d\n",
+              CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
+      return -ENODEV;
+    }
+
+  /* Now bind the SPI interface to the MMC/SD driver */
+
+  message("nsh_archinitialize: Bind SDIO to the MMC/SD driver, minor=%d\n",
+          CONFIG_EXAMPLES_NSH_MMCSDMINOR);
+  ret = mmcsd_slotinitialize(CONFIG_EXAMPLES_NSH_MMCSDMINOR, sdio);
+  if (ret != OK)
+    {
+      message("nsh_archinitialize: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
+      return ret;
+    }
+  message("nsh_archinitialize: Successfully bound SDIO to the MMC/SD driver\n");
+  
+  /* Then let's guess and say that there is a card in the slot.  I need to check to
+   * see if the STM3210E-EVAL board supports a GPIO to detect if there is a card in
+   * the slot.
+   */
+
+   sdio_mediachange(sdio, TRUE);
+#endif
  return OK;
 }
--- a/configs/stm3210e-eval/src/up_usbstrg.c
+++ b/configs/stm3210e-eval/src/up_usbstrg.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * configs/stm3210e-eval/src/up_usbstrg.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Configure and register the STM32 MMC/SD SDIO block driver.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/sdio.h>
+#include <nuttx/mmcsd.h>
+
+#include "stm32_internal.h"
+
+#ifdef CONFIG_STM32_SDIO
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_EXAMPLES_USBSTRG_DEVMINOR1
+#  define CONFIG_EXAMPLES_USBSTRG_DEVMINOR1 0
+#endif
+
+/* SLOT number(s) could depend on the board configuration */
+
+#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL
+#  undef STM32_MMCSDSLOTNO
+#  define STM32_MMCSDSLOTNO 0
+#else
+   /* Add configuration for new STM32 boards here */
+#  error "Unrecognized STM32 board"
+#endif
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) lib_lowprintf(__VA_ARGS__)
+#    define msgflush()
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#    define msgflush() fflush(stdout)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message lib_lowprintf
+#    define msgflush()
+#  else
+#    define message printf
+#    define msgflush() fflush(stdout)
+#  endif
+#endif
+
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: usbstrg_archinitialize
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+int usbstrg_archinitialize(void)
+{
+  FAR struct sdio_dev_s *sdio;
+  int ret;
+
+  /* First, get an instance of the SDIO interface */
+
+  message("usbstrg_archinitialize: "
+          "Initializing SDIO slot %d\n",
+          STM32_MMCSDSLOTNO);
+
+  sdio = sdio_initialize(STM32_MMCSDSLOTNO);
+  if (!sdio)
+    {
+      message("usbstrg_archinitialize: Failed to initialize SDIO slot %d\n",
+              STM32_MMCSDSLOTNO);
+      return -ENODEV;
+    }
+
+  /* Now bind the SPI interface to the MMC/SD driver */
+
+  message("usbstrg_archinitialize: "
+          "Bind SDIO to the MMC/SD driver, minor=%d\n",
+          CONFIG_EXAMPLES_USBSTRG_DEVMINOR1);
+
+  ret = mmcsd_slotinitialize(CONFIG_EXAMPLES_USBSTRG_DEVMINOR1, sdio);
+  if (ret != OK)
+    {
+      message("usbstrg_archinitialize: "
+              "Failed to bind SDIO to the MMC/SD driver: %d\n",
+              ret);
+      return ret;
+    }
+  message("usbstrg_archinitialize: "
+          "Successfully bound SDIO to the MMC/SD driver\n");
+  
+  /* Then let's guess and say that there is a card in the slot.  I need to check to
+   * see if the STM3210E-EVAL board supports a GPIO to detect if there is a card in
+   * the slot.
+   */
+
+   sdio_mediachange(sdio, TRUE);
+   return OK;
+}
+
+#endif /* CONFIG_STM32_SDIO */
--- a/configs/stm3210e-eval/usbserial/defconfig
+++ b/configs/stm3210e-eval/usbserial/defconfig
@@ -60,12 +60,14 @@
 # CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
 # CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
 # CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
 # CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
 #   cause a 100 second delay during boot-up.  This 100 second delay
 #   serves no purpose other than it allows you to calibrate
 #   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
 #   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
 #   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
 #
 CONFIG_ARCH=arm
 CONFIG_ARCH_ARM=y
@@ -83,7 +85,9 @@ CONFIG_ARCH_INTERRUPTSTACK=n
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH_BOOTLOADER=n
 CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_BUTTONS=n
 CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=n

 #
 # Identify toolchain and linker options
@@ -304,6 +308,24 @@ CONFIG_HAVE_LIBM=n
 # CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
 #  This format will support execution of NuttX binaries located
 #  in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
 #
 CONFIG_EXAMPLE=usbserial
 CONFIG_DEBUG=n
@@ -330,6 +352,11 @@ CONFIG_FDCLONE_DISABLE=n
 CONFIG_FDCLONE_STDIO=n
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_NXFLAT=n
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4

 #
 # The following can be used to disable categories of
@@ -454,6 +481,31 @@ CONFIG_MMCSD_NSLOTS=1
 CONFIG_MMCSD_READONLY=n
 CONFIG_MMCSD_SPICLOCK=12500000

+#
+# Block driver buffering
+#
+# CONFIG_FS_READAHEAD
+#   Enable read-ahead buffering
+# CONFIG_FS_WRITEBUFFER
+#   Enable write buffering
+#
+CONFIG_FS_READAHEAD=n
+CONFIG_FS_WRITEBUFFER=n
+
+#
+# SDIO-based MMC/SD driver
+#
+# CONFIG_SDIO_DMA
+#   SDIO driver supports DMA
+# CONFIG_MMCSD_MMCSUPPORT
+#   Enable support for MMC cards
+# CONFIG_MMCSD_HAVECARDDETECT
+#   SDIO driver card detection is 100% accurate
+#
+CONFIG_SDIO_DMA=n
+CONFIG_MMCSD_MMCSUPPORT=n
+CONFIG_MMCSD_HAVECARDDETECT=n
+
 #
 # TCP/IP and UDP support via uIP
 # CONFIG_NET - Enable or disable all network features
@@ -573,7 +625,6 @@ CONFIG_USBSER_VENDORSTR="Nuttx"
 CONFIG_USBSER_PRODUCTSTR="USBdev Serial"
 CONFIG_USBSER_RXBUFSIZE=512
 CONFIG_USBSER_TXBUFSIZE=512
-CONFIG_NXFLAT=n

 #
 # USB Storage Device Configuration
--- a/configs/stm3210e-eval/usbstorage/Make.defs
+++ b/configs/stm3210e-eval/usbstorage/Make.defs
@@ -0,0 +1,174 @@
+############################################################################
+# configs/stm3210e-eval/usbstorage/Make.defs
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+
+# Setup for the selected toolchain
+
+ifeq ($(CONFIG_STM32_DFU),y)
+  LDSCRIPT = ld.script.dfu
+else
+  LDSCRIPT = ld.script
+endif
+
+ifeq ($(CONFIG_STM32_CODESOURCERYW),y)
+  # CodeSourcery under Windows
+  CROSSDEV = arm-none-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_CODESOURCERYL),y)
+  # CodeSourcery under Linux
+  CROSSDEV = arm-none-eabi-
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  MAXOPTIMIZATION = -O2
+endif
+ifeq ($(CONFIG_STM32_DEVKITARM),y)
+  # devkitARM under Windows
+  CROSSDEV = arm-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_RAISONANCE),y)
+  # Raisonance RIDE7 under Windows
+  CROSSDEV = arm-none-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_BUILDROOT),y)
+  # NuttX buildroot under Linux or Cygwin
+  CROSSDEV = arm-elf-
+  ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+  MAXOPTIMIZATION = -Os
+endif
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/winlink.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/usbstorage/$(LDSCRIPT)}"
+  MAXOPTIMIZATION = -O2
+else
+  # Linux/Cygwin-native toolchain 
+  MKDEP = $(TOPDIR)/tools/mkdeps.sh
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/usbstorage/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+  ARCHOPTIMIZATION = -g
+else
+  ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
+ARCHWARNINGSXX = -Wall -Wshadow
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+define PREPROCESS
+	@echo "CPP: $1->$2"
+	@$(CPP) $(CPPFLAGS) $1 -o $2
+endef
+
+define COMPILE
+	@echo "CC: $1"
+	@$(CC) -c $(CFLAGS) $1 -o $2
+endef
+
+define COMPILEXX
+	@echo "CXX: $1"
+	@$(CXX) -c $(CXXFLAGS) $1 -o $2
+endef
+
+define ASSEMBLE
+	@echo "AS: $1"
+	@$(CC) -c $(AFLAGS) $1 -o $2
+endef
+
+define ARCHIVE
+	echo "AR: $2"; \
+	$(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; }
+endef
+
+define CLEAN
+	@rm -f *.o *.a
+endef
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS =
+
--- a/configs/stm3210e-eval/usbstorage/defconfig
+++ b/configs/stm3210e-eval/usbstorage/defconfig
--- a/configs/stm3210e-eval/usbstorage/ld.script
+++ b/configs/stm3210e-eval/usbstorage/ld.script
@@ -0,0 +1,111 @@
+/****************************************************************************
+ * configs/stm3210e-eval/usbstorage/ld.script
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and
+ * 64Kb of SRAM beginning at address 0x2000:0000.  When booting from FLASH,
+ * FLASH memory is aliased to address 0x0000:0000 where the code expects to
+ * begin execution by jumping to the entry point in the 0x0800:0000 address
+ * range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)        
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)        
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	_eronly = ABSOLUTE(.);		/* See below                    */
+
+	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >sram
+
+	.ARM.exidx : {
+		__exidx_start = ABSOLUTE(.);
+		*(.ARM.exidx*)
+		__exidx_end = ABSOLUTE(.);
+	} >sram
+
+	.bss : {			/* BSS				*/
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+					/* Stabs debugging sections.	*/
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
--- a/configs/stm3210e-eval/usbstorage/ld.script.dfu
+++ b/configs/stm3210e-eval/usbstorage/ld.script.dfu
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * configs/stm3210e-eval/usbstorage/ld.script.dfu
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and
+ * 64Kb of SRAM beginning at address 0x2000:0000.  Here we assume that the
+ * STM3210E-EVAL's DFU bootloader is being used.  In that case, the corrct
+ * load .text load address is 0x08003000 (leaving 464Kb).
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08003000, LENGTH = 464K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)        
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)        
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	_eronly = ABSOLUTE(.);		/* See below                    */
+
+	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >sram
+
+	.ARM.exidx : {
+		__exidx_start = ABSOLUTE(.);
+		*(.ARM.exidx*)
+		__exidx_end = ABSOLUTE(.);
+	} >sram
+
+	.bss : {			/* BSS				*/
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+					/* Stabs debugging sections.	*/
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
--- a/configs/stm3210e-eval/usbstorage/setenv.sh
+++ b/configs/stm3210e-eval/usbstorage/setenv.sh
@@ -0,0 +1,47 @@
+#!/bin/bash
+# configs/stm3210e-eval/dfu/setenv.sh
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$(basename $0)" = "setenv.sh" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi
+
+WD=`pwd`
+export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin"
+export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
--- a/configs/xtrs/README.txt
+++ b/configs/xtrs/README.txt
@@ -98,3 +98,29 @@ Then make the SDCC binaries
 and install SDCC:

  sudo make install
+
+SDCC Update
+^^^^^^^^^^^
+
+I have had some problems building sdcc-2.6.0 on my current UBUNTU
+release (9.10).  I had other problems building sdcc-2.9.0 on UBUNTU 9.10.
+I suspect that the newer gcc toolchains are causing problems for these
+older SDCC releases.
+
+A 20091106 snapshot did build with no major problems on UBUNTU 9.10, but
+has some compatibilty problems with the older SDCC compiler.  For one, you
+will need to change the Z80 assember name and options in the Make.defs
+files as follows:
+
+-AS			= as-z80
+AS			= sdasz80
+ 
+-	@$(AS) $(ASFLAGS) $2 $1
+	$(AS) $(ASFLAGS) $1
+
+For another, I had other problems building with that 20091106 that look
+like compiler bugs.  If you are using UBUNTU 9.10, you may have to either
+(1) downgrade your GCC compiler to a version 3.x compiler and use one of
+the older stable releases, or (2) wait for the next stable SDCC release
+after 2.9.0.
+
--- a/configs/z80sim/README.txt
+++ b/configs/z80sim/README.txt
@@ -73,3 +73,32 @@ Then make the SDCC binaries
 and install SDCC:

  sudo make install
+
+SDCC Update
+^^^^^^^^^^^
+
+I have had some problems building sdcc-2.6.0 on my current UBUNTU
+release (9.10).  I had other problems building sdcc-2.9.0 on UBUNTU 9.10.
+I suspect that the newer gcc toolchains are causing problems for these
+older SDCC releases.
+
+A 20091106 snapshot did build with no major problems on UBUNTU 9.10, but
+has some compatibilty problems with the older SDCC compiler.  For one, you
+will need to change the Z80 assember name and options in the Make.defs
+files as follows:
+
+-AS			= as-z80
+AS			= sdasz80
+ 
+-	@$(AS) $(ASFLAGS) $2 $1
+	$(AS) $(ASFLAGS) $1
+
+For another, I had other problems building with that 20091106 that look
+like compiler bugs.  If you are using UBUNTU 9.10, you may have to either
+(1) downgrade your GCC compiler to a version 3.x compiler and use one of
+the older stable releases, or (2) wait for the next stable SDCC release
+after 2.9.0.
+
+
+ 
+
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -90,7 +90,7 @@ CSRCS		=
 ifneq ($(CONFIG_NFILE_DESCRIPTORS),0)
 CSRCS		+= dev_null.c dev_zero.c loop.c  can.c
 ifneq ($(CONFIG_DISABLE_MOUNTPOINT),y)
-CSRCS		+= ramdisk.c
+CSRCS		+= ramdisk.c rwbuffer.c
 endif
 endif
 CSRCS		+= $(SERIAL_CSRCS) $(NET_CSRCS) $(PIPE_CSRCS) $(USBDEV_CSRCS) \
--- a/drivers/bch/bchdev_driver.c
+++ b/drivers/bch/bchdev_driver.c
@@ -137,7 +137,7 @@ static int bch_close(FAR struct file *filp)
 {
  FAR struct inode *inode = filp->f_inode;
  FAR struct bchlib_s *bch;
-  int ret;
+  int ret = OK;

  DEBUGASSERT(inode && inode->i_private);
  bch = (FAR struct bchlib_s *)inode->i_private;
--- a/drivers/bch/bchdev_unregister.c
+++ b/drivers/bch/bchdev_unregister.c
@@ -1,7 +1,7 @@
 /****************************************************************************
 * drivers/bch/bchdev_unregister.c
 *
- *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -105,10 +105,10 @@ int bchdev_unregister(const char *chardev)
  /* Open the character driver associated with chardev */

  fd = open(chardev, O_RDONLY);
-  if (ret < 0)
+  if (fd < 0)
    {
-      dbg("Failed to open %s: %d\n", chardev, -ret);
-      return ret;
+      dbg("Failed to open %s: %d\n", chardev, errno);
+      return -errno;
    }

  /* Get a reference to the internal data structure.  On success, we
--- a/drivers/mmcsd/Make.defs
+++ b/drivers/mmcsd/Make.defs
@@ -34,5 +34,5 @@
 ############################################################################

 MMCSD_ASRCS  =
-MMCSD_CSRCS  = mmcsd_spi.c mmcsd_debug.c
+MMCSD_CSRCS  = mmcsd_sdio.c mmcsd_spi.c mmcsd_debug.c

--- a/drivers/mmcsd/mmcsd_internal.h
+++ b/drivers/mmcsd/mmcsd_internal.h
@@ -61,11 +61,12 @@
 #define MMCSD_CARDTYPE_UNKNOWN       0  /* Unknown card type */
 #define MMCSD_CARDTYPE_MMC           1  /* Bit 0: MMC card */
 #define MMCSD_CARDTYPE_SDV1          2  /* Bit 1: SD version 1.x */
-#define MMCSD_CARDTYPE_SDV2          4  /* Bit 1: SD version 2.x with byte addressing */
-#define MMCSD_CARDTYPE_BLOCK         8  /* Bit 2: SD version 2.x with block addressing */
+#define MMCSD_CARDTYPE_SDV2          4  /* Bit 2: SD version 2.x with byte addressing */
+#define MMCSD_CARDTYPE_BLOCK         8  /* Bit 3: SD version 2.x with block addressing */

 #define IS_MMC(t)   (((t) & MMCSD_CARDTYPE_MMC) != 0)
 #define IS_SD(t)    (((t) & (MMCSD_CARDTYPE_SDV1|MMCSD_CARDTYPE_SDV2)) != 0)
+#define IS_SDV1(t)  (((t) & MMCSD_CARDTYPE_SDV1) != 0)
 #define IS_SDV2(t)  (((t) & MMCSD_CARDTYPE_SDV2) != 0)
 #define IS_BLOCK(t) (((t) & MMCSD_CARDTYPE_BLOCK) != 0)

--- a/drivers/mmcsd/mmcsd_sdio.c
+++ b/drivers/mmcsd/mmcsd_sdio.c
--- a/drivers/mmcsd/mmcsd_sdio.h
+++ b/drivers/mmcsd/mmcsd_sdio.h
@@ -0,0 +1,338 @@
+/********************************************************************************************
+ * drivers/mmcsd/mmcsd_sdio.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __DRIVERS_MMCSD_MMCSD_SDIO_H
+#define __DRIVERS_MMCSD_MMCSD_SDIO_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+/********************************************************************************************
+ * Pre-Processor Definitions
+ ********************************************************************************************/
+
+/* CMD8 Argument:
+ *    [31:12]: Reserved (shall be set to '0')
+ *    [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+ *    [7:0]: Check Pattern (recommended 0xaa)
+ * CMD8 Response: R7
+ */
+
+#define MMCSD_CMD8VOLTAGE_SHIFT     8          /* Bits 8-11: Supply voltage */
+#define MMCSD_CMD8VOLTAGE_MASK      (0x0f << MMCSD_CMD8VOLTAGE_SHIFT)
+#  define MMCSD_CMD8VOLTAGE_27      (0x01 << MMCSD_CMD8VOLTAGE_SHIFT) /* 2.7-3.6V */
+#define MMCSD_CMD8ECHO_SHIFT        0          /* Bits 0-7: Check pattern */
+#define MMCSD_CMD8ECHO_MASK         (0xff << MMCSD_CMD8ECHO_SHIFT)
+#  define MMCSD_CMD8CHECKPATTERN    (0xaa << MMCSD_CMD8ECHO_SHIFT)
+
+/* ACMD6 argument */
+
+#define MMCSD_ACMD6_BUSWIDTH_1       (0)       /* Bus width = 1-bit */
+#define MMCSD_ACMD6_BUSWIDTH_4       (2)       /* Bus width = 4-bit */
+
+/* ACMD41 argument */
+
+#define MMCSD_ACMD41_VOLTAGEWINDOW   0x80100000
+#define MMCSD_ACMD41_HIGHCAPACITY    (1 << 30)
+#define MMCSD_ACMD41_STDCAPACITY     (0)
+
+/* ACMD42 argument */
+
+#define MMCSD_ACMD42_CD_DISCONNECT   (0)  /* Disconnect card detection logic */
+#define MMCSD_ACMD42_CD_CONNECT      (1)  /* Connect card detection logic */
+
+/* R1 Card Status bit definitions */
+
+#define MMCSD_R1_OUTOFRANGE         (1 << 31)  /* Bad argument */
+#define MMCSD_R1_ADDRESSERROR       (1 << 30)  /* Bad address */
+#define MMCSD_R1_BLOCKLENERROR      (1 << 29)  /* Bad block length */
+#define MMCSD_R1_ERASESEQERROR      (1 << 28)  /* Erase cmd error */
+#define MMCSD_R1_ERASEPARAM         (1 << 27)  /* Bad write blocks */
+#define MMCSD_R1_WPVIOLATION        (1 << 26)  /* Erase access failure */
+#define MMCSD_R1_CARDISLOCKED       (1 << 25)  /* Card is locked */
+#define MMCSD_R1_LOCKUNLOCKFAILED   (1 << 24)  /* Password error */
+#define MMCSD_R1_COMCRCERROR        (1 << 23)  /* CRC error */
+#define MMCSD_R1_ILLEGALCOMMAND     (1 << 22)  /* Bad command */
+#define MMCSD_R1_CARDECCFAILED      (1 << 21)  /* Failed to correct data */
+#define MMCSD_R1_CCERROR            (1 << 20)  /* Card controller error */
+#define MMCSD_R1_ERROR              (1 << 19)  /* General error */
+#define MMCSD_R1_UNDERRUN           (1 << 18)  /* Underrun (MMC only) */
+#define MMCSD_R1_OVERRRUN           (1 << 17)  /* Overrun (MMC only) */
+#define MMCSD_R1_CIDCSDOVERWRITE    (1 << 16)  /* CID/CSD error */
+#define MMCSD_R1_WPERASESKIP        (1 << 15)  /* Not all erased */
+#define MMCSD_R1_CARDECCDISABLED    (1 << 14)  /* Internal ECC not used */
+#define MMCSD_R1_ERASERESET         (1 << 13)  /* Reset sequence cleared */
+#define MMCSD_R1_STATE_SHIFT        (9)        /* Current card state */
+#define MMCSD_R1_STATE_MASK         (15 << MMCSD_R1_STATE_SHIFT)
+                                                                /* Card identification mode states */
+#  define MMCSD_R1_STATE_IDLE       (0 << MMCSD_R1_STATE_SHIFT) /* 0=Idle state */
+#  define MMCSD_R1_STATE_READY      (1 << MMCSD_R1_STATE_SHIFT) /* 1=Ready state */
+#  define MMCSD_R1_STATE_IDENT      (2 << MMCSD_R1_STATE_SHIFT) /* 2=Identification state */
+                                                                /* Data transfer states */
+#  define MMCSD_R1_STATE_STBY       (3 << MMCSD_R1_STATE_SHIFT) /* 3=Standby state */
+#  define MMCSD_R1_STATE_TRAN       (4 << MMCSD_R1_STATE_SHIFT) /* 4=Transfer state */
+#  define MMCSD_R1_STATE_DATA       (5 << MMCSD_R1_STATE_SHIFT) /* 5=Sending data state */
+#  define MMCSD_R1_STATE_RCV        (6 << MMCSD_R1_STATE_SHIFT) /* 6=Receiving data state */
+#  define MMCSD_R1_STATE_PRG        (7 << MMCSD_R1_STATE_SHIFT) /* 7=Programming state */
+#  define MMCSD_R1_STATE_DIS        (8 << MMCSD_R1_STATE_SHIFT) /* 8=Disconnect state */
+#define MMCSD_R1_READYFORDATA       (1 << 8)   /* Buffer empty */
+#define MMCSD_R1_APPCMD             (1 << 5)   /* Next CMD is ACMD */
+#define MMCSD_R1_AKESEQERROR        (1 << 3)   /* Authentication error */
+#define MMCSD_R1_ERRORMASK          0xfdffe008 /* Error mask */
+
+#define IS_STATE(v,s)               (((v)&MMCSD_R1_STATE_MASK)==(s))
+
+/* R3 (OCR) */
+
+#define MMC_VDD_20_36               0x00ffff00 /* VDD voltage 2.0-3.6 */
+
+#define MMCSD_VDD_145_150           (1 << 0)   /* VDD voltage 1.45 - 1.50 */
+#define MMCSD_VDD_150_155           (1 << 1)   /* VDD voltage 1.50 - 1.55 */
+#define MMCSD_VDD_155_160           (1 << 2)   /* VDD voltage 1.55 - 1.60 */
+#define MMCSD_VDD_160_165           (1 << 3)   /* VDD voltage 1.60 - 1.65 */
+#define MMCSD_VDD_165_170           (1 << 4)   /* VDD voltage 1.65 - 1.70 */
+#define MMCSD_VDD_17_18             (1 << 5)   /* VDD voltage 1.7 - 1.8 */
+#define MMCSD_VDD_18_19             (1 << 6)   /* VDD voltage 1.8 - 1.9 */
+#define MMCSD_VDD_19_20             (1 << 7)   /* VDD voltage 1.9 - 2.0 */
+#define MMCSD_VDD_20_21             (1 << 8)   /* VDD voltage 2.0-2.1 */
+#define MMCSD_VDD_21_22             (1 << 9)   /* VDD voltage 2.1-2.2 */
+#define MMCSD_VDD_22_23             (1 << 10)  /* VDD voltage 2.2-2.3 */
+#define MMCSD_VDD_23_24             (1 << 11)  /* VDD voltage 2.3-2.4 */
+#define MMCSD_VDD_24_25             (1 << 12)  /* VDD voltage 2.4-2.5 */
+#define MMCSD_VDD_25_26             (1 << 13)  /* VDD voltage 2.5-2.6 */
+#define MMCSD_VDD_26_27             (1 << 14)  /* VDD voltage 2.6-2.7 */
+#define MMCSD_VDD_27_28             (1 << 15)  /* VDD voltage 2.7-2.8 */
+#define MMCSD_VDD_28_29             (1 << 16)  /* VDD voltage 2.8-2.9 */
+#define MMCSD_VDD_29_30             (1 << 17)  /* VDD voltage 2.9-3.0 */
+#define MMCSD_VDD_30_31             (1 << 18)  /* VDD voltage 3.0-3.1 */
+#define MMCSD_VDD_31_32             (1 << 19)  /* VDD voltage 3.1-3.2 */
+#define MMCSD_VDD_32_33             (1 << 20)  /* VDD voltage 3.2-3.3 */
+#define MMCSD_VDD_33_34             (1 << 21)  /* VDD voltage 3.3-3.4 */
+#define MMCSD_VDD_34_35             (1 << 22)  /* VDD voltage 3.4-3.5 */
+#define MMCSD_VDD_35_36             (1 << 23)  /* VDD voltage 3.5-3.6 */
+#define MMCSD_R3_HIGHCAPACITY       (1 << 30)  /* TRUE: Card supports block addressing */
+#define MMCSD_CARD_BUSY             (1 << 31)  /* Card power-up busy bit */
+
+/* R6 Card Status bit definitions */
+
+#define MMCSD_R6_RCA_SHIFT          (16)       /* New published RCA */
+#define MMCSD_R6_RCA_MASK           (0xffff << MMCSD_R6_RCA_SHIFT)
+#define MMCSD_R6_COMCRCERROR        (1 << 15)  /* CRC error */
+#define MMCSD_R6_ILLEGALCOMMAND     (1 << 14)  /* Bad command */
+#define MMCSD_R6_ERROR              (1 << 13)  /* General error */
+#define MMCSD_R6_STATE_SHIFT        (9)        /* Current card state */
+#define MMCSD_R6_STATE_MASK         (15 << MMCSD_R6_STATE_SHIFT)
+                                                                /* Card identification mode states */
+#  define MMCSD_R6_STATE_IDLE       (0 << MMCSD_R6_STATE_SHIFT) /* 0=Idle state */
+#  define MMCSD_R6_STATE_READY      (1 << MMCSD_R6_STATE_SHIFT) /* 1=Ready state */
+#  define MMCSD_R6_STATE_IDENT      (2 << MMCSD_R6_STATE_SHIFT) /* 2=Identification state */
+                                                                /* Data transfer states */
+#  define MMCSD_R6_STATE_STBY       (3 << MMCSD_R6_STATE_SHIFT) /* 3=Standby state */
+#  define MMCSD_R6_STATE_TRAN       (4 << MMCSD_R6_STATE_SHIFT) /* 4=Transfer state */
+#  define MMCSD_R6_STATE_DATA       (5 << MMCSD_R6_STATE_SHIFT) /* 5=Sending data state */
+#  define MMCSD_R6_STATE_RCV        (6 << MMCSD_R6_STATE_SHIFT) /* 6=Receiving data state */
+#  define MMCSD_R6_STATE_PRG        (7 << MMCSD_R6_STATE_SHIFT) /* 7=Programming state */
+#  define MMCSD_R6_STATE_DIS        (8 << MMCSD_R6_STATE_SHIFT) /* 8=Disconnect state */
+#define MMCSD_R6_ERRORMASK          0x0000e000 /* Error mask */
+
+/* SD Configuration Register (SCR) encoding */
+
+#define MMCSD_SCR_BUSWIDTH_1BIT     (1)
+#define MMCSD_SCR_BUSWIDTH_2BIT     (2)
+#define MMCSD_SCR_BUSWIDTH_4BIT     (4)
+#define MMCSD_SCR_BUSWIDTH_8BIT     (8)
+
+/* Last 4 bytes of the 48-bit R7 response */
+
+#define MMCSD_R7VERSION_SHIFT       28         /* Bits 28-31: Command version number */
+#define MMCSD_R7VERSION_MASK        (0x0f << MMCSD_R7VERSION_SHIFT)
+#define MMCSD_R7VOLTAGE_SHIFT       8          /* Bits 8-11: Voltage accepted */
+#define MMCSD_R7VOLTAGE_MASK        (0x0f << MMCSD_R7VOLTAGE_SHIFT)
+#  define MMCSD_R7VOLTAGE_27        (0x01 << MMCSD_R7VOLTAGE_SHIFT) /* 2.7-3.6V */
+#define MMCSD_R7ECHO_SHIFT          0          /* Bits 0-7: Echoed check pattern */
+#define MMCSD_R7ECHO_MASK           (0xff << MMCSD_R7ECHO_SHIFT)
+#  define MMCSD_R7CHECKPATTERN      (0xaa << MMCSD_R7ECHO_SHIFT)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/* Decoded Card Identification (CID) register */
+
+struct mmcsd_cid_s
+{
+  ubyte  mid;       /* 127:120  8-bit Manufacturer ID */
+  uint16 oid;       /* 119:104 16-bit OEM/Application ID (ascii) */
+  ubyte  pnm[6];    /* 103:64  40-bit Product Name (ascii) + null terminator */
+  ubyte  prv;       /*  63:56   8-bit Product revision */
+  uint32 psn;       /*  55:24  32-bit Product serial number */
+                    /*  23:20   4-bit (reserved) */
+  uint16 mdt;       /*  19:8   12-bit Manufacturing date */
+  ubyte  crc;       /*   7:1    7-bit CRC7 */
+                    /*   0:0    1-bit (not used) */
+};
+
+/* Decoded Card Specific Data (CSD) register */
+
+struct mmcsd_csd_s
+{
+  ubyte csdstructure;          /* 127:126 CSD structure */
+  ubyte mmcspecvers;           /* 125:122 MMC Spec version (MMC only) */
+
+  struct
+  {
+    ubyte timeunit;            /*   2:0   Time exponent */
+    ubyte timevalue;           /*   6:3   Time mantissa */
+  } taac;                      /* 119:112 Data read access-time-1 */
+
+  ubyte nsac;                  /* 111:104 Data read access-time-2 in CLK cycle(NSAC*100) */
+
+  struct
+  {
+    ubyte transferrateunit;    /*   2:0   Rate exponent */
+    ubyte timevalue;           /*   6:3   Rate mantissa */
+  } transpeed;                 /* 103:96  Max. data transfer rate */
+
+  uint16 ccc;                  /*  95:84  Card command classes */
+  ubyte readbllen;             /*  83:80  Max. read data block length */
+  ubyte readblpartial;         /*  79:79  Partial blocks for read allowed */
+  ubyte writeblkmisalign;      /*  78:78  Write block misalignment */
+  ubyte readblkmisalign;       /*  77:77  Read block misalignment */
+  ubyte dsrimp;                /*  76:76  DSR implemented */
+
+  union
+  {
+#ifdef CONFIG_MMCSD_MMCSUPPORT
+    struct
+    {
+      uint16 csize;            /*  73:62  Device size */
+      ubyte vddrcurrmin;       /*  61:59  Max. read current at Vdd min */
+      ubyte vddrcurrmax;       /*  58:56  Max. read current at Vdd max */
+      ubyte vddwcurrmin;       /*  55:53  Max. write current at Vdd min */
+      ubyte vddwcurrmax;       /*  52:50  Max. write current at Vdd max */
+      ubyte csizemult;         /*  49:47  Device size multiplier */
+
+      union
+      {
+        struct                 /* MMC system specification version 3.1 */
+        {
+          ubyte ergrpsize;     /*  46:42  Erase group size (MMC 3.1) */
+          ubyte ergrpmult;     /*  41:37  Erase group multiplier (MMC 3.1) */
+        } mmc31;
+        struct                 /* MMC system specification version 2.2 */
+        {
+          ubyte sectorsize;    /*  46:42  Erase sector size (MMC 2.2) */
+          ubyte ergrpsize;     /*  41:37  Erase group size (MMC 2.2) */
+        } mmc22;
+      } er;
+
+      ubyte mmcwpgrpsize;      /*  36:32  Write protect group size (MMC) */
+    } mmc;
+#endif
+    struct
+    {
+      uint16 csize;            /*  73:62  Device size */
+      ubyte vddrcurrmin;       /*  61:59  Max. read current at Vdd min */
+      ubyte vddrcurrmax;       /*  58:56  Max. read current at Vdd max */
+      ubyte vddwcurrmin;       /*  55:53  Max. write current at Vdd min */
+      ubyte vddwcurrmax;       /*  52:50  Max. write current at Vdd max */
+      ubyte csizemult;         /*  49:47  Device size multiplier */
+      ubyte sderblen;          /*  46:46  Erase single block enable (SD) */
+      ubyte sdsectorsize;      /*  45:39  Erase sector size (SD) */
+      ubyte sdwpgrpsize;       /*  38:32  Write protect group size (SD) */
+    } sdbyte;
+
+    struct
+    {
+                               /*  73:70  (reserved) */
+      uint32 csize;            /*  69:48  Device size */
+                               /*  47:47  (reserved) */
+      ubyte sderblen;          /*  46:46  Erase single block enable (SD) */
+      ubyte sdsectorsize;      /*  45:39  Erase sector size (SD) */
+      ubyte sdwpgrpsize;       /*  38:32  Write protect group size (SD) */
+    } sdblock;
+  } u;
+
+  ubyte wpgrpen;               /*  31:31  Write protect group enable */
+  ubyte mmcdfltecc;            /*  30:29  Manufacturer default ECC (MMC) */
+  ubyte r2wfactor;             /*  28:26  Write speed factor */
+  ubyte writebllen;            /*  25:22  Max. write data block length */
+  ubyte writeblpartial;        /*  21:21  Partial blocks for write allowed */
+  ubyte fileformatgrp;         /*  15:15  File format group */
+  ubyte copy;                  /*  14:14  Copy flag (OTP) */
+  ubyte permwriteprotect;      /*  13:13  Permanent write protection */
+  ubyte tmpwriteprotect;       /*  12:12  Temporary write protection */
+  ubyte fileformat;            /*  10:11  File format */
+  ubyte mmcecc;                /*   9:8   ECC (MMC) */
+  ubyte crc;                   /*   7:1   CRC */
+                               /*   0:0   Not used */
+};
+
+struct mmcsd_scr_s
+{
+  ubyte  scrversion;           /* 63:60 Version of SCR structure */
+  ubyte  sdversion;            /* 59:56 SD memory card physical layer version */
+  ubyte  erasestate;           /* 55:55 Data state after erase (1 or 0) */
+  ubyte  security;             /* 54:52 SD security support */
+  ubyte  buswidth;             /* 51:48 DAT bus widthes supported */
+                               /* 47:32 SD reserved space */
+  uint32 mfgdata;              /* 31:0  Reserved for manufacturing data */
+};
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
patacongo	9866fcecf4	Prep for 4.14 release git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2296 42af7a65-404d-4744-a932-0658087f49c3	2009-12-02 17:38:15 +00:00
patacongo	00467c9bd0	Fix a problem with TX status on resume from stall git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2295 42af7a65-404d-4744-a932-0658087f49c3	2009-12-01 21:14:56 +00:00
patacongo	1e85cbd2b0	Should not returned queued read requests on a reset git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2294 42af7a65-404d-4744-a932-0658087f49c3	2009-12-01 15:28:33 +00:00
patacongo	6c5d05074a	Add examples/usbstorage setup info git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2293 42af7a65-404d-4744-a932-0658087f49c3	2009-12-01 00:33:58 +00:00
patacongo	10e98ef71b	Add STM32-specific logic for examples/usbstorage git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2291 42af7a65-404d-4744-a932-0658087f49c3	2009-11-30 16:19:31 +00:00
patacongo	aff7cccdf6	Move LPC-specific code from examples/usbstorage to mcu123-lpc214x/src git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2290 42af7a65-404d-4744-a932-0658087f49c3	2009-11-30 15:52:06 +00:00
patacongo	447e401fea	Add USB storage example for STM32 git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2288 42af7a65-404d-4744-a932-0658087f49c3	2009-11-30 13:07:14 +00:00
patacongo	af1830dc73	SDIO now works git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2287 42af7a65-404d-4744-a932-0658087f49c3	2009-11-29 15:46:13 +00:00
patacongo	3ec785921d	Extend SDIO debug instrumentation git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2286 42af7a65-404d-4744-a932-0658087f49c3	2009-11-28 18:17:53 +00:00
patacongo	fd1fbf821c	Need to enable SDIO DMA git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2285 42af7a65-404d-4744-a932-0658087f49c3	2009-11-28 15:10:08 +00:00
patacongo	a9d40d6d92	Fix compile errors with DMA debug off git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2284 42af7a65-404d-4744-a932-0658087f49c3	2009-11-28 15:05:21 +00:00
patacongo	d343c1879e	Update STM32 TO-DO git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2282 42af7a65-404d-4744-a932-0658087f49c3	2009-11-27 13:09:55 +00:00
patacongo	ade895ea0c	Less intrusive DMA debug git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2281 42af7a65-404d-4744-a932-0658087f49c3	2009-11-27 13:09:32 +00:00
patacongo	06743c5003	Need a cancel method to stop DMA git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2280 42af7a65-404d-4744-a932-0658087f49c3	2009-11-27 13:05:02 +00:00
patacongo	04f6edbaf7	Numerous fixes for basic STM32 SDIO DMA access git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2279 42af7a65-404d-4744-a932-0658087f49c3	2009-11-26 00:18:22 +00:00
patacongo	c76c6b0e52	Fix block read/write return values; SDIO error reporting; slow down clock if interrupt mode git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2278 42af7a65-404d-4744-a932-0658087f49c3	2009-11-25 13:50:26 +00:00
patacongo	70e2fd6f6c	Fix problems when DMA2 is enabled git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2277 42af7a65-404d-4744-a932-0658087f49c3	2009-11-21 17:43:59 +00:00
patacongo	d3ea3abde6	Fix SCR data transfer git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2276 42af7a65-404d-4744-a932-0658087f49c3	2009-11-21 15:45:50 +00:00
patacongo	337b964c8b	Progress integrating SD on STM32 git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2275 42af7a65-404d-4744-a932-0658087f49c3	2009-11-20 00:24:11 +00:00
patacongo	bedc751b0b	Now correctly handles SD card ACMD41 busy git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2274 42af7a65-404d-4744-a932-0658087f49c3	2009-11-19 00:52:40 +00:00
patacongo	8c8b5f01b7	Correct identifies v1.x SD card git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2273 42af7a65-404d-4744-a932-0658087f49c3	2009-11-18 23:12:23 +00:00
patacongo	081d8a6abc	Initial MMC/SD SDIO STM32 bug fixes git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2272 42af7a65-404d-4744-a932-0658087f49c3	2009-11-18 17:31:49 +00:00
patacongo	d209d47e16	Fix error in mount() error handling git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2271 42af7a65-404d-4744-a932-0658087f49c3	2009-11-18 17:31:04 +00:00
patacongo	e252d9d752	Fix issues related to work queue timing git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2270 42af7a65-404d-4744-a932-0658087f49c3	2009-11-18 00:08:41 +00:00
patacongo	99646ff19a	Need to tell SDIO that there is a card in the slot git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2269 42af7a65-404d-4744-a932-0658087f49c3	2009-11-17 23:25:47 +00:00
patacongo	fd34e51e1c	Callbacks need to use worker thread; clean up/document configuration settings git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2268 42af7a65-404d-4744-a932-0658087f49c3	2009-11-17 23:20:08 +00:00
patacongo	108a8ede6a	Remove debug code git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2267 42af7a65-404d-4744-a932-0658087f49c3	2009-11-17 21:48:44 +00:00
patacongo	dcc16a713c	Code complete for STM32 SDIO driver and MMC/SD SDIO driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2266 42af7a65-404d-4744-a932-0658087f49c3	2009-11-17 21:31:56 +00:00
patacongo	29395f7fd1	Finish event wait logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2265 42af7a65-404d-4744-a932-0658087f49c3	2009-11-17 18:18:35 +00:00
patacongo	7ef8423ad0	Add basic data transfer logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2264 42af7a65-404d-4744-a932-0658087f49c3	2009-11-17 16:24:44 +00:00
patacongo	2142afe747	Add SDIO interrupt handling git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2263 42af7a65-404d-4744-a932-0658087f49c3	2009-11-16 23:22:36 +00:00
patacongo	0a24197444	Addition DMA setup logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2262 42af7a65-404d-4744-a932-0658087f49c3	2009-11-16 15:58:05 +00:00
patacongo	2740d04258	Redesign SDIO wait logic; add SDIO DMA logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2261 42af7a65-404d-4744-a932-0658087f49c3	2009-11-16 15:37:11 +00:00
patacongo	b1742905ff	Eliminate some warnings git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2260 42af7a65-404d-4744-a932-0658087f49c3	2009-11-15 19:56:33 +00:00
patacongo	498ae01164	Add logic to handle card insertion/removal events git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2259 42af7a65-404d-4744-a932-0658087f49c3	2009-11-15 19:48:08 +00:00
patacongo	529bbb7a2a	Add SD card initialization logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2258 42af7a65-404d-4744-a932-0658087f49c3	2009-11-15 18:23:46 +00:00
patacongo	95908c8777	Add CSD decode logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2257 42af7a65-404d-4744-a932-0658087f49c3	2009-11-14 22:00:54 +00:00
patacongo	daf843bcec	Missing breaks in switch git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2256 42af7a65-404d-4744-a932-0658087f49c3	2009-11-14 18:24:47 +00:00
patacongo	fc6a71a647	Add MMC configuration logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2255 42af7a65-404d-4744-a932-0658087f49c3	2009-11-14 18:19:51 +00:00
patacongo	1c036b928f	Need to use poll-waiting git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2254 42af7a65-404d-4744-a932-0658087f49c3	2009-11-13 23:47:36 +00:00
patacongo	ad3467a844	Add IOCTLs and card identification logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2253 42af7a65-404d-4744-a932-0658087f49c3	2009-11-13 23:30:41 +00:00
patacongo	1ae08cf310	Add to STM32 SDIO driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2252 42af7a65-404d-4744-a932-0658087f49c3	2009-11-13 15:16:33 +00:00
patacongo	1ec817c5aa	Separate STM32F103ZE pin-mapping into a separate header file git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2251 42af7a65-404d-4744-a932-0658087f49c3	2009-11-12 23:13:18 +00:00
patacongo	ec5b3cef66	Add SDIO GPIO initialization git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2250 42af7a65-404d-4744-a932-0658087f49c3	2009-11-12 17:44:52 +00:00
patacongo	35d260bda4	Finish reponse methods git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2249 42af7a65-404d-4744-a932-0658087f49c3	2009-11-12 16:49:39 +00:00
patacongo	cd8a7958eb	SDIO interface simplication git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2248 42af7a65-404d-4744-a932-0658087f49c3	2009-11-12 15:49:48 +00:00
patacongo	e12ba000d0	Incremental update to STM32 MMCSD driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2247 42af7a65-404d-4744-a932-0658087f49c3	2009-11-11 23:52:48 +00:00
patacongo	9f0c906935	Incremental update to STM32 MMCSD driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2246 42af7a65-404d-4744-a932-0658087f49c3	2009-11-11 22:34:40 +00:00
patacongo	911672589d	Incremental progress on STM32 MMCSD driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2245 42af7a65-404d-4744-a932-0658087f49c3	2009-11-11 21:20:49 +00:00
patacongo	a18a6c13c9	Add skeleton file that will hold the STM32 SDIO driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2244 42af7a65-404d-4744-a932-0658087f49c3	2009-11-11 13:19:23 +00:00
patacongo	4196c8ce60	Add skeleton file that will hold the STM32 SDIO driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2243 42af7a65-404d-4744-a932-0658087f49c3	2009-11-11 12:32:45 +00:00
patacongo	a1087ace92	Rename mmcsd.c to mmcsd_sdio.c git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2242 42af7a65-404d-4744-a932-0658087f49c3	2009-11-11 00:13:42 +00:00
patacongo	eed2313667	Separate SDIO interface from MMCSD git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2241 42af7a65-404d-4744-a932-0658087f49c3	2009-11-10 18:32:51 +00:00
patacongo	19fb20b3ef	Fixes for Z80 compile git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2240 42af7a65-404d-4744-a932-0658087f49c3	2009-11-07 00:03:22 +00:00
patacongo	cb89120bd4	Fix errors/warnings reported by eZ80 compiler git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2239 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 22:53:47 +00:00
patacongo	4da26a9817	Add SDIO register definitions git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2238 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 21:59:49 +00:00
patacongo	783d429d66	Add skeleton of SDIO-based MMCSD driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2237 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 20:44:16 +00:00
patacongo	860e284bef	First cut at SDIO MMC/SD interface git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2236 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 18:10:32 +00:00
patacongo	d9413c1214	Fix confusion between byte and block transfers git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2235 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 13:43:21 +00:00
patacongo	bf7555cc4a	Fix a potential race condition git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2234 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 13:42:49 +00:00
patacongo	7f84a8bea1	Fix compile error when workqueue disabled git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2233 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 01:07:32 +00:00
patacongo	00e7c5f8ac	Integrte work thread git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2232 42af7a65-404d-4744-a932-0658087f49c3	2009-11-06 00:44:22 +00:00
patacongo	e9f2ab2b9c	Document workqueue configuration git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2231 42af7a65-404d-4744-a932-0658087f49c3	2009-11-05 23:14:34 +00:00
patacongo	64e5bef2f6	Incorporate the work thread git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2230 42af7a65-404d-4744-a932-0658087f49c3	2009-11-05 22:58:36 +00:00
patacongo	86987e3b02	Add beginnings of a work thread git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2229 42af7a65-404d-4744-a932-0658087f49c3	2009-11-05 21:44:33 +00:00
patacongo	fcf4b9767c	cosmetic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2228 42af7a65-404d-4744-a932-0658087f49c3	2009-11-05 20:16:15 +00:00
patacongo	6b2827a112	Add generic support for read-ahead buffering and write buffering in block drivers git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2227 42af7a65-404d-4744-a932-0658087f49c3	2009-11-05 18:15:06 +00:00
patacongo	c0675a0711	Add support for GPIO interrupts & STM3210E-EVAL board buttons git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2226 42af7a65-404d-4744-a932-0658087f49c3	2009-11-05 14:07:41 +00:00