Prep for the 0.4.12 release

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2153 42af7a65-404d-4744-a932-0658087f49c3
Prep for 0.4.11 release
2025-12-17 10:16:49 +08:00 · 2009-10-17 22:12:50 +00:00 · 2009-10-17 22:04:31 +00:00 · 2009-10-17 21:45:39 +00:00 · 2009-10-17 21:14:47 +00:00 · 2009-10-17 20:42:37 +00:00
255 changed files with 20429 additions and 2834 deletions
--- a/76
+++ b/76
@@ -839,5 +839,79 @@
 	* net/accept.c: Fix bug in accept().  The logic expected parts of the
 	  return address structure to be initialized or it would return an error.

-0.4.11 2009-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+0.4.11 2009-09-16 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* fs/fs_read.c and fs/fs_write.c.  read() and write() to socket is the
+	  same as recv() and send() with flags = 0.  Fixed!
+	* net/recvfrom.c: Fix errors in return value from non-blocking socket read.
+	* lib/lib_strcasecmp.c and lib/lib_strncasecmp.c.  Use of post-incremented
+	  argument to macro caused strcasecmp() and strncasecmp() to fail.
+	* lib/lib_strstr.c:  Length of substring off by one causes false alarm
+	  sub-string matches.
+	* arch/arm/src/lm3s/lm3s_ethernet.c: Fix errors in LMS6918 FIFO length
+	  handling.  (1) The incorrect size of the ethernet header was being
+	  subtracted on outgoing messages (4 vs 14), which caused outgoing messages to
+	  be a little too long.  (2) The size of incoming FIFO messages is 6 bytes
+	  larger than it expected (2 for the length and 4 for the FCS).  The unhandled
+	  extra two bytes of length cause the driver to sometimes read one too many
+	  words from the received FIFO (corrupting the next queued receive packet,
+	  if any).
+	* net/net_poll.c and net/uip/uip_tcpbacklog.c.  Fixed an important race condition
+	  bug in polling for connections.  The logic worked if the poll was inplace
+	  before the connection was received; but the poll failed to awaken if the
+	  connection was already pending in the backlog when poll() was called.
+	* net/net_close.c.  Fixed another important TCP/IP race condition bug:  If
+	  the host closes the TCP connection just before the target calls close(), then
+	  the close operation may hang indefinitely!
+	* net/net_tcppoll.c.  Removed an unnecessary check for outstanding, un-ACKed
+	  data.  The NuttX socket layer keeps track of ACKs and doesn't need this check;
+	  removing the check should improve write throughput
+	* Add DEBUG configuration option to enable debug console output without disabling
+	  optimization (and vice versa)
+	* Changed lots of occurrents of debug macro dbg() to lldbg().  dbg() uses
+	  stdout to output debug data.  That works fine unless (1) the dbg() macro
+	  is interrupt logic and the interrupted task has redirected stdout!  Most
+	  changes were in uIP.
+	* net/uip/uip_tcpinput.c.  Connection reference count was not being set correctly
+	  when a socket is created by accepting a new connection.  Since the reference
+	  count is bad, such sockets are not successfully duplicated when being passed
+	  to new tasks.
+	* net/net_clone.c.  Similarly, after a socket is cloned, its reference count
+	  was not being initialized.
+	* lib/lib_strstr.c.  Improperly incremented pointer could cause comparison
+	  failures.
+	* net/.  Connection reference count must always be set to zero before calling
+	  uip_tcpfree() or it could trigger a DEBUGASSERT that verifies that the
+	  reference count is zero before freeing a connection structure.
+	* net/uip/uip_listen.c.  uip_accept() consulted the wrong list to find the
+	  listener on a socket.  The previous logic worked most of the time, but
+	  occasionally picked the wrong listener.
+	* net/net_close.c and net/net_sockets.c.  Sockets were not being closed
+	  when a task exits.  If many server tasks are created and exit without closing
+	  sockets (such as with CGI tasks), then eventually, you will run out of sockets.
+	* netutils/thttpd.  Basic functionality of THTTPD is complete.  This includes
+	  serving up files from a file system and executing NXFLAT-based CGI programs
+	  and pipe the stdout back to the HTTP client.
+
+0.4.12 2009-10-17 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* arch/arm/src/stm32 and configs/stm3210e-eval.  Added basic support for the
+	  STMicro STM32, Cortex-M3 MCU.  The specific port is to the STMicro STM3210E-EVAL
+	  development board based around the STM32F103ZET6 MCU.
+	* configs/stm3210e-eval/RIDE.  Added a basic STMicro RIDE7 project that can be
+	  used to perform basic STM32 board bring-up (due to RIDE7 size limitations, it
+	  cannot be used for the full NuttX bring-up).
+	* configs/stm3210e-eval/ostest.  The STM32 now passes the basic NuttX OS test
+	  at examples/ostest.  The rest should be a piece of cake.
+	* configs/stm3210e-eval/nsh.  Added NuttShell (NSH) example.
+	* configs/stm3210e-eval/src/stm32102e-internal.h.  Fix on-board LED GPIO definitions.
+	* arch/arm/src/stm32/src/stm32/stm32_dma.c.  Added DMA channel support for the STM32
+	* arch/arm/src/stm32/src/stm32/stm32_spi.c.  Added a DMA-based SPI driver for the STM32.
+	* arch/arm/src/stm32/src/stm32/stm32_serial.c.  Finished interrupt-drivent,
+	  USART console driver.  This makes NSH work perfectly.
+    * Things left to do for the STM32 deferred to the 0.4.13 release:  USB device driver,
+	  LCD driver and NX bringup on the eval board's display and MicroSD support.  An SPI
+	  driver was included in the 0.4.12 release, but is not yet tested.
+
+0.4.13 2009-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>

--- a/Documentation/NuttX.html
+++ b/Documentation/NuttX.html
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -12,7 +12,7 @@
      <h1><big><font color="#3c34ec">
        <i>NuttX RTOS Porting Guide</i>
      </font></big></h1>
-      <p>Last Updated: July 18, 2009</p>
+      <p>Last Updated: September 15, 2009</p>
    </td>
  </tr>
 </table>
@@ -2004,6 +2004,9 @@ extern void up_ledoff(int led);
  <li>
    <code>CONFIG_DEBUG_VERBOSE</code>: enables verbose debug output
  </li>
+  <li>
+    <code>CONFIG_DEBUG_SYMBOLS</code>: build without optimization and with debug symbols (needed for use with a debugger).
+  </li>
  <li>
    <code>CONFIG_DEBUG_SCHED</code>: enable OS debug output (disabled by default)
  </li>
@@ -2013,12 +2016,21 @@ extern void up_ledoff(int led);
  <li>
    <code>CONFIG_DEBUG_NET</code>: enable network debug output (disabled by default)
  </li>
+  <li>
+    <code>CONFIG_DEBUG_USB</code>: enable USB debug output (disabled by default)
+  </li>
  <li>
    <code>CONFIG_DEBUG_FS</code>: enable file system debug output (disabled by default)
  </li>
  <li>
    <code>CONFIG_DEBUG_LIB</code>: enable C library debug output (disabled by default)
  </li>
+  <li>
+    <code>CONFIG_DEBUG_BINFMT</code>: enable binary loader debug output (disabled by default)
+  </li>
+  <li>
+    <code>CONFIG_DEBUG_GRAPHICS</code>: enable NX graphics debug output (disabled by default)
+  </li>
  <li>
    <code>CONFIG_ARCH_LOWPUTC</code>: architecture supports low-level, boot
    time console output
@@ -2362,12 +2374,15 @@ extern void up_ledoff(int led);
    <code>CONFIG_THTTPD_SERVER_SOFTWARE</code>: SERVER_SOFTWARE: response
  </li>
  <li>
-    <code>CONFIG_THTTPD_CGI_PATH</code>:
+    <code>CONFIG_THTTPD_PATH</code>: Server working directory. Default: <code>/mnt/www</code>.
  </li>
  <li>
-    <code>CONFIG_THTTPD_CGI_PATTERN</code>: Only CGI programs matching this
-    pattern will be executed.  In fact, if this value is not defined
-    then no CGI logic will be built.
+    <code>CONFIG_THTTPD_CGI_PATH</code>: Path to CGI executables.  Default: <code>/mnt/www/cgi-bin</code>.
+  </li>
+  <li>
+    <code>CONFIG_THTTPD_CGI_PATTERN</code>: Only CGI programs whose expanded paths
+    match this pattern will be executed.  In fact, if this value is not defined
+    then no CGI logic will be built. Default: <code>/mnt/www/cgi-bin/*</code>.
  </li>
  <li>
    <code>CONFIG_THTTPD_CGI_PRIORITY</code>: Provides the priority of CGI child tasks
@@ -2385,7 +2400,7 @@ extern void up_ledoff(int led);
    to run before killing them.
  </li>
  <li>
-    <code>CONFIG_THTTPD_CHARSET- The default character set name to use with
+    <code>CONFIG_THTTPD_CHARSET</code>: The default character set name to use with
    text MIME types.
  </li>
  <li>
--- a/Documentation/README.html
+++ b/Documentation/README.html
@@ -0,0 +1,136 @@
+<html>
+<head>
+<title>README Files</title>
+</head>
+<body background="backgd.gif">
+<base href="http://nuttx.cvs.sourceforge.net/viewvc/*checkout*/nuttx/nuttx/" TARGET="_self">
+<hr><hr>
+<table width ="100%">
+  <tr align="center" bgcolor="#e4e4e4">
+    <td>
+      <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
+      <p>Last Updated: October 14, 2009</p>
+    </td>
+  </tr>
+</table>
+<p>
+  Additional information can be found in the <code>Documentation/</code> directory and
+  also in <code>README</code> files that are scattered throughout the source tree.
+  Below is a guide to the available <code>README</code> files.
+  Some <code>README</code> files contain more important information than others.
+  The key <code>README</code> files are shown in <code><i><b>BOLDFACE/ITALIC</i></b></code> below.
+</p>
+<ul><pre>
+ .
+ |
+ |- arch/
+ |   |
+ |   |- arm
+ |   |   `- src
+ |   |       `- <a href="arch/arm/src/lpc214x/README.txt">lpc214x/README.txt</a>
+ |   |- sh/
+ |   |   |- include/
+ |   |   |   |-<a href="arch/sh/include/m16c/README.txt">m16c/README.txt</a>
+ |   |   |   |-<a href="arch/sh/include/sh1/README.txt">sh1/README.txt</a>
+ |   |   |   `-<a href="arch/sh/include/README.txt">README.txt</a>
+ |   |   |- src/
+ |   |   |   |-<a href="arch/sh/src/common/README.txt">common/README.txt</a>
+ |   |   |   |-<a href="arch/sh/src/m16c/README.txt">m16c/README.txt</a>
+ |   |   |   |-<a href="arch/sh/src/sh1/README.txt">sh1/README.txt</a>
+ |   |   |   `-<a href="arch/sh/src/README.txt">README.txt</a>
+ |   `- z80/
+ |   |   `- src/
+ |   |       `- <a href="arch/z80/src/z80/README.txt">z80/README.txt</a>
+ |   `- <a href="arch/README.txt"><b><i>README.txt</i></b></a>
+ |- configs/
+ |   |- c5471evm/
+ |   |   |- <a href="configs/c5471evm/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/c5471evm/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/c5471evm/README.txt"><b><i>README.txt</i></b></a>
+ |   |- eagle100/
+ |   |   |- <a href="configs/eagle100/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/eagle100/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/eagle100/README.txt"><b><i>README.txt</i></b></a>
+ |   |- ez80f910200kitg/
+ |   |   |- <a href="configs/ez80f910200kitg/ostest/README.txt">ostest/README.txt</a>
+ |   |   `- <a href="configs/ez80f910200kitg/README.txt"><b><i>README.txt</i></b></a>
+ |   |- ez80f910200zco/
+ |   |   |- <a href="configs/ez80f910200zco/ostest/README.txt">dhcpd/README.txt</a>
+ |   |   |- <a href="configs/ez80f910200zco/httpd/README.txt">httpd/README.txt</a>
+ |   |   |- <a href="configs/ez80f910200zco/nettest/README.txt">nettest/README.txt</a>
+ |   |   |- <a href="configs/ez80f910200zco/nsh/README.txt">nsh/README.txt</a>
+ |   |   |- <a href="configs/ez80f910200zco/ostest/README.txt">ostest/README.txt</a>
+ |   |   |- <a href="configs/ez80f910200zco/poll/README.txt">poll/README.txt</a>
+ |   |   `- <a href="configs/ez80f910200zco/README.txt"><b><i>README.txt</i></b></a>
+ |   |- m68332evb/
+ |   |   |- <a href="configs/m68332evb/include/README.txt">include/README.txt</a>
+ |   |   `- <a href="configs/m68332evb/src/README.txt">src/README.txt</a>
+ |   |- mcu123-lpc214x/
+ |   |   |- <a href="configs/mcu123-lpc214x/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/mcu123-lpc214x/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/mcu123-lpc214x/README.txt"><b><i>README.txt</i></b></a>
+ |   |- mx1ads/
+ |   |   |- <a href="configs/mx1ads/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/mx1ads/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/mx1ads/README.txt"><b><i>README.txt</i></b></a>
+ |   |- ntosd-dm320/
+ |   |   |- <a href="configs/ntosd-dm320/doc/README.txt">doc/README.txt</a>
+ |   |   |- <a href="configs/ntosd-dm320/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/ntosd-dm320/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/ntosd-dm320/README.txt"><b><i>README.txt</i></b></a>
+ |   |- olimex-strp711/
+ |   |   |- <a href="configs/olimex-strp711/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/olimex-strp711/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/olimex-strp711/README.txt"><b><i>README.txt</i></b></a>
+ |   |- pjrc-8051/
+ |   |   |- <a href="configs/pjrc-8051/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/pjrc-8051/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/pjrc-8051/README.txt"><b><i>README.txt</i></b></a>
+ |   |- sim/
+ |   |   |- <a href="configs/sim/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/sim/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/sim/README.txt"><b><i>README.txt</i></b></a>
+ |   |- skp16c26/
+ |   |   |- <a href="configs/skp16c26/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/skp16c26/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/skp16c26/README.txt"><b><i>README.txt</i></b></a>
+ |   |- stm3210e-eval/
+ |   |   |- <a href="configs/stm3210e-eval/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/stm3210e-eval/RIDE/README.txt">RIDE/README.txt</a>
+ |   |   |- <a href="configs/stm3210e-eval/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/stm3210e-eval/README.txt"><b><i>README.txt</i></b></a>
+ |   |- us7032evb1/
+ |   |   |- <a href="configs/us7032evb1/bin/README.txt">bin/README.txt</a>
+ |   |   |- <a href="configs/us7032evb1/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/us7032evb1/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/us7032evb1/README.txt"><b><i>README.txt</i></b></a>
+ |   |- xtrs/
+ |   |   |- <a href="configs/xtrs/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/xtrs/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/xtrs/README.txt"><b><i>README.txt</i></b></a>
+ |   |- z16f2800100zcog/
+ |   |   |- <a href="configs/xtrs/ostest/README.txt">ostest/README.txt</a>
+ |   |   |- <a href="configs/xtrs/pashello/README.txt">pashello/README.txt</a>
+ |   |   `- <a href="configs/xtrs/README.txt"><b><i>README.txt</i></b></a>
+ |   |- z80sim/
+ |   |   |- <a href="configs/z80sim/include/README.txt">include/README.txt</a>
+ |   |   |- <a href="configs/z80sim/src/README.txt">src/README.txt</a>
+ |   |   `- <a href="configs/z80sim/README.txt"><b><i>README.txt</i></b></a>
+ |   |- z8encore000zco/
+ |   |   |- <a href="configs/z8encore000zco/ostest/README.txt">ostest/README.txt</a>
+ |   |   `- <a href="configs/z8encore000zco/README.txt"><b><i>README.txt</i></b></a>
+ |   |- z8f64200100kit/
+ |   |   |- <a href="configs/z8f64200100kit/ostest/README.txt">ostest/README.txt</a>
+ |   |   `- <a href="configs/z8f64200100kit/README.txt"><b><i>README.txt</i></b></a>
+ |   `- <a href="configs/README.txt"><b><i>README.txt</i></b></a>
+ |- examples/
+ |   |- <a href="examples/nsh/README.txt"><b><i>nsh/README.txt</i></b></a>
+ |   |- <a href="examples/pashello/README.txt">pashello/README.txt</a>
+ |   `- <a href="examples/README.txt"><b><i>README.txt</i></b></a>
+ |- graphics/
+ |   `- <a href="graphics/README.txt"><b><i>README.txt</i></b></a>
+ |- libxx/
+ |   `- <a href="libxx/README.txt"><b><i>README.txt</i></b></a>
+ `- netutils/
+     |- <a href="netutils/telnetd/README.txt">telnetd/README.txt</a>
+     `- <a href="netutils/README"><b><i>README</a></a>
--- a/README.txt
+++ b/README.txt
@@ -0,0 +1,116 @@
+Additional information can be found in the Documentation/ directory and
+also in README files that are scattered throughout the source tree.  Below
+is a guide to the available README files:
+
+ |
+ |- arch/
+ |   |
+ |   |- arm
+ |   |   `- src
+ |   |       `- lpc214x/README.txt
+ |   |- sh/
+ |   |   |- include/
+ |   |   |   |-m16c/README.txt
+ |   |   |   |-sh1/README.txt
+ |   |   |   `-README.txt
+ |   |   |- src/
+ |   |   |   |-common/README.txt
+ |   |   |   |-m16c/README.txt
+ |   |   |   |-sh1/README.txt
+ |   |   |   `-README.txt
+ |   `- z80/
+ |   |   `- src/
+ |   |       `- z80/README.txt
+ |   `- README.txt
+ |- configs/
+ |   |- c5471evm/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- eagle100/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- ez80f910200kitg/
+ |   |   |- ostest/README.txt
+ |   |   `- README.txt
+ |   |- ez80f910200zco/
+ |   |   |- dhcpd/README.txt
+ |   |   |- httpd/README.txt
+ |   |   |- nettest/README.txt
+ |   |   |- nsh/README.txt
+ |   |   |- ostest/README.txt
+ |   |   |- poll/README.txt
+ |   |   `- README.txt
+ |   |- m68332evb/
+ |   |   |- include/README.txt
+ |   |   `- src/README.txt
+ |   |- mcu123-lpc214x/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- mx1ads/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- ntosd-dm320/
+ |   |   |- doc/README.txt
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- olimex-strp711/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- pjrc-8051/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- sim/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- skp16c26/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- stm3210e-eval/
+ |   |   |- include/README.txt
+ |   |   |- RIDE/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- us7032evb1/
+ |   |   |- bin/README.txt
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- xtrs/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- z16f2800100zcog/
+ |   |   |- ostest/README.txt
+ |   |   |- pashello/README.txt
+ |   |   `- README.txt
+ |   |- z80sim/
+ |   |   |- include/README.txt
+ |   |   |- src/README.txt
+ |   |   `- README.txt
+ |   |- z8encore000zco/
+ |   |   |- ostest/README.txt
+ |   |   `- README.txt
+ |   |- z8f64200100kit/
+ |   |   |- ostest/README.txt
+ |   |   `- README.txt
+ |   `- README.txt
+ |- examples/
+ |   |- nsh/README.txt
+ |   |- pashello/README.txt
+ |   `- README.txt
+ |- graphics/
+ |   `- README.txt
+ |- libxx/
+ |   `- README.txt
+ `- netutils/
+     |- telnetd/README.txt
+     `- README
--- a/45
+++ b/45
@@ -957,4 +957,49 @@ added:

 This tarball contains a complete CVS snapshot from August 8, 2009.

+nuttx-0.4.11
+^^^^^^^^^^^^
+
+This is the 43rd release of NuttX. This release of NuttX incorporates the
+verified port of Jeff Poskanzer's THTTPD HTTP server (see http://acme.com/software/thttpd/.).
+Many of the key features of THTTPD have been tested on the Micromint Eagle-100
+development board (Cortex-M3).  These tests verify:
+
+	* Serving of files from any file system
+	* Execution of CGI executable.  This release supports execution of
+	  NXFLAT executables on a ROMFS file system (http://www.nuttx.org/NuttXNxFlat.html)
+
+A standard CGI interface is used:  Information is pasted to the CGI program via POST
+commands and via environment variables.  CGI socket I/O is redirected to stdin and stdout
+so that the CGI program only need to printf() to send its content back to the HTTP
+client.
+
+Another value to this THTTPD integration effort has been that THTTPD has provided a very
+good test bed for finding NuttX networking bugs.  Several very critical networking bugs
+have been fixed with this 0.4.11 release (see the ChangeLog for details).  Networking
+throughput has also been greatly improved.  Anyone using NuttX networking should consider
+upgrading to this release.
+
+This tarball contains a complete CVS snapshot from September 16, 2009
+
+nuttx-0.4.12
+^^^^^^^^^^^^
+
+This is the 44th release of NuttX.  This release adds basic support for the STMicro STM32,
+Cortex-M3 MCU.  The specific port is to the STMicro STM3210E-EVAL development board based
+around the STM32F103ZET6 MCU.  Some highlights of this port:
+
+	* This basic port includes boot-up logic, interrupt driven serial console, and system
+	  timer interrupts.
+	* Includes a basic STMicro RIDE7 project that can be used to perform basic STM32
+	  board bring-up (due to RIDE7 size limitations, it cannot be used for the full NuttX
+	  bring-up).
+	* Working, Tested Configurations:  the NuttX OS test and the NuttShell (NSH) example.
+
+This basic STM32 port will be extended in the 0.4.13 NuttX release.  Functionality needed
+for complete STM32 support includes:  USB device driver, LCD driver and NX bringup on the
+development board's display and MicroSD support.  An SPI driver and a DMA support was included
+in this 0.4.12 release, but is not yet tested.
+
+This tarball contains a complete CVS snapshot from October 17, 2009

--- a/76
+++ b/76
@@ -1,5 +1,5 @@
-NuttX TODO List (Last updated August 8, 2009)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+NuttX TODO List (Last updated September 16, 2009)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

  (5)  Task/Scheduler (sched/)
  (2)  Memory Managment (mm/)
@@ -7,14 +7,15 @@ NuttX TODO List (Last updated August 8, 2009)
  (1)  pthreads (sched/)
  (1)  C++ Support
  (5)  Binary loaders (binfmt/)
- (15)  Network (net/, netutils/)
+ (13)  Network (net/, netutils/)
+  (4)  Network Utilities (netutils/)
  (1)  USB (drivers/usbdev)
-  (4)  Libraries (lib/)
+  (5)  Libraries (lib/)
  (8)  File system/Generic drivers (fs/, drivers/)
  (2)  Graphics subystem (graphics/)
  (1)  Pascal add-on (pcode/)
  (1)  Documentation (Documentation/)
-  (6)  Build system / Toolchains
+  (5)  Build system / Toolchains
  (3)  NuttShell (NSH) (examples/nsh)
  (3)  Other Applications & Tests (examples/)
  (2)  Linux/Cywgin simulation (arch/sim)
@@ -136,15 +137,8 @@ o Binary loaders (binfmt/)
  Status:      Open
  Priority:    Low

-o Network (net/, netutils/)
-  ^^^^^^^^^^^^^^^^^^^^^^^^^
-
-  Description: One critical part of netutils/ apps is untested: The uIP
-               resolver in netutils/resolv.  The webclient code has been
-               tested on host using gethosbyname(), but still depends on the
-               untested resolve logic.
-  Status:      Open
-  Priority:    Medium, Important but not core NuttX functionality
+o Network (net/)
+  ^^^^^^^^^^^^^^

  Description: Should implement SOCK_RAW, SOCK_PACKET
  Status:      Open
@@ -204,10 +198,6 @@ o Network (net/, netutils/)
  Status:      Open
  Priority:    Medium

-  Description: Port PPP support from http://contiki.cvs.sourceforge.net/contiki/contiki-2.x/backyard/core/net/ppp/
-  Status:      Open
-  Priority:    Low
-
  Description: At present, there cannot be two concurrent active TCP send
               operations in progress using the same socket.  This is because
               the uIP ACK logic will support only one transfer at a time.  The
@@ -234,17 +224,46 @@ o Network (net/, netutils/)
  Status:      Open, depends on UDP read-ahead support
  Priority:    Medium

+  Description: poll()/select() only works for availability of buffered TCP
+               read data (when read-ahead is enabled).  The way writing is
+               handled in uIP, all sockets must wait when send and cannot
+               be notifiied when they can send without waiting.
+  Status:      Open, probably will not be fixed.
+  Priority:    Medium... this does effect porting of applications that expect
+               different behavior from poll()/select()
+
  Description: sockets do not support all modes except for O_NONBLOCK. Sockets
               support only (1) TCP/IP non-blocking read operations when read-ahead
-	       buffering is enabled, and (2) TCP/IP accept() operations when TCP/IP
-	       connection backlog is enabled.
+               buffering is enabled, and (2) TCP/IP accept() operations when TCP/IP
+               connection backlog is enabled.
  Status:      Open
  Priority:    Low.

-  Description: THTTPD is included in the source tree, but has not yet been fully
-               integrated.
+o Network Utilities (netutils/)
+
+  Description: One critical part of netutils/ apps is untested: The uIP
+               resolver in netutils/resolv.  The webclient code has been
+               tested on host using gethosbyname(), but still depends on the
+               untested resolve logic.
  Status:      Open
-  Priority:    High
+  Priority:    Medium, Important but not core NuttX functionality
+
+  Description: Port PPP support from http://contiki.cvs.sourceforge.net/contiki/contiki-2.x/backyard/core/net/ppp/
+  Status:      Open
+  Priority:    Low
+
+  Description: Not all THTTPD features/options have been verified.  In particular, there is no
+               test case of a CGI program receiving POST input.  Only the configuration of
+               examples/thttpd has been tested.
+  Status:      Open
+  Priority:    Medium
+
+  Description: The first GET received by THTTPD is not responded to.  Refreshing the page
+               from the browser solves the problem and THTTPD works fine after thatg.  I 
+               believe that this is the duplicate of another bug: "Outgoing [uIP] packets are dropped
+               and overwritten by ARP packets if the destination IP has not been mapped to a MAC."
+  Status:      Open
+  Priority:    Medium

 o USB (drivers/usbdev)
  ^^^^^^^^^^^^^^^^^^^^
@@ -285,6 +304,10 @@ o Libraries (lib/)
  Status:      Open
  Priority:    Low

+  Description: strftime() and other timing functions do not handle days of the week.
+  Status:      Open
+  Priority:    Low
+
 o File system / Generic drivers (fs/, drivers/)
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

@@ -388,13 +411,6 @@ o Build system
  Status:      Open
  Priority:    Medium (maybe higher for z80 target)

-  Description: It would be nice to de-couple some of the behaviors enabled by
-               CONFIG_DEBUG.  For example, CONFIG_DEBUG turns on debug output,
-               but also disables optimization make the binary much bigger.
-  Status:      Open
-  Priority:    Low.  There workaround is easy.. just edit the configuration's
-               Make.def file to control the behavior that you want.
-
  Description: Need a NuttX configuration tool.  The number of configuration
               settings has become quite large and difficult to manage manually.
  Status:      Open
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -134,8 +134,14 @@ arch/arm - ARM-based micro-controllers
    the following subdirectories:

    arch/arm/include and arch/arm/src/common
-        Common ARM logic.
+        Common ARM/Cortex-M3 logic.

+    arch/arm/src/arm and arch/arm/include/arm
+        Common ARM-specific logic
+
+    arch/arm/src/cortexm3 and arch/arm/include/cortexm3
+        Common Cortex-M3 logic
+        
    arch/arm/include/c5471 and arch/arm/src/c5471
        TI TMS320C5471 (also called TMS320DM180 or just C5471).
        NuttX operates on the ARM7 of this dual core processor. This port
@@ -146,6 +152,13 @@ arch/arm - ARM-based micro-controllers
        NuttX operates on the ARM9EJS of this dual core processor.  This port
        complete, verified, and included in the NuttX release 0.2.1.

+    arch/arm/include/lm3s and arch/arm/src/lm3s
+        These directories contain support for the Luminary LMS family, particularly
+        for the LM3S6918. The initial, release of this port was included in NuttX version
+        0.4.6. The current port includes timer, serial console, Ethernet, SSI, and microSD
+        support. There are working configurations the NuttX OS test, to run the NuttShell
+        (NSH), the NuttX networking test, and the uIP web server.
+
    arch/arm/include/lpc214x and arch/arm/src/lpc214x
        These directories provide support for NXP LPC214x family of
        processors.  This port boots and passes the OS test (examples/ostest).
@@ -153,6 +166,12 @@ arch/arm - ARM-based micro-controllers
        timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
        support.  A verifed NuttShell (NSH) configuration is also available.

+    arch/arm/include/stm32 and arch/arm/src/stm32
+        These directories contain support for the STMicro STM32 family, particularly
+        for the STM32F103ZET6. The initial, release of this port was included in NuttX version
+        0.4.12. The current port includes timer, and serial console.  Work is underway for
+        USB, SPI, microSD, and LCD.
+
    arch/arm/include/str71x and arch/arm/src/str71x
        These directories provide support for the STMicro STR71x processors.
        Coding is complete on the basic port (boot logic, system time, serial console),
@@ -214,7 +233,3 @@ arch/c5471
 arch/dm320
    Replaced with arch/arm/include/dm320 and arch/arm/src/dm320

-Other ports for the for the TI TMS320DM270 and for MIPS are in various states
-of progress
-
-
--- a/arch/arm/include/arch.h
+++ b/arch/arm/include/arch.h
@@ -44,10 +44,14 @@
 * Included Files
 ****************************************************************************/

+#include <nuttx/config.h>
+
 /****************************************************************************
 * Definitions
 ****************************************************************************/

+#ifdef CONFIG_PIC
+
 /* This identifies the register the is used by the processor as the PIC base
 * register.  It is usually r9 or r10
 */
@@ -82,6 +86,7 @@ do { \
  ); \
 } while (0)

+#endif

 /****************************************************************************
 * Inline functions
--- a/arch/arm/include/stm32/irq.h
+++ b/arch/arm/include/stm32/irq.h
@@ -0,0 +1,233 @@
+/************************************************************************************
+ * arch/arm/include/stm32s/irq.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_IRQ_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define STM32_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+                                     /* Vector  0: Reset stack pointer value */
+                                     /* Vector  1: Reset (not handler as an IRQ) */
+#define STM32_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define STM32_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
+#define STM32_IRQ_MPU            (4) /* Vector  4: Memory management (MPU) */
+#define STM32_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
+#define STM32_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
+#define STM32_IRQ_SVCALL        (11) /* Vector 11: SVC call */
+#define STM32_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
+                                     /* Vector 13: Reserved */
+#define STM32_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
+#define STM32_IRQ_SYSTICK       (15) /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16) */
+
+#define STM32_IRQ_INTERRUPTS    (16) /* Vector number of the first external interrupt */
+#ifdef CONFIG_STM32_CONNECTIVITY_LINE
+#  define STM32_IRQ_WWDG        (16) /* 0:  Window Watchdog interrupt */
+#  define STM32_IRQ_PVD         (17) /* 1:  PVD through EXTI Line detection interrupt */
+#  define STM32_IRQ_TAMPER      (18) /* 2:  Tamper interrupt */
+#  define STM32_IRQ_RTC         (19) /* 3:  RTC global interrupt */
+#  define STM32_IRQ_FLASH       (20) /* 4:  Flash global interrupt */
+#  define STM32_IRQ_RCC         (21) /* 5:  RCC global interrupt */
+#  define STM32_IRQ_EXTI0       (22) /* 6:  EXTI Line 0 interrupt */
+#  define STM32_IRQ_EXTI1       (23) /* 7:  EXTI Line 1 interrupt */
+#  define STM32_IRQ_EXTI2       (24) /* 8:  EXTI Line 2 interrupt */
+#  define STM32_IRQ_EXTI3       (25) /* 9:  EXTI Line 3 interrupt */
+#  define STM32_IRQ_EXTI4       (26) /* 10: EXTI Line 4 interrupt */
+#  define STM32_IRQ_DMA1CH1     (27) /* 11: DMA1 Channel 1 global interrupt */
+#  define STM32_IRQ_DMA1CH2     (28) /* 12: DMA1 Channel 2 global interrupt */
+#  define STM32_IRQ_DMA1CH3     (29) /* 13: DMA1 Channel 3 global interrupt */
+#  define STM32_IRQ_DMA1CH4     (30) /* 14: DMA1 Channel 4 global interrupt */
+#  define STM32_IRQ_DMA1CH5     (31) /* 15: DMA1 Channel 5 global interrupt */
+#  define STM32_IRQ_DMA1CH6     (32) /* 16: DMA1 Channel 7 global interrupt */
+#  define STM32_IRQ_ADC12       (34) /* 18: ADC1 and ADC2 global interrupt */
+#  define STM32_IRQ_CAN1TX      (35) /* 19: CAN1 TX interrupts */
+#  define STM32_IRQ_CAN1RX0     (36) /* 20: CAN1 RX0 interrupts */
+#  define STM32_IRQ_CAN1RX1     (37) /* 21: CAN1 RX1 interrupt */
+#  define STM32_IRQ_CAN1SCE     (38) /* 22: CAN1 SCE interrupt */
+#  define STM32_IRQ_EXTI95      (39) /* 23: EXTI Line[9:5] interrupts */
+#  define STM32_IRQ_TIM1BRK     (40) /* 24: TIM1 Break interrupt */
+#  define STM32_IRQ_TIM1UP      (41) /* 25: TIM1 Update interrupt */
+#  define STM32_IRQ_TIM1TRGCOM  (42) /* 26: TIM1 Trigger and Commutation interrupts */
+#  define STM32_IRQ_TIM1CC      (43) /* 27: TIM1 Capture Compare interrupt */
+#  define STM32_IRQ_TIM2        (44) /* 28: TIM2 global interrupt */
+#  define STM32_IRQ_TIM3        (45) /* 29: TIM3 global interrupt */
+#  define STM32_IRQ_TIM4        (46) /* 30: TIM4 global interrupt */
+#  define STM32_IRQ_I2C1EV      (47) /* 31: I2C1 event interrupt */
+#  define STM32_IRQ_I2C1ER      (48) /* 32: I2C1 error interrupt */
+#  define STM32_IRQ_I2C2EV      (49) /* 33: I2C2 event interrupt */
+#  define STM32_IRQ_I2C2ER      (50) /* 34: I2C2 error interrupt */
+#  define STM32_IRQ_SPI1        (51) /* 35: SPI1 global interrupt */
+#  define STM32_IRQ_SPI2        (52) /* 36: SPI2 global interrupt */
+#  define STM32_IRQ_USART1      (53) /* 37: USART1 global interrupt */
+#  define STM32_IRQ_USART2      (54) /* 38: USART2 global interrupt */
+#  define STM32_IRQ_USART3      (55) /* 39: USART3 global interrupt */
+#  define STM32_IRQ_EXTI1510    (56) /* 40: EXTI Line[15:10] interrupts */
+#  define STM32_IRQ_RTCALR      (57) /* 41: RTC alarm through EXTI line interrupt */
+#  define STM32_IRQ_OTGFSWKUP   (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+                                     /* 43-49: Reserved */
+#  define STM32_IRQ_TIM5        (66) /* 50: TIM5 global interrupt */
+#  define STM32_IRQ_SPI3        (67) /* 51: SPI3 global interrupt */
+#  define STM32_IRQ_UART4       (68) /* 52: UART4 global interrupt */
+#  define STM32_IRQ_UART5       (69) /* 53: UART5 global interrupt */
+#  define STM32_IRQ_TIM6        (70) /* 54: TIM6 global interrupt */
+#  define STM32_IRQ_TIM7        (71) /* 55: TIM7 global interrupt */
+#  define STM32_IRQ_DMA2CH1     (72) /* 56: DMA2 Channel 1 global interrupt */
+#  define STM32_IRQ_DMA2CH2     (73) /* 57: DMA2 Channel 2 global interrupt */
+#  define STM32_IRQ_DMA2CH3     (74) /* 58: DMA2 Channel 3 global interrupt */
+#  define STM32_IRQ_DMA2CH4     (75) /* 59: DMA2 Channel 4 global interrupt */
+#  define STM32_IRQ_DMA2CH5     (76) /* 60: DMA2 Channel 5 global interrupt */
+#  define STM32_IRQ_ETH         (77) /* 61: Ethernet global interrupt */
+#  define STM32_IRQ_ETHWKUP     (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
+#  define STM32_IRQ_CAN2TX      (79) /* 63: CAN2 TX interrupts */
+#  define STM32_IRQ_CAN2RX0     (70) /* 64: CAN2 RX0 interrupts */
+#  define STM32_IRQ_CAN2RX1     (81) /* 65: CAN2 RX1 interrupt */
+#  define STM32_IRQ_CAN2SCE     (82) /* 66: CAN2 SCE interrupt */
+#  define STM32_IRQ_OTGFS       (83) /* 67: USB On The Go FS global interrupt */
+#  define NR_IRQS               (84)
+#else
+#  define STM32_IRQ_WWDG        (16) /* 0:  Window Watchdog interrupt */
+#  define STM32_IRQ_PVD         (17) /* 1:  PVD through EXTI Line detection interrupt */
+#  define STM32_IRQ_TAMPER      (18) /* 2:  Tamper interrupt */
+#  define STM32_IRQ_RTC         (19) /* 3:  RTC global interrupt */
+#  define STM32_IRQ_FLASH       (20) /* 4:  Flash global interrupt */
+#  define STM32_IRQ_RCC         (21) /* 5:  RCC global interrupt */
+#  define STM32_IRQ_EXTI0       (22) /* 6:  EXTI Line 0 interrupt */
+#  define STM32_IRQ_EXTI1       (23) /* 7:  EXTI Line 1 interrupt */
+#  define STM32_IRQ_EXTI2       (24) /* 8:  EXTI Line 2 interrupt */
+#  define STM32_IRQ_EXTI3       (25) /* 9:  EXTI Line 3 interrupt */
+#  define STM32_IRQ_EXTI4       (26) /* 10: EXTI Line 4 interrupt */
+#  define STM32_IRQ_DMA1CH1     (27) /* 11: DMA1 Channel 1 global interrupt */
+#  define STM32_IRQ_DMA1CH2     (28) /* 12: DMA1 Channel 2 global interrupt */
+#  define STM32_IRQ_DMA1CH3     (29) /* 13: DMA1 Channel 3 global interrupt */
+#  define STM32_IRQ_DMA1CH4     (30) /* 14: DMA1 Channel 4 global interrupt */
+#  define STM32_IRQ_DMA1CH5     (31) /* 15: DMA1 Channel 5 global interrupt */
+#  define STM32_IRQ_DMA1CH6     (32) /* 16: DMA1 Channel 6 global interrupt */
+#  define STM32_IRQ_DMA1CH7     (33) /* 17: DMA1 Channel 7 global interrupt */
+#  define STM32_IRQ_ADC12       (34) /* 18: ADC1 and ADC2 global interrupt */
+#  define STM32_IRQ_USBHPCANTX  (35) /* 19: USB High Priority or CAN TX interrupts*/
+#  define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/
+#  define STM32_IRQ_CAN1RX1     (37) /* 21: CAN1 RX1 interrupt */
+#  define STM32_IRQ_CAN1SCE     (38) /* 22: CAN1 SCE interrupt */
+#  define STM32_IRQ_EXTI95      (39) /* 23: EXTI Line[9:5] interrupts */
+#  define STM32_IRQ_TIM1BRK     (40) /* 24: TIM1 Break interrupt */
+#  define STM32_IRQ_TIM1UP      (41) /* 25: TIM1 Update interrupt */
+#  define STM32_IRQ_TIM1TRGCOM  (42) /* 26: TIM1 Trigger and Commutation interrupts */
+#  define STM32_IRQ_TIM1CC      (43) /* 27: TIM1 Capture Compare interrupt */
+#  define STM32_IRQ_TIM2        (44) /* 28: TIM2 global interrupt */
+#  define STM32_IRQ_TIM3        (45) /* 29: TIM3 global interrupt */
+#  define STM32_IRQ_TIM4        (46) /* 30: TIM4 global interrupt */
+#  define STM32_IRQ_I2C1EV      (47) /* 31: I2C1 event interrupt */
+#  define STM32_IRQ_I2C1ER      (48) /* 32: I2C1 error interrupt */
+#  define STM32_IRQ_I2C2EV      (49) /* 33: I2C2 event interrupt */
+#  define STM32_IRQ_I2C2ER      (50) /* 34: I2C2 error interrupt */
+#  define STM32_IRQ_SPI1        (51) /* 35: SPI1 global interrupt */
+#  define STM32_IRQ_SPI2        (52) /* 36: SPI2 global interrupt */
+#  define STM32_IRQ_USART1      (53) /* 37: USART1 global interrupt */
+#  define STM32_IRQ_USART2      (54) /* 38: USART2 global interrupt */
+#  define STM32_IRQ_USART3      (55) /* 39: USART3 global interrupt */
+#  define STM32_IRQ_EXTI1510    (56) /* 40: EXTI Line[15:10] interrupts */
+#  define STM32_IRQ_RTCALR      (57) /* 41: RTC alarm through EXTI line interrupt */
+#  define STM32_IRQ_USBWKUP     (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/
+#  define STM32_IRQ_TIM8BRK     (59) /* 43: TIM8 Break interrupt */
+#  define STM32_IRQ_TIM8UP      (60) /* 44: TIM8 Update interrupt */
+#  define STM32_IRQ_TIM8TRGCOM  (61) /* 45: TIM8 Trigger and Commutation interrupts */
+#  define STM32_IRQ_TIM8CC      (62) /* 46: TIM8 Capture Compare interrupt */
+#  define STM32_IRQ_ADC3        (63) /* 47: ADC3 global interrupt */
+#  define STM32_IRQ_FSMC        (64) /* 48: FSMC global interrupt */
+#  define STM32_IRQ_SDIO        (65) /* 49: SDIO global interrupt */
+#  define STM32_IRQ_TIM5        (66) /* 50: TIM5 global interrupt */
+#  define STM32_IRQ_SPI3        (67) /* 51: SPI3 global interrupt */
+#  define STM32_IRQ_UART4       (68) /* 52: UART4 global interrupt */
+#  define STM32_IRQ_UART5       (69) /* 53: UART5 global interrupt */
+#  define STM32_IRQ_TIM6        (70) /* 54: TIM6 global interrupt */
+#  define STM32_IRQ_TIM7        (71) /* 55: TIM7 global interrupt */
+#  define STM32_IRQ_DMA2CH1     (72) /* 56: DMA2 Channel 1 global interrupt */
+#  define STM32_IRQ_DMA2CH2     (73) /* 57: DMA2 Channel 2 global interrupt */
+#  define STM32_IRQ_DMA2CH3     (74) /* 58: DMA2 Channel 3 global interrupt */
+#  define STM32_IRQ_DMA2CH45    (75) /* 59: DMA2 Channel 4&5 global interrupt */
+#  define NR_IRQS               (76)
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32_IRQ_H */
+
--- a/arch/arm/src/cortexm3/up_hardfault.c
+++ b/arch/arm/src/cortexm3/up_hardfault.c
@@ -135,7 +135,7 @@ int up_hardfault(int irq, FAR void *context)
 #endif

  (void)irqsave();
-  dbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
+  lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
  PANIC(OSERR_UNEXPECTEDISR);
  return OK;
 }
--- a/arch/arm/src/lm3s/lm3s_ethernet.c
+++ b/arch/arm/src/lm3s/lm3s_ethernet.c
@@ -127,6 +127,14 @@
 #define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
 #define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)

+/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */
+
+#ifdef CONFIG_LM3S_DUMPPACKET
+#  define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
+#else
+#  define lm3s_dumppacket(m,a,n)
+#endif
+
 /* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */

 #define LM3S_WDDELAY   (1*CLK_TCK)
@@ -334,7 +342,7 @@ static void lm3s_ethreset(struct lm3s_driver_s *priv)
  regval  = getreg32(LM3S_SYSCON_RCGC2);
  regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
  putreg32(regval, LM3S_SYSCON_RCGC2);
-  nvdbg("RCGC2: %08x\n", regval);
+  nllvdbg("RCGC2: %08x\n", regval);

  /* Put the Ethernet controller into the reset state */

@@ -350,7 +358,7 @@ static void lm3s_ethreset(struct lm3s_driver_s *priv)

  regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
  putreg32(regval, LM3S_SYSCON_SRCR2);
-  nvdbg("SRCR2: %08x\n", regval);
+  nllvdbg("SRCR2: %08x\n", regval);

  /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */

@@ -483,6 +491,7 @@ static int lm3s_transmit(struct lm3s_driver_s *priv)
      /* Increment statistics */

      EMAC_STAT(priv, tx_packets);
+      lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);

      /* Transfer the packet into the Tx FIFO.  The LS 16-bits of the first
       * 32-bit word written to the Tx FIFO contains the Ethernet payload
@@ -491,11 +500,11 @@ static int lm3s_transmit(struct lm3s_driver_s *priv)
       */

      pktlen     = priv->ld_dev.d_len;
-      nvdbg("Sending packet, pktlen: %d\n", pktlen);
+      nllvdbg("Sending packet, pktlen: %d\n", pktlen);
      DEBUGASSERT(pktlen > UIP_LLH_LEN);

      dbuf       = priv->ld_dev.d_buf;
-      regval     = (uint32)(pktlen - 4);
+      regval     = (uint32)(pktlen - 14);
      regval    |= ((uint32)(*dbuf++) << 16);
      regval    |= ((uint32)(*dbuf++) << 24);
      lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
@@ -579,7 +588,7 @@ static int lm3s_uiptxpoll(struct uip_driver_s *dev)
   * the field d_len is set to a value > 0.
   */

-  nvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len);
+  nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len);
  if (priv->ld_dev.d_len > 0)
    {
      /* Send the packet.  lm3s_transmit() will return zero if the
@@ -588,7 +597,7 @@ static int lm3s_uiptxpoll(struct uip_driver_s *dev)

      DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
      uip_arp_out(&priv->ld_dev);
-      ret =lm3s_transmit(priv);
+      ret = lm3s_transmit(priv);
    }

  /* If zero is returned, the polling will continue until all connections have
@@ -639,12 +648,13 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
       * word from the FIFO followed by the Ethernet header beginning
       * in the MS 16-bits of the first word.
       *
-       * Pick off the packet length from the first word.
+       * Pick off the packet length from the first word.  This packet length
+       * includes the len/type field (size 2) and the FCS (size 4).
       */

      regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET);
      pktlen = (int)(regval & 0x0000ffff);
-      nvdbg("Receiving packet, pktlen: %d\n", pktlen);
+      nllvdbg("Receiving packet, pktlen: %d\n", pktlen);

      /* Check if the pktlen is valid.  It should be large enough to
       * hold an Ethernet header and small enough to fit entirely in
@@ -657,13 +667,14 @@ static void lm3s_receive(struct lm3s_driver_s *priv)

          /* We will have to drop this packet */

+          nlldbg("Bad packet size dropped (%d)\n", pktlen);
          EMAC_STAT(priv, rx_pktsize);

-          /* This is the number of bytes and words left to read (including,
-           * the final, possibly partial word).
+          /* The number of bytes and words left to read is pktlen - 4 (including,
+           * the final, possibly partial word) because we've already read 4 bytes.
           */

-          wordlen = (pktlen + 1) >> 4;
+          wordlen = (pktlen - 1) >> 2;

          /* Read and discard the remaining words in the FIFO */

@@ -682,9 +693,12 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
      *dbuf++   = (ubyte)((regval >> 16) & 0xff);
      *dbuf++   = (ubyte)((regval >> 24) & 0xff);

-      /* Read all of the whole, 32-bit values in the middle of the packet */
+      /* Read all of the whole, 32-bit values in the middle of the packet.
+       * We've already read the length (2 bytes) plus the first two bytes
+       * of data
+       */

-      for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4)
+      for (bytesleft = pktlen - 4; bytesleft > 3; bytesleft -= 4, dbuf += 4)
        {
          /* Transfer a whole word to the user buffer.  Note, the user
           * buffer may be un-aligned.
@@ -716,9 +730,13 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
            }
        }

-      /* Pass the packet length to uIP */
+      lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, pktlen);

-      priv->ld_dev.d_len = pktlen;
+      /* Pass the packet length to uIP MINUS 2 bytes for the length and
+       * 4 bytes for the FCS.
+       */
+
+      priv->ld_dev.d_len = pktlen - 6;

      /* We only accept IP packets of the configured type and ARP packets */

@@ -728,7 +746,7 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
      if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP))
 #endif
        {
-          nvdbg("IP packet received (%02x)\n", ETHBUF->type);
+          nllvdbg("IP packet received (%02x)\n", ETHBUF->type);
          EMAC_STAT(priv, rx_ip);

          uip_arp_ipin();
@@ -746,7 +764,7 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
        }
      else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP))
        {
-          nvdbg("ARP packet received (%02x)\n", ETHBUF->type);
+          nllvdbg("ARP packet received (%02x)\n", ETHBUF->type);
          EMAC_STAT(priv, rx_arp);

          uip_arp_arpin(&priv->ld_dev);
@@ -763,7 +781,7 @@ static void lm3s_receive(struct lm3s_driver_s *priv)
 #ifdef CONFIG_DEBUG
      else
        {
-          ndbg("Unsupported packet type dropped (%02x)\n", ETHBUF->type);
+          nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type));
          EMAC_STAT(priv, rx_dropped);
        }
 #endif
@@ -915,9 +933,9 @@ static void lm3s_txtimeout(int argc, uint32 arg, ...)
 {
  struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg;

-  /* Increment statistics and dump debug info */
+  /* Increment statistics */

-  ndbg("Tx timeout\n");
+  nlldbg("Tx timeout\n");
  EMAC_STAT(priv, tx_timeouts);

  /* Then reset the hardware */
@@ -997,7 +1015,7 @@ static int lm3s_ifup(struct uip_driver_s *dev)
  uint32 div;
  uint16 phyreg;

-  ndbg("Bringing up: %d.%d.%d.%d\n",
+  nlldbg("Bringing up: %d.%d.%d.%d\n",
       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );

@@ -1018,7 +1036,7 @@ static int lm3s_ifup(struct uip_driver_s *dev)

  div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
  lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
-  nvdbg("MDV:   %08x\n", div);
+  nllvdbg("MDV:   %08x\n", div);

  /* Then configure the Ethernet Controller for normal operation 
   *
@@ -1030,7 +1048,7 @@ static int lm3s_ifup(struct uip_driver_s *dev)
  regval &= ~LM3S_TCTCL_CLRBITS;
  regval |= LM3S_TCTCL_SETBITS;
  lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
-  nvdbg("TCTL:  %08x\n", regval);
+  nllvdbg("TCTL:  %08x\n", regval);

  /* Setup the receive control register (Disable multicast frames, disable
   * promiscuous mode, disable bad CRC rejection).
@@ -1040,7 +1058,7 @@ static int lm3s_ifup(struct uip_driver_s *dev)
  regval &= ~LM3S_RCTCL_CLRBITS;
  regval |= LM3S_RCTCL_SETBITS;
  lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
-  nvdbg("RCTL:  %08x\n", regval);
+  nllvdbg("RCTL:  %08x\n", regval);

  /* Setup the time stamp configuration register */

@@ -1052,7 +1070,7 @@ static int lm3s_ifup(struct uip_driver_s *dev)
  regval &= ~(MAC_TS_EN);
 #endif
  lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
-  nvdbg("TS:    %08x\n", regval);
+  nllvdbg("TS:    %08x\n", regval);
 #endif

  /* Wait for the link to come up.  This following is not very conservative
@@ -1061,13 +1079,13 @@ static int lm3s_ifup(struct uip_driver_s *dev)
   * set
   */

-  ndbg("Waiting for link\n");
+  nlldbg("Waiting for link\n");
  do
    {
      phyreg = lm3s_phyread(priv, MII_MSR);
    }
  while ((phyreg & MII_MSR_LINKSTATUS) == 0);
-  ndbg("Link established\n");
+  nlldbg("Link established\n");

  /* Reset the receive FIFO */

@@ -1151,7 +1169,7 @@ static int lm3s_ifdown(struct uip_driver_s *dev)
  irqstate_t flags;
  uint32 regval;

-  ndbg("Taking down: %d.%d.%d.%d\n",
+  nlldbg("Taking down: %d.%d.%d.%d\n",
       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );

--- a/arch/arm/src/lm3s/lm3s_internal.h
+++ b/arch/arm/src/lm3s/lm3s_internal.h
@@ -230,7 +230,7 @@ EXTERN void up_lowsetup(void);
 * Name: lm3s_clockconfig
 *
 * Description:
- *   Called to check to new clock based on desired rcc and rcc2 settings.
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
 *   This is use to set up the initial clocking but can be used later to
 *   support slow clocked, low power consumption modes.
 *
--- a/arch/arm/src/lm3s/lm3s_irq.c
+++ b/arch/arm/src/lm3s/lm3s_irq.c
@@ -61,7 +61,7 @@
 * bringup
 */

-#undef LM2S_IRQ_DEBUG
+#undef LM3S_IRQ_DEBUG

 /* Get a 32-bit version of the default priority */

@@ -93,7 +93,7 @@ uint32 *current_regs;
 *
 ****************************************************************************/

-#if defined(LM2S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
+#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
 static void lm3s_dumpnvic(const char *msg, int irq)
 {
  irqstate_t flags;
@@ -197,7 +197,7 @@ static int lm3s_reserved(int irq, FAR void *context)
 #endif

 /****************************************************************************
- * Name: lml3s_irqinfo
+ * Name: lm3s_irqinfo
 *
 * Description:
 *   Given an IRQ number, provide the register and bit setting to enable or
@@ -205,7 +205,7 @@ static int lm3s_reserved(int irq, FAR void *context)
 *
 ****************************************************************************/

-static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
+static int lm3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
 {
  DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);

@@ -336,7 +336,7 @@ void up_irqinitialize(void)
  irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved);
 #endif

-  lm3s_dumpnvic("inital", NR_IRQS);
+  lm3s_dumpnvic("initial", NR_IRQS);

 #ifndef CONFIG_SUPPRESS_INTERRUPTS

@@ -367,7 +367,7 @@ void up_disable_irq(int irq)
  uint32 regval;
  uint32 bit;

-  if (lml3s_irqinfo(irq, &regaddr, &bit) == 0)
+  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
    {
      /* Clear the appropriate bit in the register to enable the interrupt */

@@ -392,7 +392,7 @@ void up_enable_irq(int irq)
  uint32 regval;
  uint32 bit;

-  if (lml3s_irqinfo(irq, &regaddr, &bit) == 0)
+  if (lm3s_irqinfo(irq, &regaddr, &bit) == 0)
    {
      /* Set the appropriate bit in the register to enable the interrupt */

--- a/arch/arm/src/lm3s/lm3s_start.c
+++ b/arch/arm/src/lm3s/lm3s_start.c
@@ -136,9 +136,7 @@ void __start(void)

  /* Initialize onboard resources */

-#ifdef CONFIG_ARCH_LEDS
  lm3s_boardinitialize();
-#endif
  showprogress('E');

  /* Then start NuttX */
--- a/arch/arm/src/lm3s/lm3s_syscontrol.c
+++ b/arch/arm/src/lm3s/lm3s_syscontrol.c
@@ -177,7 +177,7 @@ static inline void lm3s_plllock(void)
 * Name: lm3s_clockconfig
 *
 * Description:
- *   Called to check to new clock based on desired rcc and rcc2 settings.
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
 *   This is use to set up the initial clocking but can be used later to
 *   support slow clocked, low power consumption modes.
 *
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -0,0 +1,51 @@
+############################################################################
+# arch/arm/src/stm32/Make.defs
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= stm32_vectors.S
+
+CMN_ASRCS	= up_context.S
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+		  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
+		  up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
+		  up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
+		  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
+		  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
+		  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
+
+CHIP_ASRCS	= 
+CHIP_CSRCS	= stm32_start.c stm32_rcc.c stm32_gpio.c stm32_irq.c \
+		  stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
+		  stm32_spi.c
+
--- a/arch/arm/src/stm32/chip.h
+++ b/arch/arm/src/stm32/chip.h
@@ -0,0 +1,92 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_H
+#define __ARCH_ARM_SRC_STM32_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip (only the STM32F103Z right now) */
+
+#ifdef CONFIG_ARCH_CHIP_STM32F103ZET6
+#  undef CONFIG_STM32_LOWDENSITY            /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY        /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  define CONFIG_STM32_HIGHDENSITY      1   /* STM32F101x  and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE     /* STM32F105x and STM32F107x */
+#  define STM32_NATIM                   1   /* One advanced timers TIM1 */
+#  define STM32_NGTIM                   4   /* General timers TIM2,3,4,5 */
+#  define STM32 NBTIM                   0   /* No basic timers */
+#  define STM32_NSPI                    2   /* SPI1-2 */
+#  define STM32_NUSART                  3   /* USART1-3 */
+#  define STM32_NI2C                    2   /* I2C1-2 */
+#  define STM32_NCAN                    1   /* bxCAN1 */
+#  define STM32_NSDIO                   1   /* 1 */
+#  define STM32_NGPIO                   112 /* GPIOA-G */
+#  define STM32_NADC                    1   /* ADC1 */
+#  define STM32_NDAC                    0   /* No DAC */
+#  define STM32_NCRC                    0   /* No CRC */
+#  define STM32_NTHERNET                0   /* No ethernet */
+#else
+#  error "Unsupported STM32 chip"
+#endif
+
+/* Include only the memory map.  Other chip hardware files should then include this
+ * file for the proper setup
+ */
+
+#include "stm32_memorymap.h"
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */
--- a/arch/arm/src/stm32/stm32_adc.h
+++ b/arch/arm/src/stm32/stm32_adc.h
@@ -0,0 +1,341 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_adc.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32_STM32_ADC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_ADC_SR_OFFSET      0x0000  /* ADC status register (32-bit) */
+#define STM32_ADC_CR1_OFFSET     0x0004  /* ADC control register 1 (32-bit) */
+#define STM32_ADC_CR2_OFFSET     0x0008  /* ADC control register 2 (32-bit) */
+#define STM32_ADC_SMPR1_OFFSET   0x000c  /* ADC sample time register 1 (32-bit) */
+#define STM32_ADC_SMPR2_OFFSET   0x0010  /* ADC sample time register 2 (32-bit) */
+#define STM32_ADC_JOFR1_OFFSET   0x0014  /* ADC injected channel data offset register 1 (32-bit) */
+#define STM32_ADC_JOFR2_OFFSET   0x0018  /* ADC injected channel data offset register 2 (32-bit) */
+#define STM32_ADC_JOFR3_OFFSET   0x001c  /* ADC injected channel data offset register 3 (32-bit) */
+#define STM32_ADC_JOFR4_OFFSET   0x0020  /* ADC injected channel data offset register 4 (32-bit) */
+#define STM32_ADC_HTR_OFFSET     0x0024  /* ADC watchdog high threshold register (32-bit) */
+#define STM32_ADC_LTR_OFFSET     0x0028  /* ADC watchdog low threshold register (32-bit) */
+#define STM32_ADC_SQR1_OFFSET    0x002c  /* ADC regular sequence register 1 (32-bit) */
+#define STM32_ADC_SQR2_OFFSET    0x0030  /* ADC regular sequence register 2 (32-bit) */
+#define STM32_ADC_SQR3_OFFSET    0x0034  /* ADC regular sequence register 3 (32-bit) */
+#define STM32_ADC_JSQR_OFFSET    0x0038  /* ADC injected sequence register (32-bit) */
+#define STM32_ADC_JDR1_OFFSET    0x003c  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR2_OFFSET    0x0040  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR3_OFFSET    0x0044  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_JDR4_OFFSET    0x0048  /* ADC injected data register 1 (32-bit) */
+#define STM32_ADC_DR_OFFSET      0x004c  /* ADC regular data register (32-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NADC > 0
+#  define STM32_ADC1_SR          (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
+#  define STM32_ADC1_CR1         (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
+#  define STM32_ADC1_CR2         (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
+#  define STM32_ADC1_SMPR1       (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
+#  define STM32_ADC1_SMPR2       (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
+#  define STM32_ADC1_JOFR1       (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
+#  define STM32_ADC1_JOFR2       (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
+#  define STM32_ADC1_JOFR3       (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
+#  define STM32_ADC1_JOFR4       (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
+#  define STM32_ADC1_HTR         (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
+#  define STM32_ADC1_LTR         (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
+#  define STM32_ADC1_SQR1        (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
+#  define STM32_ADC1_SQR2        (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
+#  define STM32_ADC1_SQR3        (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
+#  define STM32_ADC1_JSQR        (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
+#  define STM32_ADC1_JDR1        (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
+#  define STM32_ADC1_JDR2        (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
+#  define STM32_ADC1_JDR3        (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
+#  define STM32_ADC1_JDR4        (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
+#  define STM32_ADC1_DR          (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+#if STM32_NADC > 1
+#  define STM32_ADC2_SR          (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
+#  define STM32_ADC2_CR1         (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
+#  define STM32_ADC2_CR2         (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
+#  define STM32_ADC2_SMPR1       (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
+#  define STM32_ADC2_SMPR2       (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
+#  define STM32_ADC2_JOFR1       (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
+#  define STM32_ADC2_JOFR2       (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
+#  define STM32_ADC2_JOFR3       (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
+#  define STM32_ADC2_JOFR4       (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
+#  define STM32_ADC2_HTR         (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
+#  define STM32_ADC2_LTR         (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
+#  define STM32_ADC2_SQR1        (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
+#  define STM32_ADC2_SQR2        (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
+#  define STM32_ADC2_SQR3        (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
+#  define STM32_ADC2_JSQR        (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
+#  define STM32_ADC2_JDR1        (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
+#  define STM32_ADC2_JDR2        (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
+#  define STM32_ADC2_JDR3        (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
+#  define STM32_ADC2_JDR4        (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
+#  define STM32_ADC2_DR          (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* ADC status register */
+
+#define ADC_SR_AWD              (1 << 0)  /* Bit 0 : Analog watchdog flag */
+#define ADC_SR_EOC              (1 << 1)  /* Bit 1 : End of conversion */
+#define ADC_SR_JEOC             (1 << 2)  /* Bit 2 : Injected channel end of conversion */
+#define ADC_SR_JSTRT            (1 << 3)  /* Bit 3 : Injected channel Start flag */
+#define ADC_SR_STRT             (1 << 4)  /* Bit 4 : Regular channel Start flag */
+
+/* ADC control register 1 */
+
+#define ADC_CR1_AWDCH_SHIFT     (0)       /* Bits 4-0: Analog watchdog channel select bits */
+#define ADC_CR1_AWDCH_MASK      (0x1f << ADC_CR1_AWDCH_SHIFT)
+#define ADC_CR1_EOCIE           (1 << 5)  /* Bit 5: Interrupt enable for EOC */
+#define ADC_CR1_AWDIE           (1 << 6)  /* Bit 6: Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE          (1 << 7)  /* Bit 7: Interrupt enable for injected channels */
+#define ADC_CR1_SCAN            (1 << 8)  /* Bit 8: Scan mode */
+#define ADC_CR1_AWDSGL          (1 << 9)  /* Bit 9: Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO           (1 << 10) /* Bit 10: Automatic Injected Group conversion */
+#define ADC_CR1_DISCEN          (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN         (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_MASK    (0x07 << ADC_CR1_DISCNUM_SHIFT)
+#define ADC_CR1_DISCNUM_SHIFT   (13)      /* Bits 15-13: Discontinuous mode channel count */
+#define ADC_CR1_DUALMOD_MASK    (0x0f << ADC_CR1_DUALMOD_SHIFT)
+#  define ADC_CR1_IND           (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */
+#  define ADC_CR1_RSIS          (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */
+#  define ADC_CR1_RSAT          (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */
+#  define ADC_CR1_ISFI          (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */
+#  define ADC_CR1_ISFL          (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */
+#  define ADC_CR1_IS            (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */
+#  define ADC_CR1_RS            (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */
+#  define ADC_CR1_FI            (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */
+#  define ADC_CR1_SI            (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */
+#  define ADC_CR1_AT            (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */
+#define ADC_CR1_DUALMOD_SHIFT   (16)      /* Bits 19-16: Dual mode selection */
+#define ADC_CR1_JAWDEN          (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN           (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
+
+/* ADC control register 2 */
+
+#define ADC_CR2_ADON            (1 << 0)  /* Bit 0: A/D Converter ON / OFF */
+#define ADC_CR2_CONT            (1 << 1)  /* Bit 1: Continuous Conversion */
+#define ADC_CR2_CAL             (1 << 2)  /* Bit 2: A/D Calibration */
+#define ADC_CR2_RSTCAL          (1 << 3)  /* Bit 3: Reset Calibration */
+#define ADC_CR2_DMA             (1 << 8)  /* Bit 8: Direct Memory access mode */
+#define ADC_CR2_ALIGN           (1 << 11) /* Bit 11: Data Alignment */
+#define ADC_CR2_JEXTSEL_SHIFT   (12)      /* Bits 14-12: External event select for injected group */
+#define ADC_CR2_JEXTSEL_MASK    (7 << ADC_CR2_JEXTSEL_SHIFT)
+#  define ADC_CR2_T1TRG0        (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
+#  define ADC_CR2_T1CC4         (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */
+#  define ADC_CR2_T2TRG0        (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
+#  define ADC_CR2_T2CC1         (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
+#  define ADC_CR2_T3CC4         (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
+#  define ADC_CR2_T4TRG0        (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
+#  define ADC_CR2_EXTI15        (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */
+#  define ADC_CR2_JSWSTART      (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
+#define ADC_CR2_JEXTTRIG        (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */
+#define ADC_CR2_EXTSEL_SHIFT    (17)      /* Bits 19-17: External Event Select for regular group */
+#define ADC_CR2_EXTSEL_MASK     (7 << ADC_CR2_EXTSEL_SHIFT)
+#  define ADC_CR2_T1CC1         (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */
+#  define ADC_CR2_T1CC2         (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */
+#  define ADC_CR2_T1CC3         (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */
+#  define ADC_CR2_T2CC2         (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
+#  define ADC_CR2_T3TRG0        (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
+#  define ADC_CR2_T4CC4         (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
+#  define ADC_CR2_EXTI11        (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */
+#  define ADC_CR2_SWSTART       (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
+#define ADC_CR2_EXTTRIG         (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART        (1 << 21) /* Bit 21: Start Conversion of injected channels */
+#define ADC_CR2_SWSTART         (1 << 22) /* Bit 22: Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE         (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */
+
+/* ADC sample time register 1 */
+
+#define ADC_SMPR1_SMP10_SHIFT   (0)       /* Bits 2-0: Channel 10 Sample time selection */
+#define ADC_SMPR1_SMP10_MASK    (7 << ADC_SMPR1_SMP10_SHIFT)
+#define ADC_SMPR1_SMP11_SHIFT   (3)       /* Bits 5-3: Channel 11 Sample time selection */
+#define ADC_SMPR1_SMP11_MASK    (7 << ADC_SMPR1_SMP11_SHIFT)
+#define ADC_SMPR1_SMP12_SHIFT   (6)       /* Bits 8-6: Channel 12 Sample time selection */
+#define ADC_SMPR1_SMP12_MASK    (7 << ADC_SMPR1_SMP12_SHIFT)
+#define ADC_SMPR1_SMP13_SHIFT   (9)       /* Bits 11-9: Channel 13 Sample time selection */
+#define ADC_SMPR1_SMP13_MASK    (7 << ADC_SMPR1_SMP13_SHIFT)
+#define ADC_SMPR1_SMP14_SHIFT   (12)      /* Bits 14-12: Channel 14 Sample time selection */
+#define ADC_SMPR1_SMP14_MASK    (7 << ADC_SMPR1_SMP14_SHIFT)
+#define ADC_SMPR1_SMP15_SHIFT   (15)      /* Bits 17-15: Channel 15 Sample time selection */
+#define ADC_SMPR1_SMP15_MASK    (7 << ADC_SMPR1_SMP15_SHIFT)
+#define ADC_SMPR1_SMP16_SHIFT   (18)      /* Bits 20-18: Channel 16 Sample time selection */
+#define ADC_SMPR1_SMP16_MASK    (7 << ADC_SMPR1_SMP16_SHIFT)
+#define ADC_SMPR1_SMP17_SHIFT   (21)      /* Bits 23-21: Channel 17 Sample time selection */
+#define ADC_SMPR1_SMP17_MASK    (7 << ADC_SMPR1_SMP17_SHIFT)
+
+#define ADC_SMPR_1p5            0         /* 000: 1.5 cycles */
+#define ADC_SMPR_7p5            1         /* 001: 7.5 cycles */
+#define ADC_SMPR_13p5           2         /* 010: 13.5 cycles */
+#define ADC_SMPR_28p5           3         /* 011: 28.5 cycles */
+#define ADC_SMPR_41p5           4         /* 100: 41.5 cycles */
+#define ADC_SMPR_55p5           5         /* 101: 55.5 cycles */
+#define ADC_SMPR_71p5           6         /* 110: 71.5 cycles */
+#define ADC_SMPR_239p5          7         /* 111: 239.5 cycles */
+
+/* ADC sample time register 2 */
+
+#define ADC_SMPR2_SMP0_SHIFT    (0)       /* Bits 2-0: Channel 0 Sample time selection */
+#define ADC_SMPR2_SMP0_MASK     (7 << ADC_SMPR1_SMP0_SHIFT)
+#define ADC_SMPR2_SMP1_SHIFT    (3)       /* Bits 5-3: Channel 1 Sample time selection */
+#define ADC_SMPR2_SMP1_MASK     (7 << ADC_SMPR1_SMP1_SHIFT)
+#define ADC_SMPR2_SMP2_SHIFT    (6)       /* Bits 8-6: Channel 2 Sample time selection */
+#define ADC_SMPR2_SMP2_MASK     (7 << ADC_SMPR1_SMP2_SHIFT)
+#define ADC_SMPR2_SMP3_SHIFT    (9)       /* Bits 11-9: Channel 3 Sample time selection */
+#define ADC_SMPR2_SMP3_MASK     (7 << ADC_SMPR1_SMP3_SHIFT)
+#define ADC_SMPR2_SMP4_SHIFT    (12)      /* Bits 14-12: Channel 4 Sample time selection */
+#define ADC_SMPR2_SMP4_MASK     (7 << ADC_SMPR1_SMP4_SHIFT)
+#define ADC_SMPR2_SMP5_SHIFT    (15)      /* Bits 17-15: Channel 5 Sample time selection */
+#define ADC_SMPR2_SMP5_MASK     (7 << ADC_SMPR1_SMP5_SHIFT)
+#define ADC_SMPR2_SMP6_SHIFT    (18)      /* Bits 20-18: Channel 6 Sample time selection */
+#define ADC_SMPR2_SMP6_MASK     (7 << ADC_SMPR1_SMP6_SHIFT)
+#define ADC_SMPR2_SMP7_SHIFT    (21)      /* Bits 23-21: Channel 7 Sample time selection */
+#define ADC_SMPR2_SMP7_MASK     (7 << ADC_SMPR1_SMP7_SHIFT)
+#define ADC_SMPR2_SMP8_SHIFT    (24)      /* Bits 26-24: Channel 8 Sample time selection */
+#define ADC_SMPR2_SMP8_MASK     (7 << ADC_SMPR1_SMP8_SHIFT)
+#define ADC_SMPR2_SMP9_SHIFT    (27)      /* Bits 29-27: Channel 9 Sample time selection */
+#define ADC_SMPR2_SMP9_MASK     (7 << ADC_SMPR1_SMP9_SHIFT)
+
+/* ADC injected channel data offset register 1-4 */
+
+#define ADC_JOFR_SHIFT         (0)        /* Bits 11-0: Data offset for injected channel x */
+#define ADC_JOFR_MASK          (0x0fff << ADC_JOFR_SHIFT)
+
+/* ADC watchdog high threshold register */
+
+#define ADC_HTR_SHIFT          (0)        /* Bits 11-0: Analog watchdog high threshold */
+#define ADC_HTR_MASK           (0x0fff << ADC_HTR_SHIFT)
+
+/* ADC watchdog low threshold register */
+
+#define ADC_LTR_SHIFT          (0)        /* Bits 11:0: Analog watchdog low threshold */
+#define ADC_LTR_MASK           (0x0fff << ADC_LTR_SHIFT)
+
+/* ADC regular sequence register 1 */
+
+#define ADC_SQR1_SQ13_SHIFT   (0)         /* Bits 4-0: 13th conversion in regular sequence */
+#define ADC_SQR1_SQ13_MASK    (0x1f << ADC_SQR1_SQ13_SHIFT)
+#define ADC_SQR1_SQ14_SHIFT   (5)         /* Bits 9-5: 14th conversion in regular sequence */
+#define ADC_SQR1_SQ14_MASK    (0x1f << ADC_SQR1_SQ14_SHIFT)
+#define ADC_SQR1_SQ15_SHIFT   (10)        /* Bits 14-10: 15th conversion in regular sequence */
+#define ADC_SQR1_SQ15_MASK    (0x1f << ADC_SQR1_SQ15_SHIFT)
+#define ADC_SQR1_SQ16_SHIFT   (15)        /* Bits 19-15: 16th conversion in regular sequence */
+#define ADC_SQR1_SQ16_MASK    (0x1f << ADC_SQR1_SQ16_SHIFT)
+#define ADC_SQR1_L_SHIFT      (20)        /* Bits 23:20 L[3:0]: Regular channel sequence length */
+#define ADC_SQR1_L_MASK       (0x0f << ADC_SQR1_L_SHIFT)
+
+/* ADC regular sequence register 2 */
+
+#define ADC_SQR1_SQ7_SHIFT    (0)         /* Bits 4-0: 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_MASK     (0x1f << ADC_SQR2_SQ7_SHIFT)
+#define ADC_SQR2_SQ8_SHIFT    (5)         /* Bits 9-5: 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_MASK     (0x1f << ADC_SQR2_SQ8_SHIFT)
+#define ADC_SQR2_SQ9_SHIFT    (10)        /* Bits 14-10: 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_MASK     (0x1f << ADC_SQR2_SQ9_SHIFT)
+#define ADC_SQR2_SQ10_SHIFT   (15)        /* Bits 19-15: 10th conversion in regular sequence */
+#define ADC_SQR2_SQ10_MASK    (0x1f << ADC_SQR2_SQ10_SHIFT)
+#define ADC_SQR2_SQ11_SHIFT   (20)        /* Bits 24:20: 11th conversion in regular sequence */
+#define ADC_SQR2_SQ11_MASK    (0x1f << ADC_SQR2_SQ11_SHIFT )
+#define ADC_SQR2_SQ12_SHIFT   (25)        /* Bits 29:25: 12th conversion in regular sequence */
+#define ADC_SQR2_SQ12_MASK    (0x1f << ADC_SQR2_SQ12_SHIFT)
+
+/* ADC regular sequence register 3 */
+
+#define ADC_SQR3_SQ1_SHIFT    (0)         /* Bits 4-0: 1st conversion in regular sequence */
+#define ADC_SQR3_SQ1_MASK     (0x1f << ADC_SQR3_SQ1_SHIFT)
+#define ADC_SQR3_SQ2_SHIFT    (5)         /* Bits 9-5: 2nd conversion in regular sequence */
+#define ADC_SQR3_SQ2_MASK     (0x1f << ADC_SQR3_SQ2_SHIFT)
+#define ADC_SQR3_SQ3_SHIFT    (10)        /* Bits 14-10: 3rd conversion in regular sequence */
+#define ADC_SQR3_SQ3_MASK     (0x1f << ADC_SQR3_SQ3_SHIFT)
+#define ADC_SQR3_SQ4_SHIFT    (15)        /* Bits 19-15: 4th conversion in regular sequence */
+#define ADC_SQR3_SQ4_MASK     (0x1f << ADC_SQR3_SQ4_SHIFT)
+#define ADC_SQR3_SQ5_SHIFT    (20)        /* Bits 24:20: 5th conversion in regular sequence */
+#define ADC_SQR3_SQ5_MASK     (0x1f << ADC_SQR3_SQ5_SHIFT )
+#define ADC_SQR3_SQ6_SHIFT    (25)        /* Bits 29:25: 6th conversion in regular sequence */
+#define ADC_SQR3_SQ6_MASK     (0x1f << ADC_SQR3_SQ6_SHIFT)
+
+/* ADC injected sequence register */
+
+#define ADC_JSQR_JSQ1_SHIFT   (0)        /* Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_MASK    (0x1f << ADC_JSQR_JSQ1_SHIFT)
+#define ADC_JSQR_JSQ2_SHIFT   (5)        /* Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_MASK    (0x1f << ADC_JSQR_JSQ2_MASK)
+#define ADC_JSQR_JSQ3_SHIFT   (10)       /* Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_MASK    (0x1f << ADC_JSQR_JSQ3_SHIFT)
+#define ADC_JSQR_JSQ4_SHIFT   (15)       /* Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_MASK    (0x1f << ADC_JSQR_JSQ4_SHIFT)
+#define ADC_JSQR_JL_SHIFT     (20)       /* Bits 21:20 JL[1:0]: Injected Sequence length */
+#define ADC_JSQR_JL_MASK      (3 << ADC_JSQR_JL_SHIFT)
+
+/* ADC injected data register 1-4 */
+
+#define ADC_JDR_SHIFT         (0)        /* Bits 15-0: Injected data */
+#define ADC_JDR_MASK          (0xffff << ADC_JDR_SHIFT)
+
+/* ADC regular data register */
+
+#define ADC_DR_DATA_SHIFT     (0)        /* Bits 15:0 Regular data */
+#define ADC_DR_DATA_MASK      (0xffff << yyyy)
+#define ADC_DR_ADC2DATA_SHIFT (16)       /* Bits 31:16: ADC2 data */
+#define ADC_DR_ADC2DATA_MASK  (0xffff << yyyy)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */
--- a/arch/arm/src/stm32/stm32_bkp.h
+++ b/arch/arm/src/stm32/stm32_bkp.h
@@ -0,0 +1,210 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_bkp.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_BKP_H
+#define __ARCH_ARM_SRC_STM32_STM32_BKP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define CONFIG_STM32_NBKP_BYTES 84
+#  define CONFIG_STM32_NBKP_REGS  42
+#else
+#  define CONFIG_STM32_NBKP_BYTES 20
+#  define CONFIG_STM32_NBKP_REGS  10
+#endif
+
+/* Register Offsets *****************************************************************/
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n))
+#else
+#  define STM32_BKP_DR_OFFSET(n)  (0x0004+4*(n))
+#endif
+
+#define STM32_BKP_DR1_OFFSET     0x0004  /* Backup data register 1 */
+#define STM32_BKP_DR2_OFFSET     0x0008  /* Backup data register 2 */
+#define STM32_BKP_DR3_OFFSET     0x000c  /* Backup data register 3 */
+#define STM32_BKP_DR4_OFFSET     0x0010  /* Backup data register 4 */
+#define STM32_BKP_DR5_OFFSET     0x0014  /* Backup data register 5 */
+#define STM32_BKP_DR6_OFFSET     0x0018  /* Backup data register 6 */
+#define STM32_BKP_DR7_OFFSET     0x001c  /* Backup data register 7 */
+#define STM32_BKP_DR8_OFFSET     0x0020  /* Backup data register 8 */
+#define STM32_BKP_DR9_OFFSET     0x0024  /* Backup data register 9 */
+#define STM32_BKP_DR10_OFFSET    0x0028  /* Backup data register 10 */
+
+#define STM32_BKP_RTCCR_OFFSET   0x002c  /* RTC clock calibration register */
+#define STM32_BKP_CR_OFFSET      0x0030  /* Backup control register */
+#define STM32_BKP_CSR_OFFSET     0x0034  /* Backup control/status register */
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define STM32_BKP_DR11_OFFSET  0x0040  /* Backup data register 11 */
+#  define STM32_BKP_DR12_OFFSET  0x0044  /* Backup data register 12 */
+#  define STM32_BKP_DR13_OFFSET  0x0048  /* Backup data register 13 */
+#  define STM32_BKP_DR14_OFFSET  0x004c  /* Backup data register 14 */
+#  define STM32_BKP_DR15_OFFSET  0x0050  /* Backup data register 15 */
+#  define STM32_BKP_DR16_OFFSET  0x0054  /* Backup data register 16 */
+#  define STM32_BKP_DR17_OFFSET  0x0058  /* Backup data register 17 */
+#  define STM32_BKP_DR18_OFFSET  0x005c  /* Backup data register 18 */
+#  define STM32_BKP_DR19_OFFSET  0x0060  /* Backup data register 19 */
+#  define STM32_BKP_DR20_OFFSET  0x0064  /* Backup data register 20 */
+#  define STM32_BKP_DR21_OFFSET  0x0068  /* Backup data register 21 */
+#  define STM32_BKP_DR22_OFFSET  0x006c  /* Backup data register 22 */
+#  define STM32_BKP_DR23_OFFSET  0x0070  /* Backup data register 23 */
+#  define STM32_BKP_DR24_OFFSET  0x0074  /* Backup data register 24 */
+#  define STM32_BKP_DR25_OFFSET  0x0078  /* Backup data register 25 */
+#  define STM32_BKP_DR26_OFFSET  0x007c  /* Backup data register 26 */
+#  define STM32_BKP_DR27_OFFSET  0x0080  /* Backup data register 27 */
+#  define STM32_BKP_DR28_OFFSET  0x0084  /* Backup data register 28 */
+#  define STM32_BKP_DR29_OFFSET  0x0088  /* Backup data register 29 */
+#  define STM32_BKP_DR30_OFFSET  0x008c  /* Backup data register 30 */
+#  define STM32_BKP_DR31_OFFSET  0x0090  /* Backup data register 31 */
+#  define STM32_BKP_DR32_OFFSET  0x0094  /* Backup data register 32 */
+#  define STM32_BKP_DR33_OFFSET  0x0098  /* Backup data register 33 */
+#  define STM32_BKP_DR34_OFFSET  0x009c  /* Backup data register 34 */
+#  define STM32_BKP_DR35_OFFSET  0x00a0  /* Backup data register 35 */
+#  define STM32_BKP_DR36_OFFSET  0x00a4  /* Backup data register 36 */
+#  define STM32_BKP_DR37_OFFSET  0x00a8  /* Backup data register 37 */
+#  define STM32_BKP_DR38_OFFSET  0x00ac  /* Backup data register 38 */
+#  define STM32_BKP_DR39_OFFSET  0x00b0  /* Backup data register 39 */
+#  define STM32_BKP_DR40_OFFSET  0x00b4  /* Backup data register 40 */
+#  define STM32_BKP_DR41_OFFSET  0x00b8  /* Backup data register 41 */
+#  define STM32_BKP_DR42_OFFSET  0x00bc  /* Backup data register 42 */
+#endif
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_BKP_RTCCR          (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET)
+#define STM32_BKP_CR             (STM32_BKP_BASE+STM32_BKP_CR_OFFSET)
+#define STM32_BKP_CSR            (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET)
+
+#define STM32_BKP_DR(n)          (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n))
+#define STM32_BKP_DR1            (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET)
+#define STM32_BKP_DR2            (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET)
+#define STM32_BKP_DR3            (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET)
+#define STM32_BKP_DR4            (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET)
+#define STM32_BKP_DR5            (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET)
+#define STM32_BKP_DR6            (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET)
+#define STM32_BKP_DR7            (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET)
+#define STM32_BKP_DR8            (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET)
+#define STM32_BKP_DR9            (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET)
+#define STM32_BKP_DR10           (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET)
+
+#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+#  define STM32_BKP_DR11         (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET)
+#  define STM32_BKP_DR12         (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET)
+#  define STM32_BKP_DR13         (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET)
+#  define STM32_BKP_DR14         (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET)
+#  define STM32_BKP_DR15         (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET)
+#  define STM32_BKP_DR16         (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET)
+#  define STM32_BKP_DR17         (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET)
+#  define STM32_BKP_DR18         (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET)
+#  define STM32_BKP_DR19         (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET)
+#  define STM32_BKP_DR20         (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET)
+#  define STM32_BKP_DR21         (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET)
+#  define STM32_BKP_DR22         (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET)
+#  define STM32_BKP_DR23         (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET)
+#  define STM32_BKP_DR24         (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET)
+#  define STM32_BKP_DR25         (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET)
+#  define STM32_BKP_DR26         (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET)
+#  define STM32_BKP_DR27         (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET)
+#  define STM32_BKP_DR28         (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET)
+#  define STM32_BKP_DR29         (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET)
+#  define STM32_BKP_DR30         (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET)
+#  define STM32_BKP_DR31         (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET)
+#  define STM32_BKP_DR32         (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET)
+#  define STM32_BKP_DR33         (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET)
+#  define STM32_BKP_DR34         (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET)
+#  define STM32_BKP_DR35         (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET)
+#  define STM32_BKP_DR36         (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET)
+#  define STM32_BKP_DR37         (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET)
+#  define STM32_BKP_DR38         (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET)
+#  define STM32_BKP_DR39         (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET)
+#  define STM32_BKP_DR40         (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET)
+#  define STM32_BKP_DR41         (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET)
+#  define STM32_BKP_DR42         (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* RTC clock calibration register */
+
+#define BKP_RTCCR_CAL_SHIFT      (0)       /* Bits 6-0: Calibration value */
+#define BKP_RTCCR_CAL_MASK       (0x7f << BKP_RTCCR_CAL_SHIFT)
+#define BKP_RTCCR_CCO            (1 << 7)  /* Bit 7: Calibration Clock Output */
+#define BKP_RTCCR_ASOE           (1 << 8)  /* Bit 8: Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS           (1 << 9)  /* Bit 9: Alarm or Second Output Selection */
+
+/* Backup control register */
+
+#define BKP_CR_TPE               (1 << 0)  /* Bit 0: TAMPER pin enable */
+#define BKP_CR_TPAL              (1 << 1)  /* Bit 1: TAMPER pin active level */
+
+/* Backup control/status register */
+
+#define BKP_CSR_CTE              (1 << 0)  /* Bit 0: Clear Tamper event */
+#define BKP_CSR_CTI              (1 << 1)  /* Bit 1: Clear Tamper Interrupt */
+#define BKP_CSR_TPIE             (1 << 2)  /* Bit 2: TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF              (1 << 8)  /* Bit 8: Tamper Event Flag */
+#define BKP_CSR_TIF              (1 << 9)  /* Bit 9: Tamper Interrupt Flag */
+
+/* Backup data register */
+
+#define BKP_DR_SHIFT             (0)       /* Bits 1510: Backup data */
+#define BKP_DR_MASK              (0xffff << BKP_DR_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */
--- a/arch/arm/src/stm32/stm32_can.h
+++ b/arch/arm/src/stm32/stm32_can.h
@@ -0,0 +1,496 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_CAN.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_CAN_H
+#define __ARCH_ARM_SRC_STM32_STM32_CAN_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* 3 TX mailboxes */
+
+#define CAN_TXMBOX1 0
+#define CAN_TXMBOX2 1
+#define CAN_TXMBOX3 2
+
+/* 2 RX mailboxes */
+
+#define CAN_RXMBOX1 0
+#define CAN_RXMBOX2 1
+
+/* Number of filters depends on silicon */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define CAN_NFILTERS 28
+#else
+#  define CAN_NFILTERS 14
+#endif
+
+/* Register Offsets *****************************************************************/
+
+/* CAN control and status registers */
+
+#define STM32_CAN_MCR_OFFSET      0x0000  /* CAN master control register */
+#define STM32_CAN_MSR_OFFSET      0x0004  /* CAN master status register */
+#define STM32_CAN_TSR_OFFSET      0x0008  /* CAN transmit status register */
+#define STM32_CAN_RF0R_OFFSET     0x000c  /* CAN receive FIFO 0 register */
+#define STM32_CAN_RF1R_OFFSET     0x0010  /* CAN receive FIFO 1 register */
+#define STM32_CAN_IER_OFFSET      0x0014  /* CAN interrupt enable register */
+#define STM32_CAN_ESR_OFFSET      0x0018  /* CAN error status register */
+#define STM32_CAN_BTR_OFFSET      0x001c  /* CAN bit timing register */
+
+/* CAN mailbox registers (3 TX and 2 RX) */
+
+#define STM32_CAN_TIR_OFFSET(m)   (0x0180+0x0010*(m))
+#define STM32_CAN_TI0R_OFFSET     0x0180  /* TX mailbox identifier register 0 */
+#define STM32_CAN_TI1R_OFFSET     0x0190  /* TX mailbox identifier register 1 */
+#define STM32_CAN_TI2R_OFFSET     0x01a0  /* TX mailbox identifier register 2 */
+
+#define STM32_CAN_TDTR_OFFSET(m)  (0x0184+0x0010*(m))
+#define STM32_CAN_TDT0R_OFFSET    0x0184  /* Mailbox data length control and time stamp register 0 */
+#define STM32_CAN_TDT1R_OFFSET    0x0194  /* Mailbox data length control and time stamp register 1 */
+#define STM32_CAN_TDT2R_OFFSET    0x01a4  /* Mailbox data length control and time stamp register 2 */
+
+#define STM32_CAN_TDLR_OFFSET(m)  (0x0188+0x0010*(m))
+#define STM32_CAN_TDL0R_OFFSET    0x0188  /* Mailbox data low register 0 */
+#define STM32_CAN_TDL1R_OFFSET    0x0198  /* Mailbox data low register 1 */
+#define STM32_CAN_TDL2R_OFFSET    0x01a8  /* Mailbox data low register 2 */
+
+#define STM32_CAN_TDHR_OFFSET(m)  (0x018c+0x0010*(m))
+#define STM32_CAN_TDH0R_OFFSET    0x018c  /* Mailbox data high register 0 */
+#define STM32_CAN_TDH1R_OFFSET    0x019c  /* Mailbox data high register 1 */
+#define STM32_CAN_TDH2R_OFFSET    0x01ac  /* Mailbox data high register 2 */
+
+#define STM32_CAN_RIR_OFFSET(m)   (0x01b0+0x0010*(m))
+#define STM32_CAN_RI0R_OFFSET     0x01b0  /* Rx FIFO mailbox identifier register 0 */
+#define STM32_CAN_RI1R_OFFSET     0x01c0  /* Rx FIFO mailbox identifier register 1 */
+
+#define STM32_CAN_RDTR_OFFSET(m)  (0x01b4+0x0010*(m))
+#define STM32_CAN_RDT0R_OFFSET    0x01b4  /* Rx FIFO mailbox data length control and time stamp register 0 */
+#define STM32_CAN_RDT1R_OFFSET    0x01c4  /* Rx FIFO mailbox data length control and time stamp register 1 */
+
+#define STM32_CAN_RDLR_OFFSET(m)  (0x01b8+0x0010*(m))
+#define STM32_CAN_RDL0R_OFFSET    0x01b8  /* Receive FIFO mailbox data low register 0 */
+#define STM32_CAN_RDL1R_OFFSET    0x01c8  /* Receive FIFO mailbox data low register 1 */
+
+#define STM32_CAN_RDHR_OFFSET(m)  (0x01bc+0x0010*(m))
+#define STM32_CAN_RDH0R_OFFSET    0x01bc  /* Receive FIFO mailbox data high register 0 */
+#define STM32_CAN_RDH1R_OFFSET    0x01cc  /* Receive FIFO mailbox data high register 1 */
+
+/* CAN filter registers */
+
+#define STM32_CAN_FMR_OFFSET      0x0200  /* CAN filter master register */
+#define STM32_CAN_FM1R_OFFSET     0x0204  /* CAN filter mode register */
+#define STM32_CAN_FS1R_OFFSET     0x020c  /* CAN filter scale register */
+#define STM32_CAN_FFA1R_OFFSET    0x0214  /* CAN filter FIFO assignment register */
+#define STM32_CAN_FA1R_OFFSET     0x021c  /* CAN filter activation register */
+
+/* There are 14 or 28 filter banks (depending) on the device.  Each filter bank is
+ * composed of two 32-bit registers, CAN_FiR:
+ */
+
+#define STM32_CAN_FIR_OFFSET(b,i) (0x240+0x0010*(b)*0x004*(i))
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NCAN > 0
+#  define STM32_CAN1_MCR          (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET)
+#  define STM32_CAN1_MSR          (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET)
+#  define STM32_CAN1_TSR          (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET)
+#  define STM32_CAN1_RF0R         (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET)
+#  define STM32_CAN1_RF1R         (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET)
+#  define STM32_CAN1_IER          (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET)
+#  define STM32_CAN1_ESR          (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET)
+#  define STM32_CAN1_BTR          (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET)
+
+#  define STM32_CAN1_TIR(m)       (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m))
+#  define STM32_CAN1_TI0R         (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET)
+#  define STM32_CAN1_TI1R         (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET)
+#  define STM32_CAN1_TI2R         (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET)
+
+#  define STM32_CAN1_TDTR(m)      (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m))
+#  define STM32_CAN1_TDT0R        (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET)
+#  define STM32_CAN1_TDT1R        (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET)
+#  define STM32_CAN1_TDT2R        (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET)
+
+#  define STM32_CAN1_TDLR(m)      (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m))
+#  define STM32_CAN1_TDL0R        (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET)
+#  define STM32_CAN1_TDL1R        (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET)
+#  define STM32_CAN1_TDL2R        (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET)
+
+#  define STM32_CAN1_TDHR(m)      (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m))
+#  define STM32_CAN1_TDH0R        (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET)
+#  define STM32_CAN1_TDH1R        (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET)
+#  define STM32_CAN1_TDH2R        (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET)
+
+#  define STM32_CAN1_RIR(m)       (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m))
+#  define STM32_CAN1_RI0R         (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET)
+#  define STM32_CAN1_RI1R         (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET)
+
+#  define STM32_CAN1_RDTR(m)      (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m))
+#  define STM32_CAN1_RDT0R        (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET)
+#  define STM32_CAN1_RDT1R        (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET)
+
+#  define STM32_CAN1_RDLR(m)      (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m))
+#  define STM32_CAN1_RDL0R        (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET)
+#  define STM32_CAN1_RDL1R        (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET)
+
+#  define STM32_CAN1_RDHR(m)      (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m))
+#  define STM32_CAN1_RDH0R        (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET)
+#  define STM32_CAN1_RDH1R        (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET)
+
+#  define STM32_CAN1_FMR          (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET)
+#  define STM32_CAN1_FM1R         (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET)
+#  define STM32_CAN1_FS1R         (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET)
+#  define STM32_CAN1_FFA1R        (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET)
+#  define STM32_CAN1_FA1R         (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET)
+#  define STM32_CAN1_FIR(b,i)     (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i))
+#endif
+
+#if STM32_NCAN > 1
+#  define STM32_CAN2_MCR          (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET)
+#  define STM32_CAN2_MSR          (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET)
+#  define STM32_CAN2_TSR          (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET)
+#  define STM32_CAN2_RF0R         (STM32_CAN2_BASE+STM32_CAN_RF0R_OFFSET)
+#  define STM32_CAN2_RF1R         (STM32_CAN2_BASE+STM32_CAN_RF1R_OFFSET)
+#  define STM32_CAN2_IER          (STM32_CAN2_BASE+STM32_CAN_IER_OFFSET)
+#  define STM32_CAN2_ESR          (STM32_CAN2_BASE+STM32_CAN_ESR_OFFSET)
+#  define STM32_CAN2_BTR          (STM32_CAN2_BASE+STM32_CAN_BTR_OFFSET)
+
+#  define STM32_CAN2_TIR(m)       (STM32_CAN2_BASE+STM32_CAN_TIR_OFFSET(m))
+#  define STM32_CAN2_TI0R         (STM32_CAN2_BASE+STM32_CAN_TI0R_OFFSET)
+#  define STM32_CAN2_TI1R         (STM32_CAN2_BASE+STM32_CAN_TI1R_OFFSET)
+#  define STM32_CAN2_TI2R         (STM32_CAN2_BASE+STM32_CAN_TI2R_OFFSET)
+
+#  define STM32_CAN2_TDTR(m)      (STM32_CAN2_BASE+STM32_CAN_TDTR_OFFSET(m))
+#  define STM32_CAN2_TDT0R        (STM32_CAN2_BASE+STM32_CAN_TDT0R_OFFSET)
+#  define STM32_CAN2_TDT1R        (STM32_CAN2_BASE+STM32_CAN_TDT1R_OFFSET)
+#  define STM32_CAN2_TDT2R        (STM32_CAN2_BASE+STM32_CAN_TDT2R_OFFSET)
+
+#  define STM32_CAN2_TDLR(m)      (STM32_CAN2_BASE+STM32_CAN_TDLR_OFFSET(m))
+#  define STM32_CAN2_TDL0R        (STM32_CAN2_BASE+STM32_CAN_TDL0R_OFFSET)
+#  define STM32_CAN2_TDL1R        (STM32_CAN2_BASE+STM32_CAN_TDL1R_OFFSET)
+#  define STM32_CAN2_TDL2R        (STM32_CAN2_BASE+STM32_CAN_TDL2R_OFFSET)
+
+#  define STM32_CAN2_TDHR(m)      (STM32_CAN2_BASE+STM32_CAN_TDHR_OFFSET(m))
+#  define STM32_CAN2_TDH0R        (STM32_CAN2_BASE+STM32_CAN_TDH0R_OFFSET)
+#  define STM32_CAN2_TDH1R        (STM32_CAN2_BASE+STM32_CAN_TDH1R_OFFSET)
+#  define STM32_CAN2_TDH2R        (STM32_CAN2_BASE+STM32_CAN_TDH2R_OFFSET)
+
+#  define STM32_CAN2_RIR(m)       (STM32_CAN2_BASE+STM32_CAN_RIR_OFFSET(m))
+#  define STM32_CAN2_RI0R         (STM32_CAN2_BASE+STM32_CAN_RI0R_OFFSET)
+#  define STM32_CAN2_RI1R         (STM32_CAN2_BASE+STM32_CAN_RI1R_OFFSET)
+
+#  define STM32_CAN2_RDTR(m)      (STM32_CAN2_BASE+STM32_CAN_RDTR_OFFSET(m))
+#  define STM32_CAN2_RDT0R        (STM32_CAN2_BASE+STM32_CAN_RDT0R_OFFSET)
+#  define STM32_CAN2_RDT1R        (STM32_CAN2_BASE+STM32_CAN_RDT1R_OFFSET)
+
+#  define STM32_CAN2_RDLR(m)      (STM32_CAN2_BASE+STM32_CAN_RDLR_OFFSET(m))
+#  define STM32_CAN2_RDL0R        (STM32_CAN2_BASE+STM32_CAN_RDL0R_OFFSET)
+#  define STM32_CAN2_RDL1R        (STM32_CAN2_BASE+STM32_CAN_RDL1R_OFFSET)
+
+#  define STM32_CAN2_RDHR(m)      (STM32_CAN2_BASE+STM32_CAN_RDHR_OFFSET(m))
+#  define STM32_CAN2_RDH0R        (STM32_CAN2_BASE+STM32_CAN_RDH0R_OFFSET)
+#  define STM32_CAN2_RDH1R        (STM32_CAN2_BASE+STM32_CAN_RDH1R_OFFSET)
+
+#  define STM32_CAN2_FMR          (STM32_CAN2_BASE+STM32_CAN_FMR_OFFSET)
+#  define STM32_CAN2_FM1R         (STM32_CAN2_BASE+STM32_CAN_FM1R_OFFSET)
+#  define STM32_CAN2_FS1R         (STM32_CAN2_BASE+STM32_CAN_FS1R_OFFSET)
+#  define STM32_CAN2_FFA1R        (STM32_CAN2_BASE+STM32_CAN_FFA1R_OFFSET)
+#  define STM32_CAN2_FA1R         (STM32_CAN2_BASE+STM32_CAN_FA1R_OFFSET)
+#  define STM32_CAN2_FIR(b,i)     (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i))
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* CAN master control register */
+
+#define CAN_MCR_INRQ              (1 << 0)  /* Bit 0: Initialization Request */
+#define CAN_MCR_SLEEP             (1 << 1)  /* Bit 1: Sleep Mode Request */
+#define CAN_MCR_TXFP              (1 << 2)  /* Bit 2: Transmit FIFO Priority */
+#define CAN_MCR_RFLM              (1 << 3)  /* Bit 3: Receive FIFO Locked Mode */
+#define CAN_MCR_NART              (1 << 4)  /* Bit 4: No Automatic Retransmission */
+#define CAN_MCR_AWUM              (1 << 5)  /* Bit 5: Automatic Wakeup Mode */
+#define CAN_MCR_ABOM              (1 << 6)  /* Bit 6: Automatic Bus-Off Management */
+#define CAN_MCR_TTCM              (1 << 7)  /* Bit 7: Time Triggered Communication Mode Enable */
+#define CAN_MCR_RESET             (1 << 15) /* Bit 15: bxCAN software master reset */
+#define CAN_MCR_DBF               (1 << 16) /* Bit 16: Debug freeze */
+
+/* CAN master status register */
+
+#define CAN_MSR_INAK              (1 << 0)  /* Bit 0: Initialization Acknowledge */
+#define CAN_MSR_SLAK              (1 << 1)  /* Bit 1: Sleep Acknowledge */
+#define CAN_MSR_ERRI              (1 << 2)  /* Bit 2: Error Interrupt */
+#define CAN_MSR_WKUI              (1 << 3)  /* Bit 3: Wakeup Interrupt */
+#define CAN_MSR_SLAKI             (1 << 4)  /* Bit 4: Sleep acknowledge interrupt */
+#define CAN_MSR_TXM               (1 << 8)  /* Bit 8: Transmit Mode */
+#define CAN_MSR_RXM               (1 << 9)  /* Bit 9: Receive Mode */
+#define CAN_MSR_SAMP              (1 << 20) /* Bit 10: Last Sample Point */
+#define CAN_MSR_RX                (1 << 11) /* Bit 11: CAN Rx Signal */
+
+/* CAN transmit status register */
+
+#define CAN_TSR_RQCP0             (1 << 0)  /* Bit 0: Request Completed Mailbox 0 */
+#define CAN_TSR_TXOK0             (1 << 1)  /* Bit 1 : Transmission OK of Mailbox 0 */
+#define CAN_TSR_ALST0             (1 << 2)  /* Bit 2 : Arbitration Lost for Mailbox 0 */
+#define CAN_TSR_TERR0             (1 << 3)  /* Bit 3 : Transmission Error of Mailbox 0 */
+#define CAN_TSR_ABRQ0             (1 << 7)  /* Bit 7 : Abort Request for Mailbox 0 */
+#define CAN_TSR_RQCP1             (1 << 8)  /* Bit 8 : Request Completed Mailbox 1 */
+#define CAN_TSR_TXOK1             (1 << 9)  /* Bit 9 : Transmission OK of Mailbox 1 */
+#define CAN_TSR_ALST1             (1 << 10) /* Bit 10 : Arbitration Lost for Mailbox 1 */
+#define CAN_TSR_TERR1             (1 << 11) /* Bit 11 : Transmission Error of Mailbox 1 */
+#define CAN_TSR_ABRQ1             (1 << 15) /* Bit 15 : Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2             (1 << 16) /* Bit 16 : Request Completed Mailbox 2 */
+#define CAN_TSR_TXOK2             (1 << 17) /* Bit 17 : Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2             (1 << 18) /* Bit 18: Arbitration Lost for Mailbox 2 */
+#define CAN_TSR_TERR2             (1 << 19) /* Bit 19: Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2             (1 << 23) /* Bit 23: Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_SHIFT        (24)      /* Bits 25-24: Mailbox Code */
+#define CAN_TSR_CODE_MASK         (3 << CAN_TSR_CODE_SHIFT)
+#define CAN_TSR_TME0              (1 << 26) /* Bit 26: Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1              (1 << 27) /* Bit 27: Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2              (1 << 28) /* Bit 28: Transmit Mailbox 2 Empty */
+#define CAN_TSR_LOW0              (1 << 29) /* Bit 29: Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1              (1 << 30) /* Bit 30: Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2              (1 << 31) /* Bit 31: Lowest Priority Flag for Mailbox 2 */
+
+/* CAN receive FIFO 0/1 registers */
+
+#define CAN_RFR_FMP_SHIFT         (0)       /* Bits 1-0: FIFO Message Pending */
+#define CAN_RFR_FMP_MASK          (3 << CAN_RFR_FMP_SHIFT)
+#define CAN_RFR_FULL              (1 << 3)  /* Bit 3: FIFO 0 Full */
+#define CAN_RFR_FOVR              (1 << 4)  /* Bit 4: FIFO 0 Overrun */
+#define CAN_RFR_RFOM              (1 << 5)  /* Bit 5: Release FIFO 0 Output Mailbox */
+
+/* CAN interrupt enable register */
+
+#define CAN_IER_TMEIE             (1 << 1)  /* Bit 0: Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0            (1 << 2)  /* Bit 1: FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0             (1 << 3)  /* Bit 2: FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0            (1 << 4)  /* Bit 3: FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1            (1 << 5)  /* Bit 4: FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1             (1 << 6)  /* Bit 5: FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1            (1 << 7)  /* Bit 6: FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE             (1 << 8)  /* Bit 8: Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE             (1 << 9)  /* Bit 9: Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE             (1 << 10) /* Bit 10: Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE             (1 << 11) /* Bit 11: Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE             (1 << 15) /* Bit 15: Error Interrupt Enable */
+#define CAN_IER_WKUIE             (1 << 16) /* Bit 16: Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE             (1 << 17) /* Bit 17: Sleep Interrupt Enable */
+
+/* CAN error status register */
+
+#define CAN_ESR_EWGF              (1 << 0)  /* Bit 0: Error Warning Flag */
+#define CAN_ESR_EPVF              (1 << 1)  /* Bit 1: Error Passive Flag */
+#define CAN_ESR_BOFF              (1 << 2)  /* Bit 2: Bus-Off Flag */
+#define CAN_ESR_LEC_SHIFT         (4)       /* Bits 6-4: Last Error Code */
+#define CAN_ESR_LEC_MASK          (7 << CAN_ESR_LEC_SHIFT)
+#  define CAN_ESR_NOERROR         (0 << CAN_ESR_LEC_SHIFT) /* 000: No Error */
+#  define CAN_ESR_STUFFERROR      (1 << CAN_ESR_LEC_SHIFT) /* 001: Stuff Error */
+#  define CAN_ESR_FORMERROR       (2 << CAN_ESR_LEC_SHIFT) /* 010: Form Error */
+#  define CAN_ESR_ACKERROR        (3 << CAN_ESR_LEC_SHIFT) /* 011: Acknowledgment Error */
+#  define CAN_ESR_BRECERROR       (4 << CAN_ESR_LEC_SHIFT) /* 100: Bit recessive Error */
+#  define CAN_ESR_BDOMERROR       (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */
+#  define CAN_ESR_CRCERRPR        (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */
+#  define CAN_ESR_SWERROR         (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */
+#define CAN_ESR_TEC_SHIFT         (16)      /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_TEC_MASK          (0xff << CAN_ESR_TEC_SHIF)
+#define CAN_ESR_REC_SHIFT         (14)      /* Bits 31-24: Receive Error Counter */
+#define CAN_ESR_REC_MASK          (0xff << CAN_ESR_REC_SHIFT)
+
+/* CAN bit timing register */
+
+#define CAN_BTR_BRP_SHIFT         (0)       /* Bits 9-0: Baud Rate Prescaler */
+#define CAN_BTR_BRP_MASK          (0x03ff << CAN_BTR_BRP_SHIFT)
+#define CAN_BTR_TS1_SHIFT         (16)      /* Bits 19-16: Time Segment 1 */
+#define CAN_BTR_TS1_MASK          (0x0f <<  CAN_BTR_TS1_SHIFT)
+#define CAN_BTR_TS2_SHIFT         (20)      /* Bits 22-20: Time Segment 2 */
+#define CAN_BTR_TS2_MASK          (7 << CAN_BTR_TS2_SHIFT)
+#define CAN_BTR_SJW_SHIFT         (24)      /* Bits 25-24: Resynchronization Jump Width */
+#define CAN_BTR_SJW_MASK          (3 << CAN_BTR_SJW_SHIFT)
+#define CAN_BTR_LBKM              (1 << 20) /* Bit 30: Loop Back Mode (Debug) */
+#define CAN_BTR_SILM              (1 << 31) /* Bit 31: Silent Mode (Debug) */
+
+/* TX mailbox identifier register */
+
+#define CAN_TIR_TXRQ              (1 << 0)  /* Bit 0: Transmit Mailbox Request */
+#define CAN_TIR_RTR               (1 << 1)  /* Bit 1: Remote Transmission Request */
+#define CAN_TIR_IDE               (1 << 2)  /* Bit 2: Identifier Extension */
+#define CAN_TIR_EXID_MASK         (3)       /* Bit 20:3: Extended Identifier */
+#define CAN_TIR_EXID_MASK         (0x0003ffff << CAN_TIR_EXID_MASK)
+#define CAN_TIR_STID_SHIFT        (21)      /* Bits 31:21: Standard Identifier */
+#define CAN_TIR_STID_MASK         (0x07ff << CAN_TIR_STID_SHIFT)
+
+/* Mailbox data length control and time stamp register */
+
+#define CAN_TDTR_DLC_SHIFT        (0)       /* Bits 3:0: Data Length Code */
+#define CAN_TDTR_DLC_MASK 	  (0x0f << CAN_TDTR_DLC_SHIFT)
+#define CAN_TDTR_TGT              (1 << 8)  /* Bit 8: Transmit Global Time */
+#define CAN_TDTR_TIME_SHIFT       (16)      /* Bits 31:16: Message Time Stamp */
+#define CAN_TDTR_TIME_MASK        (0xffff << CAN_TDTR_TIME_SHIFT)
+
+/* Mailbox data low register */
+
+#define CAN_TDLR_DATA0_SHIFT      (0)       /* Bits 7-0: Data Byte 0 */
+#define CAN_TDLR_DATA0_MASK       (0xff << CAN_TDLR_DATA0_SHIFT)
+#define CAN_TDLR_DATA1_SHIFT      (8)       /* Bits 15-8: Data Byte 1 */
+#define CAN_TDLR_DATA1_MASK       (0xff << CAN_TDLR_DATA1_SHIFT)
+#define CAN_TDLR_DATA2_SHIFT      (16)      /* Bits 23-16: Data Byte 2 */
+#define CAN_TDLR_DATA2_MASK       (0xff << CAN_TDLR_DATA2_SHIFT)
+#define CAN_TDLR_DATA3_SHIFT      (24)      /* Bits 31-24: Data Byte 3 */
+#define CAN_TDLR_DATA3_MASK       (0xff << CAN_TDLR_DATA3_SHIFT)
+
+/* Mailbox data high register */
+
+#define CAN_TDHR_DATA4_SHIFT      (0)       /* Bits 7-0: Data Byte 4 */
+#define CAN_TDHR_DATA4_MASK       (0xff << CAN_TDHR_DATA4_SHIFT)
+#define CAN_TDHR_DATA5_SHIFT      (8)       /* Bits 15-8: Data Byte 5 */
+#define CAN_TDHR_DATA5_MASK       (0xff << CAN_TDHR_DATA5_SHIFT)
+#define CAN_TDHR_DATA6_SHIFT      (16)      /* Bits 23-16: Data Byte 6 */
+#define CAN_TDHR_DATA6_MASK       (0xff << CAN_TDHR_DATA6_SHIFT)
+#define CAN_TDHR_DATA7_SHIFT      (24)      /* Bits 31-24: Data Byte 7 */
+#define CAN_TDHR_DATA7_MASK       (0xff << CAN_TDHR_DATA7_SHIFT)
+
+/* Rx FIFO mailbox identifier register */
+
+#define CAN_RIR_RTR               (1 << 1)  /* Bit 1: Remote Transmission Request */
+#define CAN_RIR_IDE               (1 << 2)  /* Bit 2: Identifier Extension */
+#define CAN_RIR_EXID_MASK         (3)       /* Bit 20:3: Extended Identifier */
+#define CAN_RIR_EXID_MASK         (0x0003ffff << CAN_TIR_EXID_MASK)
+#define CAN_RIR_STID_SHIFT        (21)      /* Bits 31:21: Standard Identifier */
+#define CAN_RIR_STID_MASK         (0x07ff << CAN_RIR_STID_SHIFT)
+
+/* Receive FIFO mailbox data length control and time stamp register */
+
+#define CAN_RDTR_DLC_SHIFT        (0)       /* Bits 3:0: Data Length Code */
+#define CAN_RDTR_DLC_MASK 	  (0x0f << CAN_RDTR_DLC_SHIFT)
+#define CAN_RDTR_FM_SHIFT         (8)       /* Bits 15-8: Filter Match Index */
+#define CAN_RDTR_FM_MASK 	  (0xff << CAN_RDTR_FM_SHIFT)
+#define CAN_RDTR_TIME_SHIFT       (16)      /* Bits 31:16: Message Time Stamp */
+#define CAN_RDTR_TIME_MASK        (0xffff << CAN_RDTR_TIME_SHIFT)
+
+/* Receive FIFO mailbox data low register */
+
+#define CAN_RDLR_DATA0_SHIFT      (0)       /* Bits 7-0: Data Byte 0 */
+#define CAN_RDLR_DATA0_MASK       (0xff << CAN_RDLR_DATA0_SHIFT)
+#define CAN_RDLR_DATA1_SHIFT      (8)       /* Bits 15-8: Data Byte 1 */
+#define CAN_RDLR_DATA1_MASK       (0xff << CAN_RDLR_DATA1_SHIFT)
+#define CAN_RDLR_DATA2_SHIFT      (16)      /* Bits 23-16: Data Byte 2 */
+#define CAN_RDLR_DATA2_MASK       (0xff << CAN_RDLR_DATA2_SHIFT)
+#define CAN_RDLR_DATA3_SHIFT      (24)      /* Bits 31-24: Data Byte 3 */
+#define CAN_RDLR_DATA3_MASK       (0xff << CAN_RDLR_DATA3_SHIFT)
+
+/* Receive FIFO mailbox data high register */
+
+#define CAN_RDHR_DATA4_SHIFT      (0)       /* Bits 7-0: Data Byte 4 */
+#define CAN_RDHR_DATA4_MASK       (0xff << CAN_RDHR_DATA4_SHIFT)
+#define CAN_RDHR_DATA5_SHIFT      (8)       /* Bits 15-8: Data Byte 5 */
+#define CAN_RDHR_DATA5_MASK       (0xff << CAN_RDHR_DATA5_SHIFT)
+#define CAN_RDHR_DATA6_SHIFT      (16)      /* Bits 23-16: Data Byte 6 */
+#define CAN_RDHR_DATA6_MASK       (0xff << CAN_RDHR_DATA6_SHIFT)
+#define CAN_RDHR_DATA7_SHIFT      (24)      /* Bits 31-24: Data Byte 7 */
+#define CAN_RDHR_DATA7_MASK       (0xff << CAN_RDHR_DATA7_SHIFT)
+
+/* CAN filter master register */
+
+#define CAN_FMR_FINIT             (1 << 0)  /* Bit 0:  Filter Init Mode */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define CAN_FMR_CAN2SB_SHIFT    (8)       /* Bits 13-8: CAN2 start bank */
+#  define CAN_FMR_CAN2SB_MASK     (0x3f << CAN_FMR_CAN2SB_SHIFT)
+#endif
+
+/* CAN filter mode register */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define CAN_FM1R_FBM_SHIFT      (0)      /* Bits 13:0: Filter Mode */
+#  define CAN_FM1R_FBM_MASK       (0x3fff << CAN_FM1R_FBM_SHIFT)
+#else
+#  define CAN_FM1R_FBM_SHIFT      (0)      /* Bits 27:0: Filter Mode */
+#  define CAN_FM1R_FBM_MASK       (0x0fffffff << CAN_FM1R_FBM_SHIFT)
+#endif
+
+/* CAN filter scale register */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define CAN_FS1R_FSC_SHIFT      (0)      /* Bits 13:0: Filter Scale Configuration */
+#  define CAN_FS1R_FSC_MASK       (0x3fff << CAN_FS1R_FSC_SHIFT)
+#else
+#  define CAN_FS1R_FSC_SHIFT      (0)      /* Bits 27:0: Filter Scale Configuration */
+#  define CAN_FS1R_FSC_MASK       (0x0fffffff << CAN_FS1R_FSC_SHIFT)
+#endif
+
+/* CAN filter FIFO assignment register */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define CAN_FFA1R_FFA_SHIFT     (0)      /* Bits 13:0: Filter FIFO Assignment */
+#  define CAN_FFA1R_FFA_MASK      (0x3fff << CAN_FFA1R_FFA_SHIFT)
+#else
+#  define CAN_FFA1R_FFA_SHIFT     (0)      /* Bits 27:0: Filter FIFO Assignment */
+#  define CAN_FFA1R_FFA_MASK      (0x0fffffff << CAN_FFA1R_FFA_SHIFT)
+#endif
+
+/* CAN filter activation register */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define CAN_FA1R_FACT_SHIFT     (0)      /* Bits 13:0: Filter Active */
+#  define CAN_FA1R_FACT_MASK      (0x3fff << CAN_FA1R_FACT_SHIFT)
+#else
+#  define CAN_FA1R_FACT_SHIFT     (0)      /* Bits 27:0: Filter Active */
+#  define CAN_FA1R_FACT_MASK      (0x0fffffff << CAN_FA1R_FACT_SHIFT)
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */
--- a/arch/arm/src/stm32/stm32_dgbmcu.h
+++ b/arch/arm/src/stm32/stm32_dgbmcu.h
@@ -0,0 +1,104 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_dbgmcu.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_DBGMCU_IDCODE       0xe0042000  /* MCU identifier */
+#define STM32_DBGMCU_CR_OFFSET    0xe0042004  /* MCU debug */
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* MCU identifier */
+
+#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
+#define DBGMCU_IDCODE_DEVID_MASK  (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
+#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16:  Revision Identifier */
+#define DBGMCU_IDCODE_REVID_MASK  (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
+
+/* MCU debug */
+
+#define DBGMCU_CR_SLEEP           (1 << 0)  /* Bit 0: Debug Sleep Mode */
+#define DBGMCU_CR_STOP            (1 << 1)  /* Bit 1: Debug Stop Mode */
+#define DBGMCU_CR_STANDBY         (1 << 2)  /* Bit 2: Debug Standby mode */
+#define DBGMCU_CR_TRACEIOEN       (1 << 5)  /* Bit 5: Trace enabled */
+#define DBGMCU_CR_TRACEMODE_SHIFT (6)        /* Bits 7-6: Trace mode pin assignement */
+#define DBGMCU_CR_TRACEMODE_MASK  (3 << DBGMCU_CR_TRACEMODE_SHIFT)
+#  define DBGMCU_CR_ASYNCH        (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
+#  define DBGMCU_CR_SYNCH1        (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
+#  define DBGMCU_CR_SYNCH2        (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
+#  define DBGMCU_CR_SYNCH4        (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
+#define DBGMCU_CR_IWDGSTOP        (1 << 8)   /* Bit 8: Independent Watchdog stopped when core is halted */
+#define DBGMCU_CR_WWDGSTOP        (1 << 9)   /* Bit 9: Window Watchdog stopped when core is halted */
+#define DBGMCU_CR_TIM1STOP        (1 << 10)  /* Bit 10: TIM1 stopped when core is halted */
+#define DBGMCU_CR_TIM2STOP        (1 << 11)  /* Bit 11: TIM2 stopped when core is halted */
+#define DBGMCU_CR_TIM3STOP        (1 << 12)  /* Bit 12: TIM3 stopped when core is halted */
+#define DBGMCU_CR_TIM4STOP        (1 << 13)  /* Bit 13: TIM4 stopped when core is halted */
+#define DBGMCU_CR_CAN1STOP        (1 << 14)  /* Bit 14: CAN1 stopped when core is halted */
+#define DBGMCU_CR_SMBUS1STOP      (1 << 15)  /* Bit 15: I2C1 SMBUS timeout mode stopped when core is halted */
+#define DBGMCU_CR_SMBUS2STOP      (1 << 16)  /* Bit 16: I2C2 SMBUS timeout mode stopped when core is halted */
+#define DBGMCU_CR_TIM8STOP        (1 << 17)  /* Bit 17: TIM8 stopped when core is halted */
+#define DBGMCU_CR_TIM5STOP        (1 << 18)  /* Bit 18: TIM5 stopped when core is halted */
+#define DBGMCU_CR_TIM6STOP        (1 << 19)  /* Bit 19: TIM6 stopped when core is halted */
+#define DBGMCU_CR_TIM7STOP        (1 << 20)  /* Bit 20: TIM7 stopped when core is halted */
+#define DBGMCU_CR_CAN2STOP        (1 << 21)  /* Bit 21: CAN2 stopped when core is halted */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */
--- a/arch/arm/src/stm32/stm32_dma.c
+++ b/arch/arm/src/stm32/stm32_dma.c
@@ -0,0 +1,468 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_dma.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <semaphore.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "chip.h"
+#include "stm32_dma.h"
+#include "stm32_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define DMA1_NCHANNELS   7
+#if STM32_NDMA > 1
+#  define DMA2_NCHANNELS 5
+#  define DMA_NCHANNELS  (DMA1_NCHANNELS+DMA2_NCHANNELS)
+#else
+#  define DMA_NCHANNELS  DMA1_NCHANNELS
+#endif
+
+/* Convert the DMA channel base address to the DMA register block address */
+ 
+#define DMA_BASE(ch)     (ch & 0xfffffc00)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure descibes one DMA channel */
+
+struct stm32_dma_s
+{
+  ubyte          chan;     /* DMA channel number */
+  ubyte          irq;      /* DMA channel IRQ number */
+  sem_t          sem;      /* Used to wait for DMA channel to become available */
+  uint32         base;     /* DMA register channel base address */
+  dma_callback_t callback; /* Callback invoked when the DMA completes */
+  void          *arg;      /* Argument passed to callback function */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This array describes the state of each DMA */
+
+static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
+{
+  {
+	.chan     = STM32_DMA1_CHAN1,
+	.irq      = STM32_IRQ_DMA1CH1,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
+  },
+  {
+	.chan     = STM32_DMA1_CHAN2,
+	.irq      = STM32_IRQ_DMA1CH2,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
+  },
+  {
+	.chan     = STM32_DMA1_CHAN3,
+	.irq      = STM32_IRQ_DMA1CH3,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
+  },
+  {
+	.chan     = STM32_DMA1_CHAN4,
+	.irq      = STM32_IRQ_DMA1CH4,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
+  },
+  {
+	.chan     = STM32_DMA1_CHAN5,
+	.irq      = STM32_IRQ_DMA1CH5,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
+  },
+  {
+	.chan     = STM32_DMA1_CHAN6,
+	.irq      = STM32_IRQ_DMA1CH6,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
+  },
+  {
+	.chan     = STM32_DMA1_CHAN7,
+	.irq      = STM32_IRQ_DMA1CH7,
+    .base     = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
+  },
+#if STM32_NDMA > 1
+  {
+	.chan     = STM32_DMA2_CHAN1,
+	.irq      = STM32_IRQ_DMA2CH1,
+    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
+  },
+  {
+	.chan     = STM32_DMA2_CHAN2,
+	.irq      = STM32_IRQ_DMA2CH2,
+    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
+  },
+  {
+	.chan     = STM32_DMA2_CHAN3,
+	.irq      = STM32_IRQ_DMA2CH3,
+    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
+  },
+  {
+	.chan     = STM32_DMA2_CHAN4,
+	.irq      = STM32_IRQ_DMA2CH4,
+    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
+  },
+  {
+	.chan     = STM32_DMA2_CHAN5,
+	.irq      = STM32_IRQ_DMA2CH5,
+    .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
+  },
+#endif
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * DMA register access functions
+ ****************************************************************************/
+
+/* Get non-channel register from DMA1 or DMA2 */
+
+static inline uint32 dmabase_getreg(struct stm32_dma_s *dmach, uint32 offset)
+{
+  return getreg32(DMA_BASE(dmach->base) + offset);
+}
+
+/* Write to non-channel register in DMA1 or DMA2 */
+
+static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32 offset, uint32 value)
+{
+  putreg32(value, DMA_BASE(dmach->base) + offset);
+}
+
+/* Get channel register from DMA1 or DMA2 */
+
+static inline uint32 dmachan_getreg(struct stm32_dma_s *dmach, uint32 offset)
+{
+  return getreg32(dmach->base + offset);
+}
+
+/* Write to channel register in DMA1 or DMA2 */
+
+static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32 offset, uint32 value)
+{
+  putreg32(value, dmach->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_dmatake() and stm32_dmagive()
+ *
+ * Description:
+ *   Used to get exclusive access to a DMA channel.
+ *
+ ************************************************************************************/
+
+static void stm32_dmatake(FAR struct stm32_dma_s *dmach)
+{
+  /* Take the semaphore (perhaps waiting) */
+
+  while (sem_wait(&dmach->sem) != 0)
+    {
+      /* The only case that an error should occur here is if the wait was awakened
+       * by a signal.
+       */
+
+      ASSERT(errno == EINTR);
+    }
+}
+
+static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach)
+{
+  (void)sem_post(&dmach->sem);
+}
+
+/************************************************************************************
+ * Name: stm32_dmainterrupt
+ *
+ * Description:
+ *  DMA interrupt handler
+ *
+ ************************************************************************************/
+
+static int stm32_dmainterrupt(int irq, void *context)
+{
+  struct stm32_dma_s *dmach;
+  uint32 isr;
+  int chan;
+
+  /* Get the channel structure from the interrupt number */
+
+  if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
+    {
+      chan = irq - STM32_IRQ_DMA1CH1;
+    }
+  else
+#if STM32_NDMA > 1
+  if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
+    {
+      chan = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
+    }
+  else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  dmach = &g_dma[chan];
+
+  /* Get the interrupt status (for this channel only) */
+
+  isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & ~DMA_ISR_CHAN_MASK(chan);
+
+  /* Clear pending interrupts (for this channel only) */
+
+  dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
+
+  /* Invoke the callback */
+
+  if (dmach->callback)
+    {
+      dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(chan), dmach->arg);
+    }
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_dmainitialize
+ *
+ * Description:
+ *   Initialize the DMA subsystem
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void weak_function stm32_dmainitialize(void)
+{
+  int chan;
+
+  /* Attach DMA interrupt vectors */
+
+  for (chan = 0; chan < DMA_NCHANNELS; chan++)
+    {
+      sem_init(&g_dma[chan].sem, 0, 1);	
+      irq_attach(g_dma[chan].irq, stm32_dmainterrupt);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32_dmachannel
+ *
+ * Description:
+ *   Allocate a DMA channel.  This function gives the caller mutually
+ *   exclusive access to the DMA channel specified by the 'chan' argument.
+ *   DMA channels are shared on the STM32:  Devices sharing the same DMA
+ *   channel cannot do DMA concurrently!  See the DMACHAN_* definitions in
+ *   stm32_dma.h.
+ *
+ *   If the DMA channel is not available, then stm32_dmachannel() will wait
+ *   until the holder of the channel relinquishes the channel by calling
+ *   stm32_dmafree().  WARNING: If you have two devices sharing a DMA
+ *   channel and the code never releases the channel, the stm32_dmachannel
+ *   call for the other will hang forever in this function!  Don't let your
+ *   design do that!
+ *
+ *   Hmm.. I suppose this interface could be extended to make a non-blocking
+ *   version.  Feel free to do that if that is what you need.
+ *
+ * Returned Value:
+ *   Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
+ *   void* DMA channel handle.  (If 'chan' is invalid, the function will
+ *   assert if debug is enabled or do something ignorant otherwise).
+ *
+ * Assumptions:
+ *   - The caller does not hold he DMA channel.
+ *   - The caller can wait for the DMA channel to be freed if it is no
+ *     available.
+ *
+ ****************************************************************************/
+
+DMA_HANDLE stm32_dmachannel(int chan)
+{
+  struct stm32_dma_s *dmach = &g_dma[chan];
+
+  DEBUGASSERT(chan < DMA_NCHANNELS);
+
+  /* Get exclusive access to the DMA channel -- OR wait until the channel
+   * is available if it is currently being used by another driver
+   */
+
+  stm32_dmatake(dmach);
+
+  /* The caller now has exclusive use of the DMA channel */
+
+  return (DMA_HANDLE)dmach;
+}
+
+/****************************************************************************
+ * Name: stm32_dmafree
+ *
+ * Description:
+ *   Release a DMA channel.  If another thread is waiting for this DMA channel
+ *   in a call to stm32_dmachannel, then this function will re-assign the
+ *   DMA channel to that thread and wake it up.  NOTE:  The 'handle' used
+ *   in this argument must NEVER be used again until stm32_dmachannel() is
+ *   called again to re-gain access to the channel.
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   - The caller holds the DMA channel.
+ *   - There is no DMA in progress
+ *
+ ****************************************************************************/
+
+void stm32_dmafree(DMA_HANDLE handle)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+
+  DEBUGASSERT(handle != NULL);
+
+  /* Release the channel */
+
+  stm32_dmagive(dmach);
+}
+
+/****************************************************************************
+ * Name: stm32_dmasetup
+ *
+ * Description:
+ *   Configure DMA before using
+ *
+ ****************************************************************************/
+
+void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, size_t ntransfers, uint32 ccr)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+  uint32 regval;
+
+  /* Set the peripheral register address in the DMA_CPARx register. The data
+   * will be moved from/to this address to/from the memory after the
+   * peripheral event.
+   */
+
+  dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr);
+
+  /* Set the memory address in the DMA_CMARx register. The data will be
+   * written to or read from this memory after the peripheral event.
+   */
+
+  dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr);
+
+  /* Configure the total number of data to be transferred in the DMA_CNDTRx
+   * register.  After each peripheral event, this value will be decremented.
+   */
+
+  dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers);
+
+  /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx
+   * register.  Configure data transfer direction, circular mode, peripheral & memory
+   * incremented mode, peripheral & memory data size, and interrupt after
+   * half and/or full transfer in the DMA_CCRx register.
+   */
+
+  regval  = dmachan_gettreg(dmach, STM32_DMACHAN_CCR_OFFSET);
+  regval &= ~(DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
+              DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
+  ccr    &=  (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
+              DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
+  regval |= ccr;
+  dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
+}
+
+/****************************************************************************
+ * Name: stm32_dmastart
+ *
+ * Description:
+ *   Start the DMA transfer
+ *
+ * Assumptions:
+ *   - DMA handle allocated by stm32_dmachannel()
+ *   - No DMA in progress
+ *
+ ****************************************************************************/
+
+void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, boolean half)
+{
+  struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
+  int irq;
+  uint32 ccr;
+
+  DEBUGASSERT(handle != NULL);
+
+  /* Save the callback info.  This will be invoked whent the DMA commpletes */
+
+  dmach->callback = callback;
+  dmach->arg      = arg;
+
+  /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
+   * As soon as the channel is enabled, it can serve any DMA request from the
+   * peripheral connected on the channel.
+   */
+
+  ccr  = dmachan_gettreg(dmach, STM32_DMACHAN_CCR_OFFSET);
+  ccr |= DMA_CCR_EN;
+
+  /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
+   * set and an interrupt is generated if the Half-Transfer Interrupt Enable
+   * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
+   * (TCIF) is set and an interrupt is generated if the Transfer Complete
+   * Interrupt Enable bit (TCIE) is set.
+   */
+
+  ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
+  dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
+}
--- a/arch/arm/src/stm32/stm32_dma.h
+++ b/arch/arm/src/stm32/stm32_dma.h
@@ -0,0 +1,367 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_dma.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA_H
+#define __ARCH_ARM_SRC_STM32_STM32_DMA_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* 7 DMA Channels */
+
+#define DMA1 0
+#define DMA2 1
+#define DMA3 2
+#define DMA4 3
+#define DMA5 4
+#define DMA6 5
+#define DMA7 6
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_DMA_ISR_OFFSET        0x0000 /* DMA interrupt status register */
+#define STM32_DMA_IFCR_OFFSET       0x0004 /* DMA interrupt flag clear register */
+
+#define STM32_DMACHAN_OFFSET(n)    (0x0014*(n))
+#define STM32_DMACHAN_CCR_OFFSET   0x0008
+#define STM32_DMACHAN_CNDTR_OFFSET 0x000c
+#define STM32_DMACHAN_CPAR_OFFSET  0x0010
+#define STM32_DMACHAN_CMAR_OFFSET  0x0014
+
+#define STM32_DMA_CCR_OFFSET(n)   (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
+#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
+#define STM32_DMA_CPAR_OFFSET(n)  (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
+#define STM32_DMA_CMAR_OFFSET(n)  (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
+
+#define STM32_DMA_CCR1_OFFSET     0x0008 /* DMA channel 1 configuration register */
+#define STM32_DMA_CCR2_OFFSET     0x001c /* DMA channel 2 configuration register */
+#define STM32_DMA_CCR3_OFFSET     0x0030 /* DMA channel 3 configuration register */
+#define STM32_DMA_CCR4_OFFSET     0x0044 /* DMA channel 4 configuration register */
+#define STM32_DMA_CCR5_OFFSET     0x0058 /* DMA channel 5 configuration register */
+#define STM32_DMA_CCR6_OFFSET     0x006c /* DMA channel 6 configuration register */
+#define STM32_DMA_CCR7_OFFSET     0x0080 /* DMA channel 7 configuration register */
+
+#define STM32_DMA_CNDTR1_OFFSET   0x000c /* DMA channel 1 number of data register */
+#define STM32_DMA_CNDTR2_OFFSET   0x0020 /* DMA channel 2 number of data register */
+#define STM32_DMA_CNDTR3_OFFSET   0x0034 /* DMA channel 3 number of data register */
+#define STM32_DMA_CNDTR4_OFFSET   0x0048 /* DMA channel 4 number of data register */
+#define STM32_DMA_CNDTR5_OFFSET   0x005c /* DMA channel 5 number of data register */
+#define STM32_DMA_CNDTR6_OFFSET   0x0070 /* DMA channel 6 number of data register */
+#define STM32_DMA_CNDTR7_OFFSET   0x0084 /* DMA channel 7 number of data register */
+
+#define STM32_DMA_CPAR1_OFFSET    0x0010 /* DMA channel 1 peripheral address register */
+#define STM32_DMA_CPAR2_OFFSET    0x0024 /* DMA channel 2 peripheral address register */
+#define STM32_DMA_CPAR3_OFFSET    0x0038 /* DMA channel 3 peripheral address register */
+#define STM32_DMA_CPAR4_OFFSET    0x004c /* DMA channel 4 peripheral address register */
+#define STM32_DMA_CPAR5_OFFSET    0x0060 /* DMA channel 5 peripheral address register */
+#define STM32_DMA_CPAR6_OFFSET    0x0074 /* DMA channel 6 peripheral address register */
+#define STM32_DMA_CPAR7_OFFSET    0x0088 /* DMA channel 7 peripheral address register */
+
+#define STM32_DMA_CMAR1_OFFSET    0x0014 /* DMA channel 1 memory address register */
+#define STM32_DMA_CMAR2_OFFSET    0x0028 /* DMA channel 2 memory address register */
+#define STM32_DMA_CMAR3_OFFSET    0x003c /* DMA channel 3 memory address register */
+#define STM32_DMA_CMAR4_OFFSET    0x0050 /* DMA channel 4 memory address register */
+#define STM32_DMA_CMAR5_OFFSET    0x0064 /* DMA channel 5 memory address register */
+#define STM32_DMA_CMAR6_OFFSET    0x0078 /* DMA channel 6 memory address register */
+#define STM32_DMA_CMAR7_OFFSET    0x008c /* DMA channel 7 memory address register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_DMA1_ISRC           (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
+#define STM32_DMA1_IFCR           (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
+
+#define STM32_DMA1_CCR(n)         (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
+#define STM32_DMA1_CCR1           (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
+#define STM32_DMA1_CCR2           (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
+#define STM32_DMA1_CCR3           (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
+#define STM32_DMA1_CCR4           (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
+#define STM32_DMA1_CCR5           (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
+#define STM32_DMA1_CCR6           (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
+#define STM32_DMA1_CCR7           (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
+
+#define STM32_DMA1_CNDTR(n)       (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
+#define STM32_DMA1_CNDTR1         (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
+#define STM32_DMA1_CNDTR2         (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
+#define STM32_DMA1_CNDTR3         (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
+#define STM32_DMA1_CNDTR4         (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
+#define STM32_DMA1_CNDTR5         (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
+#define STM32_DMA1_CNDTR6         (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
+#define STM32_DMA1_CNDTR7         (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
+
+#define STM32_DMA1_CPAR(n)        (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
+#define STM32_DMA1_CPAR1          (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
+#define STM32_DMA1_CPAR2          (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
+#define STM32_DMA1_CPAR3          (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
+#define STM32_DMA1_CPAR4          (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
+#define STM32_DMA1_CPAR5          (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
+#define STM32_DMA1_CPAR6          (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
+#define STM32_DMA1_CPAR7          (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
+
+#define STM32_DMA1_CMAR(n)        (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
+#define STM32_DMA1_CMAR1          (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
+#define STM32_DMA1_CMAR2          (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
+#define STM32_DMA1_CMAR3          (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
+#define STM32_DMA1_CMAR4          (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
+#define STM32_DMA1_CMAR5          (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
+#define STM32_DMA1_CMAR6          (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
+#define STM32_DMA1_CMAR7          (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
+
+#define STM32_DMA2_ISRC           (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
+#define STM32_DMA2_IFCR           (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
+
+#define STM32_DMA2_CCR(n)         (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
+#define STM32_DMA2_CCR1           (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
+#define STM32_DMA2_CCR2           (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
+#define STM32_DMA2_CCR3           (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
+#define STM32_DMA2_CCR4           (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
+#define STM32_DMA2_CCR5           (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
+
+#define STM32_DMA2_CNDTR(n)       (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
+#define STM32_DMA2_CNDTR1         (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
+#define STM32_DMA2_CNDTR2         (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
+#define STM32_DMA2_CNDTR3         (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
+#define STM32_DMA2_CNDTR4         (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
+#define STM32_DMA2_CNDTR5         (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
+
+#define STM32_DMA2_CPAR(n)        (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
+#define STM32_DMA2_CPAR1          (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
+#define STM32_DMA2_CPAR2          (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
+#define STM32_DMA2_CPAR3          (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
+#define STM32_DMA2_CPAR4          (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
+#define STM32_DMA2_CPAR5          (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
+
+#define STM32_DMA2_CMAR(n)        (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
+#define STM32_DMA2_CMAR1          (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
+#define STM32_DMA2_CMAR2          (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
+#define STM32_DMA2_CMAR3          (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
+#define STM32_DMA2_CMAR4          (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
+#define STM32_DMA2_CMAR5          (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define DMA_CHAN_SHIFT(n)         ((n) << 2)
+#define DMA_CHAN_MASK             0x0f
+#define DMA_CHAN_GIF_BIT          (1 << 0)  /* Bit 0: Channel Global interrupt flag */
+#define DMA_CHAN_TCIF_BIT         (1 << 1)  /* Bit 1: Channel Transfer Complete flag */
+#define DMA_CHAN_HTIF_BIT         (1 << 2)  /* Bit 2: Channel Half Transfer flag */
+#define DMA_CHAN_TEIF_BIT         (1 << 3)  /* Bit 3: Channel Transfer Error flag */
+
+/* DMA interrupt status register */
+
+#define DMA_ISR_CHAN_SHIFT(n)     DMA_CHAN_SHIFT(n)
+#define DMA_ISR_CHAN_MASK(n)      (DMA_CHAN_MASK <<  DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_CHAN1_SHIFT       (0)       /* Bits 3-0:  DMA Channel 1 interrupt status */
+#define DMA_ISR_CHAN1_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN1_SHIFT)
+#define DMA_ISR_CHAN2_SHIFT       (4)       /* Bits 7-4:  DMA Channel 2 interrupt status */
+#define DMA_ISR_CHAN2_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN2_SHIFT)
+#define DMA_ISR_CHAN3_SHIFT       (8)       /* Bits 11-8:  DMA Channel 3 interrupt status */
+#define DMA_ISR_CHAN3_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN3_SHIFT)
+#define DMA_ISR_CHAN4_SHIFT       (12)      /* Bits 15-12:  DMA Channel 4 interrupt status */
+#define DMA_ISR_CHAN4_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN4_SHIFT)
+#define DMA_ISR_CHAN5_SHIFT       (16)      /* Bits 19-16:  DMA Channel 5 interrupt status */
+#define DMA_ISR_CHAN5_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN5_SHIFT)
+#define DMA_ISR_CHAN6_SHIFT       (20)      /* Bits 23-20:  DMA Channel 6 interrupt status */
+#define DMA_ISR_CHAN6_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN6_SHIFT)
+#define DMA_ISR_CHAN7_SHIFT       (24)      /* Bits 27-24:  DMA Channel 7 interrupt status */
+#define DMA_ISR_CHAN7_MASK        (DMA_CHAN_MASK <<  DMA_ISR_CHAN7_SHIFT)
+
+#define DMA_ISR_GIF(n)            (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_TCIF(n)           (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_HTIF(n)           (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_TEIF(n)           (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+
+/* DMA interrupt flag clear register */
+
+#define DMA_IFCR_CHAN_SHIFT(n)    DMA_CHAN_SHIFT(n)
+#define DMA_IFCR_CHAN_MASK(n)     (DMA_CHAN_MASK <<  DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CHAN1_SHIFT      (0)       /* Bits 3-0:  DMA Channel 1 interrupt flag clear */
+#define DMA_IFCR_CHAN1_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN1_SHIFT)
+#define DMA_IFCR_CHAN2_SHIFT      (4)       /* Bits 7-4:  DMA Channel 2 interrupt flag clear */
+#define DMA_IFCR_CHAN2_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN2_SHIFT)
+#define DMA_IFCR_CHAN3_SHIFT      (8)       /* Bits 11-8:  DMA Channel 3 interrupt flag clear */
+#define DMA_IFCR_CHAN3_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN3_SHIFT)
+#define DMA_IFCR_CHAN4_SHIFT      (12)      /* Bits 15-12:  DMA Channel 4 interrupt flag clear */
+#define DMA_IFCR_CHAN4_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN4_SHIFT)
+#define DMA_IFCR_CHAN5_SHIFT      (16)      /* Bits 19-16:  DMA Channel 5 interrupt flag clear */
+#define DMA_IFCR_CHAN5_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN5_SHIFT)
+#define DMA_IFCR_CHAN6_SHIFT      (20)      /* Bits 23-20:  DMA Channel 6 interrupt flag clear */
+#define DMA_IFCR_CHAN6_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN6_SHIFT)
+#define DMA_IFCR_CHAN7_SHIFT      (24)      /* Bits 27-24:  DMA Channel 7 interrupt flag clear */
+#define DMA_IFCR_CHAN7_MASK       (DMA_CHAN_MASK <<  DMA_IFCR_CHAN7_SHIFT)
+
+#define DMA_IFCR_CGIF(n)          (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CTCIF(n)         (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CHTIF(n)         (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CTEIF(n)         (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+
+/* DMA channel configuration register */
+
+#define DMA_CCR_MEM2MEM           (1 << 14) /* Bit 14: Memory to memory mode */
+#define DMA_CCR_PL_SHIFT          (12)      /* Bits 13-12: Channel Priority level */
+#define DMA_CCR_PL_MASK           (3 << DMA_CCR_PL_SHIFT)
+#  define DMA_CCR_PRILO           (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
+#  define DMA_CCR_PRIMED          (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
+#  define DMA_CCR_PRIHI           (2 << DMA_CCR_PL_SHIFT) /* 10: High */
+#  define DMA_CCR_PRIVERYHI       (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
+#define DMA_CCR_MSIZE_SHIFT       (10)      /* Bits 11-10: Memory size */
+#define DMA_CCR_MSIZE_MASK        (3 << DMA_CCR_MSIZE_SHIFT)
+#  define DMA_CCR_MSIZE_8BITS     (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
+#  define DMA_CCR_MSIZE_16BITS    (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
+#  define DMA_CCR_MSIZE_32BITS    (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
+#define DMA_CCR_PSIZE_SHIFT       (8)       /* Bits 9-8: Peripheral size */
+#define DMA_CCR_PSIZE_MASK        (3 << DMA_CCR_PSIZE_SHIFT)
+#  define DMA_CCR_PSIZE_8BITS     (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
+#  define DMA_CCR_PSIZE_16BITS    (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
+#  define DMA_CCR_PSIZE_32BITS    (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
+#define DMA_CCR_MINC              (1 << 7)  /* Bit 7: Memory increment mode */
+#define DMA_CCR_PINC              (1 << 6)  /* Bit 6: Peripheral increment mode */
+#define DMA_CCR_CIRC              (1 << 5)  /* Bit 5: Circular mode */
+#define DMA_CCR_DIR               (1 << 4)  /* Bit 4: Data transfer direction */
+#define DMA_CCR_TEIE              (1 << 3)  /* Bit 3: Transfer error interrupt enable */
+#define DMA_CCR_HTIE              (1 << 2)  /* Bit 2: Half Transfer interrupt enable */
+#define DMA_CCR_TCIE              (1 << 1)  /* Bit 1: Transfer complete interrupt enable */
+#define DMA_CCR_EN                (1 << 0)  /* Bit 0: Channel enable */
+
+/* DMA channel number of data register */
+
+#define DMA_CNDTR_NDT_SHIFT       (0)       /* Bits 15-0: Number of data to Transfer */
+#define DMA_CNDTR_NDT_MASK       (0xffff << DMA_CNDTR_NDT_SHIFT)
+
+/* DMA Channel mapping.  Each DMA channel has a mapping to several possible
+ * sources/sinks of data.  The requests from peripherals assigned to a channel
+ * are simply OR'ed together before entering the DMA block.  This means that only
+ * one request on a given channel can be enabled at once.
+ */
+
+#define STM32_DMA1_CHAN1          (0)
+#define STM32_DMA1_CHAN2          (1)
+#define STM32_DMA1_CHAN3          (2)
+#define STM32_DMA1_CHAN4          (3)
+#define STM32_DMA1_CHAN5          (4)
+#define STM32_DMA1_CHAN6          (5)
+#define STM32_DMA1_CHAN7          (6)
+
+#define STM32_DMA2_CHAN1          (7)
+#define STM32_DMA2_CHAN2          (8)
+#define STM32_DMA2_CHAN3          (1)
+#define STM32_DMA2_CHAN4          (10)
+#define STM32_DMA2_CHAN5          (11)
+
+#define DMACHAN_ADC1              STM32_DMA1_CHAN1
+#define DMACHAN_TIM2_CH3          STM32_DMA1_CHAN1
+#define DMACHAN_TIM4_CH1          STM32_DMA1_CHAN1
+#define DMACHAN_SPI1_RX           STM32_DMA1_CHAN2
+#define DMACHAN_USART3_TX         STM32_DMA1_CHAN2
+#define DMACHAN_TIM1_CH1          STM32_DMA1_CHAN2
+#define DMACHAN_TIM2_UP           STM32_DMA1_CHAN2
+#define DMACHAN_TIM3_CH3          STM32_DMA1_CHAN2
+#define DMACHAN_SPI1_TX           STM32_DMA1_CHAN3
+#define DMACHAN_USART3_RX         STM32_DMA1_CHAN3
+#define DMACHAN_TIM1_CH2          STM32_DMA1_CHAN3
+#define DMACHAN_TIM3_CH4          STM32_DMA1_CHAN3
+#define DMACHAN_TIM3_UP           STM32_DMA1_CHAN3
+#define DMACHAN_SPI2_RX           STM32_DMA1_CHAN4
+#define DMACHAN_I2S2_RX           STM32_DMA1_CHAN4
+#define DMACHAN_USART1_TX         STM32_DMA1_CHAN4
+#define DMACHAN_I2C2_TX           STM32_DMA1_CHAN4
+#define DMACHAN_TIM1_CH4          STM32_DMA1_CHAN4
+#define DMACHAN_TIM1_TRIG         STM32_DMA1_CHAN4
+#define DMACHAN_TIM1_COM          STM32_DMA1_CHAN4
+#define DMACHAN_TIM4_CH2          STM32_DMA1_CHAN4
+#define DMACHAN_SPI2_TX           STM32_DMA1_CHAN5
+#define DMACHAN_I2S2_TX           STM32_DMA1_CHAN5
+#define DMACHAN_USART1_RX         STM32_DMA1_CHAN5
+#define DMACHAN_I2C2_RX           STM32_DMA1_CHAN5
+#define DMACHAN_TIM1_UP           STM32_DMA1_CHAN5
+#define DMACHAN_TIM2_CH1          STM32_DMA1_CHAN5
+#define DMACHAN_TIM4_CH3          STM32_DMA1_CHAN5
+#define DMACHAN_USART2_RX         STM32_DMA1_CHAN6
+#define DMACHAN_I2C1_TX           STM32_DMA1_CHAN6
+#define DMACHAN_TIM1_CH3          STM32_DMA1_CHAN6
+#define DMACHAN_TIM3_CH1          STM32_DMA1_CHAN6
+#define DMACHAN_TIM3_TRIG         STM32_DMA1_CHAN6
+#define DMACHAN_USART2_TX         STM32_DMA1_CHAN7
+#define DMACHAN_I2C1_RX           STM32_DMA1_CHAN7
+#define DMACHAN_TIM2_CH2          STM32_DMA1_CHAN7
+#define DMACHAN_TIM2_CH4          STM32_DMA1_CHAN7
+#define DMACHAN_TIM4_UP           STM32_DMA1_CHAN7
+#define DMACHAN_SPI3_RX           STM32_DMA2_CHAN1
+#define DMACHAN_I2S3_RX           STM32_DMA2_CHAN1
+#define DMACHAN_TIM5_CH4          STM32_DMA2_CHAN1
+#define DMACHAN_TIM5_TRIG         STM32_DMA2_CHAN1
+#define DMACHAN_TIM8_CH3          STM32_DMA2_CHAN1
+#define DMACHAN_TIM8_UP           STM32_DMA2_CHAN1
+#define DMACHAN_SPI3_TX           STM32_DMA2_CHAN2
+#define DMACHAN_I2S3_TX           STM32_DMA2_CHAN2
+#define DMACHAN_TIM5_CH3          STM32_DMA2_CHAN2
+#define DMACHAN_TIM5_UP           STM32_DMA2_CHAN2
+#define DMACHAN_TIM5_UP           STM32_DMA2_CHAN2
+#define DMACHAN_TIM8_TRIG         STM32_DMA2_CHAN2
+#define DMACHAN_TIM8_COM          STM32_DMA2_CHAN2
+#define DMACHAN_UART4_RX          STM32_DMA2_CHAN3
+#define DMACHAN_TIM6_UP           STM32_DMA2_CHAN3
+#define DMACHAN_DAC_CHAN1         STM32_DMA2_CHAN3
+#define DMACHAN_TIM8_CH1          STM32_DMA2_CHAN3
+#define DMACHAN_SDIO              STM32_DMA2_CHAN4
+#define DMACHAN_TIM5_CH2          STM32_DMA2_CHAN4
+#define DMACHAN_TIM7_UP           STM32_DMA2_CHAN4
+#define DMACHAN_DAC_CHAN2         STM32_DMA2_CHAN4
+#define DMACHAN_ADC3              STM32_DMA2_CHAN5
+#define DMACHAN_UART4_TX          STM32_DMA2_CHAN5
+#define DMACHAN_TIM5_CH1          STM32_DMA2_CHAN5
+#define DMACHAN_TIM8_CH2          STM32_DMA2_CHAN5
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA_H */
--- a/arch/arm/src/stm32/stm32_exti.h
+++ b/arch/arm/src/stm32/stm32_exti.h
@@ -0,0 +1,123 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_exti.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32_STM32_EXTI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_NEXTI            20
+#  define STM32_EXTI_MASK        0x000fffff
+#else
+#  define STM32_NEXTI            19
+#  define STM32_EXTI_MASK        0x0007ffff
+#endif
+
+#define STM32_EXTI_BIT(n)        (1 << (n))
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_EXTI_IMR_OFFSET    0x0000  /* Interrupt mask register */
+#define STM32_EXTI_EMR_OFFSET    0x0004  /* Event mask register */
+#define STM32_EXTI_RTSR_OFFSET   0x0008  /* Rising Trigger selection register */
+#define STM32_EXTI_FTSR_OFFSET   0x000c  /* Falling Trigger selection register */
+#define STM32_EXTI_SWIER_OFFSET  0x0010  /* Software interrupt event register */
+#define STM32_EXTI_PR_OFFSET     0x0014  /* Pending register */
+
+/* Register Addresses ***************************************************************/
+
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Interrupt mask register */
+
+#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Interrupt Mask on line n */
+#define EXTI_IMR_MASK            STM32_EXTI_MASK
+
+/* Event mask register */
+
+#define EXTI_EMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_EMR_SHIFT           (0)     /* Bits 18/19-0:  Event Mask on line n */
+#define EXTI_EMR_MASK            STM32_EXTI_MASK
+
+/* Rising Trigger selection register */
+
+#define EXTI_RTSR_BIT(n)         STM32_EXTI_BIT(n)
+#define EXTI_RTSR_SHIFT          (0)     /* Bits 18/19-0: Rising trigger event configuration bit of line n */
+#define EXTI_RTSR_MASK           STM32_EXTI_MASK
+
+/* Falling Trigger selection register */
+
+#define EXTI_FTSR_BIT(n)         STM32_EXTI_BIT(n)
+#define EXTI_FTSR_SHIFT          (0)     /* Bits 18/19-0: Falling trigger event configuration bit of line n */
+#define EXTI_FTSR_MASK           STM32_EXTI_MASK
+
+/* Software interrupt event register  */
+
+#define EXTI_SWIER_BIT(n)        STM32_EXTI_BIT(n)
+#define EXTI_SWIER_SHIFT         (0)     /*  Bits 18/19-0: Software Interrupt on line n */
+#define EXTI_SWIER_MASK          STM32_EXTI_MASK
+
+/* Pending register */
+
+#define EXTI_IMR_BIT(n)          STM32_EXTI_BIT(n)
+#define EXTI_IMR_SHIFT           (0)     /* Bits 18/19-0: Pending bit on line x */
+#define EXTI_IMR_MASK            STM32_EXTI_MASK
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */
--- a/arch/arm/src/stm32/stm32_flash.h
+++ b/arch/arm/src/stm32/stm32_flash.h
@@ -0,0 +1,99 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_flash.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H
+#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+#include "stm32_memorymap.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_FLASH_ACR_OFFSET     0x0000
+#define STM32_FLASH_KEYR_OFFSET    0x0004
+#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
+#define STM32_FLASH_SR_OFFSET      0x000c
+#define STM32_FLASH_CR_OFFSET      0x0010
+#define STM32_FLASH_AR_OFFSET      0x0014
+#define STM32_FLASH_OBR_OFFSET     0x001c
+#define STM32_FLASH_WRPR_OFFSET    0x0020
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_FLASH_ACR            (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
+#define STM32_FLASH_KEYR           (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
+#define STM32_FLASH_OPTKEYR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
+#define STM32_FLASH_SR             (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
+#define STM32_FLASH_CR             (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
+#define STM32_FLASH_AR             (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
+#define STM32_FLASH_OBR            (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
+#define STM32_FLASH_WRPR           (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+/* TODO: FLASH details from the STM32F10xxx Flash programming manual. */
+
+/* Flash Access Control Register (ACR) */
+
+#define ACR_LATENCY_SHIFT          (0)
+#define ACR_LATENCY_MASK           (7 << ACR_LATENCY_SHIFT)
+#  define ACR_LATENCY_0            (0 << ACR_LATENCY_SHIFT)  /* FLASH Zero Latency cycle */
+#  define ACR_LATENCY_1            (1 << ACR_LATENCY_SHIFT)) /* FLASH One Latency cycle */
+#  define ACR_LATENCY_2            (2 << ACR_LATENCY_SHIFT)  /* FLASH Two Latency cycles */
+#define ACR_HLFCYA                 (1 << 3)                  /* FLASH half cycle access */
+#define ACR_PRTFBE                 (1 << 4)                  /* FLASH prefetch enable */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -0,0 +1,357 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_gpio.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "stm32_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+ 
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const uint32 g_gpiobase[STM32_NGPIO_PORTS] =
+{
+#if STM32_NGPIO_PORTS > 0
+	STM32_GPIOA_BASE,
+#endif
+#if STM32_NGPIO_PORTS > 1
+	STM32_GPIOB_BASE,
+#endif
+#if STM32_NGPIO_PORTS > 2
+	STM32_GPIOC_BASE,
+#endif
+#if STM32_NGPIO_PORTS > 3
+	STM32_GPIOD_BASE,
+#endif
+#if STM32_NGPIO_PORTS > 4
+	STM32_GPIOE_BASE,
+#endif
+#if STM32_NGPIO_PORTS > 5
+	STM32_GPIOF_BASE,
+#endif
+#if STM32_NGPIO_PORTS > 6
+	STM32_GPIOG_BASE,
+#endif
+};
+
+#ifdef CONFIG_DEBUG
+static const char g_portchar[8]   = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int stm32_configgpio(uint32 cfgset)
+{
+  uint32 base;
+  uint32 cr;
+  uint32 regval;
+  uint32 regaddr;
+  unsigned int port;
+  unsigned int pin;
+  unsigned int pos;
+  unsigned int modecnf;
+  boolean input;
+ 
+  /* Verify that this hardware supports the select GPIO port */
+
+  port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  if (port < STM32_NGPIO_PORTS)
+    {
+      /* Get the port base address */
+
+      base = g_gpiobase[port];
+
+      /* Get the pin number and select the port configuration register for that pin */
+
+      pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+      if (pin < 8)
+        {
+          cr  = base + STM32_GPIO_CRL_OFFSET;
+          pos = pin;
+        }
+      else
+        {
+          cr  = base + STM32_GPIO_CRH_OFFSET;
+          pos = pin - 8;
+        }
+
+      /* Input or output? */
+
+      input = ((cfgset & GPIO_INPUT) != 0);
+
+      /* Decode the mode and configuration */
+
+      if (input)
+        {
+          /* Input.. force mode = INPUT */
+
+          modecnf = 0;
+        }
+      else
+        {
+          /* Output or alternate function */
+
+          modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
+        }
+
+      modecnf |= ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) << 2;
+     
+      /* Set the port configuration register */
+
+      regval = getreg32(cr);
+      regval &= ~(GPIO_CR_MODECNF_MASK(pos));
+      regval |= (modecnf << GPIO_CR_MODECNF_SHIFT(pos));
+      putreg32(regval, cr);
+
+      /* Set or reset the corresponding BRR/BSRR bit */
+
+      if (!input)
+        {
+          /* It is an output or an alternate function.  We have to look at the CNF
+           * bits to know which.
+           */
+
+          unsigned int cnf = (cfgset & GPIO_CNF_MASK);
+          if (cnf == GPIO_CNF_OUTPP || cnf == GPIO_CNF_OUTOD)
+            {
+
+              /* Its an output... set the pin to the correct initial state */
+
+              if ((cfgset & GPIO_OUTPUT_SET) != 0)
+               {
+                  /* Use the BSRR register to set the output */
+
+                  regaddr = base + STM32_GPIO_BSRR_OFFSET;
+                }
+              else
+                {
+                  /* Use the BRR register to clear */
+
+                  regaddr = base + STM32_GPIO_BRR_OFFSET;
+                }
+            }
+          else
+            {
+              /* Its an alternate function pin... we can return early */
+
+              return OK;
+            }
+        }
+      else
+        {
+          /* It is an input pin... If it is pull-down or pull up,
+           * then we need to set the ODR appropriately for that
+           * function.
+           */
+        
+          if ((cfgset & GPIO_CNF_MASK) == GPIO_CNF_INPULLUP)
+            {
+              /* Set the ODR bit (using BSRR) to one for the PULL-UP functionality */
+            
+	          regaddr = base + STM32_GPIO_BSRR_OFFSET;
+            }
+          else if ((cfgset & GPIO_CNF_MASK) == GPIO_CNF_INPULLDWN)
+            {
+              /* Clear the ODR bit (using BRR) to zero for the PULL-DOWN functionality */
+
+	          regaddr = base + STM32_GPIO_BRR_OFFSET;
+            }
+            else
+            {
+              /* Neither... we can return early */
+
+              return OK;
+            }
+        }
+
+        regval = getreg32(regaddr);
+        regval |= (1 << pin);
+        putreg32(regval, regaddr);
+        return OK;
+    }
+  return ERROR;
+}
+
+/****************************************************************************
+ * Name: stm32_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void stm32_gpiowrite(uint32 pinset, boolean value)
+{
+  uint32 base;
+  uint32 offset;
+  unsigned int port;
+  unsigned int pin;
+
+  port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  if (port < STM32_NGPIO_PORTS)
+    {
+      /* Get the port base address */
+
+      base = g_gpiobase[port];
+
+      /* Get the pin number  */
+
+      pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+
+      /* Set or clear the output on the pin */
+
+      if (value)
+        {
+          offset = STM32_GPIO_BSRR_OFFSET;
+        }
+      else
+          offset = STM32_GPIO_BRR_OFFSET;
+        {
+        }
+      putreg32((1 << pin), base + offset);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+boolean stm32_gpioread(uint32 pinset)
+{
+  uint32 base;
+  unsigned int port;
+  unsigned int pin;
+
+  port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  if (port < STM32_NGPIO_PORTS)
+    {
+      /* Get the port base address */
+
+      base = g_gpiobase[port];
+
+      /* Get the pin number and return the input state of that pin */
+
+      pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+      return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
+    }
+  return 0;
+}
+
+/****************************************************************************
+ * Function:  stm32_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+int stm32_dumpgpio(uint32 pinset, const char *msg)
+{
+  irqstate_t   flags;
+  uint32       base;
+  unsigned int port;
+  unsigned int pin;
+
+  /* Get the base address associated with the GPIO port */
+
+  port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  pin  = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+  base = g_gpiobase[port];
+
+  /* The following requires exclusive access to the GPIO registers */
+
+  flags = irqsave();
+  lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
+        g_portchar[port], pinset, base, msg);
+  if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
+    {
+      lldbg("  CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
+            getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET),
+            getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET),
+            getreg32(base + STM32_GPIO_LCKR_OFFSET));
+      lldbg("  EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
+            getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
+            getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2),
+            getreg32(STM32_AFIO_EXTICR3), getreg32(STM32_AFIO_EXTICR4));
+    }
+  else
+    {
+      lldbg("  GPIO%c not enabled: APB2ENR: %08x\n",
+            g_portchar[port], getreg32(STM32_RCC_APB2ENR));
+    }
+  irqrestore(flags);
+  return OK;
+}
+#endif
+
+
+
--- a/arch/arm/src/stm32/stm32_gpio.h
+++ b/arch/arm/src/stm32/stm32_gpio.h
@@ -0,0 +1,375 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_gpio.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_GPIO_H
+#define __ARCH_ARM_SRC_STM32_STM32_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+#define STM32_NGPIO_PORTS            ((STM32_NGPIO + 15) >> 4)
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_GPIO_CRL_OFFSET        0x0000  /* Port configuration register low */
+#define STM32_GPIO_CRH_OFFSET        0x0004  /* Port configuration register high */
+#define STM32_GPIO_IDR_OFFSET        0x0008  /* Port input data register */
+#define STM32_GPIO_ODR_OFFSET        0x000c  /* Port output data register */
+#define STM32_GPIO_BSRR_OFFSET       0x0010  /* Port bit set/reset register */
+#define STM32_GPIO_BRR_OFFSET        0x0014  /* Port bit reset register */
+#define STM32_GPIO_LCKR_OFFSET       0x0018  /* Port configuration lock register */
+
+#define STM32_AFIO_EVCR_OFFSET       0x0000  /* Event control register */
+#define STM32_AFIO_MAPR_OFFSET       0x0004  /* AF remap and debug I/O configuration register */
+#define STM32_AFIO_EXTICR1_OFFSET    0x0008  /* External interrupt configuration register 1 */
+#define STM32_AFIO_EXTICR2_OFFSET    0x000c  /* External interrupt configuration register 2 */
+#define STM32_AFIO_EXTICR3_OFFSET    0x0010  /* External interrupt configuration register 3 */
+#define STM32_AFIO_EXTICR4_OFFSET    0x0014  /* External interrupt configuration register 4 */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NGPIO_PORTS > 0
+#  define STM32_GPIOA_CRL            (STM32_GPIOA_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOA_CRH            (STM32_GPIOA_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOA_IDR            (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOA_ODR            (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOA_BSRR           (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOA_BRR            (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOA_LCKR           (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 1
+#  define STM32_GPIOB_CRL            (STM32_GPIOB_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOB_CRH            (STM32_GPIOB_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOB_IDR            (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOB_ODR            (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOB_BSRR           (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOB_BRR            (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOB_LCKR           (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 2
+#  define STM32_GPIOC_CRL            (STM32_GPIOC_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOC_CRH            (STM32_GPIOC_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOC_IDR            (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOC_ODR            (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOC_BSRR           (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOC_BRR            (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOC_LCKR           (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 3
+#  define STM32_GPIOD_CRL            (STM32_GPIOD_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOD_CRH            (STM32_GPIOD_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOD_IDR            (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOD_ODR            (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOD_BSRR           (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOD_BRR            (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOD_LCKR           (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 4
+#  define STM32_GPIOE_CRL            (STM32_GPIOE_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOE_CRH            (STM32_GPIOE_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOE_IDR            (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOE_ODR            (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOE_BSRR           (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOE_BRR            (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOE_LCKR           (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 5
+#  define STM32_GPIOF_CRL            (STM32_GPIOF_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOF_CRH            (STM32_GPIOF_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOF_IDR            (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOF_ODR            (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOF_BSRR           (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOF_BRR            (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOF_LCKR           (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 6
+#  define STM32_GPIOG_CRL            (STM32_GPIOG_BASE+STM32_GPIO_CRL_OFFSET)
+#  define STM32_GPIOG_CRH            (STM32_GPIOG_BASE+STM32_GPIO_CRH_OFFSET)
+#  define STM32_GPIOG_IDR            (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
+#  define STM32_GPIOG_ODR            (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
+#  define STM32_GPIOG_BSRR           (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
+#  define STM32_GPIOG_BRR            (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET)
+#  define STM32_GPIOG_LCKR           (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#define STM32_AFIO_EVCR              (STM32_AFIO_BASE+STM32_AFIO_EVCR_OFFSET)
+#define STM32_AFIO_MAPR              (STM32_AFIO_BASE+STM32_AFIO_MAPR_OFFSET)
+#define STM32_AFIO_EXTICR1           (STM32_AFIO_BASE+STM32_AFIO_EXTICR1_OFFSET)
+#define STM32_AFIO_EXTICR2           (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
+#define STM32_AFIO_EXTICR3           (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
+#define STM32_AFIO_EXTICR4           (STM32_AFIO_BASE+STM32_AFIO_EXTICR4_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Port configuration register low */
+
+#define GPIO_CR_MODE_SHIFT(n)        ((n) << 2)
+#define GPIO_CR_MODE_MASK(n)         (3 << GPIO_CR_MODE_SHIFT(n))
+#define GPIO_CR_CNF_SHIFT(n)         (2 + ((n) << 2))
+#define GPIO_CR_CNF_MASK(n)          (3 << GPIO_CR_CNF_SHIFT(n))
+
+#define GPIO_CR_MODECNF_SHIFT(n)     ((n) << 2)
+#define GPIO_CR_MODECNF_MASK(n)      (0x0f << GPIO_CR_MODECNF_SHIFT(n))
+
+#define GPIO_CRL_MODE0_SHIFT         (0)     /* Bits 1:0: Port mode bits */
+#define GPIO_CRL_MODE0_MASK          (3 << GPIO_CRL_MODE0_SHIFT)
+#define GPIO_CRL_CNF0_SHIFT          (2)     /* Bits 3:2: Port configuration bits */
+#define GPIO_CRL_CNF0_MASK           (3 << GPIO_CRL_CNF0_SHIFT)
+#define GPIO_CRL_MODE1_SHIFT         (4)     /* Bits 5:4: Port mode bits */
+#define GPIO_CRL_MODE1_MASK          (3 << GPIO_CRL_MODE1_SHIFT)
+#define GPIO_CRL_CNF1_SHIFT          (6)     /* Bits 7:6: Port configuration bits */
+#define GPIO_CRL_CNF1_MASK           (3 << GPIO_CRL_CNF1_SHIFT)
+#define GPIO_CRL_MODE2_SHIFT         (8)     /* Bits 9:8: Port mode bits */
+#define GPIO_CRL_MODE2_MASK          (3 << GPIO_CRL_MODE2_SHIFT)
+#define GPIO_CRL_CNF2_SHIFT          (10)     /* Bits 11:10: Port configuration bits */
+#define GPIO_CRL_CNF2_MASK           (3 << GPIO_CRL_CNF2_SHIFT)
+#define GPIO_CRL_MODE3_SHIFT         (12)     /* Bits 13:12: Port mode bits */
+#define GPIO_CRL_MODE3_MASK          (3 << GPIO_CRL_MODE3_SHIFT)
+#define GPIO_CRL_CNF3_SHIFT          (14)     /* Bits 15:14: Port configuration bits */
+#define GPIO_CRL_CNF3_MASK           (3 << GPIO_CRL_CNF3_SHIFT)
+#define GPIO_CRL_MODE4_SHIFT         (16)     /* Bits 17:16: Port mode bits */
+#define GPIO_CRL_MODE4_MASK          (3 << GPIO_CRL_MODE4_SHIFT)
+#define GPIO_CRL_CNF4_SHIFT          (18)     /* Bits 19:18: Port configuration bits */
+#define GPIO_CRL_CNF4_MASK           (3 << GPIO_CRL_CNF4_SHIFT)
+#define GPIO_CRL_MODE5_SHIFT         (20)     /* Bits 21:20: Port mode bits */
+#define GPIO_CRL_MODE5_MASK          (3 << GPIO_CRL_MODE5_SHIFT)
+#define GPIO_CRL_CNF5_SHIFT          (22)     /* Bits 23:22: Port configuration bits */
+#define GPIO_CRL_CNF5_MASK           (3 << GPIO_CRL_CNF5_SHIFT)
+#define GPIO_CRL_MODE6_SHIFT         (24)     /* Bits 25:24: Port mode bits */
+#define GPIO_CRL_MODE6_MASK          (3 << GPIO_CRL_MODE6_SHIFT)
+#define GPIO_CRL_CNF6_SHIFT          (26)     /* Bits 27:26: Port configuration bits */
+#define GPIO_CRL_CNF6_MASK           (3 << GPIO_CRL_CNF6_SHIFT)
+#define GPIO_CRL_MODE7_SHIFT         (28)     /* Bits 29:28: Port mode bits */
+#define GPIO_CRL_MODE7_MASK          (3 << GPIO_CRL_MODE7_SHIFT)
+#define GPIO_CRL_CNF7_SHIFT          (30)     /* Bits 31:30: Port configuration bits */
+#define GPIO_CRL_CNF7_MASK           (3 << GPIO_CRL_CNF7_SHIFT)
+
+#define GPIO_CR_CNF_INANALOG         (0)       /* 00: Analog input mode */
+#define GPIO_CR_CNF_INFLOAT          (1)       /* 01: Floating input (reset state) */
+#define GPIO_CR_CNF_INPULLUD         (2)       /* 10: Input with pull-up / pull-down */
+
+#define GPIO_CR_CNF_OUTPP            (0)       /* 00: General purpose output push-pull */
+#define GPIO_CR_CNF_OUTOD            (1)       /* 01: General purpose output Open-drain */
+#define GPIO_CR_CNF_OUTALTPP         (3)       /* 10: Alternate function output Push-pull */
+#define GPIO_CR_CNF_OUTALTOD         (6)       /* 11: Alternate function output Open-drain */
+
+#define GPIO_CR_MODE_INRST           (0)       /* 00: Input mode (reset state) */
+#define GPIO_CR_MODE_OUT10MHz        (1)       /* 01: Output mode, max speed 10 MHz */
+#define GPIO_CR_MODE_OUT2MHz         (2)       /* 10: Output mode, max speed 2 MHz */
+#define GPIO_CR_MODE_OUT50MHz        (3)       /* 11: Output mode, max speed 50 MHz */
+
+/* Port configuration register high */
+
+#define GPIO_CRH_MODE8_SHIFT         (0)     /* Bits 1:0: Port mode bits */
+#define GPIO_CRH_MODE8_MASK          (3 << GPIO_CRH_MODE8_SHIFT)
+#define GPIO_CRH_CNF8_SHIFT          (2)     /* Bits 3:2: Port configuration bits */
+#define GPIO_CRH_CNF8_MASK           (3 << GPIO_CRH_CNF8_SHIFT)
+#define GPIO_CRH_MODE9_SHIFT         (4)     /* Bits 5:4: Port mode bits */
+#define GPIO_CRH_MODE9_MASK          (3 << GPIO_CRH_MODE9_SHIFT)
+#define GPIO_CRH_CNF9_SHIFT          (6)     /* Bits 7:6: Port configuration bits */
+#define GPIO_CRH_CNF9_MASK           (3 << GPIO_CRH_CNF9_SHIFT)
+#define GPIO_CRH_MODE10_SHIFT        (8)     /* Bits 9:8: Port mode bits */
+#define GPIO_CRH_MODE10_MASK         (3 << GPIO_CRH_MODE10_SHIFT)
+#define GPIO_CRH_CNF10_SHIFT         (10)     /* Bits 11:10: Port configuration bits */
+#define GPIO_CRH_CNF10_MASK          (3 << GPIO_CRH_CNF10_SHIFT)
+#define GPIO_CRH_MODE11_SHIFT        (12)     /* Bits 13:12: Port mode bits */
+#define GPIO_CRH_MODE11_MASK         (3 << GPIO_CRH_MODE11_SHIFT)
+#define GPIO_CRH_CNF11_SHIFT         (14)     /* Bits 15:14: Port configuration bits */
+#define GPIO_CRH_CNF11_MASK          (3 << GPIO_CRH_CNF11_SHIFT)
+#define GPIO_CRH_MODE12_SHIFT        (16)     /* Bits 17:16: Port mode bits */
+#define GPIO_CRH_MODE12_MASK         (3 << GPIO_CRH_MODE12_SHIFT)
+#define GPIO_CRH_CNF12_SHIFT         (18)     /* Bits 19:18: Port configuration bits */
+#define GPIO_CRH_CNF12_MASK          (3 << GPIO_CRH_CNF12_SHIFT)
+#define GPIO_CRH_MODE13_SHIFT        (20)     /* Bits 21:20: Port mode bits */
+#define GPIO_CRH_MODE13_MASK         (3 << GPIO_CRH_MODE13_SHIFT)
+#define GPIO_CRH_CNF13_SHIFT         (22)     /* Bits 23:22: Port configuration bits */
+#define GPIO_CRH_CNF13_MASK          (3 << GPIO_CRH_CNF13_SHIFT)
+#define GPIO_CRH_MODE14_SHIFT        (24)     /* Bits 25:24: Port mode bits */
+#define GPIO_CRH_MODE14_MASK         (3 << GPIO_CRH_MODE14_SHIFT)
+#define GPIO_CRH_CNF14_SHIFT         (26)     /* Bits 27:26: Port configuration bits */
+#define GPIO_CRH_CNF14_MASK          (3 << GPIO_CRH_CNF14_SHIFT)
+#define GPIO_CRH_MODE15_SHIFT        (28)     /* Bits 29:28: Port mode bits */
+#define GPIO_CRH_MODE15_MASK         (3 << GPIO_CRH_MODE15_SHIFT)
+#define GPIO_CRH_CNF15_SHIFT         (30)     /* Bits 31:30: Port configuration bits */
+#define GPIO_CRL_CNF15_MASK          (3 << GPIO_CRL_CNF15_SHIFT)
+
+/* Port input/ouput data register */
+
+#define GPIO_IDR(n)                  (1 << (n))
+#define GPIO_ODR(n)                  (1 << (n))
+
+/* Port bit set/reset register */
+
+#define GPIO_BSRR_RESET(n)           (1 << ((n)+16))
+#define GPIO_BSRR_SET(n)             (1 << (n))
+#define GPIO_BRR(n)                  (1 << (n))
+
+/* Port configuration lock register */
+
+#define GPIO_LCKR_LCKK               (1 << 16) /* Bit 16: Lock key */
+#define GPIO_LCKR_LCK(n)             (1 << (n))
+
+/* Event control register */
+
+#define AFIO_EVCR_PIN_SHIFT          (0)       /* Bits 3-0: Pin selection */
+#define AFIO_EVCR_PIN_MASK           (0x0f << AFIO_EVCR_PIN_SHIFT)
+#define AFIO_EVCR_PORT_SHIFT         (4)       /* Bits 6-4: Port selection */
+#define AFIO_EVCR_PORT_MASK          (7 << AFIO_EVCR_PORT_SHIFT)
+#  define AFIO_EVCR_PORTA            (0 << AFIO_EVCR_PORT_SHIFT) /* 000: PA selected */
+#  define AFIO_EVCR_PORTB            (1 << AFIO_EVCR_PORT_SHIFT) /* 001: PB selected */
+#  define AFIO_EVCR_PORTC            (2 << AFIO_EVCR_PORT_SHIFT) /* 010: PC selected */
+#  define AFIO_EVCR_PORTD            (3 << AFIO_EVCR_PORT_SHIFT) /* 011: PD selected */
+#  define AFIO_EVCR_PORTE            (4 << AFIO_EVCR_PORT_SHIFT) /* 100: PE selected */
+#define AFIO_EVCR_EVOE               (1 << 7)  /* Bit 7: Event Output Enable */
+
+/* AF remap and debug I/O configuration register */
+
+#define AFIO_MAPR_SWJ_CFG_SHIFT      (24)      /* Bits 26-24: Serial Wire JTAG configuration*/
+#define AFIO_MAPR_SWJ_CFG_MASK       (7 << AFIO_MAPR_SWJ_CFG_SHIFT)
+#  define AFIO_MAPR_SWJRST           (0 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 000: Full SWJ (JTAG-DP + SW-DP): Reset State */
+#  define AFIO_MAPR_SWJ              (1 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#  define AFIO_MAPR_SWDP             (2 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 010: JTAG-DP Disabled and SW-DP Enabled */
+#  define AFIO_MAPR_DISAB            (4 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 100: JTAG-DP Disabled and SW-DP Disabled */
+#define AFIO_MAPR_PD01_REMAP         (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_CAN_REMAP_SHIFT    (13)      /* Bits 14-13: CAN Alternate function remapping */
+#define AFIO_MAPR_CAN_REMAP_MASK     (3 << AFIO_MAPR_CAN_REMAP_SHIFT)
+#  define AFIO_MAPR_PA1112           (0 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 00: CANRX mapped to PA11, CANTX mapped to PA12 */
+#  define AFIO_MAPR_PB89             (2 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */
+#  define AFIO_MAPR_PD01             (3 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */
+#define AFIO_MAPR_TIM4_REMAP         (1 << 12) /* Bit 12: TIM4 remapping */
+#define AFIO_MAPR_TIM3_REMAP_SHIFT  (10)      /* Bits 11-10: TIM3 remapping */
+#define AFIO_MAPR_TIM3_REMAP_MASK    (3 << AFIO_MAPR_TIM3_REMAP_SHIFT)
+#  define AFIO_MAPR_TIM3_NOREMAP     (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#  define AFIO_MAPR_TIM3_PARTREMAP   (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#  define AFIO_MAPR_TIM3_FULLREMAP   (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+#define AFIO_MAPR_TIM2_REMAP_SHIFT   (8)       /* Bits 9-8: TIM2 remapping */
+#define AFIO_MAPR_TIM2_REMAP_MASK    (3 << AFIO_MAPR_TIM2_REMAP_SHIFT)
+#  define AFIO_MAPR_TIM2_NOREMAP     (0 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#  define AFIO_MAPR_TIM2_PARTREMAP1  (1 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#  define AFIO_MAPR_TIM2_PARTREMAP2  (2 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#  define AFIO_MAPR_TIM2_FULLREMAP   (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM1_REMAP_SHIFT   (6)       /* Bits 7-6: TIM1 remapping */
+#define AFIO_MAPR_TIM1_REMAP_MASK    (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) 
+#  define AFIO_MAPR_TIM1_NOREMAP     (0 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#  define AFIO_MAPR_TIM1_PARTREMAP   (1 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#  define AFIO_MAPR_TIM1_FULLREMAP   (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+#define AFIO_MAPR_USART3_REMAP_SHIFT (6)       /* Bits 5-4: USART3 remapping */
+#define AFIO_MAPR_USART3_REMAP_MASK  (3 << AFIO_MAPR_USART3_REMAP_SHIFT) 
+#  define AFIO_MAPR_USART3_NOREMAP   (0 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#  define AFIO_MAPR_USART3_PARTREMAP (1 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#  define AFIO_MAPR_USART3_FULLREMAP (3 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+#define AFIO_MAPR_USART2_REMAP       (1 << 3)  /* Bit 3: USART2 remapping */
+#define AFIO_MAPR_USART1_REMAP       (1 << 2)  /* Bit 2: USART1 remapping */
+#define AFIO_MAPR_I2C1_REMAP         (1 << 1)  /* Bit 1: I2C1 remapping */
+#define AFIO_MAPR_SPI1_REMAP         (1 << 0)  /* Bit 0: SPI1 remapping */
+
+/* External interrupt configuration register 1 */
+
+#define AFIO_EXTICR1_EXTI0_SHIFT     (0)       /* Bits 3-0: EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI0_MASK      (0x0f << AFIO_EXTICR1_EXTI0_SHIFT)
+#define AFIO_EXTICR1_EXTI1_SHIFT     (4)       /* Bits 7-4: EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI1_MASK      (0x0f << AFIO_EXTICR1_EXTI1_SHIFT)
+#define AFIO_EXTICR1_EXTI2_SHIFT     (8)       /* Bits 11-8: EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI2_MASK      (0x0f << AFIO_EXTICR1_EXTI2_SHIFT)
+#define AFIO_EXTICR1_EXTI3_SHIFT     (12)      /* Bits 15-12: EXTI 3 configuration */
+#define AFIO_EXTICR1_EXTI3_MASK      (0x0f << AFIO_EXTICR1_EXTI3_SHIFT)
+
+#define AFIO_EXTICR_PORTA            (0)       /* 0000: PA[x] pin */
+#define AFIO_EXTICR_PORTB            (1)       /* 0001: PB[x] pin */
+#define AFIO_EXTICR_PORTC            (2)       /* 0010: PC[x] pin */
+#define AFIO_EXTICR_PORTD            (3)       /* 0011: PD[x] pin */
+#define AFIO_EXTICR_PORTE            (4)       /* 0100: PE[x] pin */
+
+/* External interrupt configuration register 2 */
+
+#define AFIO_EXTICR2_EXTI4_SHIFT     (0)       /* Bits 3-0: EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI4_MASK      (0x0f << AFIO_EXTICR2_EXTI4_SHIFT)
+#define AFIO_EXTICR2_EXTI5_SHIFT     (4)       /* Bits 7-4: EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI5_MASK      (0x0f << AFIO_EXTICR2_EXTI5_SHIFT)
+#define AFIO_EXTICR2_EXTI6_SHIFT     (8)       /* Bits 11-8: EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI6_MASK      (0x0f << AFIO_EXTICR2_EXTI6_SHIFT)
+#define AFIO_EXTICR2_EXTI7_SHIFT     (12)      /* Bits 15-12: EXTI 7 configuration */
+#define AFIO_EXTICR2_EXTI7_MASK      (0x0f << AFIO_EXTICR2_EXTI7_SHIFT)
+
+/* External interrupt configuration register 3 */
+
+#define AFIO_EXTICR3_EXTI8_SHIFT     (0)       /* Bits 3-0: EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI8_MASK      (0x0f << AFIO_EXTICR3_EXTI8_SHIFT)
+#define AFIO_EXTICR3_EXTI9_SHIFT     (4)       /* Bits 7-4: EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI9_MASK      (0x0f << AFIO_EXTICR3_EXTI9_SHIFT)
+#define AFIO_EXTICR3_EXTI10_SHIFT    (8)       /* Bits 11-8: EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI10_MASK     (0x0f << AFIO_EXTICR3_EXTI10_SHIFT)
+#define AFIO_EXTICR3_EXTI11_SHIFT    (12)      /* Bits 15-12: EXTI 11 configuration */
+#define AFIO_EXTICR3_EXTI11_MASK     (0x0f << AFIO_EXTICR3_EXTI11_SHIFT)
+
+/* External interrupt configuration register 4 */
+
+#define AFIO_EXTICR4_EXTI12_SHIFT    (0)       /* Bits 3-0: EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI12_MASK     (0x0f << AFIO_EXTICR4_EXTI12_SHIFT)
+#define AFIO_EXTICR4_EXTI13_SHIFT    (4)       /* Bits 7-4: EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI13_MASK     (0x0f << AFIO_EXTICR4_EXTI13_SHIFT)
+#define AFIO_EXTICR4_EXTI14_SHIFT    (8)       /* Bits 11-8: EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI14_MASK     (0x0f << AFIO_EXTICR4_EXTI14_SHIFT)
+#define AFIO_EXTICR4_EXTI15_SHIFT    (12)      /* Bits 15-12: EXTI 15 configuration */
+#define AFIO_EXTICR4_EXTI15_MASK     (0x0f << AFIO_EXTICR4_EXTI15_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_GPIO_H */
--- a/arch/arm/src/stm32/stm32_i2c.h
+++ b/arch/arm/src/stm32/stm32_i2c.h
@@ -0,0 +1,192 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_i2c.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32_STM32_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_I2C_CR1_OFFSET    0x0000  /* Control register 1 (16-bit) */
+#define STM32_I2C_CR2_OFFSET    0x0004  /* Control register 2 (16-bit) */
+#define STM32_I2C_OAR1_OFFSET   0x0008  /* Own address register 1 (16-bit) */
+#define STM32_I2C_OAR2_OFFSET   0x000c  /* Own address register 2 (16-bit) */
+#define STM32_I2C_DR_OFFSET     0x0010  /* Data register (16-bit) */
+#define STM32_I2C_SR1_OFFSET    0x0014  /* Status register 1 (16-bit) */
+#define STM32_I2C_SR2_OFFSET    0x0018  /* Status register 2 (16-bit) */
+#define STM32_I2C_CCR_OFFSET    0x001c  /* Clock control register (16-bit) */
+#define STM32_I2C_TRISE_OFFSET  0x0020  /* TRISE Register (16-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NI2C > 0
+#  define STM32_I2C1_CR1        (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
+#  define STM32_I2C1_CR2        (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
+#  define STM32_I2C1_OAR1       (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
+#  define STM32_I2C1_OAR2       (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
+#  define STM32_I2C1_DR         (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET)
+#  define STM32_I2C1_SR1        (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET)
+#  define STM32_I2C1_SR2        (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET)
+#  define STM32_I2C1_CCR        (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
+#  define STM32_I2C1_TRISE      (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
+#endif
+
+#if STM32_NI2C > 1
+#  define STM32_I2C2_CR1        (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
+#  define STM32_I2C2_CR2        (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
+#  define STM32_I2C2_OAR1       (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
+#  define STM32_I2C2_OAR2       (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
+#  define STM32_I2C2_DR         (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET)
+#  define STM32_I2C2_SR1        (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET)
+#  define STM32_I2C2_SR2        (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET)
+#  define STM32_I2C2_CCR        (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
+#  define STM32_I2C2_TRISE      (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Control register 1 */
+
+#define I2C_CR1_PE              (1 << 0)  /* Bit 0: Peripheral Enable*/
+#define I2C_CR1_SMBUS           (1 << 1)  /* Bit 1: SMBus Mode */
+#define I2C_CR1_SMBTYPE         (1 << 3)  /* Bit 3: SMBus Type */
+#define I2C_CR1_ENARP           (1 << 4)  /* Bit 4: ARP Enable */
+#define I2C_CR1_ENPEC           (1 << 5)  /* Bit 5: PEC Enable */
+#define I2C_CR1_ENGC            (1 << 6)  /* Bit 6: General Call Enable */
+#define I2C_CR1_NOSTRETCH       (1 << 7)  /* Bit 7: Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START           (1 << 8)  /* Bit 8: Start Generation */
+#define I2C_CR1_STOP            (1 << 9)  /* Bit 9: Stop Generation */
+#define I2C_CR1_ACK             (1 << 10) /* Bit 10: Acknowledge Enable */
+#define I2C_CR1_POS             (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC             (1 << 12) /* Bit 12: Packet Error Checking */
+#define I2C_CR1_ALERT           (1 << 13) /* Bit 13: SMBus Alert */
+#define I2C_CR1_SWRST           (1 << 15) /* Bit 15: Software Reset */
+
+/* Control register 2 */
+
+#define I2C_CR2_FREQ_SHIFT      (0)       /* Bits 5-0: Peripheral Clock Frequency */
+#define I2C_CR2_FREQ_MASK       (0x3f << I2C_CR2_FREQ_SHIFT)
+#define I2C_CR2_ITERREN         (1 << 8)  /* Bit 8: Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN         (1 << 9)  /* Bit 9: Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN         (1 << 10  /* Bit 10: Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN           (1 << 11) /* Bit 11: DMA Requests Enable */
+#define I2C_CR2_LAST            (1 << 12) /* Bit 12: DMA Last Transfer */
+
+/* Own address register 1 */
+
+#define I2C_OAR1_ADD0           (1 << 0)  /* Bit 0: Interface Address */
+#define I2C_OAR1_ADD8_SHIFT     (1)       /* Bits 7-1: Interface Address */
+#define I2C_OAR1_ADD8_MASK      (0x007f << I2C_OAR1_ADD8_SHIFT)
+#define I2C_OAR1_ADD10_SHIFT    (1)       /* Bits 9-1: Interface Address (10-bit addressing mode)*/
+#define I2C_OAR1_ADD10_MASK     (0x01ff << I2C_OAR1_ADD10_SHIFT)
+#define I2C_OAR1_ONE            (1 << 14) /* Bit 14: Must be configured and kept at 1 */
+#define I2C_OAR1_ADDMODE        (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */
+
+/* Own address register 2 */
+
+#define I2C_OAR2_ENDUAL         (1 << 0)  /* Bit 0: Dual addressing mode enable */
+#define I2C_OAR2_ADD2_SHIFT     (1)       /* Bits 7-1: Interface address */
+#define I2C_OAR2_ADD2_MASK      (0x7f << I2C_OAR2_ADD2_SHIFT)
+
+/* Data register */
+
+#define I2C_DR_SHIFT            (0)       /* Bits 7-0: 8-bit Data Register */
+#define I2C_DR_MASK             (0x00ff << I2C_DR_SHIFT)
+
+/* Status register 1 */
+
+#define I2C_SR1_SB              (1 << 0)  /* Bit 0: Start Bit (Master mode) */
+#define I2C_SR1_ADDR            (1 << 1)  /* Bit 1: Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF             (1 << 2)  /* Bit 2: Byte Transfer Finished */
+#define I2C_SR1_ADD10           (1 << 3)  /* Bit 3: 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF           (1 << 4)  /* Bit 4: Stop detection (Slave mode) */
+#define I2C_SR1_RXNE            (1 << 6)  /* Bit 6: Data Register not Empty (receivers) */
+#define I2C_SR1_TXE             (1 << 7)  /* Bit 7: Data Register Empty (transmitters) */
+#define I2C_SR1_BERR            (1 << 8)  /* Bit 8: Bus Error */
+#define I2C_SR1_ARLO            (1 << 9)  /* Bit 9: Arbitration Lost (master mode) */
+#define I2C_SR1_AF              (1 << 10) /* Bit 10: Acknowledge Failure */
+#define I2C_SR1_OVR             (1 << 11) /* Bit 11: Overrun/Underrun */
+#define I2C_SR1_PECERR          (1 << 12) /* Bit 12: PEC Error in reception */
+#define I2C_SR1_TIMEOUT         (1 << 14) /* Bit 14: Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT        (1 << 15) /* Bit 15: SMBus Alert */
+
+/* Status register 2 */
+
+#define I2C_SR2_MSL             (1 << 0)  /* Bit 0: Master/Slave */
+#define I2C_SR2_BUSY            (1 << 1)  /* Bit 1: Bus Busy */
+#define I2C_SR2_TRA             (1 << 2)  /* Bit 2: Transmitter/Receiver */
+#define I2C_SR2_GENCALL         (1 << 4)  /* Bit 4: General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT      (1 << 5)  /* Bit 5: SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST         (1 << 6)  /* Bit 6: SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF           (1 << 7)  /* Bit 7: Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_SHIFT       (1)       /* Bits 15-8: Packet Error Checking Register */
+#define I2C_SR2_PEC_MASK        (0xff << I2C_SR2_PEC_SHIFT)
+
+/* Clock control register */
+
+#define I2C_CCR_CCR_SHIFT       (0)       /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_CCR_MASK        (0x0fff << I2C_CCR_CCR_SHIFT)
+#define I2C_CCR_DUTY            (1 << 14) /* Bit 14: Fast Mode Duty Cycle */
+#define I2C_CCR_FS              (1 << 15) /* Bit 15: I2C Master Mode Selection */
+
+/* TRISE Register */
+
+#define I2C_TRISE_SHIFT         (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */
+#define I2C_TRISE_MASK          (0x3f << I2C_TRISE_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */
--- a/arch/arm/src/stm32/stm32_internal.h
+++ b/arch/arm/src/stm32/stm32_internal.h
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@@ -0,0 +1,474 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_irq.c
+ * arch/arm/src/chip/stm32_irq.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+#include "stm32_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Enable NVIC debug features that are probably only desireable during
+ * bringup
+ */
+
+#undef STM32_IRQ_DEBUG
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+  (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
+   NVIC_SYSH_PRIORITY_DEFAULT << 8  |\
+   NVIC_SYSH_PRIORITY_DEFAULT)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+uint32 *current_regs;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_dumpnvic
+ *
+ * Description:
+ *   Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(STM32_IRQ_DEBUG) && defined (CONFIG_DEBUG)
+static void stm32_dumpnvic(const char *msg, int irq)
+{
+  irqstate_t flags;
+
+  flags = irqsave();
+  slldbg("NVIC (%s, irq=%d):\n", msg, irq);
+  slldbg("  INTCTRL:    %08x VECTAB: %08x\n",
+         getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+#if 0
+  slldbg("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+         getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+         getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+#endif
+  slldbg("  IRQ ENABLE: %08x %08x %08x\n",
+         getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+         getreg32(NVIC_IRQ64_95_ENABLE));
+  slldbg("  SYSH_PRIO:  %08x %08x %08x\n",
+         getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+         getreg32(NVIC_SYSH12_15_PRIORITY));
+  slldbg("  IRQ PRIO:   %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+        getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+        getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+        getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+        getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+  slldbg("              %08x\n", 
+        getreg32(NVIC_IRQ64_67_PRIORITY));
+  irqrestore(flags);
+}
+#else
+#  define stm32_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: stm32_nmi, stm32_mpu, stm32_busfault, stm32_usagefault, stm32_pendsv,
+ *       stm32_dbgmonitor, stm32_pendsv, stm32_reserved
+ *
+ * Description:
+ *   Handlers for various execptions.  None are handled and all are fatal
+ *   error conditions.  The only advantage these provided over the default
+ *   unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+static int stm32_nmi(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! NMI received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int stm32_mpu(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! MPU interrupt received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int stm32_busfault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Bus fault recived\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int stm32_usagefault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Usage fault received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int stm32_pendsv(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! PendSV received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int stm32_dbgmonitor(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Debug Monitor receieved\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int stm32_reserved(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Reserved interrupt\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_irqinfo
+ *
+ * Description:
+ *   Given an IRQ number, provide the register and bit setting to enable or
+ *   disable the irq.
+ *
+ ****************************************************************************/
+
+static int stm32_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
+{
+  DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
+
+  /* Check for external interrupt */
+
+  if (irq >= STM32_IRQ_INTERRUPTS)
+    {
+      if (irq < STM32_IRQ_INTERRUPTS + 32)
+        {
+           *regaddr = NVIC_IRQ0_31_ENABLE;
+           *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS);
+        }
+      if (irq < STM32_IRQ_INTERRUPTS + 64)
+        {
+           *regaddr = NVIC_IRQ32_63_ENABLE;
+           *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS - 32);
+        }
+      else if (irq < NR_IRQS)
+        {
+           *regaddr = NVIC_IRQ64_95_ENABLE;
+           *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS - 64);
+        }
+      else
+        {
+          return ERROR; /* Invalid interrupt */
+        }
+    }
+
+  /* Handle processor exceptions.  Only a few can be disabled */
+
+  else
+    {
+       *regaddr = NVIC_SYSHCON;
+       if (irq == STM32_IRQ_MPU)
+        {
+          *bit = NVIC_SYSHCON_MEMFAULTENA;
+        }
+      else if (irq == STM32_IRQ_BUSFAULT)
+        {
+          *bit = NVIC_SYSHCON_BUSFAULTENA;
+        }
+      else if (irq == STM32_IRQ_USAGEFAULT)
+        {
+          *bit = NVIC_SYSHCON_USGFAULTENA;
+        }
+      else if (irq == STM32_IRQ_SYSTICK)
+        {
+          *regaddr = NVIC_SYSTICK_CTRL;
+          *bit = NVIC_SYSTICK_CTRL_ENABLE;
+        }
+      else
+        {
+          return ERROR; /* Invalid or unsupported exception */
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Disable all interrupts */
+
+  putreg32(0, NVIC_IRQ0_31_ENABLE);
+  putreg32(0, NVIC_IRQ32_63_ENABLE);
+
+  /* The standard location for the vector table is at the beginning of FLASH
+   * at address 0x0800:0000.  If we are using the STMicro DFU bootloader, then
+   * the vector table will be offset to a different location in FLASH and we
+   * will need to set the NVIC vector location to this alternative location.
+   */
+
+#ifdef CONFIG_STM32_DFU
+  putreg32((uint32)stm32_vectors, NVIC_VECTAB);
+#endif
+
+  /* Set all interrrupts (and exceptions) to the default priority */
+
+  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+  putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_IRQ64_67_PRIORITY);
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
+   * exception is used for performing context switches; The Hard Fault
+   * must also be caught because a SVCall may show up as a Hard Fault
+   * under certain conditions.
+   */
+
+  irq_attach(STM32_IRQ_SVCALL, up_svcall);
+  irq_attach(STM32_IRQ_HARDFAULT, up_hardfault);
+
+  /* Set the priority of the SVCall interrupt */
+
+#ifdef CONFIG_ARCH_IRQPRIO
+/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
+#endif
+
+  /* Attach all other processor exceptions (except reset and sys tick) */
+
+#ifdef CONFIG_DEBUG
+  irq_attach(STM32_IRQ_NMI, stm32_nmi);
+  irq_attach(STM32_IRQ_MPU, stm32_mpu);
+  irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);
+  irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault);
+  irq_attach(STM32_IRQ_PENDSV, stm32_pendsv);
+  irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor);
+  irq_attach(STM32_IRQ_RESERVED, stm32_reserved);
+#endif
+
+  stm32_dumpnvic("initial", NR_IRQS);
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* Initialize FIQs */
+
+#ifdef CONFIG_ARCH_FIQ
+  up_fiqinitialize();
+#endif
+
+  /* And finally, enable interrupts */
+
+  setbasepri(NVIC_SYSH_PRIORITY_MAX);
+  irqrestore(0);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  uint32 regaddr;
+  uint32 regval;
+  uint32 bit;
+
+  if (stm32_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Clear the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval &= ~bit;
+      putreg32(regval, regaddr);
+    }
+  stm32_dumpnvic("disable", irq);
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  uint32 regaddr;
+  uint32 regval;
+  uint32 bit;
+
+  if (stm32_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Set the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval |= bit;
+      putreg32(regval, regaddr);
+    }
+  stm32_dumpnvic("enable", irq);
+}
+
+/****************************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ****************************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  up_disable_irq(irq);
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32 regaddr;
+  uint32 regval;
+  int shift;
+
+  DEBUGASSERT(irq >= STM32_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+
+  if (irq < STM32_IRQ_INTERRUPTS)
+    {
+      irq    -= 4;
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+    }
+  else
+    {
+      irq    -= STM32_IRQ_INTERRUPTS;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  regval      = getreg32(regaddr);
+  shift       = ((irq & 3) << 3);
+  regval     &= ~(0xff << shift);
+  regval     |= (priority << shift);
+  putreg32(regval, regaddr);
+
+  stm32_dumpnvic("prioritize", irq);
+  return OK;
+}
+#endif
--- a/arch/arm/src/stm32/stm32_lowputc.c
+++ b/arch/arm/src/stm32/stm32_lowputc.c
@@ -0,0 +1,365 @@
+/**************************************************************************
+ * arch/arm/src/stm32/stm32_lowputc.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_rcc.h"
+#include "stm32_gpio.h"
+#include "stm32_uart.h"
+#include "stm32_internal.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1)
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2)
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3)
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* Select USART parameters for the selected console */
+
+#if defined(CONFIG_USART1_SERIAL_CONSOLE)
+#  define STM32_CONSOLE_BASE     STM32_USART1_BASE
+#  define STM32_APBCLOCK         STM32_PCLK2_FREQUENCY
+#  define STM32_CONSOLE_BAUD     CONFIG_USART1_BAUD
+#  define STM32_CONSOLE_BITS     CONFIG_USART1_BITS
+#  define STM32_CONSOLE_PARITY   CONFIG_USART1_PARITY
+#  define STM32_CONSOLE_2STOP    CONFIG_USART1_2STOP
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#  define STM32_CONSOLE_BASE     STM32_USART2_BASE
+#  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
+#  define STM32_CONSOLE_BAUD     CONFIG_USART2_BAUD
+#  define STM32_CONSOLE_BITS     CONFIG_USART2_BITS
+#  define STM32_CONSOLE_PARITY   CONFIG_USART2_PARITY
+#  define STM32_CONSOLE_2STOP    CONFIG_USART2_2STOP
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#  define STM32_CONSOLE_BASE     STM32_USART2_BASE
+#  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
+#  define STM32_CONSOLE_BAUD     CONFIG_USART2_BAUD
+#  define STM32_CONSOLE_BITS     CONFIG_USART2_BITS
+#  define STM32_CONSOLE_PARITY   CONFIG_USART2_PARITY
+#  define STM32_CONSOLE_2STOP    CONFIG_USART2_2STOP
+#else
+#  error "No CONFIG_USARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* CR1 settings */
+
+#if CONFIG_USART2_BITS == 9
+#  define USART_CR1_M_VALUE USART_CR1_M
+#else
+#  define USART_CR1_M_VALUE 0
+#endif
+
+#if CONFIG_USART2_PARITY == 1
+#  define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
+#elif CONFIG_USART2_PARITY == 2
+#  define USART_CR1_PARITY_VALUE USART_CR1_PCE
+#else
+#  define USART_CR1_PARITY_VALUE 0
+#endif
+
+#define USART_CR1_CLRBITS (USART_CR1_M|USART_CR1_PCE|USART_CR1_PS|USART_CR1_TE|USART_CR1_RE|USART_CR1_ALLINTS)
+#define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE)
+
+/* CR2 settings */
+
+#if CONFIG_USART2_2STOP != 0
+#  define USART_CR2_STOP2_VALUE USART_CR2_STOP2
+#else
+#  define USART_CR2_STOP2_VALUE 0
+#endif
+
+#define USART_CR2_CLRBITS (USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE)
+#define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
+
+/* CR3 settings */
+
+#define USART_CR3_CLRBITS (USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
+#define USART_CR3_SETBITS 0
+
+/* Calculate USART BAUD rate divider
+ *
+ * The baud rate for the receiver and transmitter (Rx and Tx) are both set to
+ * the same value as programmed in the Mantissa and Fraction values of USARTDIV.
+ *
+ *   baud     = fCK / (16 * usartdiv)
+ *   usartdiv = fCK / (16 * baud)
+ *
+ * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, 5
+ * or PCLK2 for USART1).  Example, fCK=72MHz baud=115200, usartdiv=39.0625=39 1/16th;
+ *
+ * First calculate:
+ *
+ *   usartdiv32 = 32 * usartdiv = fCK / (baud/2)
+ *
+ * (NOTE: all standard baud values are even so dividing by two does not
+ * lose precision).  Eg. (same fCK and buad), usartdiv32 = 1250
+ */
+
+#define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1))
+
+/* The mantissa is then usartdiv32 * 32:
+ *
+ *   mantissa = 32 * usartdiv32
+ *
+ * Eg. usartdiv32=1250, mantissa = 39 
+ */
+
+#define STM32_MANTISSA   (STM32_USARTDIV32 >> 5)
+
+/* And the fraction:
+ *
+ *  fraction = (usartdiv32 - mantissa*32 + 1) / 2
+ *
+ * Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625)
+ */
+ 
+#define STM32_FRACTION   ((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
+
+/* And, finally, the BRR value is: */
+
+#define STM32_BRR_VALUE  ((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | (STM32_FRACTION << USART_BRR_FRAC_SHIFT))
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Wait until the TX data register is empty */
+
+  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0);
+
+  /* Then send the character */
+
+  putreg32((uint32)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
+#endif
+}
+
+/**************************************************************************
+ * Name: stm32_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the USART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void stm32_lowsetup(void)
+{
+#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3)
+  uint32 mapr;
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG)
+  uint32 cr;
+#endif
+
+  /* Enable the selected USARTs and configure GPIO pins need byed the
+   * the selected USARTs.  NOTE: The serial driver later depends on
+   * this pin configuration -- whether or not a serial console is selected.
+   *
+   * NOTE: Clocking for USART1, USART2, and/or USART3 was already provided in stm32_rcc.c
+   */
+
+  mapr = getreg32(STM32_AFIO_MAPR);
+
+#ifdef CONFIG_STM32_USART1
+  /* Assume default pin mapping:
+   *
+   *   Alternate  USART1_REMAP USART1_REMAP
+   *   Function   = 0          = 1
+   *   ---------- ------------ ------------
+   *   USART1_TX  PA9          PB6
+   *   USART1_RX  PA10         PB7
+   */
+
+#ifdef CONFIG_STM32_USART1_REMAP
+  mapr |= AFIO_MAPR_USART1_REMAP;
+#else
+  mapr &= ~AFIO_MAPR_USART1_REMAP;
+#endif
+  putreg32(mapr, STM32_AFIO_MAPR);
+
+  stm32_configgpio(GPIO_USART1_TX);
+  stm32_configgpio(GPIO_USART1_RX);
+#endif /* CONFIG_STM32_USART1 */
+
+#ifdef CONFIG_STM32_USART2
+  /* Assume default pin mapping:
+   *
+   *   Alternate  USART2_REMAP USART2_REMAP
+   *   Function   = 0          = 1
+   *   ---------- ------------ ------------
+   *   USART2_CTS PA0          PD3
+   *   USART2_RTS PA1          PD4
+   *   USART2_TX  PA2          PD5
+   *   USART2_RX  PA3          PD6
+   *   USART3_CK  PA4          PD7
+   */
+
+#ifdef CONFIG_STM32_USART2_REMAP
+  mapr |= ~AFIO_MAPR_USART2_REMAP;
+#else
+  mapr &= ~AFIO_MAPR_USART2_REMAP;
+#endif
+  putreg32(mapr, STM32_AFIO_MAPR);
+
+  stm32_configgpio(GPIO_USART2_TX);
+  stm32_configgpio(GPIO_USART2_RX);
+#endif /* CONFIG_STM32_USART2 */
+
+#ifdef CONFIG_STM32_USART3
+  /* Assume default pin mapping:
+   *
+   * Alternate  USART3_REMAP[1:0]  USART3_REMAP[1:0]      USART3_REMAP[1:0]
+   * Function   = “00” (no remap)  = “01” (partial remap) = “11” (full remap)
+   * ---------_ ------------------ ---------------------- --------------------
+   * USART3_TX  PB10               PC10                   PD8
+   * USART3_RX  PB11               PC11                   PD9
+   * USART3_CK  PB12               PC12                   PD10
+   * USART3_CTS PB13               PB13                   PD11
+   * USART3_RTS PB14               PB14                   PD12
+   */
+
+  mapr &= ~AFIO_MAPR_USART3_REMAP_MASK;
+#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
+  mapr |= AFIO_MAPR_USART3_PARTREMAP;
+#elif defined(CONFIG_STM32_USART3_FULL_REMAP)
+  mapr |= AFIO_MAPR_USART3_FULLREMAP;
+#endif
+  putreg32(mapr, STM32_AFIO_MAPR);
+
+  stm32_configgpio(GPIO_USART3_TX);
+  stm32_configgpio(GPIO_USART3_RX);
+#endif /* CONFIG_STM32_USART3 */
+
+  /* Enable and configure the selected console device */
+
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG)
+  /* Configure CR2 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+  cr &= ~USART_CR2_CLRBITS;
+  cr |= USART_CR2_SETBITS;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+
+  /* Configure CR1 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+  cr &= ~USART_CR1_CLRBITS;
+  cr |= USART_CR1_SETBITS;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+
+  /* Configure CR3 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
+  cr &= ~USART_CR3_CLRBITS;
+  cr |= USART_CR3_SETBITS;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
+
+  /* Configure the USART Baud Rate */
+
+  putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
+
+  /* Enable Rx, Tx, and the USART */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+  cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+#endif
+#endif /* CONFIG_STM32_USART1 || CONFIG_STM32_USART2 || CONFIG_STM32_USART3 */
+}
+
+
--- a/arch/arm/src/stm32/stm32_memorymap.h
+++ b/arch/arm/src/stm32/stm32_memorymap.h
@@ -0,0 +1,145 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_memorymap.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* FLASH and SRAM *******************************************************************/
+
+#define STM32_FLASH_BASE    0x08000000     /* 0x08000000 - Up to 512Kb */
+#define STM32_SRAM_BASE     0x20000000     /* 0x20000000 - 64Kb SRAM */
+
+/* Register Base Address ************************************************************/
+
+/* APB1 bus */
+
+#define STM32_TIM2_BASE      0x40000000     /* 0x40000000 - 0x400003ff: TIM2 timer */
+#define STM32_TIM3_BASE      0x40000400     /* 0x40000400 - 0x400007ff: TIM3 timer */
+#define STM32_TIM4_BASE      0x40000800     /* 0x40000800 - 0x40000bff: TIM4 timer */
+#define STM32_TIM5_BASE      0x40000c00     /* 0x40000c00 - 0x40000fff: TIM5 timer */
+#define STM32_TIM6_BASE      0x40001000     /* 0x40001000 - 0x400013ff: TIM6 timer */
+#define STM32_TIM7_BASE      0x40001400     /* 0x40001400 - 0x400007ff: TIM7 timer */
+                                            /* 0x40001800 - 0x40000fff: Reserved */
+#define STM32_RTC_BASE       0x40002800     /* 0x40002800 - 0x40002bff: RTC */
+#define STM32_WWDG_BASE      0x40002C00     /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
+#define STM32_IWDG_BASE      0x40003000     /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
+                                            /* 0x40003400 - 0x400037ff: Reserved */
+#define STM32_SPI2_BASE      0x40003800     /* 0x40003800 - 0x40003bff: SPI2/I22 */
+#define STM32_I2S2_BASE      0x40003800
+#define STM32_SPI3_BASE      0x40003c00     /* 0x40003c00 - 0x40003fff: SPI3/I23 */
+#define STM32_I2S3_BASE      0x40003c00
+                                            /* 0x40004000 - 0x400043ff: Reserved */
+#define STM32_USART2_BASE    0x40004400     /* 0x40004400 - 0x400047ff: USART2 */
+#define STM32_USART3_BASE    0x40004800     /* 0x40004800 - 0x40004bff: USART3 */
+#define STM32_UART4_BASE     0x40004c00     /* 0x40004c00 - 0x40004fff: UART4 */
+#define STM32_UART5_BASE     0x40005000     /* 0x40005000 - 0x400053ff: UART5 */
+#define STM32_I2C1_BASE      0x40005400     /* 0x40005400 - 0x400057ff: I2C1 */
+#define STM32_I2C2_BASE      0x40005800     /* 0x40005800 - 0x40005Bff: I2C2 */
+#define STM32_USB_BASE       0x40005c00     /* 0x40005c00 - 0x40005fff: USB device FS registers */
+#define STM32_USBCANRAM_BASE 0x40006000     /* 0x40006000 - 0x400063ff: Shared USB/CAN SRAM 512 bytes */
+#define STM32_CAN1_BASE      0x40006400     /* 0x40006400 - 0x400067ff: bxCAN1 */
+#define STM32_CAN2_BASE      0x40006800     /* 0x40006800 - 0x40006bff: bxCAN2 */
+#define STM32_BKP_BASE       0x40006c00     /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
+#define STM32_PWR_BASE       0x40007000     /* 0x40007000 - 0x400073ff: Power control PWR */
+#define STM32_DAC_BASE       0x40007400     /* 0x40007400 - 0x400077ff: DAC */
+                                            /* 0x40007800 - 0x4000ffff: Reserved */
+
+/* APB2 bus */
+
+#define STM32_AFIO_BASE      0x40010000     /* 0x40010000 - 0x400103ff: AFIO */
+#define STM32_EXTI_BASE      0x40010400     /* 0x40010400 - 0x400107ff: EXTI */
+#define STM32_GPIOA_BASE     0x40010800     /* 0x40010800 - 0x40010bff: GPIO Port A */
+#define STM32_GPIOB_BASE     0X40010c00     /* 0X40010c00 - 0x40010fff: GPIO Port B */
+#define STM32_GPIOC_BASE     0x40011000     /* 0x40011000 - 0x400113ff: GPIO Port C */
+#define STM32_GPIOD_BASE     0x40011400     /* 0x40011400 - 0x400117ff: GPIO Port D */
+#define STM32_GPIOE_BASE     0x40011800     /* 0x40011800 - 0x40011bff: GPIO Port E */
+#define STM32_GPIOF_BASE     0x40011c00     /* 0x4001c000 - 0x400111ff: GPIO Port F */
+#define STM32_GPIOG_BASE     0x40012000     /* 0x40012000 - 0x400123ff: GPIO Port G */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400 - 0x400127ff: ADC1 */
+#define STM32_ADC2_BASE      0x40012800     /* 0x40012800 - 0x40012bff: ADC2 */
+#define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00 - 0x40012fff: TIM1 timer */
+#define STM32_SPI1_BASE      0x40013000     /* 0x40013000 - 0x400133ff: SPI1 */
+#define STM32_TIM8_BASE      0x40012c00     /* 0x40013400 - 0x400137ff: TIM8 timer */
+#define STM32_USART1_BASE    0x40013800     /* 0x40013800 - 0x40013bff: USART1 */
+#define STM32_ADC3_BASE      0x40012800     /* 0x40012800 - 0x40013fff: ADC3 */
+                                            /* 0x40014000 - 0x40017fff: Reserved */
+/* AHB bus */
+
+#define STM32_SDIO_BASE     0x40020000     /* 0x40018000 - 0x400183ff: SDIO  */
+                                           /* 0x40018400 - 0x40017fff: Reserved */
+#define STM32_DMA1_BASE     0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
+#define STM32_DMA2_BASE     0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
+                                           /* 0x40020800 - 0x40020fff: Reserved */
+#define STM32_RCC_BASE      0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
+                                           /* 0x40021400 - 0x40021fff:  Reserved */
+#define STM32_OTGFS_BASE    0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
+#define STM32_FLASHIF_BASE  0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE      0x40028000     /* 0x40023000 - 0x400233ff: RC */
+                                           /* 0x40023400 - 0x40027fff: Reserved */
+#define STM32_ETHERNET_BASE 0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
+                                           /* 0x40030000 - 0x4fffffff: Reserved */
+
+/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
+ * address range
+ */
+
+#define STM32_SCS_BASE      0xe000e000
+#define STM32_DEBUGMCU_BASE 0xe0042000
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H */
--- a/arch/arm/src/stm32/stm32_pwr.h
+++ b/arch/arm/src/stm32/stm32_pwr.h
@@ -0,0 +1,99 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_pwr.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32_STM32_PWR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_PWR_CR_OFFSET    000x00  /* Power control register */
+#define STM32_PWR_CSR_OFFSET   0x0004  /* Power control/status register */
+
+/* Register Addresses ***************************************************************/
+
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Power control register */
+
+#define PWR_CR_LPDS            (1 << 0)  /* Bit 0: Low-Power Deepsleep */
+#define PWR_CR_PDDS            (1 << 1)  /* Bit 1: Power Down Deepsleep */
+#define PWR_CR_CWUF            (1 << 2)  /* Bit 2: Clear Wakeup Flag */
+#define PWR_CR_CSBF            (1 << 3)  /* Bit 3: Clear Standby Flag */
+#define PWR_CR_PVDE            (1 << 4)  /* Bit 4: Power Voltage Detector Enable */
+#define PWR_CR_PLS_SHIFT       (5)       /* Bits 7-5: PVD Level Selection */
+#define PWR_CR_PLS_MASK        (7 << PWR_CR_PLS_SHIFT)
+#  define PWR_CR_2p2V          (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
+#  define PWR_CR_2p3V          (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
+#  define PWR_CR_2p4V          (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
+#  define PWR_CR_2p5V          (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
+#  define PWR_CR_2p6V          (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
+#  define PWR_CR_2p7V          (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
+#  define PWR_CR_2p8V          (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
+#  define PWR_CR_2p9V          (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
+#define PWR_CR_DBP             (1 << 8)  /* Bit 8: Disable Backup Domain write protection */
+
+/* Power control/status register */
+
+#define PWR_CSR_WUF            (1 << 0)  /* Bit 0: Wakeup Flag */
+#define PWR_CSR_SBF            (1 << 1)  /* Bit 1: Standby Flag */
+#define PWR_CSR_PVDO           (1 << 2)  /* Bit 2: PVD Output */
+#define PWR_CSR_EWUP           (1 << 8)  /* Bit 8: Enable WKUP pin */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */
--- a/arch/arm/src/stm32/stm32_rcc.c
+++ b/arch/arm/src/stm32/stm32_rcc.c
@@ -0,0 +1,421 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_rcc.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <debug.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_rcc.h"
+#include "stm32_flash.h"
+#include "stm32_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+#define HSERDY_TIMEOUT 256
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Put all RCC registers in reset state */
+
+static inline void rcc_reset(void)
+{
+  uint32 regval;
+
+  putreg32(0, STM32_RCC_APB2RSTR);			/* Disable APB2 Peripheral Reset */
+  putreg32(0, STM32_RCC_APB1RSTR);			/* Disable APB1 Peripheral Reset */
+  putreg32(RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR);	/* FLITF and SRAM Clock ON */
+  putreg32(0, STM32_RCC_APB2ENR);			/* Disable APB2 Peripheral Clock */
+  putreg32(0, STM32_RCC_APB1ENR);			/* Disable APB1 Peripheral Clock */
+
+  regval  = getreg32(STM32_RCC_CR);			/* Set the HSION bit */
+  regval |= RCC_CR_HSION;
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CFGR);		/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+  regval &= ~(RCC_CFGR_SW_MASK|RCC_CFGR_HPRE_MASK|RCC_CFGR_PPRE1_MASK|RCC_CFGR_PPRE2_MASK|RCC_CFGR_ADCPRE_MASK|RCC_CFGR_MCO_MASK);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  regval  = getreg32(STM32_RCC_CR);			/* Reset HSEON, CSSON and PLLON bits */
+  regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CR);			/* Reset HSEBYP bit */
+  regval &= ~RCC_CR_HSEBYP;
+  putreg32(regval, STM32_RCC_CR);
+ 
+  regval  = getreg32(STM32_RCC_CFGR);		/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  putreg32(0, STM32_RCC_CIR);				/* Disable all interrupts */
+}
+
+static inline void rcc_enableapb1(void)
+{
+  uint32 regval;
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+#if CONFIG_STM32_TIM2
+  /* Timer 2 clock enable */
+
+  regval |= RCC_APB1ENR_TIM2EN;
+#endif
+
+#if CONFIG_STM32_TIM3
+  /* Timer 3 clock enable */
+
+  regval |= RCC_APB1ENR_TIM3EN;
+#endif
+
+#if CONFIG_STM32_TIM4
+  /* Timer 4 clock enable */
+
+  regval |= RCC_APB1ENR_TIM4EN;
+#endif
+
+#if CONFIG_STM32_TIM5
+  /* Timer 5 clock enable */
+
+  regval |= RCC_APB1ENR_TIM5EN;
+#endif
+
+#if CONFIG_STM32_TIM6
+  /* Timer 6 clock enable */
+
+  regval |= RCC_APB1ENR_TIM6EN;
+#endif
+
+#if CONFIG_STM32_TIM7
+  /* Timer 7 clock enable */
+
+  regval |= RCC_APB1ENR_TIM7EN;
+#endif
+
+#if CONFIG_STM32_WWDG
+  /* Window Watchdog clock enable */
+
+  regval |= RCC_APB1ENR_WWDGEN;
+#endif
+
+#if CONFIG_STM32_SPI2
+  /* SPI 2 clock enable */
+
+  regval |= RCC_APB1ENR_SPI2EN;
+#endif
+  
+#if CONFIG_STM32_SPI4
+  /* SPI 3 clock enable */
+
+  regval |= RCC_APB1ENR_SPI3EN;
+#endif
+
+#if CONFIG_STM32_USART2
+  /* USART 2 clock enable */
+
+  regval |= RCC_APB1ENR_USART2EN;
+#endif
+
+#if CONFIG_STM32_USART3
+  /* USART 3 clock enable */
+
+  regval |= RCC_APB1ENR_USART3EN;
+#endif
+
+#if CONFIG_STM32_UART4
+  /* UART 4 clock enable */
+
+  regval |= RCC_APB1ENR_UART4EN;
+#endif
+
+#if CONFIG_STM32_UART5
+  /* UART 5 clock enable */
+
+  regval |= RCC_APB1ENR_UART5EN;
+#endif
+
+#if CONFIG_STM32_I2C1
+  /* I2C 1 clock enable */
+
+  regval |= RCC_APB1ENR_I2C1EN;
+#endif
+
+#if CONFIG_STM32_I2C2
+  /* I2C 2 clock enable */
+
+  regval |= RCC_APB1ENR_I2C2EN;
+#endif
+
+#if CONFIG_STM32_USB
+  /* USB clock enable */
+
+  regval |= RCC_APB1ENR_USBEN;
+#endif
+
+#if CONFIG_STM32_CAN
+  /* CAN clock enable */
+
+  regval |= RCC_APB1ENR_CANEN;
+#endif
+
+#if CONFIG_STM32_BKP
+  /* Backup interface clock enable */
+
+  regval |= RCC_APB1ENR_BKPEN;
+#endif
+
+#if CONFIG_STM32_PWR
+  /*  Power interface clock enable */
+
+  regval |= RCC_APB1ENR_PWREN;
+#endif
+
+#if CONFIG_STM32_DAC
+  /* DAC interface clock enable */
+
+  regval |= RCC_APB1ENR_DACEN;
+#endif
+  putreg32(regval, STM32_RCC_APB1ENR);
+
+#if CONFIG_STM32_USB
+  /* USB clock divider */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_USBPRE;
+  regval |= STM32_CFGR_USBPRE;
+  putreg32(regval, STM32_RCC_CFGR);
+#endif
+}
+
+static inline void rcc_enableapb2(void)
+{
+  uint32 regval;
+
+  /* Enable GPIOA, GPIOB, ... and AFIO clocks */
+
+  regval = getreg32(STM32_RCC_APB2ENR);
+  regval |= (RCC_APB2ENR_AFIOEN
+#if STM32_NGPIO > 0
+             |RCC_APB2ENR_IOPAEN
+#endif
+#if STM32_NGPIO > 16
+             |RCC_APB2ENR_IOPBEN
+#endif
+#if STM32_NGPIO > 32
+             |RCC_APB2ENR_IOPCEN
+#endif
+#if STM32_NGPIO > 48
+             |RCC_APB2ENR_IOPDEN
+#endif
+#if STM32_NGPIO > 64
+             |RCC_APB2ENR_IOPEEN
+#endif
+#if STM32_NGPIO > 80
+             |RCC_APB2ENR_IOPFEN
+#endif
+#if STM32_NGPIO > 96
+             |RCC_APB2ENR_IOPGEN
+#endif
+             );
+
+#if CONFIG_STM32_ADC1
+  /* ADC 1 interface clock enable */
+
+  regval |= RCC_APB2ENR_ADC1EN;
+#endif
+
+#if CONFIG_STM32_ADC2
+  /* ADC 2 interface clock enable */
+
+  regval |= RCC_APB2ENR_ADC2EN;
+#endif
+
+#if CONFIG_STM32_TIM1
+  /* TIM1 Timer clock enable */
+
+  regval |= RCC_APB2ENR_TIM1EN;
+#endif
+
+#if CONFIG_STM32_SPI1
+  /* SPI 1 clock enable */
+
+  regval |= RCC_APB2ENR_SPI1EN;
+#endif
+
+#if CONFIG_STM32_TIM8
+  /* TIM8 Timer clock enable */
+
+  regval |= RCC_APB2ENR_TIM8EN;
+#endif
+
+#if CONFIG_STM32_USART1
+  /* USART1 clock enable */
+
+  regval |= RCC_APB2ENR_USART1EN;
+#endif
+
+#if CONFIG_STM32_ADC3
+  /*ADC3 interface clock enable */
+
+  regval |= RCC_APB2ENR_ADC3EN;
+#endif
+  putreg32(regval, STM32_RCC_APB2ENR);
+}
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on settings in board.h.
+ *   NOTE:  This logic needs to be extended so that we can selected low-power
+ *   clocking modes as well!
+ *
+ ****************************************************************************/
+
+void stm32_clockconfig(void)
+{
+  uint32 regval;
+  sint32 timeout;
+
+  /* Make sure that we are starting in the reset state */
+
+  rcc_reset();
+
+  /* Enable External High-Speed Clock (HSE) */
+ 
+  regval  = getreg32(STM32_RCC_CR);
+  regval &= ~RCC_CR_HSEBYP;			/* Disable HSE clock bypass */
+  regval |= RCC_CR_HSEON;			/* Enable HSE */
+  putreg32(regval, STM32_RCC_CR);
+   
+  /* Wait until the HSE is ready (or until a timeout elapsed) */
+
+  for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
+  {
+    /* Check if the HSERDY flag is the set in the CR */
+
+    if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+      {
+        /* If so, then break-out with timeout > 0 */
+
+        break;
+      }
+  }
+
+  if( timeout > 0)
+    {
+    /* Enable FLASH prefetch buffer and 2 wait states */
+
+    regval  = getreg32(STM32_FLASH_ACR);
+    regval &= ~ACR_LATENCY_MASK;
+    regval |= (ACR_LATENCY_2|ACR_PRTFBE);
+    putreg32(regval, STM32_FLASH_ACR);
+
+    /* Set the HCLK source/divider */
+ 
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_HPRE_MASK;
+    regval |= STM32_RCC_CFGR_HPRE;
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* Set the PCLK2 divider */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_PPRE2_MASK;
+    regval |= STM32_RCC_CFGR_PPRE2;
+    putreg32(regval, STM32_RCC_CFGR);
+  
+    /* Set the PCLK1 divider */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_PPRE1_MASK;
+    regval |= STM32_RCC_CFGR_PPRE1;
+    putreg32(regval, STM32_RCC_CFGR);
+ 
+    /* Set the PLL divider and multipler */
+
+    regval = getreg32(STM32_RCC_CFGR);
+    regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
+    regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
+    putreg32(regval, STM32_RCC_CFGR);
+ 
+    /* Enable the PLL */
+
+    regval = getreg32(STM32_RCC_CR);
+    regval |= RCC_CR_PLLON;
+    putreg32(regval, STM32_RCC_CR);
+ 
+    /* Wait until the PLL is ready */
+  
+    while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+ 
+    /* Select the system clock source (probably the PLL) */
+ 
+    regval  = getreg32(STM32_RCC_CFGR);
+    regval &= ~RCC_CFGR_SW_MASK;
+    regval |= STM32_SYSCLK_SW;
+    putreg32(regval, STM32_RCC_CFGR);
+
+    /* Wait until the selected source is used as the system clock source */
+  
+    while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
+  }
+
+  /* Enable periperal clocking */
+
+  rcc_enableapb2();
+  rcc_enableapb1();
+}
--- a/arch/arm/src/stm32/stm32_rcc.h
+++ b/arch/arm/src/stm32/stm32_rcc.h
@@ -0,0 +1,316 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_rcc.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_RRC_H
+#define __ARCH_ARM_SRC_STM32_STM32_RRC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_RCC_CR_OFFSET         0x0000  /* Clock control register */
+#define STM32_RCC_CFGR_OFFSET       0x0004  /* Clock configuration register */
+#define STM32_RCC_CIR_OFFSET        0x0008  /* Clock interrupt register */
+#define STM32_RCC_APB2RSTR_OFFSET   0x000c  /* APB2 Peripheral reset register */
+#define STM32_RCC_APB1RSTR_OFFSET   0x0010  /* APB1 Peripheral reset register */
+#define STM32_RCC_AHBENR_OFFSET     0x0014  /* AHB Peripheral Clock enable register */
+#define STM32_RCC_APB2ENR_OFFSET    0x0018  /* APB2 Peripheral Clock enable register */
+#define STM32_RCC_APB1ENR_OFFSET    0x001c  /* APB1 Peripheral Clock enable register */
+#define STM32_RCC_BDCR_OFFSET       0x0020  /* Backup domain control register */
+#define STM32_RCC_CSR_OFFSET        0x0024  /* Control/status register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_RCC_CR                (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
+#define STM32_RCC_CFGR              (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
+#define STM32_RCC_CIR               (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
+#define STM32_RCC_APB2RSTR          (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
+#define STM32_RCC_APB1RSTR          (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
+#define STM32_RCC_AHBENR            (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
+#define STM32_RCC_APB2ENR           (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
+#define STM32_RCC_APB1ENR           (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
+#define STM32_RCC_BDCR              (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
+#define STM32_RCC_CSR               (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Clock control register */
+
+#define RCC_CR_HSION                (1 << 0)  /* Bit 0: Internal High Speed clock enable */
+#define RCC_CR_HSIRDY               (1 << 1)  /* Bit 1: Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_SHIFT        (3)       /* Bits 7-3: Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
+#define RCC_CR_HSICAL_SHIFT         (8)       /* Bits 15-8: Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_MASK          (0xff << RCC_CR_HSICAL_SHIFT)
+#define RCC_CR_HSEON                (1 << 16) /* Bit 16: External High Speed clock enable */
+#define RCC_CR_HSERDY               (1 << 17) /* Bit 17: External High Speed clock ready flag */
+#define RCC_CR_HSEBYP               (1 << 18) /* Bit 18: External High Speed clock Bypass */
+#define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock Security System enable */
+#define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
+#define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
+
+/* Clock configuration register */
+
+#define RCC_CFGR_SW_SHIFT           (0)       /* Bits 1-0: System clock Switch */
+#define RCC_CFGR_SW_MASK            (3 << RCC_CFGR_SW_SHIFT)
+#  define RCC_CFGR_SW_HSI           (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
+#  define RCC_CFGR_SW_HSE           (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
+#  define RCC_CFGR_SW_PLL           (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
+#define RCC_CFGR_SWS_SHIFT          (2)       /* Bits 3-2: System Clock Switch Status */
+#define RCC_CFGR_SWS_MASK           (3 << RCC_CFGR_SWS_SHIFT)
+#  define RCC_CFGR_SWS_HSI          (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
+#  define RCC_CFGR_SWS_HSE          (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
+#  define RCC_CFGR_SWS_PLL          (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
+#define RCC_CFGR_HPRE_SHIFT         (4)       /* Bits 7-4: AHB prescaler */
+#define RCC_CFGR_HPRE_MASK          (0x0f << RCC_CFGR_HPRE_SHIFT)
+#  define RCC_CFGR_HPRE_SYSCLK      (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
+#  define RCC_CFGR_HPRE_SYSCLKd2    (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+#  define RCC_CFGR_HPRE_SYSCLKd4    (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+#  define RCC_CFGR_HPRE_SYSCLKd8    (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+#  define RCC_CFGR_HPRE_SYSCLKd16   (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+#  define RCC_CFGR_HPRE_SYSCLKd64   (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+#  define RCC_CFGR_HPRE_SYSCLKd128  (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+#  define RCC_CFGR_HPRE_SYSCLKd256  (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+#  define RCC_CFGR_HPRE_SYSCLKd512  (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+#define RCC_CFGR_PPRE1_SHIFT        (8)       /* Bits 10-8: APB Low speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_MASK         (7 << RCC_CFGR_PPRE1_SHIFT)
+#  define RCC_CFGR_PPRE1_HCLK       (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
+#  define RCC_CFGR_PPRE1_HCLKd2     (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
+#  define RCC_CFGR_PPRE1_HCLKd4     (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
+#  define RCC_CFGR_PPRE1_HCLKd8     (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
+#  define RCC_CFGR_PPRE1_HCLKd16    (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_SHIFT        (11)      /* Bits 13-11: APB High speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_MASK         (7 << RCC_CFGR_PPRE2_SHIFT)
+#  define RCC_CFGR_PPRE2_HCLK       (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
+#  define RCC_CFGR_PPRE2_HCLKd2     (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
+#  define RCC_CFGR_PPRE2_HCLKd4     (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
+#  define RCC_CFGR_PPRE2_HCLKd8     (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
+#  define RCC_CFGR_PPRE2_HCLKd16    (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
+#define RCC_CFGR_ADCPRE_SHIFT       (14)      /* Bits 15-14: ADC prescaler */
+#define RCC_CFGR_ADCPRE_MASK        (3 << RCC_CFGR_ADCPRE_SHIFT)
+#  define RCC_CFGR_PLCK2d2          (0 << RCC_CFGR_ADCPRE_SHIFT) /* 00: PLCK2 divided by 2 */
+#  define RCC_CFGR_PLCK2d4          (1 << RCC_CFGR_ADCPRE_SHIFT) /* 01: PLCK2 divided by 4 */
+#  define RCC_CFGR_PLCK2d6          (2 << RCC_CFGR_ADCPRE_SHIFT) /* 10: PLCK2 divided by 6 */
+#  define RCC_CFGR_PLCK2d8          (3 << RCC_CFGR_ADCPRE_SHIFT) /* 11: PLCK2 divided by 8 */
+#define RCC_CFGR_PLLSRC             (1 << 16) /* Bit 16: PLL entry clock source */
+#define RCC_CFGR_PLLXTPRE           (1 << 17) /* Bit 17: HSE divider for PLL entry */
+#define RCC_CFGR_PLLMUL_SHIFT       (18)      /* Bits 21-18: PLL Multiplication Factor */
+#define RCC_CFGR_PLLMUL_MASK        (0x0f << RCC_CFGR_PLLMUL_SHIFT)
+#  define RCC_CFGR_PLLMUL_CLKx2     (0 << RCC_CFGR_PLLMUL_SHIFT)  /* 0000: PLL input clock x 2 */
+#  define RCC_CFGR_PLLMUL_CLKx3     (1 << RCC_CFGR_PLLMUL_SHIFT)  /* 0001: PLL input clock x 3 */
+#  define RCC_CFGR_PLLMUL_CLKx4     (2 << RCC_CFGR_PLLMUL_SHIFT)  /* 0010: PLL input clock x 4 */
+#  define RCC_CFGR_PLLMUL_CLKx5     (3 << RCC_CFGR_PLLMUL_SHIFT)  /* 0011: PLL input clock x 5 */
+#  define RCC_CFGR_PLLMUL_CLKx6     (4 << RCC_CFGR_PLLMUL_SHIFT)  /* 0100: PLL input clock x 6 */
+#  define RCC_CFGR_PLLMUL_CLKx7     (5 << RCC_CFGR_PLLMUL_SHIFT)  /* 0101: PLL input clock x 7 */
+#  define RCC_CFGR_PLLMUL_CLKx8     (6 << RCC_CFGR_PLLMUL_SHIFT)  /* 0110: PLL input clock x 8 */
+#  define RCC_CFGR_PLLMUL_CLKx9     (7 << RCC_CFGR_PLLMUL_SHIFT)  /* 0111: PLL input clock x 9 */
+#  define RCC_CFGR_PLLMUL_CLKx10    (8 << RCC_CFGR_PLLMUL_SHIFT)  /* 1000: PLL input clock x 10 */
+#  define RCC_CFGR_PLLMUL_CLKx11    (9 << RCC_CFGR_PLLMUL_SHIFT)  /* 1001: PLL input clock x 11 */
+#  define RCC_CFGR_PLLMUL_CLKx12    (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
+#  define RCC_CFGR_PLLMUL_CLKx13    (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
+#  define RCC_CFGR_PLLMUL_CLKx14    (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
+#  define RCC_CFGR_PLLMUL_CLKx15    (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
+#  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
+#define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 26-24: Microcontroller Clock Output */
+#define RCC_CFGR_MCO_MASK           (7 << RCC_CFGR_MCO_SHIFT)
+#  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT) /* 0xx: No clock */
+#  define RCC_CFGR_SYSCLK           (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock selected */
+#  define RCC_CFGR_INTCLK           (5 << RCC_CFGR_MCO_SHIFT) /* 101: Internal 8 MHz RC oscillator clock selected */
+#  define RCC_CFGR_EXTCLK           (6 << RCC_CFGR_MCO_SHIFT) /* 110: External 1-25 MHz oscillator clock selected */
+#  define RCC_CFGR_PLLCLKd2         (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */
+#define RCC_CFGR_USBPRE             (1 << 22) /* Bit 22: USB prescaler */
+
+/* Clock interrupt register */
+
+#define RCC_CIR_LSIRDYF             (1 << 0)  /* Bit 0: LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF             (1 << 1)  /* Bit 1: LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF             (1 << 2)  /* Bit 2: HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF             (1 << 3)  /* Bit 3: HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF             (1 << 4)  /* Bit 4: PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF                (1 << 7)  /* Bit 7: Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE            (1 << 8)  /* Bit 8: LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE            (1 << 9)  /* Bit 9: LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE            (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE            (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE            (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC             (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC             (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC             (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC             (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC             (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC                (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */
+
+/* APB2 Peripheral reset register */
+
+#define RCC_APB2RSTR_AFIORST        (1 << 0) /* Bit 0: Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST        (1 << 2)  /* Bit 2: I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST        (1 << 3)  /* Bit 3: IO port B reset */
+#define RCC_APB2RSTR_IOPCRST        (1 << 4)  /* Bit 4: IO port C reset */
+#define RCC_APB2RSTR_IOPDRST        (1 << 5)  /* Bit 5: IO port D reset */
+#define RCC_APB2RSTR_IOPERST        (1 << 6)  /* Bit 6: IO port E reset */
+#define TCC_APB2RSTR_IOPFRST        (1 << 7)  /* Bit 7: IO port F reset */
+#define TCC_APB2RSTR_IOPGRST        (1 << 8)  /* Bit 8: IO port G reset */
+#define RCC_APB2RSTR_ADC1RST        (1 << 9)  /* Bit 9: ADC 1 interface reset */
+#define RCC_APB2RSTR_ADC2RST        (1 << 10) /* Bit 10: ADC 2 interface reset */
+#define RCC_APB2RSTR_TIM1RST        (1 << 11) /* Bit 11: TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST        (1 << 12) /* Bit 12: SPI 1 reset */
+#define RCC_APB2RSTR_TIM8RST        (1 << 13) /* Bit 13: TIM8 Timer reset */
+#define RCC_APB2RSTR_USART1RST      (1 << 14) /* Bit 14: USART1 reset */
+#define RCC_APB2RTST_ADC2RST        (1 << 15) /* Bit 15: ADC3 interface reset */
+
+/* APB1 Peripheral reset register */
+
+#define RCC_APB1RSTR_TIM2RST        (1 << 0)  /* Bit 0: Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST        (1 << 1)  /* Bit 1: Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST        (1 << 2)  /* Bit 2: Timer 4 reset */
+#define RCC_APB1RSTR_TIM5RST        (1 << 3)  /* Bit 3: Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST        (1 << 4)  /* Bit 4: Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST        (1 << 5)  /* Bit 5: Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST        (1 << 11) /* Bit 11: Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST        (1 << 14) /* Bit 14: SPI 2 reset */
+#define RCC_APB1RSTR_SPI3RST        (1 << 15) /* Bit 15: SPI 3 reset */
+#define RCC_APB1RSTR_USART2RST      (1 << 17) /* Bit 17: USART 2 reset */
+#define RCC_APB1RSTR_USART3RST      (1 << 18) /* Bit 18: USART 3 reset */
+#define RCC_APB1RSTR_UART4RST       (1 << 19) /* Bit 19: UART 4 reset */
+#define RCC_APB1RSTR_UART5RST       (1 << 20) /* Bit 18: UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST        (1 << 22) /* Bit 22: I2C 2 reset */
+#define RCC_APB1RSTR_USBRST         (1 << 23) /* Bit 23: USB reset */
+#define RCC_APB1RSTR_CANRST         (1 << 25) /* Bit 25: CAN reset */
+#define RCC_APB1RSTR_BKPRST         (1 << 27) /* Bit 27: Backup interface reset */
+#define RCC_APB1RSTR_PWRRST         (1 << 28) /* Bit 28: Power interface reset */
+#define RCC_APB1RSTR_DACRST         (1 << 29) /* Bit 29: DAC interface reset */
+
+/* AHB Peripheral Clock enable register */
+
+#define RCC_AHBENR_DMA1EN           (1 << 0)  /* Bit 0: DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN           (1 << 0)  /* Bit 0: DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN           (1 << 2)  /* Bit 2: SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN          (1 << 4)  /* Bit 4: FLITF clock enable */
+#define RCC_AHBENR_CRCEN            (1 << 6)  /* Bit 6: CRC clock enable */
+#define RCC_AHBENR_FSMCEN           (1 << 8)  /* Bit 8: FSMC clock enable */
+#define RCC_AHBENR_SDIOEN           (1 << 10) /* Bit 10: SDIO clock enable */
+
+/* APB2 Peripheral Clock enable register */
+
+#define RCC_APB2ENR_AFIOEN          (1 << 0)  /* Bit 0: Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPEN(n)        (1 << ((n)+2))
+#define RCC_APB2ENR_IOPAEN          (1 << 2)  /* Bit 2: I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN          (1 << 3)  /* Bit 3: I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN          (1 << 4)  /* Bit 4: I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN          (1 << 5)  /* Bit 5: I/O port D clock enable */
+#define RCC_APB2ENR_IOPEEN          (1 << 6)  /* Bit 6: I/O port E clock enable */
+#define RCC_APB2ENR_IOPFEN          (1 << 7)  /* Bit 7: I/O port F clock enable */
+#define RCC_APB2ENR_IOPGEN          (1 << 8)  /* Bit 8: I/O port G clock enable */
+#define RCC_APB2ENR_ADC1EN          (1 << 9)  /* Bit 9: ADC 1 interface clock enable */
+#define RCC_APB2ENR_ADC2EN          (1 << 10) /* Bit 10: ADC 2 interface clock enable */
+#define RCC_APB2ENR_TIM1EN          (1 << 11) /* Bit 11: TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN          (1 << 12) /* Bit 12: SPI 1 clock enable */
+#define RCC_APB2ENR_TIM8EN          (1 << 13) /* Bit 13: TIM8 Timer clock enable */
+#define RCC_APB2ENR_USART1EN        (1 << 14) /* Bit 14: USART1 clock enable */
+#define RCC_APB2ENR_ADC3EN          (1 << 15) /* Bit 14: ADC3 interface clock enable */
+
+/* APB1 Peripheral Clock enable register */
+
+#define RCC_APB1ENR_TIM2EN          (1 << 0)  /* Bit 0: Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN          (1 << 1)  /* Bit 1: Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN          (1 << 2)  /* Bit 2: Timer 4 clock enable */
+#define RCC_APB1ENR_TIM5EN          (1 << 3)  /* Bit 3: Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN          (1 << 4)  /* Bit 4: Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN          (1 << 5)  /* Bit 5: Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN          (1 << 11) /* Bit 11: Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN          (1 << 14) /* Bit 14: SPI 2 clock enable */
+#define RCC_APB1ENR_SPI3EN          (1 << 15) /* Bit 15: SPI 3 clock enable */
+#define RCC_APB1ENR_USART2EN        (1 << 17) /* Bit 17: USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN        (1 << 18) /* Bit 18: USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN         (1 << 19) /* Bit 19: UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN         (1 << 20) /* Bit 20: UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN          (1 << 21) /* Bit 21: I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN          (1 << 22) /* Bit 22: I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN           (1 << 23) /* Bit 23: USB clock enable */
+#define RCC_APB1ENR_CANEN           (1 << 25) /* Bit 25: CAN clock enable */
+#define RCC_APB1ENR_BKPEN           (1 << 27) /* Bit 27: Backup interface clock enable */
+#define RCC_APB1ENR_PWREN           (1 << 28) /* Bit 28: Power interface clock enable */
+#define RCC_APB1ENR_DACEN           (1 << 29) /* Bit 29: DAC interface clock enable */
+
+/* Backup domain control register */
+
+#define RCC_BDCR_BDRST              (1 << 16) /* Bit 16: Backup domain software reset */
+#define RCC_BDCR_RTCEN              (1 << 15) /* Bit 15: RTC clock enable */
+#define RCC_BDCR_RTCSEL_SHIFT       (8)       /* Bits 9:8: RTC clock source selection */
+#define RCC_BDCR_RTCSEL_MASK        (3 << RCC_BDCR_RTCSEL_SHIFT)
+#  define RCC_BDCR_RTCSEL_NOCLK     (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
+#  define RCC_BDCR_RTCSEL_LSE       (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
+#  define RCC_BDCR_RTCSEL_LSI       (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
+#  define RCC_BDCR_RTCSEL_HSE       (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_LSEBYP             (1 << 2)  /* Bit 2: External Low Speed oscillator Bypass */
+#define RCC_BDCR_LSERDY             (1 << 1)  /* Bit 1: External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEON              (1 << 0)  /* Bit 0: External Low Speed oscillator enable */
+
+/* Control/status register */
+
+#define RCC_CSR_LSION               (1 << 0)  /* Bit 0: Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY              (1 << 1)  /* Bit 1: Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF                (1 << 24) /* Bit 24: Remove reset flag */
+#define RCC_CSR_PINRSTF             (1 << 26) /* Bit 26: PIN reset flag */
+#define RCC_CSR_PORRSTF             (1 << 27) /* Bit 27: POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF             (1 << 28) /* Bit 28: Software Reset flag */
+#define RCC_CSR_IWDGRSTF            (1 << 29) /* Bit 29: Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF            (1 << 30) /* Bit 30: Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */
--- a/arch/arm/src/stm32/stm32_rtc.h
+++ b/arch/arm/src/stm32/stm32_rtc.h
@@ -0,0 +1,116 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_rtc.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
+#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_RTC_CRH_OFFSET    0x0000    /* RTC control register High (16-bit) */
+#define STM32_RTC_CRL_OFFSET    0x0004    /* RTC control register low (16-bit) */
+#define STM32_RTC_PRLH_OFFSET   0x0008    /* RTC prescaler load register high (16-bit) */ 
+#define STM32_RTC_PRLL_OFFSET   0x000c    /* RTC prescaler load register low (16-bit) */
+#define STM32_RTC_DIVH_OFFSET   0x0010    /* RTC prescaler divider register high (16-bit) */
+#define STM32_RTC_DIVL_OFFSET   0x0014    /* RTC prescaler divider register low (16-bit) */
+#define STM32_RTC_CNTH_OFFSET   0x0018    /* RTC counter register high (16-bit) */
+#define STM32_RTC_CNTL_OFFSET   0x001c    /* RTC counter register low (16-bit) */
+#define STM32_RTC_ALRH_OFFSET   0x0020    /* RTC alarm register high (16-bit) */
+#define STM32_RTC_ALRL_OFFSET   0x0024    /* RTC alarm register low (16-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_RTC_CRH           (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET)
+#define STM32_RTC_CRL           (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET)
+#define STM32_RTC_PRLH          (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET)
+#define STM32_RTC_PRLL          (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET)
+#define STM32_RTC_DIVH          (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET)
+#define STM32_RTC_DIVL          (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET)
+#define STM32_RTC_CNTH          (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET)
+#define STM32_RTC_CNTL          (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET)
+#define STM32_RTC_ALRH          (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET)
+#define STM32_RTC_ALRL          (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* RTC control register High (16-bit) */
+
+#define RTC_CRH_SECIE           (1 << 0)  /* Bit 0 : Second Interrupt Enable*/
+#define RTC_CRH_ALRIE           (1 << 1)  /* Bit 1: Alarm Interrupt Enable*/
+#define RTC_CRH_OWIE            (1 << 2)  /* Bit 2: OverfloW Interrupt Enable*/
+
+/* RTC control register low (16-bit) */
+
+#define RTC_CRL_SECF            (1 << 0)  /* Bit 0: Second Flag*/
+#define RTC_CRL_ALRF            (1 << 1)  /* Bit 1: Alarm Flag*/
+#define RTC_CRL_OWF             (1 << 2)  /* Bit 2: Overflow Flag*/
+#define RTC_CRL_RSF             (1 << 3)  /* Bit 3: Registers Synchronized Flag*/
+#define RTC_CRL_CNF             (1 << 4)  /* Bit 4: Configuration Flag*/
+#define RTC_CRL_RTOFF           (1 << 5)  /* Bit 5: RTC operation OFF*/
+
+/* RTC prescaler load register high (16-bit) */
+
+#define RTC_PRLH_PRL_SHIFT      (0)      /* Bits 3-0: RTC Prescaler Reload Value High */
+#define RTC_PRLH_PRL_MASK       (0x0f << RTC_PRLH_PRL_SHIFT)
+
+/* RTC prescaler divider register high (16-bit) */
+
+#define RTC_DIVH_RTC_DIV_SHIFT  (0)      /* Bits 3-0: RTC Clock Divider High */
+#define RTC_DIVH_RTC_DIV_MASK   (0x0f << RTC_DIVH_RTC_DIV_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */
--- a/arch/arm/src/stm32/stm32_serial.c
+++ b/arch/arm/src/stm32/stm32_serial.c
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
--- a/arch/arm/src/stm32/stm32_spi.h
+++ b/arch/arm/src/stm32/stm32_spi.h
@@ -0,0 +1,158 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_spi.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H
+#define __ARCH_ARM_STC_STM32_STM32_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SPI_CR1_OFFSET      0x0000  /* SPI Control Register 1 (16-bit) */
+#define STM32_SPI_CR2_OFFSET      0x0004  /* SPI control register 2 (16-bit) */
+#define STM32_SPI_SR_OFFSET       0x0008  /* SPI status register (16-bit) */
+#define STM32_SPI_DR_OFFSET       0x000c  /* SPI data register (16-bit) */
+#define STM32_SPI_CRCPR_OFFSET    0x0010  /* SPI CRC polynomial register (16-bit) */
+#define STM32_SPI_RXCRCR_OFFSET   0x0014  /* SPI Rx CRC register (16-bit) */
+#define STM32_SPI_TXCRCR_OFFSET   0x0018  /* SPI Tx CRC register (16-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NSPI > 0
+#  define STM32_SPI1_CR1          (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI1_CR2          (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI1_SR           (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI1_DR           (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI1_CRCPR        (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32_NSPI > 1
+#  define STM32_SPI2_CR1          (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI2_CR2          (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI2_SR           (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI2_DR           (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI2_CRCPR        (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA              (1 << 0)  /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL              (1 << 1)  /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR              (1 << 2)  /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT          (3)       /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK           (7 << SPI_CR1_BR_SHIFT)
+#  define SPI_CR1_FPCLCKd2        (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+#  define SPI_CR1_FPCLCKd4        (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+#  define SPI_CR1_FPCLCKd8        (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+#  define SPI_CR1_FPCLCKd16       (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+#  define SPI_CR1_FPCLCKd32       (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+#  define SPI_CR1_FPCLCKd64       (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+#  define SPI_CR1_FPCLCKd128      (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+#  define SPI_CR1_FPCLCKd256      (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+#define SPI_CR1_SPE               (1 << 6)  /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST          (1 << 7)  /* Bit 7: Frame Format */
+#define SPI_CR1_SSI               (1 << 8)  /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM               (1 << 9)  /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY            (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_DFF               (1 << 11) /* Bit 11: Data Frame Format */
+#define SPI_CR1_CRCNEXT           (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN             (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE            (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE          (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN           (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN           (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE              (1 << 2)  /* Bit 2: SS Output Enable */
+#define SPI_CR2_ERRIE             (1 << 5)  /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE            (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE             (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE               (1 << 0)  /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE                (1 << 1)  /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CRCERR             (1 << 4)  /* Bit 4: CRC error flag */
+#define SPI_SR_MODF               (1 << 5)  /* Bit 5: Mode fault */
+#define SPI_SR_OVR                (1 << 6)  /* Bit 6: Overrun flag */
+#define SPI_SR_BSY                (1 << 7)  /* Bit 7: Busy flag */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -0,0 +1,149 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_start.c
+ * arch/arm/src/chip/stm32_start.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "stm32_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+#  define showprogress(c) up_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  const uint32 *src;
+  uint32 *dest;
+
+  /* Configure the uart so that we can get debug output as soon as possible */
+
+  stm32_clockconfig();
+  stm32_lowsetup();
+  showprogress('A');
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+  showprogress('B');
+
+  /* Move the intialized data section from his temporary holding spot in
+   * FLASH into the correct place in SRAM.  The correct place in SRAM is
+   * give by _sdata and _edata.  The temporary location is in FLASH at the
+   * end of all of the other read-only data (.text, .rodata) at _eronly.
+   */
+
+  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+    {
+      *dest++ = *src++;
+    }
+  showprogress('C');
+
+  /* Perform early serial initialization */
+
+#ifdef CONFIG_USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+  showprogress('D');
+
+  /* Initialize onboard resources */
+
+  stm32_boardinitialize();
+  showprogress('E');
+
+  /* Then start NuttX */
+
+  showprogress('\r');
+  showprogress('\n');
+  os_start();
+
+  /* Shoulnd't get here */
+
+  for(;;);
+}
--- a/arch/arm/src/stm32/stm32_tim.h
+++ b/arch/arm/src/stm32/stm32_tim.h
--- a/arch/arm/src/stm32/stm32_timerisr.c
+++ b/arch/arm/src/stm32/stm32_timerisr.c
@@ -0,0 +1,163 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_timerisr.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
+ * divided by 8.  The SysTick can work either with this clock or with the
+ * Cortex clock (HCLK), configurable in the SysTick Control and Status
+ * register.
+ */
+
+#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
+                                   /* And I don't know now to re-configure it yet */
+
+#if CONFIG_STM32_SYSTICK_HCLKd8
+#  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
+#else
+#  define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
+#endif
+
+/* The size of the reload field is 24 bits.  Verify taht the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32 *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint32 regval;
+
+  /* Set the SysTick interrupt to the default priority */
+
+  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+  /* Make sure that the SYSTICK clock source is set correctly */
+
+#if 0 /* Does not work.  Comes up with HCLK source and I can't change it */
+  regval = getreg32(NVIC_SYSTICK_CTRL);
+#if CONFIG_STM32_SYSTICK_HCLKd8
+  regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
+#else
+  regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
+#endif
+  putreg32(regval, NVIC_SYSTICK_CTRL);
+#endif
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+  /* Enable SysTick interrupts */
+
+  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(STM32_IRQ_SYSTICK);
+}
--- a/arch/arm/src/stm32/stm32_uart.h
+++ b/arch/arm/src/stm32/stm32_uart.h
@@ -0,0 +1,211 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_uart.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H
+#define __ARCH_ARM_STC_STM32_STM32_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_USART_SR_OFFSET     0x0000  /* Status register (32-bits) */
+#define STM32_USART_DR_OFFSET     0x0004  /* Data register (32-bits) */
+#define STM32_USART_BRR_OFFSET    0x0008  /* Baud Rate Register (32-bits) */
+#define STM32_USART_CR1_OFFSET    0x000c  /* Control register 1 (32-bits) */
+#define STM32_USART_CR2_OFFSET    0x0010  /* Control register 2 (32-bits) */
+#define STM32_USART_CR3_OFFSET    0x0014  /* Control register 3 (32-bits) */
+#define STM32_USART_GTPR_OFFSET   0x0018  /* Guard time and prescaler register (32-bits) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NUSART > 0
+#  define STM32_USART1_SR         (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART1_DR         (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART1_BRR        (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART1_CR1        (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART1_CR2        (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART1_CR3        (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
+#  define STM32_USART1_GTPR       (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 1
+#  define STM32_USART2_SR         (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART2_DR         (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART2_BRR        (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART2_CR1        (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART2_CR2        (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART2_CR3        (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
+#  define STM32_USART2_GTPR       (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 0
+#  define STM32_USART3_SR         (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART3_DR         (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART3_BRR        (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART3_CR1        (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART3_CR2        (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART3_CR3        (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
+#  define STM32_USART3_GTPR       (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 3
+#  define STM32_UART4_SR          (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_UART4_DR          (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_UART4_BRR         (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_UART4_CR1         (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_UART4_CR2         (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_UART4_CR3         (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
+#endif
+
+#if STM32_NUSART > 4
+#  define STM32_UART5_SR          (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_UART5_DR          (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_UART5_BRR         (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_UART5_CR1         (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_UART5_CR2         (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_UART5_CR3         (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Status register */
+
+#define USART_SR_PE               (1 << 0)  /* Bit 0: Parity Error */
+#define USART_SR_FE               (1 << 1)  /* Bit 1: Framing Error */
+#define USART_SR_NE               (1 << 2)  /* Bit 2: Noise Error Flag */
+#define USART_SR_ORE              (1 << 3)  /* Bit 3: OverRun Error */
+#define USART_SR_IDLE             (1 << 4)  /* Bit 4: IDLE line detected */
+#define USART_SR_RXNE             (1 << 5)  /* Bit 5: Read Data Register Not Empty */
+#define USART_SR_TC               (1 << 6)  /* Bit 6: Transmission Complete */
+#define USART_SR_TXE              (1 << 7)  /* Bit 7: Transmit Data Register Empty */
+#define USART_SR_LBD              (1 << 8)  /* Bit 8: LIN Break Detection Flag */
+#define USART_SR_CTS              (1 << 9)  /* Bit 9: CTS Flag */
+
+#define USART_SR_ALLBITS          (0x03ff)
+#define USART_SR_CLRBITS          (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
+
+/* Data register */
+
+#define USART_DR_SHIFT            (0)       /* Bits 8:0: Data value */
+#define USART_DR_MASK             (0xff << USART_DR_SHIFT)
+
+/* Baud Rate Register */
+
+#define USART_BRR_FRAC_SHIFT      (0)       /* Bits 3-0: fraction of USARTDIV */
+#define USART_BRR_FRAC_MASK       (0x0f << USART_BRR_FRAC_SHIFT)
+#define USART_BRR_MANT_SHIFT      (4)       /* Bits 15-4: mantissa of USARTDIV */
+#define USART_BRR_MANT_MASK       (0x0fff << USART_BRR_MANT_SHIFT)
+
+/* Control register 1 */
+
+#define USART_CR1_SBK             (1 << 0)  /* Bit 0: Send Break */
+#define USART_CR1_RWU             (1 << 1)  /* Bit 1: Receiver wakeup */
+#define USART_CR1_RE              (1 << 2)  /* Bit 2: Receiver Enable */
+#define USART_CR1_TE              (1 << 3)  /* Bit 3: Transmitter Enable */
+#define USART_CR1_IDLEIE          (1 << 4)  /* Bit 4: IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE          (1 << 5)  /* Bit 5: RXNE Interrupt Enable */
+#define USART_CR1_TCIE            (1 << 6)  /* Bit 6: Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE           (1 << 7)  /* Bit 7: TXE Interrupt Enable */
+#define USART_CR1_PEIE            (1 << 8)  /* Bit 8: PE Interrupt Enable */
+#define USART_CR1_PS              (1 << 9)  /* Bit 9: Parity Selection */
+#define USART_CR1_PCE             (1 << 10) /* Bit 10: Parity Control Enable */
+#define USART_CR1_WAKE            (1 << 11) /* Bit 11: Wakeup method */
+#define USART_CR1_M               (1 << 12) /* Bit 12: word length */
+#define USART_CR1_UE              (1 << 13) /* Bit 13: USART Enable */
+
+#define USART_CR1_ALLINTS         (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
+
+/* Control register 2 */
+
+#define USART_CR2_ADD_SHIFT       (0)       /* Bits 3-0: Address of the USART node */
+#define USART_CR2_ADD_MASK        (0x0f << USART_CR2_ADD_SHIFT)
+#define USART_CR2_LBDL            (1 << 6)  /* Bit 5: LIN Break Detection Length */
+#define USART_CR2_LBDIE           (1 << 7)  /* Bit 6: LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL            (1 << 8)  /* Bit 8: Last Bit Clock pulse */
+#define USART_CR2_CPHA            (1 << 9)  /* Bit 9: Clock Phase */
+#define USART_CR2_CPOL            (1 << 10) /* Bit 10: Clock Polarity */
+#define USART_CR2_CLKEN           (1 << 11) /* Bit 11: Clock Enable */
+#define USART_CR2_STOP_SHIFT      (12)      /* Bits 13-12: STOP bits */
+#define USART_CR2_STOP_MASK       (3 << USART_CR2_STOP_SHIFT)
+#  define USART_CR2_STOP1         (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
+#  define USART_CR2_STOP0p5       (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
+#  define USART_CR2_STOP2         (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
+#  define USART_CR2_STOP1p5       (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
+#define USART_CR2_LINEN           (1 << 14) /* Bit 14: LIN mode enable */
+
+/* Control register 3 */
+
+#define USART_CR3_EIE             (1 << 0)  /* Bit 0: Error Interrupt Enable */
+#define USART_CR3_IREN            (1 << 1)  /* Bit 1: IrDA mode Enable */
+#define USART_CR3_IRLP            (1 << 2)  /* Bit 2: IrDA Low-Power */
+#define USART_CR3_HDSEL           (1 << 3)  /* Bit 3: Half-Duplex Selection */
+#define USART_CR3_NACK            (1 << 4)  /* Bit 4: Smartcard NACK enable */
+#define USART_CR3_SCEN            (1 << 5)  /* Bit 5: Smartcard mode enable */
+#define USART_CR3_DMAR            (1 << 6)  /* Bit 6: DMA Enable Receiver */
+#define USART_CR3_DMAT            (1 << 7)  /* Bit 7: DMA Enable Transmitter */
+#define USART_CR3_RTSE            (1 << 8)  /* Bit 8: RTS Enable */
+#define USART_CR3_CTSE            (1 << 9)  /* Bit 9: CTS Enable */
+#define USART_CR3_CTSIE           (1 << 10) /* Bit 10: CTS Interrupt Enable */
+
+/* Guard time and prescaler register */
+
+#define USART_GTPR_GT_SHIFT       (8) /* Bits 15-8: Guard time value */
+#define USART_GTPR_GT_MASK        (0xff <<  USART_GTPR_GT_SHIFT)
+#define USART_GTPR_PSC_SHIFT      (0) /* Bits 7:0 [7:0]: Prescaler value */
+#define USART_GTPR_PSC_MASK       (0xff << USART_GTPR_PSC_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */
--- a/arch/arm/src/stm32/stm32_usbdev.h
+++ b/arch/arm/src/stm32/stm32_usbdev.h
@@ -0,0 +1,209 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_usbdev.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_USBDEV_H
+#define __ARCH_ARM_SRC_STM32_STM32_USBDEV_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+/* Endpoint Registers */
+
+#define STM32_USB_EPR_OFFSET(n)      (4*(n)) /* USB endpoint n register (16-bits) */
+#define STM32_USB_EP0R_OFFSET        0x0000  /* USB endpoint 0 register (16-bits) */
+#define STM32_USB_EP1R_OFFSET        0x0004  /* USB endpoint 1 register (16-bits) */
+#define STM32_USB_EP2R_OFFSET        0x0008  /* USB endpoint 2 register (16-bits) */
+#define STM32_USB_EP3R_OFFSET        0x000c  /* USB endpoint 3 register (16-bits) */
+#define STM32_USB_EP4R_OFFSET        0x0010  /* USB endpoint 4 register (16-bits) */
+#define STM32_USB_EP5R_OFFSET        0x0014  /* USB endpoint 5 register (16-bits) */
+#define STM32_USB_EP6R_OFFSET        0x0018  /* USB endpoint 6 register (16-bits) */
+#define STM32_USB_EP7R_OFFSET        0x001c  /* USB endpoint 7 register (16-bits) */
+
+/* Common Registers */
+
+#define STM32_USB_CNTR_OFFSET        0x0040  /* USB control register (16-bits) */
+#define STM32_USB_ISTR_OFFSET        0x0044  /* USB interrupt status register (16-bits) */
+#define STM32_USB_FNR_OFFSET         0x0048  /* USB frame number register (16-bits) */
+#define STM32_USB_DADDR_OFFSET       0x004c  /* USB device address (16-bits) */
+#define STM32_USB_BTABLE_OFFSET      0x0050  /* Buffer table address (16-bits) */
+
+/* Buffer Descriptor Table (Relatative to BTABLE address) */
+
+#define STM32_USB_ADDR_TX_OFFSET     ((n)<<4)      /* Transmission buffer address n (16-bits) */
+#define STM32_USB_COUNT_TX_OFFSET    (((n)<<4)+4)  /* Transmission byte count n (16-bits) */
+#define STM32_USB_ADDR_RX_OFFSET     (((n)<<4)+8)  /* Reception buffer address n (16-bits) */
+#define STM32_USB_COUNT_RX_OFFSET    (((n)<<4)+12) /* Reception byte count n (16-bits) */
+
+/* Register Addresses ***************************************************************/
+
+/* Endpoint Registers */
+
+#define STM32_USB_EPR(n)             (STM32_USB_BASE+STM32_USB_EPR_OFFSET)
+#define STM32_USB_EP0R               (STM32_USB_BASE+STM32_USB_EP0R_OFFSET)
+#define STM32_USB_EP1R               (STM32_USB_BASE+STM32_USB_EP1R_OFFSET)
+#define STM32_USB_EP2R               (STM32_USB_BASE+STM32_USB_EP2R_OFFSET)
+#define STM32_USB_EP3R               (STM32_USB_BASE+STM32_USB_EP3R_OFFSET)
+#define STM32_USB_EP4R               (STM32_USB_BASE+STM32_USB_EP4R_OFFSET)
+#define STM32_USB_EP5R               (STM32_USB_BASE+STM32_USB_EP5R_OFFSET)
+#define STM32_USB_EP6R               (STM32_USB_BASE+STM32_USB_EP6R_OFFSET)
+#define STM32_USB_EP7R               (STM32_USB_BASE+STM32_USB_EP7R_OFFSET)
+
+/* Common Registers */
+
+#define STM32_USB_CNTR               (STM32_USB_BASE+STM32_USB_CNTR_OFFSET)
+#define STM32_USB_ISTR               (STM32_USB_BASE+STM32_USB_ISTR_OFFSET)
+#define STM32_USB_FNR                (STM32_USB_BASE+STM32_USB_FNR_OFFSET)
+#define STM32_USB_DADDR              (STM32_USB_BASE+STM32_USB_DADDR_OFFSET)
+#define STM32_USB_BTABLE             (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* USB endpoint register */
+
+#define USB_EPR_EA_SHIFT             (0)       /* Bits 3:0 [3:0]: Endpoint Address */
+#define USB_EPR_EA_MASK              (0X0f << USB_EPR_EA_SHIFT)
+#define USB_EPR_STAT_TX_SHIFT        (4)       /* Bits 5-4: Status bits, for transmission transfers */
+#define USB_EPR_STAT_TX_MASK         (3 << USB_EPR_STAT_TX_SHIFT)
+#define USB_EPR_DTOG_TX              (1 << 6)  /* Bit 6: Data Toggle, for transmission transfers */
+#define USB_EPR_CTR_TX               (1 << 7)  /* Bit 7: Correct Transfer for transmission */
+#define USB_EPR_EP_KIND              (1 << 8)  /* Bit 8: Endpoint Kind */
+#define USB_EPR_EP_TYPE_SHIFT        (9)       /* Bits 10-9: Endpoint type */
+#define USB_EPR_EP_TYPE_MASK         (3 << USB_EPR_EP_TYPE_SHIFT)
+#define USB_EPR_SETUP                (1 << 11) /* Bit 11: Setup transaction completed */
+#define USB_EPR_STAT_RX_SHIFT        (12)      /* Bits 13-12: Status bits, for reception transfers */
+#define USB_EPR_STAT_RX_MASK         (3 << USB_EPR_STAT_RX_SHIFT)
+#define USB_EPR_DTOG_RX              (1 << 14) /* Bit 14: Data Toggle, for reception transfers */
+#define USB_EPR_CTR_RX               (1 << 15) /* Bit 15: Correct Transfer for reception */
+
+/* USB control register */
+
+#define USB_CNTR_FRES                (1 << 0)  /* Bit 0: Force USB Reset */
+#define USB_CNTR_PDWN                (1 << 1)  /* Bit 1: Power down */
+#define USB_CNTR_LP_MODE             (1 << 2)  /* Bit 2: Low-power mode */
+#define USB_CNTR_FSUSP               (1 << 3)  /* Bit 3: Force suspend */
+#define USB_CNTR_RESUME              (1 << 4)  /* Bit 4: Resume request */
+#define USB_CNTR_ESOFM               (1 << 8)  /* Bit 8: Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM                (1 << 9)  /* Bit 9: Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM              (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
+#define USB_CNTR_SUSPM               (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM               (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM                (1 << 13) /* Bit 13: Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM             (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM                (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
+
+/* USB interrupt status register */
+
+#define USB_ISTR_EP_ID_SHIFT         (0)       /* Bits 3-0: Endpoint Identifier */
+#define USB_ISTR_EP_ID_MASK          (0x0f << USB_ISTR_EP_ID_SHIFT)
+#define USB_ISTR_DIR                 (1 << 4)  /* Bit 4: Direction of transaction */
+#define USB_ISTR_ESOF                (1 << 8)  /* Bit 8: Expected Start Of Frame */
+#define USB_ISTR_SOF                 (1 << 9)  /* Bit 9: Start Of Frame */
+#define USB_ISTR_RESET               (1 << 10) /* Bit 10: USB RESET request */
+#define USB_ISTR_SUSP                (1 << 11) /* Bit 11: Suspend mode request */
+#define USB_ISTR_WKUP                (1 << 12) /* Bit 12: Wake up */
+#define USB_ISTR_ERR                 (1 << 13) /* Bit 13: Error */
+#define USB_ISTR_PMAOVR              (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR                 (1 << 15) /* Bit 15: Correct Transfer */
+
+/* USB frame number register */
+
+#define USB_FNR_FN_SHIFT             (0)       /* Bits 10-0: Frame Number */
+#define USB_FNR_FN_MASK              (0x07ff << USB_FNR_FN_SHIFT)
+#define USB_FNR_LSOF_SHIFT           (11)      /* Bits 12-11: Lost SOF */
+#define USB_FNR_LSOF_MASK            (3 << USB_FNR_LSOF_SHIFT)
+#define USB_FNR_LCK                  (1 << 13) /* Bit 13: Locked */
+#define USB_FNR_RXDM                 (1 << 14) /* Bit 14: Receive Data - Line Status */
+#define USB_FNR_RXDP                 (1 << 15) /* Bit 15: Receive Data + Line Status */
+
+/* USB device address */
+
+#define USB_DADDR_ADD_SHIFT          (0)       /* Bits 6-0: Device Address */
+#define USB_DADDR_ADD_MASK           (0x7f << USB_DADDR_ADD_SHIFT)
+#define USB_DADDR_EF                 (1 << 7)  /* Bit 7: Enable Function */
+
+/* Buffer table address */
+
+#define USB_BTABLE_SHIFT             (3)       /* Bits 15:3: Buffer Table */
+#define USB_BTABLE_MASK              (0x1fff << USB_BTABLE_SHIFT)
+
+/* Transmission buffer address */
+
+#define USB_ADDR_TX_ZERO             (1 << 0)  /* Bit 0 Must always be written as ‘0’ */
+#define USB_ADDR_TX_SHIFT            (1)       /* Bits 15-1: Transmission Buffer Address */
+#define USB_ADDR_TX_MASK             (0x7fff << USB_ADDR_ADDR_TX_SHIFT)
+
+/* Transmission byte count */
+
+#define USB_COUNT_TX_SHIFT           (0)       /* Bits 9-0: Transmission Byte Count */
+#define USB_COUNT_TX_MASK            (0x03ff << USB_COUNT_COUNT_TX_SHIFT)
+
+/* Reception buffer address */
+
+#define USB_ADDR_RX_ZERO             (1 << 0)  /* Bit 0 This bit must always be written as ‘0’ */
+#define USB_ADDR_RX_SHIFT            (1)       /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */
+#define USB_ADDR_RX_MASK             (0x7fff << USB_ADDR_RX_SHIFT)
+
+/* Reception byte count */
+
+#define USB_COUNT_RX_BL_SIZE         (1 << 15) /* Bit 15: BLock SIZE. */
+#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10)      /* Bits 14-10: Number of blocks */
+#define USB_COUNT_RX_NUM_BLOCK_MASK  (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
+#define USB_COUNT_RX_SHIFT           (0)       /* Bits 9-0: Reception Byte Count */
+#define USB_COUNT_RX_MASK            (0x03ff << USB_COUNT_RX_COUNT_RX_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_USBDEV_H */
--- a/arch/arm/src/stm32/stm32_vectors.S
+++ b/arch/arm/src/stm32/stm32_vectors.S
--- a/arch/arm/src/stm32/stm32_wdg.h
+++ b/arch/arm/src/stm32/stm32_wdg.h
@@ -0,0 +1,136 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_wdg.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_WDG_H
+#define __ARCH_ARM_SRC_STM32_STM32_WDG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_IWDG_KR_OFFSET    0x0000  /* Key register (32-bit) */
+#define STM32_IWDG_PR_OFFSET    0x0004  /* Prescaler register (32-bit) */
+#define STM32_IWDG_RLR_OFFSET   0x0008  /* Reload register (32-bit) */
+#define STM32_IWDG_SR_OFFSET    0x000c  /* Status register (32-bit) */
+
+#define STM32_WWDG_CR_OFFSET    0x0000  /* Control Register (32-bit) */
+#define STM32_WWDG_CFR_OFFSET   0x0004  /* Configuration register (32-bit) */
+#define STM32_WWDG_SR_OFFSET    0x0008  /* Status register (32-bit) */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_IWDG_KR           (STM32_IWDG_OFFSET+STM32_IWDG_KR_OFFSET)
+#define STM32_IWDG_PR           (STM32_IWDG_OFFSET+STM32_IWDG_PR_OFFSET)
+#define STM32_IWDG_RLR          (STM32_IWDG_OFFSET+STM32_IWDG_RLR_OFFSET)
+#define STM32_IWDG_SR           (STM32_IWDG_OFFSET+STM32_IWDG_SR_OFFSET)
+
+#define STM32_WWDG_CR           (STM32_WWDG_OFFSET+STM32_WWDG_CR_OFFSET)
+#define STM32_WWDG_CFR          (STM32_WWDG_OFFSET+STM32_WWDG_CFR_OFFSET)
+#define STM32_WWDG_SR           (STM32_WWDG_OFFSET+STM32_WWDG_SR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Key register (32-bit) */
+
+#define IWDG_KR_KEY_SHIFT       (0)       /* Bits 15-0: Key value (write only, read 0000h) */
+#define IWDG_KR_KEY_MASK        (0xffff << IWDG_KR_KEY_SHIFT)
+
+/* Prescaler register (32-bit) */
+
+#define IWDG_PR_SHIFT           (0)       /* Bits 2-0: Prescaler divider */
+#define IWDG_PR_MASK            (7 << IWDG_PR_SHIFT)
+#  define IWDG_PR_DIV4          (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
+#  define IWDG_PR_DIV8          (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
+#  define IWDG_PR_DIV16         (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
+#  define IWDG_PR_DIV32         (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
+#  define IWDG_PR_DIV64         (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
+#  define IWDG_PR_DIV128        (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
+#  define IWDG_PR_DIV256        (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
+
+/* Reload register (32-bit) */
+
+#define IWDG_RLR_RL_SHIFT       (0)       /* Bits11:0 RL[11:0]: Watchdog counter reload value */
+#define IWDG_RLR_RL_MASK        (0x0fff << IWDG_RLR_RL_SHIFT)
+
+/* Status register (32-bit) */
+
+#define IWDG_SR_PVU             (1 << 0)  /* Bit 0: Watchdog prescaler value update */
+#define IWDG_SR_RVU             (1 << 1)  /* Bit 1: Watchdog counter reload value update */
+
+/* Control Register (32-bit) */
+
+#define WWDG_CR_T_SHIFT         (0)       /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
+#define WWDG_CR_T_MASK          (0x7f << WWDG_CR_T_SHIFT)
+#define WWDG_CR_WDGA            (1 << 7)  /* Bit 7: Activation bit */
+
+/* Configuration register (32-bit) */
+
+#define WWDG_CFR_W_SHIFT        (0)       /* Bits 6:0 W[6:0] 7-bit window value */
+#define WWDG_CFR_W_MASK         (0x7f << WWDG_CFR_W_SHIFT)
+#define WWDG_CFR_WDGTB_SHIFT    (7)       /* Bits 8:7 [1:0]: Timer Base */
+#define WWDG_CFR_WDGTB_MASK     (3 << WWDG_CFR_WDGTB_SHIFT)
+#  define WWDG_CFR_PCLK1        (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
+#  define WWDG_CFR_PCLK1d2      (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
+#  define WWDG_CFR_PCLK1d4      (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
+#  define WWDG_CFR_PCLK1d8      (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
+#define WWDG_CFR_EWI            (1 << 9)  /* Bit 9: Early Wakeup Interrupt */
+
+/* Status register (32-bit) */
+
+#define WWDG_SR_EWIF            (1 << 0)  /* Bit 0: Early Wakeup Interrupt Flag */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */
--- a/configs/README.txt
+++ b/configs/README.txt
@@ -163,16 +163,24 @@ defconfig -- This is a configuration file similar to the Linux
 		  that will be used in the build
 		CONFIG_DEBUG - enables built-in debug options
 		CONFIG_DEBUG_VERBOSE - enables verbose debug output
+		CONFIG_DEBUG_SYMBOLS - build without optimization and with
+		  debug symbols (needed for use with a debugger).
 		CONFIG_DEBUG_SCHED - enable OS debug output (disabled by
 		  default)
 		CONFIG_DEBUG_MM - enable memory management debug output
 		  (disabled by default)
 		CONFIG_DEBUG_NET - enable network debug output (disabled
 		  by default)
+		CONFIG_DEBUG_USB - enable usb debug output (disabled by
+		  default)
 		CONFIG_DEBUG_FS - enable filesystem debug output (disabled
 		  by default)
 		CONFIG_DEBUG_LIB - enable C library debug output (disabled
 		  by default)
+		CONFIG_DEBUG_BINFMT - enable binary loader debug output (disabled
+		  by default)
+		CONFIG_DEBUG_GRAPHICS - enable NX graphics debug output
+		  (disabled by default)
 		CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot
 		  time console output
 		CONFIG_MM_REGIONS - If the architecture includes multiple
@@ -358,7 +366,8 @@ defconfig -- This is a configuration file similar to the Linux
 		CONFIG_THTTPD_IPADDR - Server IP address (no host name)
 		CONFIG_THTTPD_SERVER_ADDRESS - SERVER_ADDRESS: response
 		CONFIG_THTTPD_SERVER_SOFTWARE - SERVER_SOFTWARE: response
-		CONFIG_THTTPD_CGI_PATH -
+		CONFIG_THTTPD_PATH - Server working directory
+		CONFIG_THTTPD_CGI_PATH - Path to CGI executables
 		CONFIG_THTTPD_CGI_PATTERN - Only CGI programs matching this
 		  pattern will be executed.  In fact, if this value is not defined
 		  then no CGI logic will be built.
@@ -609,6 +618,11 @@ configs/skp16c26
    Renesas M16C processor on the Renesas SKP16C26 StarterKit.  This port
    uses the GNU m32c toolchain.

+configs/stm3210e-evel
+    STMicrco STM3210E-EVAL development board based on the STMicro STM32F103ZET6
+    microcontroller (ARM Cortex-M3).  This port uses the GNU Cortex-M3
+    toolchain.
+
 configs/us7032evb1
    This is a port of the Hitachi SH-1 on the Hitachi SH-1/US7032EVB1 board.
    STATUS:  Work has just began on this port.
--- a/configs/c5471evm/Make.defs
+++ b/configs/c5471evm/Make.defs
@@ -47,7 +47,7 @@ OBJDUMP			= $(CROSSDEV)objdump
 ARCHCCVERSION		= ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
 ARCHCCMAJOR		= ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}

-ifeq ("${CONFIG_DEBUG}","y")
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
  ARCHOPTIMIZATION	= -g
 else
  ARCHOPTIMIZATION	= -Os -fno-strict-aliasing -fno-strength-reduce \
@@ -81,7 +81,7 @@ OBJEXT			= .o
 LIBEXT			= .a
 EXEEXT			=

-ifeq ("${CONFIG_DEBUG}","y")
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
  LDFLAGS		+= -g
 endif

--- a/configs/c5471evm/defconfig
+++ b/configs/c5471evm/defconfig
@@ -139,6 +139,8 @@ CONFIG_HAVE_LIBM=n
 #   that will be used in the build
 # CONFIG_DEBUG - enables built-in debug options
 # CONFIG_DEBUG_VERBOSE - enables verbose debug output
+# CONFIG_DEBUG_SYMBOLS - build without optimization and with
+#   debug symbols (needed for use with a debugger).
 # CONFIG_MM_REGIONS - If the architecture includes multiple
 #   regions of memory to allocate from, this specifies the
 #   number of memory regions that the memory manager must
@@ -201,6 +203,7 @@ CONFIG_HAVE_LIBM=n
 CONFIG_EXAMPLE=ostest
 CONFIG_DEBUG=n
 CONFIG_DEBUG_VERBOSE=n
+CONFIG_DEBUG_SYMBOLS=n
 CONFIG_MM_REGIONS=1
 CONFIG_ARCH_LOWPUTC=y
 CONFIG_RR_INTERVAL=200
--- a/Show More
+++ b/Show More