tcp: Remove incomplete support for TCP reassembly

net/tcp/tcp_input.c: Correct bad check of urgent data length
Urgent data preceded "normal" data in the TCP payload. If the urgent data is larger than the size of the TCP payload, this indicates that the entire payload is urgent data and that urgent data continues in the next packet. This case was handled correctly for the case where urgent data was present but was not being handled correctly in the case where the urgent data was NOT present.
2025-12-12 05:34:38 +08:00 · 2020-12-05 21:38:42 -08:00 · 2020-12-05 21:38:39 -08:00 · 2020-12-05 21:34:52 -08:00 · 2020-11-25 23:49:45 -08:00 · 2020-11-24 18:12:19 -08:00
171 changed files with 3947 additions and 2885 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -124,7 +124,7 @@ jobs:

    strategy:
      matrix:
-        boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, avr-mips-riscv-x86-xtensa, sim, renesas]
+        boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, sim]

    steps:
      - name: Download Source Artifact
@@ -150,7 +150,7 @@ jobs:
          command: docker pull docker.pkg.github.com/apache/incubator-nuttx-testing/nuttx-ci-linux

      - name: Export NuttX Repo SHA
-        run:  echo "::set-env name=nuttx_sha::`git -C sources/nuttx rev-parse HEAD`"
+        run:  echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV
      - name: Run builds
        uses: ./sources/testing/.github/actions/ci-container
        env:
@@ -161,15 +161,20 @@ jobs:
            export CCACHE_DIR=`pwd`/ccache
            mkdir $CCACHE_DIR
            cd sources/testing
-            ./cibuild.sh -c testlist/${{matrix.boards}}.dat
+            export ARTIFACTDIR=`pwd`/../../buildartifacts
+            ./cibuild.sh -A -c testlist/${{matrix.boards}}.dat
            ccache -s
+      - uses: actions/upload-artifact@v2
+        with:
+          name: linux-builds
+          path: buildartifacts/

  macOS:
    runs-on: macos-10.15
    needs: Fetch-Source
    strategy:
      matrix:
-        boards: [arm-12, avr-mips-riscv-x86-xtensa, sim]
+        boards: [arm-12, other, sim]
    steps:
      - name: Download Source Artifact
        uses: actions/download-artifact@v1
@@ -188,12 +193,17 @@ jobs:
          key: ${{ runner.os }}-tools-${{ hashFiles('./sources/testing/cibuild.sh') }}

      - name: Export NuttX Repo SHA
-        run:  echo "::set-env name=nuttx_sha::`git -C sources/nuttx rev-parse HEAD`"
+        run:  echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV
      - name: Run Builds
        run: |
          echo "::add-matcher::sources/nuttx/.github/gcc.json"
          export CCACHE_DIR=`pwd`/ccache
          mkdir $CCACHE_DIR
          cd sources/testing
-          ./cibuild.sh -i -c testlist/${{matrix.boards}}.dat
+          export ARTIFACTDIR=`pwd`/../../buildartifacts
+          ./cibuild.sh -i -A -c testlist/${{matrix.boards}}.dat
          ccache -s
+      - uses: actions/upload-artifact@v2
+        with:
+          name: macos-builds
+          path: buildartifacts/
--- a/Documentation/Makefile
+++ b/Documentation/Makefile
@@ -23,7 +23,7 @@

 # You can set these variables from the command line, and also
 # from the environment for the first two.
-SPHINXOPTS    ?= -j auto
+SPHINXOPTS    ?= -j auto -A nuttx_versions="latest,${NUTTX_VERSIONS}"
 SPHINXBUILD   ?= sphinx-build
 SOURCEDIR     = .
 BUILDDIR      = _build
--- a/Documentation/_static/custom.css
+++ b/Documentation/_static/custom.css
@@ -78,3 +78,16 @@ kbd {
  -webkit-border-radius: 3px;
  text-shadow: 0 1px 0 #fff;
 }
+
+span.menuselection
+{
+  margin: 0px 0.1em;
+  padding: 0.1em 0.1em;
+  border-radius: 3px;
+  border: 1px solid rgb(204, 204, 204);
+}
+
+div.version-selector
+{
+  margin-bottom: 1em;
+}
--- a/Documentation/_templates/layout.html
+++ b/Documentation/_templates/layout.html
@@ -37,9 +37,9 @@
       more modern -->
       
  <div class="version-selector">
-    <select>
-    {% for nuttx_version in nuttx_versions %}
-      <option value="{{ nuttx_version }}" {% if nuttx_version == version %}selected="selected"{% endif %}>{{ nuttx_version }}</option>
+    <select onchange="javascript:location.href = this.value;">
+    {% for nuttx_version in nuttx_versions.split(',') %}
+    <option value="{{ url_root }}../{{ nuttx_version }}" {% if nuttx_version == version %}selected="selected"{% endif %}>{{ nuttx_version }}</option>
    {% endfor %}
    </select>
  </div>
--- a/Documentation/conf.py
+++ b/Documentation/conf.py
@@ -74,10 +74,12 @@ templates_path = ['_templates']
 # This pattern also affects html_static_path and html_extra_path.
 exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']

-# list of documentation versions to offer (besides latest)
+# list of documentation versions to offer (besides latest). this will be
+# overriden by command line option but we can provide a sane default
+# this way

 html_context = dict()
-html_context['nuttx_versions'] = ['latest']
+html_context['nuttx_versions'] = 'latest'

 # TODO: append other options using releases detected from git (or maybe just
 # a few hand-selected ones, or maybe just a "stable" option)
--- a/Documentation/quickstart/configuring.rst
+++ b/Documentation/quickstart/configuring.rst
@@ -32,7 +32,6 @@ has your configuration options selected.
       -l selects the Linux (l) host environment.
       -m selects the macOS (m) host environment.
       -c selects the Windows host and Cygwin (c) environment.
-       -u selects the Windows host and Ubuntu under Windows 10 (u) environment.
       -g selects the Windows host and MinGW/MSYS environment.
       -n selects the Windows host and Windows native (n) environment.

--- a/6
+++ b/6
@@ -93,12 +93,6 @@ config WINDOWS_CYGWIN
 		Build natively in a Cygwin environment with POSIX style paths (like
 		/cygdrive/c/Program Files)

-config WINDOWS_UBUNTU
-	bool "Ubuntu under Windows 10"
-	---help---
-		Build natively in an Ubuntu shell under Windows 10 environment with
-		POSIX style paths (like /mnt/c/Program Files)
-
 config WINDOWS_MSYS
 	bool "MSYS or MSYS2"
 	select TOOLCHAIN_WINDOWS
--- a/1264
+++ b/1264
--- a/84
+++ b/84
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated July 19, 2020)
+NuttX TODO List (Last updated November 20, 2020)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -10,7 +10,7 @@ issues related to each board port.
 nuttx/:

 (16)  Task/Scheduler (sched/)
-  (5)  SMP
+  (3)  SMP
  (1)  Memory Management (mm/)
  (0)  Power Management (drivers/pm)
  (5)  Signals (sched/signal, arch/)
@@ -18,7 +18,7 @@ nuttx/:
  (0)  Message Queues (sched/mqueue)
  (1)  Work Queues (sched/wqueue)
  (6)  Kernel/Protected Build
-  (3)  C++ Support
+  (2)  C++ Support
  (5)  Binary loaders (binfmt/)
 (17)  Network (net/, drivers/net)
  (4)  USB (drivers/usbdev, drivers/usbhost)
@@ -448,34 +448,6 @@ o Task/Scheduler (sched/)
 o SMP
  ^^^

-  Title:       SMP AND DATA CACHES
-  Description: When spinlocks, semaphores, etc. are used in an SMP system with
-               a data cache, then there may be problems with cache coherency
-               in some CPU architectures:  When one CPU modifies the shared
-               object, the changes may not be visible to another CPU if it
-               does not share the data cache. That would cause failure in
-               the IPC logic.
-
-               Flushing the D-cache on writes and invalidating before a read is
-               not really an option.  That would essentially effect every memory
-               access and there may be side-effects due to cache line sizes
-               and alignment.
-
-               For the same reason a separate, non-cacheable memory region is
-               not an option.  Essentially all data would have to go in the
-               non-cached region and you would have no benefit from the data
-               cache.
-
-               On ARM Cortex-A, each CPU has a separate data cache.  However,
-               the MPCore's Snoop Controller Unit supports coherency among
-               the different caches.  The SCU is enabled by the SCU control
-               register and each CPU participates in the SMP coherency by
-               setting the ACTLR_SMP bit in the auxiliary control register
-               (ACTLR).
-
-  Status:      Closed
-  Priority:    High on platforms that may have the issue.
-
  Title:       MISUSE OF sched_lock() IN SMP MODE
  Description: The OS API sched_lock() disables pre-emption and locks a
               task in place.  In the single CPU case, it is also often
@@ -496,37 +468,6 @@ o SMP
  Priority:    Medium for SMP system.  Not critical to single CPU systems.
               NOTE:  There are no known bugs from this potential problem.

-  Title:       CORTEX-A GIC SGI INTERRUPT MASKING
-  Description: In the ARMv7-A GICv2 architecture, the inter-processor
-               interrupts (SGIs) are non maskable and will occur even if
-               interrupts are disabled.  This adds a lot of complexity
-               to the ARMV7-A critical section design.
-
-               Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR
-               register to control SGI interrupts.  This register (much like
-               the ARMv7-M BASEPRI register) can be used to mask interrupts
-               by interrupt priority.  Since SGIs may be assigned priorities
-               the ICCMPR should be able to block execution of SGIs as well.
-
-               Such an implementation would be very similar to the BASEPRI
-               (vs PRIMASK) implementation for the ARMv7-M:  (1) The
-               up_irq_save() and up_irq_restore() registers would have to
-               set/restore the ICCMPR register, (2) register setup logic in
-               arch/arm/src/armv7-a for task start-up and signal dispatch
-               would have to set the ICCMPR correctly, and (3) the 'xcp'
-               structure would have to be extended to hold the ICCMPR
-               register;  logic would have to added be save/restore the
-               ICCMPR register in the 'xcp' structure on each interrupt and
-               context switch.
-
-               This would also be an essential part of a high priority,
-               nested interrupt implementation (unrelated).
-  Status:      Open
-  Priority:    Low.  There are no known issues with the current non-maskable
-               SGI implementation.  This change would, however, lead to
-               simplification in the design and permit commonality with
-               other, non-GIC implementations.
-
  Title:       ISSUES WITH ACCESSING CPU INDEX
  Description: The CPU number is accessed usually with the macro this_cpu().
               The returned CPU number is then used for various things,
@@ -550,7 +491,7 @@ o SMP
               can that occur?  I think it can occur in the following
               situation:

-               The log below was reported is Nuttx running on two cores
+               The log below was reported is NuttX running on two cores
               Cortex-A7 architecture in SMP mode.  You can notice see that
               when nxsched_add_readytorun() was called, the g_cpu_irqset is 3.

@@ -1077,23 +1018,6 @@ o Kernel/Protected Build
 o C++ Support
  ^^^^^^^^^^^

-  Title:       USE OF SIZE_T IN NEW OPERATOR
-  Description: The argument of the 'new' operators should take a type of
-               size_t (see libxx/libxx_new.cxx and libxx/libxx_newa.cxx).  But
-               size_t has an unknown underlying.  In the nuttx sys/types.h
-               header file, size_t is typed as uint32_t (which is determined by
-               architecture-specific logic).  But the C++ compiler may believe
-               that size_t is of a different type resulting in compilation errors
-               in the operator.  Using the underlying integer type Instead of
-               size_t seems to resolve the compilation issues.
-  Status:      Kind of open. There is a workaround. Setting CONFIG_ARCH_SIZET_LONG
-               =y will define the operators with argument of type unsigned long;
-               Setting CONFIG_ARCH_SIZET_LONG=n will define the operators with
-               argument of type unsigned int. But this is pretty ugly!  A better
-               solution would be to get a hold of the compilers definition of
-               size_t.
-  Priority:    Low.
-
  Title:       STATIC CONSTRUCTORS AND MULTITASKING
  Description: The logic that calls static constructors operates on the main
               thread of the initial user application task.  Any static
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -1270,8 +1270,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
         * that only one speed is supported.
         */

-        /* Get the c_speed field in the termios struct */
-
        priv->baud = cfgetispeed(termiosp);

        /* TODO: Re-calculate the optimal CCLK divisor for the new baud and
--- a/arch/arm/src/am335x/am335x_serial.c
+++ b/arch/arm/src/am335x/am335x_serial.c
@@ -515,7 +515,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
 * Name: up_serialout
 ****************************************************************************/

-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+                                uint32_t value)
 {
  putreg32(value, priv->uartbase + offset);
 }
@@ -565,13 +566,13 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
  up_serialout(priv, AM335X_UART_LCR_OFFSET, lcr);
 }

-/************************************************************************************
+/****************************************************************************
 * Name: am335x_uart0config, uart1config, uart2config, ..., uart5config
 *
 * Descrption:
 *   Configure the UART
 *
- ************************************************************************************/
+ ****************************************************************************/

 #ifdef CONFIG_AM335X_UART0
 static inline void am335x_uart0config(void)
@@ -699,7 +700,7 @@ static inline void am335x_uart5config(void)
 };
 #endif

-/************************************************************************************
+/****************************************************************************
 * Name: am335x_uartdl
 *
 * Description:
@@ -708,7 +709,7 @@ static inline void am335x_uart5config(void)
 *     BAUD = PCLK / (16 * DL), or
 *     DL   = PCLK / BAUD / 16
 *
- ************************************************************************************/
+ ****************************************************************************/

 static inline uint32_t am335x_uartdl(uint32_t baud)
 {
@@ -758,11 +759,13 @@ static int up_setup(struct uart_dev_s *dev)

  /* Clear FIFOs */

-  up_serialout(priv, AM335X_UART_FCR_OFFSET, (UART_FCR_RFIFO_CLEAR | UART_FCR_TFIFO_CLEAR));
+  up_serialout(priv, AM335X_UART_FCR_OFFSET,
+               (UART_FCR_RFIFO_CLEAR | UART_FCR_TFIFO_CLEAR));

  /* Configure the FIFOs */

-  up_serialout(priv, AM335X_UART_FCR_OFFSET, (UART_FCR_FIFO_EN | UART_FCR_RFT_60CHAR | UART_FCR_TFT_56CHAR));
+  up_serialout(priv, AM335X_UART_FCR_OFFSET,
+    (UART_FCR_FIFO_EN | UART_FCR_RFT_60CHAR | UART_FCR_TFT_56CHAR));

  /* Set up the IER */

@@ -846,14 +849,15 @@ static void up_shutdown(struct uart_dev_s *dev)
 * Name: up_attach
 *
 * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
 *   the setup() method is called, however, the serial console may operate in
 *   a non-interrupt driven mode during the boot phase.
 *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
 *
 ****************************************************************************/

@@ -882,8 +886,8 @@ static int up_attach(struct uart_dev_s *dev)
 *
 * Description:
 *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception is
- *   the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
 *
 ****************************************************************************/

@@ -990,7 +994,9 @@ static int uart_interrupt(int irq, void *context, void *arg)
              return OK;
            }

-            /* Otherwise we have received an interrupt that we cannot handle */
+            /* Otherwise we have received an interrupt that we cannot
+             * handle
+             */

          default:
            {
@@ -1090,16 +1096,16 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
         * that only one speed is supported.
         */

-        /* Get the c_speed field in the termios struct */
-
        priv->baud = cfgetispeed(termiosp);

        /* TODO: Re-calculate the optimal CCLK divisor for the new baud and
         * and reset the divider in the CLKSEL0/1 register.
         */

-        /* DLAB open latch */
-        /* REVISIT:  Shouldn't we just call up_setup() to do all of the following? */
+        /* DLAB open latch
+         * REVISIT:  Shouldn't we just call up_setup() to do all of the
+         *           following?
+         */

        lcr = up_serialin(priv, AM335X_UART_LCR_OFFSET);
        up_serialout(priv, AM335X_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
@@ -1107,7 +1113,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
        /* Set the BAUD divisor */

        dl = am335x_uartdl(priv->baud);
-        up_serialout(priv, AM335X_UART_DLH_OFFSET, (dl >> 8) & UART_DLH_MASK);
+        up_serialout(priv, AM335X_UART_DLH_OFFSET,
+                     (dl >> 8) & UART_DLH_MASK);
        up_serialout(priv, AM335X_UART_DLL_OFFSET, dl & UART_DLL_MASK);

        /* Clear DLAB */
--- a/arch/arm/src/arm/arm_assert.c
+++ b/arch/arm/src/arm/arm_assert.c
@@ -210,18 +210,12 @@ static void up_dumpstate(void)
   * stack?
   */

-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
    {
      /* Yes.. dump the interrupt stack */

+      _alert("Interrupt Stack\n", sp);
      up_stackdump(sp, istackbase);
-
-      /* Extract the user stack pointer which should lie
-       * at the base of the interrupt stack.
-       */
-
-      sp = g_intstackbase;
-      _alert("sp:     %08x\n", sp);
    }
  else if (CURRENT_REGS)
    {
@@ -229,6 +223,17 @@ static void up_dumpstate(void)
      up_stackdump(istackbase - istacksize, istackbase);
    }

+  /* Extract the user stack pointer if we are in an interrupt handler.
+   * If we are not in an interrupt handler.  Then sp is the user stack
+   * pointer (and the above range check should have failed).
+   */
+
+  if (CURRENT_REGS)
+    {
+      sp = CURRENT_REGS[REG_R13];
+      _alert("User sp: %08x\n", sp);
+    }
+
  /* Show user stack info */

  _alert("User stack:\n");
--- a/arch/arm/src/arm/arm_vectors.S
+++ b/arch/arm/src/arm/arm_vectors.S
@@ -132,7 +132,7 @@ arm_vectorirq:

 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	ldr	sp, .Lirqstackbase	/* SP = interrupt stack base */
-	str	r0, [sp]		/* Save the user stack pointer */
+	str	r0, [sp, #-4]!		/* Save the xcp address at SP-4 then update SP */
 	bl	arm_decodeirq		/* Call the handler */
 	ldr	sp, [sp]		/* Restore the user stack pointer */
 #else
@@ -432,13 +432,13 @@ arm_vectorfiq:

 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	.bss
-	.align	4
+	.balign	4
 	.globl	g_intstackalloc
 	.type	g_intstackalloc, object
 	.globl	g_intstackbase
 	.type	g_intstackbase, object
 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4
--- a/arch/arm/src/armv6-m/arm_assert.c
+++ b/arch/arm/src/armv6-m/arm_assert.c
@@ -247,7 +247,7 @@ static void up_dumpstate(void)
   * stack?
   */

-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
    {
      /* Yes.. dump the interrupt stack */

--- a/arch/arm/src/armv6-m/arm_exception.S
+++ b/arch/arm/src/armv6-m/arm_exception.S
@@ -270,7 +270,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global g_intstackbase
-	.align	4
+	.balign	4
 g_intstackalloc:
 	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
 g_intstackbase:
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -252,7 +252,7 @@ static void up_dumpstate(void)
  if (rtcb->xcp.kstack)
    {
      kstackbase = (uint32_t)rtcb->xcp.kstack +
-                   CONFIG_ARCH_KERNEL_STACKSIZE - 4;
+                   CONFIG_ARCH_KERNEL_STACKSIZE;

      _alert("Kernel stack:\n");
      _alert("  base: %08x\n", kstackbase);
@@ -265,24 +265,10 @@ static void up_dumpstate(void)

  if (sp > istackbase - istacksize && sp < istackbase)
    {
-      uint32_t *stackbase;
-
      /* Yes.. dump the interrupt stack */

      _alert("Interrupt Stack\n", sp);
      up_stackdump(sp, istackbase);
-
-      /* Extract the user stack pointer which should lie
-       * at the base of the interrupt stack.
-       */
-
-#ifdef CONFIG_SMP
-      stackbase = (uint32_t *)arm_intstack_base();
-#else
-      stackbase = (uint32_t *)&g_intstackbase;
-#endif
-      sp        = *stackbase;
-      _alert("User sp: %08x\n", sp);
    }
  else if (CURRENT_REGS)
    {
@@ -291,6 +277,17 @@ static void up_dumpstate(void)
    }
 #endif

+  /* Extract the user stack pointer if we are in an interrupt handler.
+   * If we are not in an interrupt handler.  Then sp is the user stack
+   * pointer (and the above range check should have failed).
+   */
+
+  if (CURRENT_REGS)
+    {
+      sp = CURRENT_REGS[REG_R13];
+      _alert("User sp: %08x\n", sp);
+    }
+
  /* Dump the user stack if the stack pointer lies within the allocated user
   * stack memory.
   */
--- a/arch/arm/src/armv7-a/arm_cpuhead.S
+++ b/arch/arm/src/armv7-a/arm_cpuhead.S
@@ -420,12 +420,13 @@ __cpu3_start:
 	 */

 	adr		r3, .Lstkinit
-	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of stack; R2 = coloration */
+	mov		r0, sp		/* R0 = end of IDLE stack */
+	ldmia		r3, {r1, r2}	/* R1 = Size of stack; R2 = coloration */

 1:								/* Top of the loop */
 	sub		r1, r1, #1			/* R1 = Number of words remaining */
 	cmp		r1, #0				/* Check (nwords == 0) */
-	str		r2, [r0], #4		/* Save stack color word, increment stack address */
+	str		r2, [r0, #-4]!		/* Save stack color word, increment stack address */
 	bne		1b					/* Bottom of the loop */
 #endif

@@ -494,14 +495,5 @@ g_cpu3_idlestack:
 #endif /* CONFIG_SMP_NCPUS > 3 */
 #endif /* CONFIG_SMP_NCPUS > 2 */
 #endif /* CONFIG_SMP_NCPUS > 1 */
-
-	.align	8
-	.globl	g_idle_topstack
-	.type	g_idle_topstack, object
-
-g_idle_topstack:
-	.long	_enoinit
-	.size	g_idle_topstack, .-g_idle_topstack
-
 #endif /* CONFIG_SMP */
 	.end
--- a/arch/arm/src/armv7-a/arm_cpuidlestack.c
+++ b/arch/arm/src/armv7-a/arm_cpuidlestack.c
@@ -133,10 +133,9 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)

  /* Get the top of the stack */

-
  stack_alloc          = (uintptr_t)g_cpu_stackalloc[cpu];
  DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
-  top_of_stack         = stack_alloc + SMP_STACK_TOP;
+  top_of_stack         = stack_alloc + SMP_STACK_SIZE;

  tcb->adj_stack_size  = SMP_STACK_SIZE;
  tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc;
--- a/arch/arm/src/armv7-a/arm_cpustart.c
+++ b/arch/arm/src/armv7-a/arm_cpustart.c
@@ -171,10 +171,6 @@ int up_cpu_start(int cpu)
  sched_note_cpu_start(this_task(), cpu);
 #endif

-  /* Make the content of CPU0 L1 cache has been written to coherent L2 */
-
-  cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
-
  /* Execute SGI1 */

  return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -754,6 +754,8 @@ arm_data_initialize:
 .Lstackpointer:
 #ifdef CONFIG_BOOT_SDRAM_DATA
 	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE-4
+#elif defined(CONFIG_SMP)
+	.long	_enoinit+CONFIG_IDLETHREAD_STACKSIZE-4
 #else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
 #endif
@@ -773,6 +775,8 @@ arm_data_initialize:
 .Lstkinit:
 #ifdef CONFIG_BOOT_SDRAM_DATA
 	.long	IDLE_STACK_VBASE		/* Beginning of the IDLE stack, then words of IDLE stack */
+#elif defined(CONFIG_SMP)
+	.long	_enoinit
 #else
 	.long	_ebss					/* Beginning of the IDLE stack, then words of IDLE stack */
 #endif
@@ -785,7 +789,6 @@ arm_data_initialize:
 * Data section variables
 ***************************************************************************/

-#ifndef CONFIG_SMP
 	/* This global variable is unsigned long g_idle_topstack and is
 	 * exported from here only because of its coupling to .Linitparms
 	 * above.
@@ -800,10 +803,11 @@ g_idle_topstack:

 #ifdef CONFIG_BOOT_SDRAM_DATA
 	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE
+#elif defined(CONFIG_SMP)
+	.long	_enoinit+CONFIG_IDLETHREAD_STACKSIZE
 #else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
 #endif
 	.size	g_idle_topstack, .-g_idle_topstack
-#endif
 	.end
 #endif
--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
 * arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c
 *
 *   Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
@@ -36,7 +36,7 @@
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
- ************************************************************************************/
+ ****************************************************************************/

 /****************************************************************************
 * Included Files
@@ -59,13 +59,15 @@
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
-/* Configuration ***********************************************************/
+
+/* Configuration ************************************************************/
+
 /* Number of ways depends on ARM configuration */

 #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
 #  define PL310_NWAYS      8
 #  define PL310_WAY_MASK   0x000000ff
-#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
 #  define PL310_NWAYS 16
 #  define PL310_WAY_MASK   0x0000ffff
 #else
@@ -315,38 +317,45 @@ void arm_l2ccinitialize(void)

  /* Make sure that this is a PL310 cache, version r3p2.
   *
-   * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is
-   * r3p2, but the chip that I have actually* reports 0x410000C9 which is some
-   * later revision.
+   * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which
+   * is r3p2, but the chip that I have actually* reports 0x410000C9 which
+   * is some later revision.
   */

-  //DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
+  /* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) ==
+   *             L2CC_IDR_REV_R3P2);
+   */

  /* Make sure that actual cache configuration agrees with the configured
   * cache configuration.
   */

-
 #if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
 #elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
 #else
 #  error No associativity selected
 #endif

 #if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_16KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_32KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_64KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_128KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_256KB);
 #elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
-  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
+              L2CC_ACR_WAYSIZE_512KB);
 #else
 #  error No way size selected
 #endif
--- a/arch/arm/src/armv7-a/arm_vectors.S
+++ b/arch/arm/src/armv7-a/arm_vectors.S
@@ -261,7 +261,7 @@ arm_vectorirq:
 	/* Call arm_decodeirq() on the interrupt stack */

 	setirqstack r1, r3				/* SP = IRQ stack top */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodeirq			/* Call the handler */
@@ -1004,7 +1004,7 @@ arm_vectorfiq:

 #if CONFIG_ARCH_INTERRUPTSTACK > 7
 	setfiqstack r1, r4				/* SP = FIQ stack top */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodefiq			/* Call the handler */
@@ -1072,7 +1072,7 @@ arm_vectorfiq:

 #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
 	.bss
-	.align	4
+	.balign	8

 	.globl	g_intstackalloc
 	.type	g_intstackalloc, object
@@ -1080,7 +1080,7 @@ arm_vectorfiq:
 	.type	g_intstackbase, object

 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4
@@ -1096,7 +1096,7 @@ g_intstackbase:
 	.type	g_fiqstackbase, object

 g_fiqstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_fiqstackbase:
 	.skip	4
 	.size	g_fiqstackbase, 4
--- a/arch/arm/src/armv7-a/l2cc_pl310.h
+++ b/arch/arm/src/armv7-a/l2cc_pl310.h
@@ -52,11 +52,12 @@
 * header file as L2CC_VBASE.
 */

-#include "chip/chip.h"
+#include "chip.h"

 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
+
 /* General Definitions **************************************************************/

 #define PL310_CACHE_LINE_SIZE      32
@@ -110,7 +111,7 @@

 #define L2CC_DLKR_OFFSET(n)        (0x0900 + ((n) << 3)) /* Data Lockdown Register */
 #define L2CC_ILKR_OFFSET(n)        (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */
-                                          /* 0x0940-0x0f4c Reserved */
+                                                         /* 0x0940-0x0f4c Reserved */
 #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
 #  define L2CC_LKLN_OFFSET         0x0950 /* Lock Line Enable Register */
 #  define L2CC_UNLKW_OFFSET        0x0954 /* Unlock Way Register */
@@ -170,23 +171,23 @@
 /* Cache ID Register (32-bit ID) */

 #define L2CC_IDR_REV_MASK          0x0000003f
-#  define L2CC_IDR_REV_R0P0        0x00000000
-#  define L2CC_IDR_REV_R1P0        0x00000002
-#  define L2CC_IDR_REV_R2P0        0x00000004
-#  define L2CC_IDR_REV_R3P0        0x00000005
-#  define L2CC_IDR_REV_R3P1        0x00000006
-#  define L2CC_IDR_REV_R3P2        0x00000008
+#define L2CC_IDR_REV_R0P0          0x00000000
+#define L2CC_IDR_REV_R1P0          0x00000002
+#define L2CC_IDR_REV_R2P0          0x00000004
+#define L2CC_IDR_REV_R3P0          0x00000005
+#define L2CC_IDR_REV_R3P1          0x00000006
+#define L2CC_IDR_REV_R3P2          0x00000008

 /* Cache Type Register */

 #define L2CC_TYPR_IL2ASS           (1 << 6)  /* Bit 6:  Instruction L2 Cache Associativity */
 #define L2CC_TYPR_IL2WSIZE_SHIFT   (8)       /* Bits 8-10: Instruction L2 Cache Way Size */
 #define L2CC_TYPR_IL2WSIZE_MASK    (7 << L2CC_TYPR_IL2WSIZE_SHIFT)
-#  define L2CC_TYPR_IL2WSIZE(n)    ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
+#define L2CC_TYPR_IL2WSIZE(n)      ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
 #define L2CC_TYPR_DL2ASS           (1 << 18) /* Bit 18: Data L2 Cache Associativity */
 #define L2CC_TYPR_DL2WSIZE_SHIFT   (20)      /* Bits 20-22: Data L2 Cache Way Size */
 #define L2CC_TYPR_DL2WSIZE_MASK    (7 << L2CC_TYPR_DL2WSIZE_SHIFT)
-#  define L2CC_TYPR_DL2WSIZE(n)    ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)
+#define L2CC_TYPR_DL2WSIZE(n)      ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)

 /* Control Register */

@@ -202,21 +203,22 @@
 #define L2CC_ACR_ASS               (1 << 16) /* Bit 16: Associativity */
 #define L2CC_ACR_WAYSIZE_SHIFT     (17)      /* Bits 17-19: Way Size */
 #define L2CC_ACR_WAYSIZE_MASK      (7 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_16KB    (1 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_32KB    (2 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_64KB    (3 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_128KB   (4 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_256KB   (5 << L2CC_ACR_WAYSIZE_SHIFT)
-#  define L2CC_ACR_WAYSIZE_512KB   (6 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_16KB      (1 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_32KB      (2 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_64KB      (3 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_128KB     (4 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_256KB     (5 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_WAYSIZE_512KB     (6 << L2CC_ACR_WAYSIZE_SHIFT)
 #define L2CC_ACR_EMBEN             (1 << 20) /* Bit 20: Event Monitor Bus Enable */
 #define L2CC_ACR_PEN               (1 << 21) /* Bit 21: Parity Enable */
 #define L2CC_ACR_SAOEN             (1 << 22) /* Bit 22: Shared Attribute Override Enable */
 #define L2CC_ACR_FWA_SHIFT         (23)      /* Bits 23-24:  Force Write Allocate */
 #define L2CC_ACR_FWA_MASK          (3 << L2CC_ACR_FWA_SHIFT)
-#  define L2CC_ACR_FWA_AWCACHE     (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
-#  define L2CC_ACR_FWA_NOALLOC     (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
-#  define L2CC_ACR_FWA_OVERRIDE    (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
-#  define L2CC_ACR_FWA_MAPPED      (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
+#define L2CC_ACR_FWA_AWCACHE       (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
+#define L2CC_ACR_FWA_NOALLOC       (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
+#define L2CC_ACR_FWA_OVERRIDE      (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
+#define L2CC_ACR_FWA_MAPPED        (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
+
 #define L2CC_ACR_CRPOL             (1 << 25) /* Bit 25: Cache Replacement Policy */
 #define L2CC_ACR_NSLEN             (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
 #define L2CC_ACR_NSIAC             (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
@@ -230,25 +232,25 @@

 #define L2CC_TRCR_TSETLAT_SHIFT    (0)       /* Bits 0-2: Setup Latency */
 #define L2CC_TRCR_TSETLAT_MASK     (7 << L2CC_TRCR_TSETLAT_SHIFT)
-#  define L2CC_TRCR_TSETLAT(n)     ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
+#define L2CC_TRCR_TSETLAT(n)       ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
 #define L2CC_TRCR_TRDLAT_SHIFT     (4)       /* Bits 4-6: Read Access Latency */
 #define L2CC_TRCR_TRDLAT_MASK      (7 << L2CC_TRCR_TRDLAT_SHIFT)
-#  define L2CC_TRCR_TRDLAT(n)      ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
+#define L2CC_TRCR_TRDLAT(n)        ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
 #define L2CC_TRCR_TWRLAT_SHIFT     (8)       /* Bits 8-10: Write Access Latency */
 #define L2CC_TRCR_TWRLAT_MASK      (7 << L2CC_TRCR_TWRLAT_SHIFT)
-#  define L2CC_TRCR_TWRLAT(n)      ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)
+#define L2CC_TRCR_TWRLAT(n)        ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)

 /* Data RAM Control Register */

 #define L2CC_DRCR_DSETLAT_SHIFT    (0)       /* Bits 0-2: Setup Latency */
 #define L2CC_DRCR_DSETLAT_MASK     (7 << L2CC_DRCR_DSETLAT_SHIFT)
-#  define L2CC_DRCR_DSETLAT(n)     ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
+#define L2CC_DRCR_DSETLAT(n)       ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
 #define L2CC_DRCR_DRDLAT_SHIFT     (4)       /* Bits 4-6: Read Access Latency */
 #define L2CC_DRCR_DRDLAT_MASK      (7 << L2CC_DRCR_DRDLAT_SHIFT)
-#  define L2CC_DRCR_DRDLAT(n)      ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
+#define L2CC_DRCR_DRDLAT(n)        ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
 #define L2CC_DRCR_DWRLAT_SHIFT     (8)       /* Bits 8-10: Write Access Latency */
 #define L2CC_DRCR_DWRLAT_MASK      (7 << L2CC_DRCR_DWRLAT_SHIFT)
-#  define L2CC_DRCR_DWRLAT(n)      ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)
+#define L2CC_DRCR_DWRLAT(n)        ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)

 /* Event Counter Control Register */

@@ -258,60 +260,60 @@

 /* Event Counter 1 Configuration Register */

-
-#define L2CC_ECFGR1_EIGEN_SHIFT    (0)       /* Bits 0-1: Event Counter Interrupt Generation */
-#define L2CC_ECFGR1_EIGEN_MASK     (3 << L2CC_ECFGR1_EIGEN_SHIFT)
-#  define L2CC_ECFGR1_EIGEN_INTDIS    (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
-#  define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
-#  define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
-#  define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
-#define L2CC_ECFGR1_ESRC_SHIFT     (2)       /* Bits 2-5: Event Counter Source */
-#define L2CC_ECFGR1_ESRC_MASK      (15 << L2CC_ECFGR1_ESRC_SHIFT)
-#  define L2CC_ECFGR1_ESRC_CNTDIS     (0 << L2CC_ECFGR1_ESRC_SHIFT)  /* Counter Disabled */
-#  define L2CC_ECFGR1_ESRC_CO         (1 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is CO */
-#  define L2CC_ECFGR1_ESRC_DRHIT      (2 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRHIT */
-#  define L2CC_ECFGR1_ESRC_DRREQ      (3 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRREQ */
-#  define L2CC_ECFGR1_ESRC_DWHIT      (4 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWHIT */
-#  define L2CC_ECFGR1_ESRC_DWREQ      (5 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWREQ */
-#  define L2CC_ECFGR1_ESRC_DWTREQ     (6 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWTREQ */
-#  define L2CC_ECFGR1_ESRC_IRHIT      (7 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRHIT */
-#  define L2CC_ECFGR1_ESRC_IRREQ      (8 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRREQ */
-#  define L2CC_ECFGR1_ESRC_WA         (9 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is WA */
-#  define L2CC_ECFGR1_ESRC_IPFALLOC   (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
-#  define L2CC_ECFGR1_ESRC_EPFHIT     (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
-#  define L2CC_ECFGR1_ESRC_EPFALLOC   (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
-#  define L2CC_ECFGR1_ESRC_SRRCVD     (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
-#  define L2CC_ECFGR1_ESRC_SRCONF     (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
-#  define L2CC_ECFGR1_ESRC_EPFRCVD    (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */
+#define L2CC_ECFGR1_EIGEN_SHIFT     (0)       /* Bits 0-1: Event Counter Interrupt Generation */
+#define L2CC_ECFGR1_EIGEN_MASK      (3 << L2CC_ECFGR1_EIGEN_SHIFT)
+#define L2CC_ECFGR1_EIGEN_INTDIS    (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
+#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
+#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
+#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
+#define L2CC_ECFGR1_ESRC_SHIFT      (2)                            /* Bits 2-5: Event Counter Source */
+#define L2CC_ECFGR1_ESRC_MASK       (15 << L2CC_ECFGR1_ESRC_SHIFT)
+#define L2CC_ECFGR1_ESRC_CNTDIS     (0 << L2CC_ECFGR1_ESRC_SHIFT)  /* Counter Disabled */
+#define L2CC_ECFGR1_ESRC_CO         (1 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is CO */
+#define L2CC_ECFGR1_ESRC_DRHIT      (2 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRHIT */
+#define L2CC_ECFGR1_ESRC_DRREQ      (3 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DRREQ */
+#define L2CC_ECFGR1_ESRC_DWHIT      (4 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWHIT */
+#define L2CC_ECFGR1_ESRC_DWREQ      (5 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWREQ */
+#define L2CC_ECFGR1_ESRC_DWTREQ     (6 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is DWTREQ */
+#define L2CC_ECFGR1_ESRC_IRHIT      (7 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRHIT */
+#define L2CC_ECFGR1_ESRC_IRREQ      (8 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is IRREQ */
+#define L2CC_ECFGR1_ESRC_WA         (9 << L2CC_ECFGR1_ESRC_SHIFT)  /* Source is WA */
+#define L2CC_ECFGR1_ESRC_IPFALLOC   (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
+#define L2CC_ECFGR1_ESRC_EPFHIT     (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
+#define L2CC_ECFGR1_ESRC_EPFALLOC   (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
+#define L2CC_ECFGR1_ESRC_SRRCVD     (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
+#define L2CC_ECFGR1_ESRC_SRCONF     (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
+#define L2CC_ECFGR1_ESRC_EPFRCVD    (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */

 /* Event Counter 0 Configuration Register */

-#define L2CC_ECFGR0_EIGEN_SHIFT    (0)       /* Bits 0-1: Event Counter Interrupt Generation */
-#define L2CC_ECFGR0_EIGEN_MASK     (3 << L2CC_ECFGR0_EIGEN_SHIFT)
-#  define L2CC_ECFGR0_EIGEN_INTDIS    (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
-#  define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
-#  define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
-#  define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
-#define L2CC_ECFGR0_ESRC_SHIFT     (2)       /* Bits 2-5: Event Counter Source */
-#define L2CC_ECFGR0_ESRC_MASK      (15 << L2CC_ECFGR0_ESRC_SHIFT)
-#  define L2CC_ECFGR0_ESRC_CNTDIS     (0 << L2CC_ECFGR0_ESRC_SHIFT)  /* Counter Disabled */
-#  define L2CC_ECFGR0_ESRC_CO         (1 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is CO */
-#  define L2CC_ECFGR0_ESRC_DRHIT      (2 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRHIT */
-#  define L2CC_ECFGR0_ESRC_DRREQ      (3 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRREQ */
-#  define L2CC_ECFGR0_ESRC_DWHIT      (4 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWHIT */
-#  define L2CC_ECFGR0_ESRC_DWREQ      (5 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWREQ */
-#  define L2CC_ECFGR0_ESRC_DWTREQ     (6 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWTREQ */
-#  define L2CC_ECFGR0_ESRC_IRHIT      (7 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRHIT */
-#  define L2CC_ECFGR0_ESRC_IRREQ      (8 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRREQ */
-#  define L2CC_ECFGR0_ESRC_WA         (9 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is WA */
-#  define L2CC_ECFGR0_ESRC_IPFALLOC   (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
-#  define L2CC_ECFGR0_ESRC_EPFHIT     (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
-#  define L2CC_ECFGR0_ESRC_EPFALLOC   (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
-#  define L2CC_ECFGR0_ESRC_SRRCVD     (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
-#  define L2CC_ECFGR0_ESRC_SRCONF     (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
-#  define L2CC_ECFGR0_ESRC_EPFRCVD    (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */
+#define L2CC_ECFGR0_EIGEN_SHIFT     (0)       /* Bits 0-1: Event Counter Interrupt Generation */
+#define L2CC_ECFGR0_EIGEN_MASK      (3 << L2CC_ECFGR0_EIGEN_SHIFT)
+#define L2CC_ECFGR0_EIGEN_INTDIS    (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
+#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
+#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
+#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
+#define L2CC_ECFGR0_ESRC_SHIFT      (2)                            /* Bits 2-5: Event Counter Source */
+#define L2CC_ECFGR0_ESRC_MASK       (15 << L2CC_ECFGR0_ESRC_SHIFT)
+#define L2CC_ECFGR0_ESRC_CNTDIS     (0 << L2CC_ECFGR0_ESRC_SHIFT)  /* Counter Disabled */
+#define L2CC_ECFGR0_ESRC_CO         (1 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is CO */
+#define L2CC_ECFGR0_ESRC_DRHIT      (2 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRHIT */
+#define L2CC_ECFGR0_ESRC_DRREQ      (3 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DRREQ */
+#define L2CC_ECFGR0_ESRC_DWHIT      (4 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWHIT */
+#define L2CC_ECFGR0_ESRC_DWREQ      (5 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWREQ */
+#define L2CC_ECFGR0_ESRC_DWTREQ     (6 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is DWTREQ */
+#define L2CC_ECFGR0_ESRC_IRHIT      (7 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRHIT */
+#define L2CC_ECFGR0_ESRC_IRREQ      (8 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is IRREQ */
+#define L2CC_ECFGR0_ESRC_WA         (9 << L2CC_ECFGR0_ESRC_SHIFT)  /* Source is WA */
+#define L2CC_ECFGR0_ESRC_IPFALLOC   (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
+#define L2CC_ECFGR0_ESRC_EPFHIT     (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
+#define L2CC_ECFGR0_ESRC_EPFALLOC   (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
+#define L2CC_ECFGR0_ESRC_SRRCVD     (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
+#define L2CC_ECFGR0_ESRC_SRCONF     (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
+#define L2CC_ECFGR0_ESRC_EPFRCVD    (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */

 /* Event Counter 1 Value Register (32-bit value) */
+
 /* Event Counter 0 Value Register (32-bit value) */

 /* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status
@@ -337,110 +339,110 @@
 #define L2CC_IPALR_C               (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_IPALR_IDX_SHIFT       (5)       /* Bits 5-13: Index Number */
 #define L2CC_IPALR_IDX_MASK        (0x1ff << L2CC_IPALR_IDX_SHIFT)
-#  define L2CC_IPALR_IDX(n)        ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
+#define L2CC_IPALR_IDX(n)          ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
 #define L2CC_IPALR_TAG_SHIFT       (14)      /* Bits 14-31: Tag Number */
 #define L2CC_IPALR_TAG_MASK        (0x3ffff << L2CC_IPALR_TAG_SHIFT)
-#  define L2CC_IPALR_TAG(n)        ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)
+#define L2CC_IPALR_TAG(n)          ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)

 /* Invalidate Way Register */

 #define L2CC_IWR_WAY(n)            (1 << (n)) /* Bist 0-7:  Invalidate Way Number n, n=0..7 */
-#  define L2CC_IWR_WAY0            (1 << 0)   /* Bit 0:  Invalidate Way Number 0 */
-#  define L2CC_IWR_WAY1            (1 << 1)   /* Bit 1:  Invalidate Way Number 1 */
-#  define L2CC_IWR_WAY2            (1 << 2)   /* Bit 2:  Invalidate Way Number 2 */
-#  define L2CC_IWR_WAY3            (1 << 3)   /* Bit 3:  Invalidate Way Number 3 */
-#  define L2CC_IWR_WAY4            (1 << 4)   /* Bit 4:  Invalidate Way Number 4 */
-#  define L2CC_IWR_WAY5            (1 << 5)   /* Bit 5:  Invalidate Way Number 5 */
-#  define L2CC_IWR_WAY6            (1 << 6)   /* Bit 6:  Invalidate Way Number 6 */
-#  define L2CC_IWR_WAY7            (1 << 7)   /* Bit 7:  Invalidate Way Number 7 */
+#define L2CC_IWR_WAY0              (1 << 0)   /* Bit 0:  Invalidate Way Number 0 */
+#define L2CC_IWR_WAY1              (1 << 1)   /* Bit 1:  Invalidate Way Number 1 */
+#define L2CC_IWR_WAY2              (1 << 2)   /* Bit 2:  Invalidate Way Number 2 */
+#define L2CC_IWR_WAY3              (1 << 3)   /* Bit 3:  Invalidate Way Number 3 */
+#define L2CC_IWR_WAY4              (1 << 4)   /* Bit 4:  Invalidate Way Number 4 */
+#define L2CC_IWR_WAY5              (1 << 5)   /* Bit 5:  Invalidate Way Number 5 */
+#define L2CC_IWR_WAY6              (1 << 6)   /* Bit 6:  Invalidate Way Number 6 */
+#define L2CC_IWR_WAY7              (1 << 7)   /* Bit 7:  Invalidate Way Number 7 */

 /* Clean Physical Address Line Register */

 #define L2CC_CPALR_C               (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CPALR_IDX_SHIFT       (5)       /* Bits 5-13: Index number */
 #define L2CC_CPALR_IDX_MASK        (0x1ff << L2CC_CPALR_IDX_SHIFT)
-#  define L2CC_CPALR_IDX(n)        ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
+#define L2CC_CPALR_IDX(n)          ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
 #define L2CC_CPALR_TAG_SHIFT       (14)      /* Bits 14-31: Tag number */
 #define L2CC_CPALR_TAG_MASK        (0x3ffff << L2CC_CPALR_TAG_SHIFT)
-#  define L2CC_CPALR_TAG(n)        ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)
+#define L2CC_CPALR_TAG(n)          ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)

 /* Clean Index Register */

 #define L2CC_CIR_C                 (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CIR_IDX_SHIFT         (5)       /* Bits 5-13: Index number */
 #define L2CC_CIR_IDX_MASK          (0x1ff << L2CC_CIR_IDX_SHIFT)
-#  define L2CC_CIR_IDX(n)          ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
+#define L2CC_CIR_IDX(n)            ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
 #define L2CC_CIR_WAY_SHIFT         (28)      /* Bits 28-30: Way number */
 #define L2CC_CIR_WAY_MASK          (7 << L2CC_CIR_WAY_SHIFT)
-#  define L2CC_CIR_WAY(n)          ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)
+#define L2CC_CIR_WAY(n)            ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)

 /* Clean Way Register */

 #define L2CC_CWR_WAY(n)            (1 << (n)) /* Bits 0-7:  Clean Way Number n, n=0..7 */
-#  define L2CC_CWR_WAY0            (1 << 0)   /* Bit 0:  Clean Way Number 0 */
-#  define L2CC_CWR_WAY1            (1 << 1)   /* Bit 1:  Clean Way Number 1 */
-#  define L2CC_CWR_WAY2            (1 << 2)   /* Bit 2:  Clean Way Number 2 */
-#  define L2CC_CWR_WAY3            (1 << 3)   /* Bit 3:  Clean Way Number 3 */
-#  define L2CC_CWR_WAY4            (1 << 4)   /* Bit 4:  Clean Way Number 4 */
-#  define L2CC_CWR_WAY5            (1 << 5)   /* Bit 5:  Clean Way Number 5 */
-#  define L2CC_CWR_WAY6            (1 << 6)   /* Bit 6:  Clean Way Number 6 */
-#  define L2CC_CWR_WAY7            (1 << 7)   /* Bit 7:  Clean Way Number 7 */
+#define L2CC_CWR_WAY0              (1 << 0)   /* Bit 0:  Clean Way Number 0 */
+#define L2CC_CWR_WAY1              (1 << 1)   /* Bit 1:  Clean Way Number 1 */
+#define L2CC_CWR_WAY2              (1 << 2)   /* Bit 2:  Clean Way Number 2 */
+#define L2CC_CWR_WAY3              (1 << 3)   /* Bit 3:  Clean Way Number 3 */
+#define L2CC_CWR_WAY4              (1 << 4)   /* Bit 4:  Clean Way Number 4 */
+#define L2CC_CWR_WAY5              (1 << 5)   /* Bit 5:  Clean Way Number 5 */
+#define L2CC_CWR_WAY6              (1 << 6)   /* Bit 6:  Clean Way Number 6 */
+#define L2CC_CWR_WAY7              (1 << 7)   /* Bit 7:  Clean Way Number 7 */

 /* Clean Invalidate Physical Address Line Register */

 #define L2CC_CIPALR_C              (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CIPALR_IDX_SHIFT      (5)       /* Bits 5-13: Index Number */
 #define L2CC_CIPALR_IDX_MASK       (0x1ff << L2CC_CIPALR_IDX_SHIFT)
-#  define L2CC_CIPALR_IDX(n)       ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
+#define L2CC_CIPALR_IDX(n)         ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
 #define L2CC_CIPALR_TAG_SHIFT      (14)      /* Bits 14-31: Tag Number */
 #define L2CC_CIPALR_TAG_MASK       (0x3ffff << L2CC_CIPALR_TAG_SHIFT)
-#  define L2CC_CIPALR_TAG(n)       ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)
+#define L2CC_CIPALR_TAG(n)         ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)

 /* Clean Invalidate Index Register */

 #define L2CC_CIIR_C                (1 << 0)  /* Bit 0:  Cache Synchronization Status */
 #define L2CC_CIIR_IDX_SHIFT        (5)       /* Bits 5-13: Index Number */
 #define L2CC_CIIR_IDX_MASK         (0x1ff << L2CC_CIIR_IDX_SHIFT)
-#  define L2CC_CIIR_IDX(n)         ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
+#define L2CC_CIIR_IDX(n)           ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
 #define L2CC_CIIR_WAY_SHIFT        (28)      /* Bits 28-30: Way Number */
 #define L2CC_CIIR_WAY_MASK         (7 << L2CC_CIIR_WAY_SHIFT)
-#  define L2CC_CIIR_WAY(n)         ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)
+#define L2CC_CIIR_WAY(n)           ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)

 /* Clean Invalidate Way Register */

 #define L2CC_CIWR_WAY(n)           (1 << (n)) /* Bits 0-7:  Clean Invalidate Way Number n, n=1..7 */
-#  define L2CC_CIWR_WAY0           (1 << 0)   /* Bit 0:  Clean Invalidate Way Number 0 */
-#  define L2CC_CIWR_WAY1           (1 << 1)   /* Bit 1:  Clean Invalidate Way Number 1 */
-#  define L2CC_CIWR_WAY2           (1 << 2)   /* Bit 2:  Clean Invalidate Way Number 2 */
-#  define L2CC_CIWR_WAY3           (1 << 3)   /* Bit 3:  Clean Invalidate Way Number 3 */
-#  define L2CC_CIWR_WAY4           (1 << 4)   /* Bit 4:  Clean Invalidate Way Number 4 */
-#  define L2CC_CIWR_WAY5           (1 << 5)   /* Bit 5:  Clean Invalidate Way Number 5 */
-#  define L2CC_CIWR_WAY6           (1 << 6)   /* Bit 6:  Clean Invalidate Way Number 6 */
-#  define L2CC_CIWR_WAY7           (1 << 7)   /* Bit 7:  Clean Invalidate Way Number 7 */
+#define L2CC_CIWR_WAY0             (1 << 0)   /* Bit 0:  Clean Invalidate Way Number 0 */
+#define L2CC_CIWR_WAY1             (1 << 1)   /* Bit 1:  Clean Invalidate Way Number 1 */
+#define L2CC_CIWR_WAY2             (1 << 2)   /* Bit 2:  Clean Invalidate Way Number 2 */
+#define L2CC_CIWR_WAY3             (1 << 3)   /* Bit 3:  Clean Invalidate Way Number 3 */
+#define L2CC_CIWR_WAY4             (1 << 4)   /* Bit 4:  Clean Invalidate Way Number 4 */
+#define L2CC_CIWR_WAY5             (1 << 5)   /* Bit 5:  Clean Invalidate Way Number 5 */
+#define L2CC_CIWR_WAY6             (1 << 6)   /* Bit 6:  Clean Invalidate Way Number 6 */
+#define L2CC_CIWR_WAY7             (1 << 7)   /* Bit 7:  Clean Invalidate Way Number 7 */

 /* Data Lockdown Register */

 #define L2CC_DLKR_DLK(n)           (1 << (n)) /* Bits 0-7:  Data Lockdown in Way Number n, n=0..7 */
-#  define L2CC_DLKR_DLK0           (1 << 0)   /* Bit 0:  Data Lockdown in Way Number 0 */
-#  define L2CC_DLKR_DLK1           (1 << 1)   /* Bit 1:  Data Lockdown in Way Number 1 */
-#  define L2CC_DLKR_DLK2           (1 << 2)   /* Bit 2:  Data Lockdown in Way Number 2 */
-#  define L2CC_DLKR_DLK3           (1 << 3)   /* Bit 3:  Data Lockdown in Way Number 3 */
-#  define L2CC_DLKR_DLK4           (1 << 4)   /* Bit 4:  Data Lockdown in Way Number 4 */
-#  define L2CC_DLKR_DLK5           (1 << 5)   /* Bit 5:  Data Lockdown in Way Number 5 */
-#  define L2CC_DLKR_DLK6           (1 << 6)   /* Bit 6:  Data Lockdown in Way Number 6 */
-#  define L2CC_DLKR_DLK7           (1 << 7)   /* Bit 7:  Data Lockdown in Way Number 7 */
+#define L2CC_DLKR_DLK0             (1 << 0)   /* Bit 0:  Data Lockdown in Way Number 0 */
+#define L2CC_DLKR_DLK1             (1 << 1)   /* Bit 1:  Data Lockdown in Way Number 1 */
+#define L2CC_DLKR_DLK2             (1 << 2)   /* Bit 2:  Data Lockdown in Way Number 2 */
+#define L2CC_DLKR_DLK3             (1 << 3)   /* Bit 3:  Data Lockdown in Way Number 3 */
+#define L2CC_DLKR_DLK4             (1 << 4)   /* Bit 4:  Data Lockdown in Way Number 4 */
+#define L2CC_DLKR_DLK5             (1 << 5)   /* Bit 5:  Data Lockdown in Way Number 5 */
+#define L2CC_DLKR_DLK6             (1 << 6)   /* Bit 6:  Data Lockdown in Way Number 6 */
+#define L2CC_DLKR_DLK7             (1 << 7)   /* Bit 7:  Data Lockdown in Way Number 7 */

 /* Instruction Lockdown Register */

 #define L2CC_ILKR_ILK(n)           (1 << (n)) /* Bits 0-7:  Instruction Lockdown in Way Number n, n=0..7 */
-#  define L2CC_ILKR_ILK0           (1 << 0)   /* Bit 0:  Instruction Lockdown in Way Number 0 */
-#  define L2CC_ILKR_ILK1           (1 << 1)   /* Bit 1:  Instruction Lockdown in Way Number 1 */
-#  define L2CC_ILKR_ILK2           (1 << 2)   /* Bit 2:  Instruction Lockdown in Way Number 2 */
-#  define L2CC_ILKR_ILK3           (1 << 3)   /* Bit 3:  Instruction Lockdown in Way Number 3 */
-#  define L2CC_ILKR_ILK4           (1 << 4)   /* Bit 4:  Instruction Lockdown in Way Number 4 */
-#  define L2CC_ILKR_ILK5           (1 << 5)   /* Bit 5:  Instruction Lockdown in Way Number 5 */
-#  define L2CC_ILKR_ILK6           (1 << 6)   /* Bit 6:  Instruction Lockdown in Way Number 6 */
-#  define L2CC_ILKR_ILK7           (1 << 7)   /* Bit 7:  Instruction Lockdown in Way Number 7 */
+#define L2CC_ILKR_ILK0             (1 << 0)   /* Bit 0:  Instruction Lockdown in Way Number 0 */
+#define L2CC_ILKR_ILK1             (1 << 1)   /* Bit 1:  Instruction Lockdown in Way Number 1 */
+#define L2CC_ILKR_ILK2             (1 << 2)   /* Bit 2:  Instruction Lockdown in Way Number 2 */
+#define L2CC_ILKR_ILK3             (1 << 3)   /* Bit 3:  Instruction Lockdown in Way Number 3 */
+#define L2CC_ILKR_ILK4             (1 << 4)   /* Bit 4:  Instruction Lockdown in Way Number 4 */
+#define L2CC_ILKR_ILK5             (1 << 5)   /* Bit 5:  Instruction Lockdown in Way Number 5 */
+#define L2CC_ILKR_ILK6             (1 << 6)   /* Bit 6:  Instruction Lockdown in Way Number 6 */
+#define L2CC_ILKR_ILK7             (1 << 7)   /* Bit 7:  Instruction Lockdown in Way Number 7 */

 /* Lock Line Enable Register */

@@ -453,8 +455,8 @@
 #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
 #  define L2CC_UNLKW_WAY_SHIFT     (0)       /* Bits 0-15: Unlock line for corresponding way */
 #  define L2CC_UNLKW_WAY_MASK      (0xffff << L2CC_UNLKW_WAY_SHIFT)
-#    define L2CC_UNLKW_WAY_SET(n)  ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
-#    define L2CC_UNLKW_WAY_BIT(n)  ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
+#  define L2CC_UNLKW_WAY_SET(n)    ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
+#  define L2CC_UNLKW_WAY_BIT(n)    ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
 #endif

 /* Address filter start */
@@ -480,7 +482,7 @@

 #define L2CC_PCR_SHIFT             (0)       /* Bits 0-4: Prefetch Offset */
 #define L2CC_PCR_MASK              (31 << L2CC_PCR_SHIFT)
-#  define L2CC_PCR_PREFETCH(n)     ((uint32_t)(n) << L2CC_PCR_SHIFT)
+#define L2CC_PCR_PREFETCH(n)       ((uint32_t)(n) << L2CC_PCR_SHIFT)
 #define L2CC_PCR_NSIDEN            (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */
 #define L2CC_PCR_IDLEN             (1 << 23) /* Bit 23: INCR Double Linefill Enable */
 #define L2CC_PCR_PDEN              (1 << 24) /* Bit 24: Prefetch Drop Enable */
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
--- a/arch/arm/src/armv7-a/smp.h
+++ b/arch/arm/src/armv7-a/smp.h
@@ -58,7 +58,6 @@
 #define SMP_STACK_MASK       7
 #define SMP_STACK_SIZE       ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
 #define SMP_STACK_WORDS      (SMP_STACK_SIZE >> 2)
-#define SMP_STACK_TOP        (SMP_STACK_SIZE - 8)

 /****************************************************************************
 * Public Data
@@ -122,9 +121,9 @@ void __cpu3_start(void);
 *
 * Description:
 *   Continues the C-level initialization started by the assembly language
- *   __cpu[n]_start function.  At a minimum, this function needs to initialize
- *   interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
- *   issue an SGI.
+ *   __cpu[n]_start function.  At a minimum, this function needs to
+ *   initialize interrupt handling and, perhaps, wait on WFI for
+ *   arm_cpu_start() to issue an SGI.
 *
 *   This function must be provided by the each ARMv7-A MCU and implement
 *   MCU-specific initialization logic.
--- a/arch/arm/src/armv7-m/arm_assert.c
+++ b/arch/arm/src/armv7-m/arm_assert.c
@@ -244,7 +244,7 @@ static void up_dumpstate(void)
   * stack?
   */

-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
    {
      /* Yes.. dump the interrupt stack */

--- a/arch/arm/src/armv7-m/gnu/arm_exception.S
+++ b/arch/arm/src/armv7-m/gnu/arm_exception.S
@@ -67,7 +67,7 @@
   * no privileged task has run.
   */

-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif

@@ -197,7 +197,7 @@ exception_common:
 	 * here prohibits nested interrupts without some additional logic!
 	 */

-	setintstack	r2, r3
+	setintstack	r2, r3				/* SP = IRQ stack top */

 #else
 	/* Otherwise, we will re-use the interrupted thread's stack.  That may
@@ -321,7 +321,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
--- a/arch/arm/src/armv7-m/gnu/arm_lazyexception.S
+++ b/arch/arm/src/armv7-m/gnu/arm_lazyexception.S
@@ -50,7 +50,7 @@
   * nested interrupt, the interrupt stack if no privileged task has run.
   */

-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif

@@ -192,7 +192,7 @@ exception_common:
 	 * here prohibits nested interrupts without some additional logic!
 	 */

-	setintstack	r2, r3
+	setintstack	r2, r3				/* SP = IRQ stack top */

 #else
 	/* Otherwise, we will re-use the interrupted thread's stack.  That may
@@ -340,7 +340,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -195,7 +195,7 @@ static void up_dumpstate(void)
  uint32_t sp   = arm_getsp();
  uint32_t ustackbase;
  uint32_t ustacksize;
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
  uint32_t istackbase;
  uint32_t istacksize;
 #endif
@@ -214,11 +214,11 @@ static void up_dumpstate(void)

  _alert("Current sp: %08x\n", sp);

-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
  /* Get the limits on the interrupt stack memory */

  istackbase = (uint32_t)&g_intstackbase;
-  istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+  istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~7);

  /* Show interrupt stack info */

@@ -253,7 +253,7 @@ static void up_dumpstate(void)
    }
 #endif

-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
  /* Does the current stack pointer lie within the interrupt stack? */

  if (sp > istackbase - istacksize && sp < istackbase)
@@ -262,13 +262,6 @@ static void up_dumpstate(void)

      _alert("Interrupt Stack\n", sp);
      up_stackdump(sp, istackbase);
-
-      /* Extract the user stack pointer which should lie
-       * at the base of the interrupt stack.
-       */
-
-      sp = g_intstackbase;
-      _alert("User sp: %08x\n", sp);
    }
  else if (CURRENT_REGS)
    {
@@ -277,6 +270,17 @@ static void up_dumpstate(void)
    }
 #endif

+  /* Extract the user stack pointer if we are in an interrupt handler.
+   * If we are not in an interrupt handler.  Then sp is the user stack
+   * pointer (and the above range check should have failed).
+   */
+
+  if (CURRENT_REGS)
+    {
+      sp = CURRENT_REGS[REG_R13];
+      _alert("User sp: %08x\n", sp);
+    }
+
  /* Dump the user stack if the stack pointer lies within the allocated user
   * stack memory.
   */
--- a/arch/arm/src/armv7-r/arm_vectors.S
+++ b/arch/arm/src/armv7-r/arm_vectors.S
@@ -179,9 +179,9 @@ arm_vectorirq:
 	mov		fp, #0					/* Init frame pointer */
 	mov		r0, sp					/* Get r0=xcp */

-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 	ldr		sp, .Lirqstackbase		/* SP = interrupt stack base */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodeirq			/* Call the handler */
@@ -232,7 +232,7 @@ arm_vectorirq:

 .Lirqtmp:
 	.word	g_irqtmp
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 .Lirqstackbase:
 	.word	g_intstackbase
 #endif
@@ -890,9 +890,9 @@ arm_vectorfiq:
 	mov		fp, #0					/* Init frame pointer */
 	mov		r0, sp					/* Get r0=xcp */

-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 	ldr		sp, .Lfiqstackbase		/* SP = interrupt stack base */
-	str		r0, [sp]				/* Save the user stack pointer */
+	str		r0, [sp, #-4]!			/* Save the xcp address at SP-4 then update SP */
 	mov		r4, sp					/* Save the SP in a preserved register */
 	bic		sp, sp, #7				/* Force 8-byte alignment */
 	bl		arm_decodefiq			/* Call the handler */
@@ -943,7 +943,7 @@ arm_vectorfiq:

 .Lfiqtmp:
 	.word	g_fiqtmp
-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 .Lfiqstackbase:
 	.word	g_intstackbase
 #endif
@@ -957,9 +957,9 @@ arm_vectorfiq:
 *  Name: g_intstackalloc/g_intstackbase
 ************************************************************************************/

-#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
 	.bss
-	.align	4
+	.balign	8

 	.globl	g_intstackalloc
 	.type	g_intstackalloc, object
@@ -967,11 +967,11 @@ arm_vectorfiq:
 	.type	g_intstackbase, object

 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4
-	.size	g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+	.size	g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~7)

-#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */
+#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
 	.end
--- a/arch/arm/src/armv8-m/arm_assert.c
+++ b/arch/arm/src/armv8-m/arm_assert.c
@@ -244,7 +244,7 @@ static void up_dumpstate(void)
   * stack?
   */

-  if (sp <= istackbase && sp > istackbase - istacksize)
+  if (sp < istackbase && sp > istackbase - istacksize)
    {
      /* Yes.. dump the interrupt stack */

--- a/arch/arm/src/armv8-m/arm_exception.S
+++ b/arch/arm/src/armv8-m/arm_exception.S
@@ -67,7 +67,7 @@
   * no privileged task has run.
   */

-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif

@@ -355,7 +355,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
--- a/arch/arm/src/armv8-m/arm_lazyexception.S
+++ b/arch/arm/src/armv8-m/arm_lazyexception.S
@@ -50,7 +50,7 @@
   * nested interrupt, the interrupt stack if no privileged task has run.
   */

-#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
+#  if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 8
 #    error Interrupt stack must be used with high priority interrupts in kernel mode
 #  endif

@@ -373,7 +373,7 @@ exception_common:
 	.bss
 	.global	g_intstackalloc
 	.global	g_intstackbase
-	.align	8
+	.balign	8
 g_intstackalloc:
 	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
--- a/arch/arm/src/c5471/c5471_vectors.S
+++ b/arch/arm/src/c5471/c5471_vectors.S
@@ -162,7 +162,7 @@ arm_vectorirq:

 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	ldr	sp, .Lirqstackbase	/* SP = interrupt stack base */
-	str	r1, [sp]		/* Save the user stack pointer */
+	str	r1, [sp, #-4]!		/* Save the xcp address at SP-4 then update SP */
 	bl	arm_doirq		/* Call the handler */
 	ldr	sp, [sp]		/* Restore the user stack pointer */
 #else
@@ -471,13 +471,13 @@ arm_vectoraddrexcptn:

 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	.bss
-	.align	4
+	.balign	4
 	.global	g_intstackalloc
 	.global	g_intstackbase
 	.type	g_intstackalloc, object
 	.type	g_intstackbase, object
 g_intstackalloc:
-	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~3)
 g_intstackbase:
 	.skip	4
 	.size	g_intstackbase, 4
--- a/arch/arm/src/common/arm_checkstack.c
+++ b/arch/arm/src/common/arm_checkstack.c
@@ -55,17 +55,31 @@

 #ifdef CONFIG_STACK_COLORATION

+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* 32bit alignment macros */
+
+#define INT32_ALIGN_MASK    (3)
+#define INT32_ALIGN_DOWN(a) ((a) & ~INT32_ALIGN_MASK)
+#define INT32_ALIGN_UP(a)   (((a) + INT32_ALIGN_MASK) & ~INT32_ALIGN_MASK)
+
 /****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/

-static size_t do_stackcheck(uintptr_t alloc, size_t size);
+static size_t do_stackcheck(FAR void *stackbase, size_t nbytes);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/

 /****************************************************************************
 * Name: do_stackcheck
 *
 * Description:
- *   Determine (approximately) how much stack has been used be searching the
+ *   Determine (approximately) how much stack has been used by searching the
 *   stack memory for a high water mark.  That is, the deepest level of the
 *   stack that clobbered some recognizable marker in the stack memory.
 *
@@ -78,26 +92,26 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size);
 *
 ****************************************************************************/

-static size_t do_stackcheck(uintptr_t alloc, size_t size)
+static size_t do_stackcheck(FAR void *stackbase, size_t nbytes)
 {
-  FAR uintptr_t start;
-  FAR uintptr_t end;
+  uintptr_t start;
+  uintptr_t end;
  FAR uint32_t *ptr;
  size_t mark;

-  if (size == 0)
+  if (nbytes == 0)
    {
      return 0;
    }

-  /* Get aligned addresses of the top and bottom of the stack */
+  /* Take extra care that we do not check outside the stack boundaries */

-  start = alloc & ~3;
-  end   = (alloc + size + 3) & ~3;
+  start = INT32_ALIGN_UP((uintptr_t)stackbase);
+  end   = INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes);

  /* Get the adjusted size based on the top and bottom of the stack */

-  size  = end - start;
+  nbytes  = end - start;

  /* The ARM uses a push-down stack:  the stack grows toward lower addresses
   * in memory.  We need to start at the lowest address in the stack memory
@@ -105,7 +119,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
   * that does not have the magic value is the high water mark.
   */

-  for (ptr = (FAR uint32_t *)start, mark = (size >> 2);
+  for (ptr = (FAR uint32_t *)start, mark = (nbytes >> 2);
       *ptr == STACK_COLOR && mark > 0;
       ptr++, mark--);

@@ -126,7 +140,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
      int j;

      ptr = (FAR uint32_t *)start;
-      for (i = 0; i < size; i += 4 * 64)
+      for (i = 0; i < nbytes; i += 4 * 64)
        {
          for (j = 0; j < 64; j++)
            {
@@ -157,6 +171,39 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
 * Public Functions
 ****************************************************************************/

+/****************************************************************************
+ * Name: arm_stack_color
+ *
+ * Description:
+ *   Write a well know value into the stack
+ *
+ ****************************************************************************/
+
+void arm_stack_color(FAR void *stackbase, size_t nbytes)
+{
+  uintptr_t start;
+  uintptr_t end;
+  size_t nwords;
+  FAR uint32_t *ptr;
+
+  /* Take extra care that we do not write outside the stack boundaries */
+
+  start = INT32_ALIGN_UP((uintptr_t)stackbase);
+  end   = INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes);
+
+  /* Get the adjusted size based on the top and bottom of the stack */
+
+  nwords = (end - start) >> 2;
+  ptr  = (FAR uint32_t *)start;
+
+  /* Set the entire stack to the coloration value */
+
+  while (nwords-- > 0)
+    {
+      *ptr++ = STACK_COLOR;
+    }
+}
+
 /****************************************************************************
 * Name: up_check_stack and friends
 *
@@ -175,8 +222,8 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)

 size_t up_check_tcbstack(FAR struct tcb_s *tcb)
 {
-  return do_stackcheck((uintptr_t)tcb->adj_stack_ptr - tcb->adj_stack_size,
-      tcb->adj_stack_size);
+  return do_stackcheck((FAR void *)((uintptr_t)tcb->adj_stack_ptr -
+      tcb->adj_stack_size), tcb->adj_stack_size);
 }

 ssize_t up_check_tcbstack_remain(FAR struct tcb_s *tcb)
@@ -198,17 +245,17 @@ ssize_t up_check_stack_remain(void)
 size_t up_check_intstack(void)
 {
 #ifdef CONFIG_SMP
-  return do_stackcheck(arm_intstack_base(),
-                       (CONFIG_ARCH_INTERRUPTSTACK & ~3));
+  return do_stackcheck((FAR void *)arm_intstack_alloc(),
+                        INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK));
 #else
-  return do_stackcheck((uintptr_t)&g_intstackalloc,
-                       (CONFIG_ARCH_INTERRUPTSTACK & ~3));
+  return do_stackcheck((FAR void *)&g_intstackalloc,
+                        INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK));
 #endif
 }

 size_t up_check_intstack_remain(void)
 {
-  return (CONFIG_ARCH_INTERRUPTSTACK & ~3) - up_check_intstack();
+  return INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK) - up_check_intstack();
 }
 #endif

--- a/arch/arm/src/common/arm_createstack.c
+++ b/arch/arm/src/common/arm_createstack.c
@@ -58,6 +58,12 @@
 #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
 #define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)

+/* 32bit alignment macros */
+
+#define INT32_ALIGN_MASK    (3)
+#define INT32_ALIGN_DOWN(a) ((a) & ~INT32_ALIGN_MASK)
+#define INT32_ALIGN_UP(a)   (((a) + INT32_ALIGN_MASK) & ~INT32_ALIGN_MASK)
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@@ -103,10 +109,12 @@
 int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
 {
  size_t alloc_size;
+  size_t tls_size;

-  /* Add the size of the TLS information structure and align */
+  /* Add the size of the TLS information structure and align. */

-  alloc_size = STACK_ALIGN_UP(stack_size + sizeof(struct tls_info_s));
+  tls_size   = INT32_ALIGN_UP(sizeof(struct tls_info_s));
+  alloc_size = STACK_ALIGN_UP(stack_size + tls_size);

 #ifdef CONFIG_TLS_ALIGNED
  /* The allocated stack size must not exceed the maximum possible for the
@@ -117,10 +125,11 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
  if (alloc_size > TLS_MAXSTACK)
    {
      alloc_size = TLS_MAXSTACK;
-      stack_size = alloc_size - sizeof(struct tls_info_s);
    }
 #endif

+  stack_size = alloc_size - tls_size;
+
  /* Is there already a stack allocated of a different size? */

  if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size)
@@ -209,7 +218,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)

      /* Initialize the TLS data structure */

-      memset(tcb->stack_alloc_ptr, 0, sizeof(struct tls_info_s));
+      memset(tcb->stack_alloc_ptr, 0, tls_size);

 #ifdef CONFIG_STACK_COLORATION
      /* If stack debug is enabled, then fill the stack with a
@@ -227,29 +236,3 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)

  return ERROR;
 }
-
-/****************************************************************************
- * Name: arm_stack_color
- *
- * Description:
- *   Write a well know value into the stack
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STACK_COLORATION
-void arm_stack_color(FAR void *stackbase, size_t nbytes)
-{
-  /* Take extra care that we do not write outsize the stack boundaries */
-
-  uint32_t *stkptr = (uint32_t *)(((uintptr_t)stackbase + 3) & ~3);
-  uintptr_t stkend = (((uintptr_t)stackbase + nbytes) & ~3);
-  size_t    nwords = (stkend - (uintptr_t)stackbase) >> 2;
-
-  /* Set the entire stack to the coloration value */
-
-  while (nwords-- > 0)
-    {
-      *stkptr++ = STACK_COLOR;
-    }
-}
-#endif
--- a/arch/arm/src/common/arm_initialize.c
+++ b/arch/arm/src/common/arm_initialize.c
@@ -62,13 +62,17 @@
 static inline void up_color_intstack(void)
 {
 #ifdef CONFIG_SMP
-  uint32_t *ptr = (uint32_t *)arm_intstack_base();
+  uint32_t *ptr = (uint32_t *)arm_intstack_alloc();
 #else
  uint32_t *ptr = (uint32_t *)&g_intstackalloc;
 #endif
  ssize_t size;

+#ifdef CONFIG_SMP
+  for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~3) * CONFIG_SMP_NCPUS);
+#else
  for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+#endif
       size > 0;
       size -= sizeof(uint32_t))
    {
--- a/arch/arm/src/common/arm_interruptcontext.c
+++ b/arch/arm/src/common/arm_interruptcontext.c
@@ -60,12 +60,6 @@
 bool up_interrupt_context(void)
 {
 #ifdef CONFIG_SMP
-  /* REVISIT:  Currently up_irq_save() will not disable the Software
-   * Generated Interrupts (SGIs) for the case of ARMv7-A architecture using
-   * the GIC.  So this will not be sufficient in that case, at least not
-   * until we add support for the ICCMPR.
-   */
-
  irqstate_t flags = up_irq_save();
 #endif

--- a/arch/arm/src/common/arm_usestack.c
+++ b/arch/arm/src/common/arm_usestack.c
@@ -53,6 +53,12 @@
 #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
 #define STACK_ALIGN_UP(a)   (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)

+/* 32bit alignment macros */
+
+#define INT32_ALIGN_MASK    (3)
+#define INT32_ALIGN_DOWN(a) ((a) & ~INT32_ALIGN_MASK)
+#define INT32_ALIGN_UP(a)   (((a) + INT32_ALIGN_MASK) & ~INT32_ALIGN_MASK)
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@@ -87,12 +93,16 @@

 int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
 {
+  size_t tls_size;
+
 #ifdef CONFIG_TLS_ALIGNED
  /* Make certain that the user provided stack is properly aligned */

  DEBUGASSERT(((uintptr_t)stack & TLS_STACK_MASK) == 0);
 #endif

+  tls_size = INT32_ALIGN_UP(sizeof(struct tls_info_s));
+
  /* Is there already a stack allocated? */

  if (tcb->stack_alloc_ptr)
@@ -125,7 +135,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)

  /* Offset by tls_size */

-  stack = (FAR void *)((uintptr_t)stack + sizeof(struct tls_info_s));
+  stack = (FAR void *)((uintptr_t)stack + tls_size);

  /* Is there enough room for at least TLS ? */

@@ -138,7 +148,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)

  /* Initialize the TLS data structure */

-  memset(tcb->stack_alloc_ptr, 0, sizeof(struct tls_info_s));
+  memset(tcb->stack_alloc_ptr, 0, tls_size);

 #ifdef CONFIG_STACK_COLORATION
  /* If stack debug is enabled, then fill the stack with a
--- a/arch/arm/src/cxd56xx/chip.h
+++ b/arch/arm/src/cxd56xx/chip.h
@@ -42,6 +42,10 @@

 #include <nuttx/config.h>

+#ifndef __ASSEMBLY__
+#  include <nuttx/arch.h>
+#endif
+
 /* Include the chip capabilities file */

 #include <arch/cxd56xx/chip.h>
@@ -50,4 +54,35 @@

 #include "hardware/cxd5602_memorymap.h"

+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+#  include "cxd56_cpuindex.h"
+#  include "cxd56_irq.h"
+#endif
+
+/****************************************************************************
+ * Macro Definitions
+ ****************************************************************************/
+
+#ifdef __ASSEMBLY__
+
+/****************************************************************************
+ * Name: setintstack
+ *
+ * Description:
+ *   Set the current stack pointer to the  "top" the correct interrupt stack
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+  .macro  setintstack, tmp1, tmp2
+  ldr \tmp1, =CXD56_ADSP_PID
+  ldr \tmp1, [\tmp1, 0]
+  sub \tmp1, 2                   /* tmp1 = getreg32(CXD56_ADSP_PID) - 2 */
+  ldr \tmp2, =g_cpu_intstack_top
+  ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */
+  .endm
+#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
+
+#endif /* __ASSEMBLY__  */
 #endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_H */
--- a/arch/arm/src/cxd56xx/cxd56_cpuindex.c
+++ b/arch/arm/src/cxd56xx/cxd56_cpuindex.c
@@ -42,15 +42,10 @@
 #include <nuttx/arch.h>

 #include "arm_arch.h"
+#include "cxd56_cpuindex.h"

 #ifdef CONFIG_SMP

-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define CXD56_ADSP_PID 0x0e002040  /* APP_DSP Processor ID */
-
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
--- a/arch/arm/src/cxd56xx/cxd56_cpuindex.h
+++ b/arch/arm/src/cxd56xx/cxd56_cpuindex.h
@@ -0,0 +1,30 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_cpuindex.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CXD56_ADSP_PID 0x0e002040  /* APP_DSP Processor ID */
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CPUINDEX_H */
--- a/arch/arm/src/cxd56xx/cxd56_cpupause.c
+++ b/arch/arm/src/cxd56xx/cxd56_cpupause.c
@@ -210,6 +210,13 @@ bool up_cpu_pausereq(int cpu)

 int up_cpu_paused(int cpu)
 {
+  /* Fistly, check if this IPI is to enable/disable IRQ */
+
+  if (handle_irqreq(cpu))
+    {
+      return OK;
+    }
+
  FAR struct tcb_s *tcb = this_task();

  /* Update scheduler parameters */
@@ -283,13 +290,6 @@ int arm_pause_handler(int irq, void *c, FAR void *arg)

  putreg32(0, CXD56_CPU_P2_INT + (4 * cpu));

-  /* Check if this IPI is to enable/disable IRQ */
-
-  if (handle_irqreq(cpu))
-    {
-      return OK;
-    }
-
  /* Check for false alarms.  Such false could occur as a consequence of
   * some deadlock breaking logic that might have already serviced the SG2
   * interrupt by calling up_cpu_paused.
--- a/arch/arm/src/cxd56xx/cxd56_irq.c
+++ b/arch/arm/src/cxd56xx/cxd56_irq.c
@@ -72,6 +72,10 @@

 #define INTC_EN(n) (CXD56_INTC_BASE + 0x10 + (((n) >> 5) << 2))

+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+#  define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
+#endif
+
 /****************************************************************************
 * Public Data
 ****************************************************************************/
@@ -97,6 +101,36 @@ static volatile int8_t g_cpu_for_irq[CXD56_IRQ_NIRQS];
 extern void up_send_irqreq(int idx, int irq, int cpu);
 #endif

+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+/* In the SMP configuration, we will need custom interrupt stacks.
+ * These definitions provide the aligned stack allocations.
+ */
+
+static uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3];
+
+/* These definitions provide the "top" of the push-down stacks. */
+
+const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
+{
+  (uint32_t)g_intstack_alloc + INTSTACK_SIZE,
+#if CONFIG_SMP_NCPUS > 1
+  (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 2
+  (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 3
+  (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 4
+  (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE),
+#if CONFIG_SMP_NCPUS > 5
+  (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE),
+#endif /* CONFIG_SMP_NCPUS > 5 */
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+};
+#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 */
+
 /* This is the address of the  exception vector table (determined by the
 * linker script).
 */
@@ -604,3 +638,35 @@ int up_prioritize_irq(int irq, int priority)
  return OK;
 }
 #endif
+
+/****************************************************************************
+ * Name: arm_intstack_base
+ *
+ * Description:
+ *   Return a pointer to the "base" the correct interrupt stack allocation
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_base(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()];
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE;
+}
+#endif
--- a/arch/arm/src/cxd56xx/cxd56_irq.h
+++ b/arch/arm/src/cxd56xx/cxd56_irq.h
@@ -48,6 +48,12 @@
 * Pre-processor Definitions
 ****************************************************************************/

+/* The size of one interrupt stack.  This is the configured value aligned
+ * the 8-bytes as required by the ARM EABI.
+ */
+
+#define INTSTACK_SIZE  (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+
 /****************************************************************************
 * Public Types
 ****************************************************************************/
@@ -67,14 +73,15 @@ extern "C"
 #define EXTERN extern
 #endif

-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
 /****************************************************************************
 * Public Functions Prototypes
 ****************************************************************************/

+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+EXTERN uintptr_t arm_intstack_base(void);
+EXTERN uintptr_t arm_intstack_alloc(void);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
--- a/arch/arm/src/cxd56xx/cxd56_serial.c
+++ b/arch/arm/src/cxd56xx/cxd56_serial.c
@@ -778,8 +778,6 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)

          flags = spin_lock_irqsave();

-          cfsetispeed(termiosp, priv->baud);
-
          termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
                              ((priv->parity == 1) ? PARODD : 0) |
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
@@ -790,6 +788,8 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 #endif
                              ((priv->stopbits2) ? CSTOPB : 0);

+          cfsetispeed(termiosp, priv->baud);
+
          switch (priv->bits)
            {
              case 5:
--- a/arch/arm/src/efm32/efm32_serial.c
+++ b/arch/arm/src/efm32/efm32_serial.c
@@ -68,7 +68,9 @@
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
-/* Some sanity checks *******************************************************/
+
+/* Some sanity checks */
+
 /* Is there at least one UART enabled and configured as a RS-232 device? */

 #ifndef HAVE_UART_DEVICE
@@ -81,8 +83,9 @@

 #ifdef USE_SERIALDRIVER

-/* Which UART with be ttyS0/console and which tty1-4?  The console will always
- * be ttyS0.  If there is no console then will use the lowest numbered UART.
+/* Which UART with be ttyS0/console and which tty1-4?  The console will
+ * always be ttyS0.  If there is no console then will use the lowest
+ * numbered UART.
 */

 /* First pick the console and ttys0.  This could be any of USART0-2 or
@@ -240,7 +243,8 @@ struct efm32_usart_s
 * Private Function Prototypes
 ****************************************************************************/

-static inline uint32_t efm32_serialin(struct efm32_usart_s *priv, int offset);
+static inline uint32_t efm32_serialin(struct efm32_usart_s *priv,
+                                      int offset);
 static inline void efm32_serialout(struct efm32_usart_s *priv, int offset,
                                   uint32_t value);
 static inline void efm32_setuartint(struct efm32_usart_s *priv);
@@ -331,18 +335,18 @@ static struct efm32_usart_s g_usart0priv =

 static struct uart_dev_s g_usart0port =
 {
-  .recv      =
-  {
-    .size    = CONFIG_USART0_RXBUFSIZE,
-    .buffer  = g_usart0rxbuffer,
-  },
-  .xmit      =
-  {
-    .size    = CONFIG_USART0_TXBUFSIZE,
-    .buffer  = g_usart0txbuffer,
-   },
-  .ops       = &g_uart_ops,
-  .priv      = &g_usart0priv,
+  .recv        =
+    {
+      .size    = CONFIG_USART0_RXBUFSIZE,
+      .buffer  = g_usart0rxbuffer,
+    },
+  .xmit        =
+    {
+      .size    = CONFIG_USART0_TXBUFSIZE,
+      .buffer  = g_usart0txbuffer,
+    },
+  .ops         = &g_uart_ops,
+  .priv        = &g_usart0priv,
 };
 #endif

@@ -367,18 +371,18 @@ static struct efm32_usart_s g_usart1priv =

 static struct uart_dev_s g_usart1port =
 {
-  .recv      =
-  {
-    .size    = CONFIG_USART1_RXBUFSIZE,
-    .buffer  = g_usart1rxbuffer,
-  },
-  .xmit      =
-  {
-    .size    = CONFIG_USART1_TXBUFSIZE,
-    .buffer  = g_usart1txbuffer,
-   },
-  .ops       = &g_uart_ops,
-  .priv      = &g_usart1priv,
+  .recv        =
+    {
+      .size    = CONFIG_USART1_RXBUFSIZE,
+      .buffer  = g_usart1rxbuffer,
+    },
+  .xmit        =
+    {
+      .size    = CONFIG_USART1_TXBUFSIZE,
+      .buffer  = g_usart1txbuffer,
+    },
+  .ops         = &g_uart_ops,
+  .priv        = &g_usart1priv,
 };
 #endif

@@ -403,18 +407,18 @@ static struct efm32_usart_s g_usart2priv =

 static struct uart_dev_s g_usart2port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_USART2_RXBUFSIZE,
-    .buffer = g_usart2rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_USART2_TXBUFSIZE,
-    .buffer = g_usart2txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_usart2priv,
+  .recv       =
+    {
+      .size   = CONFIG_USART2_RXBUFSIZE,
+      .buffer = g_usart2rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_USART2_TXBUFSIZE,
+      .buffer = g_usart2txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_usart2priv,
 };
 #endif

@@ -439,18 +443,18 @@ static struct efm32_usart_s g_uart0priv =

 static struct uart_dev_s g_uart0port =
 {
-  .recv      =
-  {
-    .size    = CONFIG_UART0_RXBUFSIZE,
-    .buffer  = g_uart0rxbuffer,
-  },
-  .xmit      =
-  {
-    .size    = CONFIG_UART0_TXBUFSIZE,
-    .buffer  = g_uart0txbuffer,
-   },
-  .ops       = &g_uart_ops,
-  .priv      = &g_uart0priv,
+  .recv        =
+    {
+      .size    = CONFIG_UART0_RXBUFSIZE,
+      .buffer  = g_uart0rxbuffer,
+    },
+  .xmit        =
+    {
+      .size    = CONFIG_UART0_TXBUFSIZE,
+      .buffer  = g_uart0txbuffer,
+    },
+  .ops         = &g_uart_ops,
+  .priv        = &g_uart0priv,
 };
 #endif

@@ -475,18 +479,18 @@ static struct efm32_usart_s g_uart1priv =

 static struct uart_dev_s g_uart1port =
 {
-  .recv     =
-  {
-    .size   = CONFIG_UART1_RXBUFSIZE,
-    .buffer = g_uart1rxbuffer,
-  },
-  .xmit     =
-  {
-    .size   = CONFIG_UART1_TXBUFSIZE,
-    .buffer = g_uart1txbuffer,
-   },
-  .ops      = &g_uart_ops,
-  .priv     = &g_uart1priv,
+  .recv       =
+    {
+      .size   = CONFIG_UART1_RXBUFSIZE,
+      .buffer = g_uart1rxbuffer,
+    },
+  .xmit       =
+    {
+      .size   = CONFIG_UART1_TXBUFSIZE,
+      .buffer = g_uart1txbuffer,
+    },
+  .ops        = &g_uart_ops,
+  .priv       = &g_uart1priv,
 };
 #endif

@@ -530,7 +534,9 @@ static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien)
 {
  irqstate_t flags;

-  /* Re-enable/re-disable interrupts corresponding to the state of bits in ien */
+  /* Re-enable/re-disable interrupts corresponding to the state of bits in
+   * ien
+   */

  flags     = enter_critical_section();
  priv->ien = ien;
@@ -624,14 +630,15 @@ static void efm32_shutdown(struct uart_dev_s *dev)
 * Name: efm32_attach
 *
 * Description:
- *   Configure the UART to operation in interrupt driven mode.  This method is
- *   called when the serial port is opened.  Normally, this is just after the
+ *   Configure the UART to operation in interrupt driven mode.  This method
+ *   is called when the serial port is opened.  Normally, this is just after
 *   the setup() method is called, however, the serial console may operate in
 *   a non-interrupt driven mode during the boot phase.
 *
- *   RX and TX interrupts are not enabled when by the attach method (unless the
- *   hardware supports multiple levels of interrupt enabling).  The RX and TX
- *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX
+ *   and TX interrupts are not enabled until the txint() and rxint() methods
+ *   are called.
 *
 ****************************************************************************/

@@ -668,8 +675,8 @@ static int efm32_attach(struct uart_dev_s *dev)
 *
 * Description:
 *   Detach UART interrupts.  This method is called when the serial port is
- *   closed normally just before the shutdown method is called.  The exception
- *   is the serial console which is never shutdown.
+ *   closed normally just before the shutdown method is called.  The
+ *   exception is the serial console which is never shutdown.
 *
 ****************************************************************************/

@@ -839,8 +846,6 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
            break;
          }

-        cfsetispeed(termiosp, priv->config->baud);
-
        /* Note that since we only support 8/9 bit modes and
         * there is no way to report 9-bit mode, we always claim 8.
         */
@@ -848,6 +853,8 @@ static int efm32_ioctl(struct file *filep, int cmd, unsigned long arg)
        termiosp->c_cflag = CS8;

        /* TODO: PARENB, PARODD, CSTOPB, CCTS_IFLOW, CCTS_OFLOW */
+
+        cfsetispeed(termiosp, priv->config->baud);
      }
      break;

@@ -979,8 +986,8 @@ static void efm32_rxint(struct uart_dev_s *dev, bool enable)
  flags = enter_critical_section();
  if (enable)
    {
-      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
-       * timeout occurs).
+      /* Receive an interrupt when their is anything in the Rx data register
+       * (or an RX timeout occurs).
       */

 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -1011,7 +1018,8 @@ static bool efm32_rxavailable(struct uart_dev_s *dev)

  /* Return true if the receive data is available (RXDATAV). */

-  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & USART_STATUS_RXDATAV) != 0;
+  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & \
+          USART_STATUS_RXDATAV) != 0;
 }

 /****************************************************************************
@@ -1085,7 +1093,8 @@ static bool efm32_txready(struct uart_dev_s *dev)
   * buffer is half-full or empty.
   */

-  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & USART_STATUS_TXBL) != 0;
+  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & \
+          USART_STATUS_TXBL) != 0;
 }

 /****************************************************************************
@@ -1104,7 +1113,8 @@ static bool efm32_txempty(struct uart_dev_s *dev)
   * data is available in the transmit buffer.
   */

-  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & USART_STATUS_TXC) != 0;
+  return (efm32_serialin(priv, EFM32_USART_STATUS_OFFSET) & \
+          USART_STATUS_TXC) != 0;
 }

 /****************************************************************************
@@ -1118,8 +1128,8 @@ static bool efm32_txempty(struct uart_dev_s *dev)
 *   Performs the low level UART initialization early in debug so that the
 *   serial console will be available during bootup.  This must be called
 *   before arm_serialinit.  NOTE:  This function depends on GPIO pin
- *   configuration performed in efm32_consoleinit() and main clock iniialization
- *   performed in efm32_clkinitialize().
+ *   configuration performed in efm32_consoleinit() and main clock
+ *   iniialization performed in efm32_clkinitialize().
 *
 ****************************************************************************/

--- a/arch/arm/src/imx6/Make.defs
+++ b/arch/arm/src/imx6/Make.defs
@@ -117,6 +117,10 @@ endif

 CMN_CSRCS += arm_cache.c

+ifeq ($(CONFIG_ARCH_L2CACHE),y)
+CMN_CSRCS += arm_l2cc_pl310.c
+endif
+
 ifeq ($(CONFIG_ARCH_FPU),y)
 CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
 CMN_CSRCS += arm_copyarmstate.c
--- a/arch/arm/src/imx6/chip.h
+++ b/arch/arm/src/imx6/chip.h
@@ -61,22 +61,11 @@

 #define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION

-/****************************************************************************
- * Public Types
- ****************************************************************************/
+/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it
+ * to provide the address of the L2CC-PL310 implementation.
+ */

-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.globl	g_irqstack_top
-	.globl	g_fiqstack_top
-#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
-
-#endif /* __ASSEMBLY__ */
+#define L2CC_VBASE IMX_PL310_VBASE

 /****************************************************************************
 * Macro Definitions
@@ -84,7 +73,7 @@

 #ifdef __ASSEMBLY__

-/***************************************************************************
+/****************************************************************************
 * Name: cpuindex
 *
 * Description:
@@ -93,30 +82,30 @@
 ****************************************************************************/

 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	cpuindex, index
-	mrc		p15, 0, \index, c0, c0, 5	/* Read the MPIDR */
-	and		\index, \index, #3			/* Bits 0-1=CPU ID */
-	.endm
+  .macro  cpuindex, index
+  mrc  p15, 0, \index, c0, c0, 5  /* Read the MPIDR */
+  and  \index, \index, #3         /* Bits 0-1=CPU ID */
+  .endm
 #endif

-/***************************************************************************
+/****************************************************************************
 * Name: setirqstack
 *
 * Description:
 *   Set the current stack pointer to the  -"top" of the IRQ interrupt
 *   stack for the current CPU.
 *
- ***************************************************************************/
+ ****************************************************************************/

 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	setirqstack, tmp1, tmp2
-	mrc		p15, 0, \tmp1, c0, c0, 5	/* tmp1=MPIDR */
-	and		\tmp1, \tmp1, #3			/* Bits 0-1=CPU ID */
-	ldr		\tmp2, =g_irqstack_top		/* tmp2=Array of IRQ stack pointers */
-	lsls	\tmp1, \tmp1, #2			/* tmp1=Array byte offset */
-	add		\tmp2, \tmp2, \tmp1			/* tmp2=Offset address into array */
-	ldr		sp, [\tmp2, #0]				/* sp=Address in stack allocation */
-	.endm
+  .macro  setirqstack, tmp1, tmp2
+  mrc  p15, 0, \tmp1, c0, c0, 5  /* tmp1=MPIDR */
+  and  \tmp1, \tmp1, #3          /* Bits 0-1=CPU ID */
+  ldr  \tmp2, =g_irqstack_top    /* tmp2=Array of IRQ stack pointers */
+  lsls \tmp1, \tmp1, #2          /* tmp1=Array byte offset */
+  add  \tmp2, \tmp2, \tmp1       /* tmp2=Offset address into array */
+  ldr  sp, [\tmp2, #0]           /* sp=Address in stack allocation */
+  .endm
 #endif

 /****************************************************************************
@@ -129,67 +118,16 @@
 ****************************************************************************/

 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	setfiqstack, tmp1, tmp2
-	mrc		p15, 0, \tmp1, c0, c0, 5	/* tmp1=MPIDR */
-	and		\tmp1, \tmp1, #3			/* Bits 0-1=CPU ID */
-	ldr		\tmp2, =g_fiqstack_top		/* tmp2=Array of FIQ stack pointers */
-	lsls	\tmp1, \tmp1, #2			/* tmp1=Array byte offset */
-	add		\tmp2, \tmp2, \tmp1			/* tmp2=Offset address into array */
-	ldr		sp, [\tmp2, #0]				/* sp=Address in stack allocation */
-	.endm
+  .macro  setfiqstack, tmp1, tmp2
+  mrc  p15, 0, \tmp1, c0, c0, 5  /* tmp1=MPIDR */
+  and  \tmp1, \tmp1, #3          /* Bits 0-1=CPU ID */
+  ldr  \tmp2, =g_fiqstack_top    /* tmp2=Array of FIQ stack pointers */
+  lsls \tmp1, \tmp1, #2          /* tmp1=Array byte offset */
+  add  \tmp2, \tmp2, \tmp1       /* tmp2=Offset address into array */
+  ldr  sp, [\tmp2, #0]           /* sp=Address in stack allocation */
+  .endm
 #endif

 #endif /* __ASSEMBLY__ */

-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Name: arm_intstack_base
- *
- * Description:
- *   Return a pointer to the "base" the correct interrupt stack allocation
- *   for the  current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_base(void)
-{
-  uintptr_t base = (uintptr_t)g_irqstack_alloc;
-#if CONFIG_SMP_NCPUS > 1
-  uint32_t cpu = up_cpu_index();
-
-  base += cpu * INTSTACK_SIZE;
-#endif
-
-  return base;
-}
-#endif
-
-/****************************************************************************
- * Name: arm_intstack_top
- *
- * Description:
- *   Return a pointer to the "top" the correct interrupt stack for the
- *   current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_top(void)
-{
-  return arm_intstack_base() + INTSTACK_SIZE;
-}
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */
--- a/arch/arm/src/imx6/imx_irq.c
+++ b/arch/arm/src/imx6/imx_irq.c
@@ -90,13 +90,13 @@ uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS] =
 {
  (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE,
 #if CONFIG_SMP_NCPUS > 1
-  (uintptr_t)g_irqstack_alloc + 2 * INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + (2 * INTSTACK_SIZE),
 #endif
 #if CONFIG_SMP_NCPUS > 2
-  (uintptr_t)g_irqstack_alloc + 3 * INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + (3 * INTSTACK_SIZE),
 #endif
 #if CONFIG_SMP_NCPUS > 3
-  (uintptr_t)g_irqstack_alloc + 4 * INTSTACK_SIZE
+  (uintptr_t)g_irqstack_alloc + (4 * INTSTACK_SIZE)
 #endif
 };

@@ -186,3 +186,35 @@ void up_irqinitialize(void)
  up_irq_enable();
 #endif
 }
+
+/****************************************************************************
+ * Name: arm_intstack_base
+ *
+ * Description:
+ *   Return a pointer to the "base" the correct interrupt stack allocation
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_base(void)
+{
+  return g_irqstack_top[up_cpu_index()];
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_irqstack_top[up_cpu_index()] - INTSTACK_SIZE;
+}
+#endif
--- a/Show More
+++ b/Show More