Commit Graph

17583 Commits

Author SHA1 Message Date
Masayuki Ishikawa dc9223f4cf arch: rp2040: Fix the initial stack pointer
Summary:
- The NuttX for raspberrypi-pico boots via the boot_stage2 provided
  by the pico-sdk which sets the MSP at the end of the SRAM.
- However, the NuttX expects the MSP is set to the top of the idle stack.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with nsh, nshsram and smp configrations
2021-04-25 03:19:24 -05:00
Sara Souza 5c562c1068 risc-v/esp32-c3: Reorganize the timer logic for wireless use 2021-04-22 21:38:16 -05:00
Sara Souza 0c440cfdfe xtensa/esp32: Reorganize the timer logic for wireless use 2021-04-22 21:38:16 -05:00
Dong Heng fecdd27df3 esp32 & esp32c3: Update Wi-Fi BT and Wi-Fi libraries to fix some issues 2021-04-22 07:34:06 -03:00
Sara Souza 7a80cbf93f risc-v/esp32-c3: Adds oneshot timer driver. 2021-04-22 09:13:58 +01:00
Sara Souza f696364b6a xtensa/esp32: Adds freerun wrapper 2021-04-21 16:37:39 -03:00
Masayuki Ishikawa 1b00e5d518 spinlock: Remove SP_SECTION
Summary:
- SP_SECTION was introduced to allocate spinlock in non-cachable
  region mainly for Cortex-A to stabilize the NuttX SMP kernel
- However, all spinlocks are now allocated in cachable area and
  works without any problems
- So SP_SECTION should be removed to simplify the kernel code

Impact:
- None

Testing:
- Build test only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-04-20 22:41:44 -05:00
Masayuki Ishikawa 1a9e7efde5 smp: Remove CONFIG_SMP_IDLETHREAD_STACKSIZE
Summary:
- The CONFIG_SMP_IDLETHREAD_STACKSIZE was introduced to optimize
  the idle stack size for other than CPU0
- However, there are no big differences between the idle stacks.
- This commit removes the config to simplify the kernel code

Impact:
- All SMP configurations

Testing:
- Tested with ostest with the following configs
- spresense:smp, spresense:rndis_smp
- esp32-devkitc:smp (QEMU), maix-bit:smp (QEMU)
- sabre-6quad:smp (QEMU), sabre-6quad:netnsh_smp (QEMU)
- raspberrypi-pico:smp, sim:smp (x86_64)

Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
2021-04-19 21:46:39 -05:00
Anthony Merlino 14db894caf stm32h7: Allow selection of SDMMC clock source. 2021-04-19 08:57:49 -07:00
Abdelatif Guettouche c1b0ee436c arch/xtensa/src/esp32/Kconfig: Make bank switching default to disabled.
This config is only useful when there is a > 4MB PSRAM and thus needs to
be selected by the user explicitly.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-04-19 07:48:35 -05:00
YAMAMOTO Takashi 7f307f9765 sim: Restore stack alignemnt
Reapply the following commit [1], which has been reverted by
the recent change [2] with no obvious reasons.

Also, add a comment block to explain the calculation.

[1]
```
commit 298c2e5e4f
Author: YAMAMOTO Takashi <yamamoto@midokura.com>
Date:   Wed Jan 29 03:26:43 2020 +0900

    sim: Fix stack alignment

    The recent x86-64 convention requires 16-byte alignment before
    (not after) calling a function.

    This fixes snprintf crash I observed on macOS while saving XMM registers.
```

[2]
```
commit 2335b69120
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Mon Apr 12 23:44:08 2021 +0800

    arch: Allocate the space from the beginning in up_stack_frame

    arch: Allocate the space from the beginning in up_stack_frame

    and modify the affected portion:
    1.Correct the stack dump and check
    2.Allocate tls_info_s by up_stack_frame too
    3.Move the stack fork allocation from arch to sched

    Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
```
2021-04-19 01:29:38 -05:00
Masayuki Ishikawa 64f46b7f7e arch: k210: Add coloration for the idle stacks
Summary:
- This commit adds coloration for the idle stacks

Impact:
- k210 only

Testing:
- Tested with smp and nsh configs with QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-04-19 01:09:22 -05:00
Masayuki Ishikawa 44bc681daa arch: fe310: Add coloration for the idle stack
Summary:
- This commit adds coloration for the idle stack
- Also, apply la pseudo-instruction instead of lui and addi

Impact:
- fe310 only

Testing:
- Tested with nsh with QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-04-19 01:05:40 -05:00
Yuichi Nakamura 048802bcd2 arm/rp2040: Add RP2040 I2S driver 2021-04-19 09:39:51 +09:00
Yuichi Nakamura 41b193e07f arm/rp2040: Add RP2040 PIO APIs 2021-04-19 09:39:51 +09:00
David Sidrane c801de4201 stm32h7:Serial Add RX and TX DMA
stm32h7:Serial Use Idel to poll RX DMA

stm32h7:Serial Do not loop in an ISR!

stm32h7:Serial signal txdma completion with semaphore

stm32h7:Serial Apply formatting suggestions from code review

Co-authored-by: Mateusz Szafoni <raiden00pl@gmail.com>

stm32h7: Serail Add Power Managment (Untested)
2021-04-17 09:56:41 +02:00
Xiang Xiao 2335b69120 arch: Allocate the space from the beginning in up_stack_frame
arch: Allocate the space from the beginning in up_stack_frame

and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-16 12:41:41 +09:00
Xiang Xiao 8640d82ce0 arch: Rename g_intstackbase to g_intstacktop
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-16 12:41:41 +09:00
David Sidrane 3feb3a247d stm32:Serial DMA config USART{4578} -> UART{4578} 2021-04-15 21:26:32 -05:00
raiden00pl 82ce1de7cd stm32/stm32_foc: remove the debug message before the calibration start
For unknown reasons this message may interferre with the calibration
procedure and result in invalid calibariton data.
We leave only a message informing about the end of the the calibration.
The problem was observed for STM32G4 + IHM16M1.
2021-04-15 06:37:15 -05:00
raiden00pl 13f62d15cc stm32/stm32_foc: do not enable PWM outputs that are not in use 2021-04-15 06:37:15 -05:00
YAMAMOTO Takashi 3806803a7a arch/xtensa/src/esp32/esp32_user.c: Implement L16SI emulation
I don't know why this was not necessary before.
Probably I was just lucky about the combination of configs.
Or maybe some of recent changes happened to make the compiler
to use the instruction.

```
400d38f0 <mm_givesemaphore>:
400d38f0:       004136          entry   a1, 32
400d38f3:       228c            beqz.n  a2, 400d38f9 <mm_givesemaphore+0x9>
400d38f5:       0228            l32i.n  a2, a2, 0
400d38f7:       52cc            bnez.n  a2, 400d3900 <mm_givesemaphore+0x10>
400d38f9:       fea0b2          movi    a11, 254
400d38fc:       000306          j       400d390c <mm_givesemaphore+0x1c>
400d38ff:       00              .byte 00
400d3900:       019232          l16si   a3, a2, 2
400d3903:       feebe5          call8   400d27c0 <getpid>
400d3906:       0813a7          beq     a3, a10, 400d3912 <mm_givesemaphore+0x22>
400d3909:       05a1b2          movi    a11, 0x105
400d390c:       f241a1          l32r    a10, 400d0210 <_stext+0x1f0>
400d390f:       ff23e5          call8   400d2b4c <_assert>
400d3912:       1288            l32i.n  a8, a2, 4
400d3914:       0828a6          blti    a8, 2, 400d3920 <mm_givesemaphore+0x30>
400d3917:       880b            addi.n  a8, a8, -1
400d3919:       1289            s32i.n  a8, a2, 4
400d391b:       000606          j       400d3937 <mm_givesemaphore+0x47>
400d391e:       00              .byte 00
400d391f:       00              .byte 00
400d3920:       ffaf82          movi    a8, -1
400d3923:       015282          s16i    a8, a2, 2
400d3926:       00a082          movi    a8, 0
400d3929:       016282          s32i    a8, a2, 4
400d392c:       02ad            mov.n   a10, a2
400d392e:       feb125          call8   400d2440 <sem_post>
400d3931:       19a1b2          movi    a11, 0x119
400d3934:       fd4a96          bltz    a10, 400d390c <mm_givesemaphore+0x1c>
400d3937:       f01d            retw.n
400d3939:       000000          ill
```
2021-04-15 12:18:52 +01:00
YAMAMOTO Takashi a28de1d681 arch/xtensa/src/esp32/esp32_user.c: Fix S16I/L16LU emulation
I misunderstood how imm8 is used to calculate the address.
2021-04-15 12:18:52 +01:00
Anthony Merlino b1f637a6ea stm32h7: Don't automatically select HSI48 as it may depend on USBSEL.
Add preprocessor logic that can catch the condition where the board is selecting the HSI48 as the USBSEL source, but the HSI48 isn't enabled.
2021-04-15 02:00:37 -07:00
Anthony Merlino 4c8d70dd2e stm32h7: Initialize CSI and HSI48 clocks as needed based on enabled peripherals. 2021-04-15 02:00:37 -07:00
YAMAMOTO Takashi 51490bad55 modlib: Implement sh_addralign handling
I've seen a module with 16 bytes .rodata alignment for xmm operations.
It was getting SEGV on sim/Linux because of the alignment issue.
The same module binary seems working fine after applying this patch.

Also, tested on sim/macOS and esp32 on qemu,
using a module with an artificially large alignment. (64 bytes)
2021-04-14 21:17:07 -05:00
jturnsek 33b071ecb9 MIMXRT1064-EVK support 2021-04-14 14:57:26 -07:00
raiden00pl ad8c09d0a1 stm32: include support for TIMERS_V3 2021-04-14 10:53:50 -04:00
raiden00pl 7c11397469 stm32: add definitions for TIMERS_V3. All credit goes to Nathan Hartman (hartmannathan) 2021-04-14 10:53:50 -04:00
raiden00pl 6d69600905 stm32/Kconfig: move configuration common for G4 under STM32_STM32G4XXX option 2021-04-14 10:53:50 -04:00
Marco Krahl 8456f3615e drivers/1wire: Moves header and adjusts include paths
Moves header to 1wire include sub directory.
Moves over common crc definitions to new interface.

Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
2021-04-14 02:49:28 -05:00
raiden00pl beebb57445 stm32g4xx: add support for FOC 2021-04-13 14:38:28 -05:00
raiden00pl 835b129c94 stm32g4xx: add DBGMCU definitions 2021-04-13 14:38:28 -05:00
Anthony Merlino 9c8c2b0db2 Separate CLOCK_TIMEKEEPING and SCHED_TICKLESS. 2021-04-13 11:42:31 -05:00
raiden00pl c90a6bdf2b stm32/Kconfig: enable ADCx DMA support if DMAMUX enabled 2021-04-13 12:08:17 -03:00
raiden00pl bf04ef9a3c stm32g4: add support for DMA (DMAMUX) 2021-04-13 12:08:17 -03:00
raiden00pl fbb7e95ebf stm32g4xxxx_dmamux.h: rename defs to match other chips and add DMAMAP defs 2021-04-13 09:20:18 -05:00
raiden00pl a735252d78 stm32h7,stm32g0: fix typos in DMAMUX 2021-04-13 09:20:18 -05:00
raiden00pl 62001bff3b stm32g4xx: add support for PWM 2021-04-13 09:19:52 -05:00
raiden00pl 4c741bc9a5 stm32/Kconfig: G4 chips use TIMERS_V2 2021-04-13 09:19:52 -05:00
raiden00pl ff2ae3e894 stm32g4xx: add support for ADC 2021-04-13 09:29:09 -03:00
Alin Jerpelea 20d315abfe NuttX: Falker Atomacao Agrícola Ltda: update licenses to Apache
Falker Atomacao Agrícola Ltda has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-13 05:28:28 -05:00
Anthony Merlino 1a5a7a1b63 stm32h7: Allow OTGHS to use internal FS PHY 2021-04-12 23:21:34 -05:00
Jukka Laitinen 3f6bb76e01 arch/arm/src/stm32f7/stm32_allocateheap.c: Fix MPU alignments
Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
  allocation; use the previous calculation directly

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-04-12 23:20:18 -05:00
Jukka Laitinen ea36c2c7ea Remove MPU_RASR_S bit from stm32f7 MPU user mode intsram configration
For some reason, setting the "shareable" bit makes the SRAM not writable

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-04-12 23:20:18 -05:00
Xiang Xiao 3f9908f7d1 Remove the unnecessary math.h inclusion
or move from header file to source file since math.h doesn't always exist

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-12 22:58:23 -04:00
Anthony Merlino 2b46a0fdde stm32h7: Adds guards around stm32_iocompensation. 2021-04-12 15:08:52 -07:00
Anthony Merlino a45b8cc17c stm32h7: Add support for IO compensation. 2021-04-12 15:08:52 -07:00
jturnsek bbe875876d Modified FlexSPI driver 2021-04-12 17:22:14 -03:00
jturnsek 7453e76d98 FlexSPI NOR driver 2021-04-12 11:35:44 -03:00