reason:
In kernel mode, sighand_test() may failed.
because nxsig_unmask_pendingsignal may change tcb->xcp.regs,and we should update return value(regs).
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Fix a memory corruption & deadlocks while calling gran_free.
The function expects a GRAN_HANDLE as a paramter, not a pointer to it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
In up_addrenv_kmap_pages, the MMU_MT_NORMAL_FLAGS are needed for the MMU
mappings in order for the memory & caches to function normally
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
update sensors documentation:
- add info about different sensor frameworks in one place
- fix headers style for sensors_uorb.rst: headers
- fix long lines for sensors_uorb.rst so it's possible to read this file in terminal IDE
- add code sections for sensors_uorb.rst
Signed-off-by: raiden00pl <raiden00@railab.me>
This moves ARM_HAVE_NEON from QEMU ARM family level down to the
processor level as not all processors have it (e.g. Cortex R5).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
It was dis overed during debug of the ethernet driver that the EMAC base was incorrect. After examination, it was determined that ICACHE and DCACHE also had incorrect base addresses. This commit fixes the base addresses according to the reference manual.
Summary:
This commit removes the riscv_mhartid function and replaces all its
usages with up_cpu_index. The functionality is consolidated into
up_cpu_index which provides a more consistent API for getting the
current CPU/hart ID across different execution modes (machine/supervisor).
Impact:
- Removes riscv_mhartid.S and its references from build systems
- Updates all arch-specific code to use up_cpu_index instead
- Adds more detailed documentation for up_cpu_index behavior
- Changes the implementation of up_cpu_index to use percpu scratch
register in supervisor mode
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Separated CPU index functionality from CPU ID mapping configuration
- Moved CPU ID mapping functions to new riscv_cpuidmap.c file
- Made up_cpu_index() implementation dependent on ARCH_USE_S_MODE
- Updated build system to handle new file organization
Impact:
- Improves code organization by separating concerns between basic CPU index
functionality and advanced CPU ID mapping features
- Makes CPU index functionality available independently of CPU ID mapping
- Reduces conditional compilation complexity in header files
- Better aligns with RISC-V architecture modes (M-mode vs S-mode)
Testing:
GitHub CI and local testing
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This would fix readv/writev issues mentioned in
https://github.com/apache/nuttx/pull/12674.
(only for this specific driver though. with this approach,
we basically have to fix every single drivers and
filesystems.)
Lightly tested on the serial console, using micropython REPL
on toywasm with esp32s3-devkit:toywasm, which used to be
suffered by the readv issue.
* Make readv/writev implementations update struct uio
This can simplify partial result handling.
* change the error number on the overflow from EOVERFLOW to EINVAL
to match NetBSD
* add a commented out uio_offset field. I used "#if 0" here as
C comments can't nest.
* add a few helper functions
Note on uio_copyfrom/uio_copyto:
although i'm not quite happy with the "offset" functionality,
it's necessary to simplify the adaptation of some drivers like
drivers/serial/serial.c, which (ab)uses the user-supplied buffer
as a line-buffer.
arch/risc-v/src/common/riscv_addrenv.c:418:
{
...
database = resvbase + MM_PGALIGNUP(resvsize);
...
}
need use MM_PGALIGNUP(resvsize) inside of ARCH_DATA_RESERVE_SIZE
if not add MM_PGALIGNUP(resvsize), will mismatch address load .data
section
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Sumamry:
Adjust VIRT_FLASH_PSECTION from 0x00000000-0x08000000 -> 0x00600000-0x08000000
The above changes avoid the problem of directly restarting when the process accesses/executes at address 0x0 without causing assert
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
It will be used to distinguish between hardware KASan and software KASan. Hardware KASan does not need to use plug-in
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
