Commit Graph

4879 Commits

Author SHA1 Message Date
Filipe Cavalcanti
e57d2a5247 arch/risc-v: update lower-half drivers for ESP32-C3|C6|H2 2025-06-30 22:40:26 +08:00
Filipe Cavalcanti
187a386cc7 arch/xtensa: update lower-half drivers for ESP32|S2|S3 2025-06-30 22:40:26 +08:00
wangmingrong1
2d7e4f7e52 arch/arm64/fvp-v8r: enable Cmake
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-06-30 17:12:38 +08:00
michal matias
e0ba2efdca boards/risc-v/esp32c6: Add the NCV7410 10BASE-T1S MAC-PHY support for the ESP32-C6 boards
This commit adds NCV7410 10BASE-T1S SPI MAC-PHY support for
* esp32c6-devkitc
* esp32c6-devkitm

Signed-off-by: michal matias <mich4l.matias@gmail.com>
2025-06-29 09:11:46 -03:00
wangmingrong1
ecd6a1db1a ci/arm64: Enhance CI inspection
1. nsh_fiq: arm64 clang makefile
2. nsh_gicv2: arm64 clang cmake

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-06-27 20:44:41 +08:00
wangjianyu3
5079105e17 boards: net tcp backlog is enabled by default
The configuration NET_TCPBACKLOG is enabled by default.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-06-26 09:32:54 -03:00
simbit18
7c0bda7f9f boards: Fix Kconfig style
Remove spaces from Kconfig
Add TABs
2025-06-26 02:30:46 +08:00
halyssonJr
3ecdcf556e add lcd suport 2025-06-24 16:29:00 +08:00
Filipe Cavalcanti
02dae3e5eb boards/xtensa: add SDMMC SPI defconfig to ESP32|S2|S3 boards
Adds a defconfig for SDMMC over SPI to the following boards:
esp32-devkitc, esp32s2-saola-1 and esp32s3-devkit.

Renames the defconfig name for:
esp32-lyrat and esp32-wrover-kit.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-06-24 08:08:55 +08:00
Filipe Cavalcanti
aedce4c648 boards/xtensa/esp32: use common board source for SDMMC
Deletes board specific sdmmc implementation in favor of a common source and header file.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-06-24 08:08:55 +08:00
Filipe Cavalcanti
452292159b boards/xtensa: support SDMMC over SPI on ESP32-S2|S3
Adds support for SDMMC over SPI on ESP32S2 and ESP32S3.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-06-24 08:08:55 +08:00
halyssonJr
4193fe6e2b add support to a new board : esp32s3-8048s043. 2025-06-24 01:10:49 +08:00
kywwilson11
04c4f5d229 Initial commit for STM32G0 dma support. Added DMA mux mappings. Added Kconfig for enabling DMA2. Added basic defines for number of channels and mux channels in dma_v1mux.
Added subclasses of STM32G0 (such as STM32G07X) to Kconfig for use in dmamux driver. Added definitions to stm32g0_dmamux.h. Added configuration of number of dma and dmamux channels.

Added missing dma mappings for stm32g0.

Remove reserved defines.

Formatting fixes.

Added DMA2 IRQ mappings for STM32G0B and STM32G0C. Changed STM32_DMAMUX_BASE to STM32_DMAMUX1_BASE to align with stm32_dma_v1mux.c and C0 defines.

Provide correct mapping for ADC1_DMA_CHAN. Add STM32F0L0G0_HAVE_ADC1_DMA to STM32G0.

Add support for continuous mode to the ADC. Also added support to set smp1 and smp2 in board.h, as well as smpsel.

Removed unnecessary selects of STM32F0L0G0_STM32G0. Changed board level files to properly define A0-A3 on nucleo-g0b1re.

Add new Kconfig changes.

Made combined configs for STM32G0. Ex. STM32G0BX for STM32G0B0 and STM32G0B1.

Fixed defines and references in Kconfig and stm32_dma_v1mux.c

Defined adc_sampletime_write and adc_sampletime_set. Changed adc_sample_time_s structure to be much simpler. Old way made no sense. You can only have 2 sample times, so defining one for each channel makes no sense. The new adc_sample_time_s contains smp1, smp2, and smpsel. Also define ADC_HAVE_SMPR_SMP2 for STM32C0.

Added adc_sampletime_write and adc_sampletime_set. Altered adc_sample_time_s structure to be more appropriate for g0 and c0. Only two sample times can be defined. Added rcc support for DMA2.

Added defconfig for nucleo-g0b1re:adc_dma config.

Restore correct Kconfig from my original branch

Removed redundant ifdefs. If we select for G0 and C0, we know they have SMP2. Fixed formatting.

Formatting feedback. Aligned columns in irq and dma headers.
2025-06-23 15:46:28 +08:00
Tiago Medicci Serrano
14af1c6ef7 boards/risc-v/qemu-rv: Add missing section on ld-nuttsbi.script
Fix an issue regarding the `rv-virt:nsbi` defconfig, which wasn't
booting properly because `sbi_set_mtimecmp` failed to get the
mtimecmp's register address when evaluating `g_mtimecmp`. This
variable, which should be located at the `.noinit` section, wasn't
being set accordingly by the linker script, ending up on `bss
section which is zero-initialized, overwriting its value previously
set by `sbi_init_mtimer`.
2025-06-22 14:57:11 +08:00
wangjianyu3
1c7da08b94 boards/esp32s3-devkit: update config for fastboot
Initializing configuration for Fastboot TCP network device.

esp32s3-devkit:fastboot     : Fastboot TCP and USB transport enabled
esp32s3-devkit:fastboot_usb : Fastboot USB transport enabled only
esp32s3-devkit:fastboot_tcp : Fastboot TCP transport enabled only

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-06-21 04:21:29 +08:00
wangjianyu3
af36267762 boards/szpi-esp32s3: update config for fastboot
Initializing configuration for Fastboot TCP network device.

lckfb-szpi-esp32s3:fastboot     : Fastboot TCP and USB transport enabled
lckfb-szpi-esp32s3:fastboot_usb : Fastboot USB transport enabled only
lckfb-szpi-esp32s3:fastboot_tcp : Fastboot TCP transport enabled only

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-06-21 04:21:29 +08:00
wangjianyu3
bb1cc40159 arm64/qemu: add config for fastboot tcp
Initialize configuration for fastboot TCP network device.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-06-19 10:10:01 +08:00
Tyler Bennett
54b7bf6e36 ADC Hardware register file updated for G0
First commit of ADC for G0. Have it working basically. Need to make changes regarding adccmn stuff.

Added changes to make stm32_adc.c compatible with both G0 and other families.

Add oversampling support. This is for G0 and L0. Add ADC oversampling to Kconfig. Use adccmn_modifyreg for all, updated hw file to accomodate G0.

Style fixes. Move init of oversampling to a function, and call it if OVERSAMPLE is configured.

Limited changes to stm32_bringup.c

Style fixes to hardware/stm32_adc.h

Changed nucleo-g0b1re to run at 64 MHz. Fixed errors in clock setup. Added defines for setting up ADC clock.

Added code for STM32G0 ADC clock configuration.

Added adc_ckmode_cfg function. ckmode bits were previously neglected, assuming async clock to ADC was used. Added other feedback from pull request #16500.

Added feedback from pull request #16500.

Changed format of STM32F0L0G0_HAVE_ADC_OVERSAMPLE config.

Removed FARs from ioc_set_oversample.

Fixed formatting of helps in Kconfig. Adjusted spacing on help content.

Simplified adc_common_cfg. CCR_PRESC relies on board.h

Fixed formatting

Add ADC pinmaps for stm32g0
2025-06-17 21:25:39 +08:00
raiden00pl
b37e8ecf3c boards/nucleo-f446re: fix adc example
fix adc example for nucleo-f446re:

- the second ADC channel should be different from first channel
- enable ADC SCAN mode so we get convertion on CH0 and CH1
- disable software trigger from application, we use hardware triggering
from timer

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-06-14 10:44:37 -03:00
raiden00pl
64c7354853 boards/nucleo-c0{71rb|92rc}: add clock definition for timers
add clock definitions for TIMERS in nucleo-c071rb adn nucleo-c092rc

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-06-13 12:10:13 -03:00
Anthony Tran
e82d69533c riscv qemu-rv: fix kernel mapping by enabling CONFIG_MM_KMAP in knsh defconfig 2025-06-12 10:11:57 -03:00
dongjiuzhu1
3bc3092e6a fs/fs: remove unnecessary FS_REFCOUNT config
Previously, this config was added to ensure that the size of the struct
file remained unchanged, thereby preventing the Flash memory of
resource-constrained MCUs from being unnecessarily increased.

However, we have now refactored the relationship between struct fd and struct file,
reducing their memory footprint in both Flash and RAM.
Consequently, this config can be removed.

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2025-06-12 18:12:42 +08:00
robert
be8471625f Add BLE config to esp32-sparrow 2025-06-11 15:48:25 +08:00
raiden00pl
13fba11e9b boards/nucleo-c092rc: add FDCAN examples
add FDCAN examples for nucleo-c092rc based on
SocketCAN interface and CAN character driver interface.

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-06-09 15:26:12 -03:00
George Poulios
67c7a4018a arm64/imx9: Support & configure RGMII-ID on RTL8211F
For the RTL8211F PHY, configuration of RX/TXDLY was missing.
At least on my i.MX93 EVK, this is necessary for transmission
to work (RXDLY defaults to true on the PHY).

This commit brings support for RGMII internal delay configuration
(on or off for both directions) and enables it on the i.MX93 EVK
board. The introduced Kconfig is set to default to 'n', to avoid
breaking the functionality of other, out-of-tree boards based on
i.MX93, running the RTL8211F PHY, or to avoid introducing
unnecessary code on boards running other PHYs.

Configuration of internal delay on other PHYs is not
implemented, and results in a warning (but no error).

Signed-off-by: George Poulios <gpoulios@census-labs.com>
2025-06-05 08:58:24 +02:00
George Poulios
e382e2d525 arm64/imx9: Add missing ENET1 RGMII TXC pin muxing
MUX_ENET1_TXC was missing from both the EVK board
definition and the IO muxing configuration function
of the ENET1 driver. As a result, transmission does
not work (unless the muxing is set by default in some
board? -not the case with EVK). This commit adds the
configuration and adds the definition to i.MX93 EVK.

WARN: other, out-of-tree i.MX93 boards need to define
MUX_ENET1_TXC accordingly, otherwise build will break.

Signed-off-by: George Poulios <gpoulios@census-labs.com>
2025-06-05 08:58:24 +02:00
George Poulios
08f41244bc boards/imx93-evk: Tidy up board.h ENET1 section
i.MX93 EVK board.h had an unmatched #endif directive
accidentally matching the top-level header file guard.
It also had a dual definition of BOARD_ENET1_PHY_LIST
with the same values. None of these issues affect the
functionality, as they ended up (almost) with equivalent
end result.

Signed-off-by: George Poulios <gpoulios@census-labs.com>
2025-06-05 08:58:24 +02:00
Ville Juven
436c814c2e mcx-nxxx: Add LPI2C driver for mcx-nxxx architecture
This adds a LPI2C driver for the mcx-nxxx chip, and the necessary board
definitions for the frdm-mcxn236 evaluation kit.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-06-02 23:09:59 +08:00
Matteo Golin
ef04b4ccb6 boards/avr/atmega: Added Elegoo Mega2560r3 board support
Some checks failed
Build Documentation / build-html (push) Has been cancelled
Preliminary support for the Elegoo Mega2560r3 board by Elegoo with NSH
configuration.
2025-05-31 00:29:18 +08:00
Matteo Golin
40ec988502 arduino-mega2560: Fix incorrect RAM_START address
Fixes an incorrect RAM_START address, which should be 0x800200 for SRAM.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2025-05-29 16:24:06 -03:00
Matteo Golin
557c83cea3 avr/atmega: Resolve memory corruption preventing boot
Resolve memory corruption issue where the memory values to be loaded
from flash to sram at boot contained incorrect values. Also added a
KEEP() guard around `.vectors` to prevent debug stripping from removing
them, as suggested by KR.

Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
2025-05-29 16:24:06 -03:00
raiden00pl
0b3245f701 boards: unify Private Types banners
unify Private Types banners according to NuttX coding standard

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-28 10:17:15 +08:00
Kerogit
2c43595dfd boards/avr/avrdx/breadxavr: fix board LED constants
During initial development of AVR DA/DB support, the board LED code
and constants it uses were based on different AVR boards. The resulting
code therefore did not work for most indicated states.

This patch fixes LED status codes to match what the board LED code
expects. Tested by manually triggering reset_board function which
caused the board LED to blink (whereas it was not blinking before
the fix.)

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2025-05-27 20:46:22 +08:00
Aung Khant Maw
29c4c87e2c boards/xtensa: Add GC9A01 LCD support for esp32 boards
esp32 based boards will now be able to use GC9A01 LCD driver for LVGL.

- Enabling CONFIG_LCD_GC9A01 will now flip spi_cmddata pin
- Added esp32_gc9a01.c file.

Signed-off-by: Aung Khant Maw <aungkhantmaw64@gmail.com>
2025-05-26 22:01:22 +08:00
Vlad Pruteanu
82effd4b2f xtensa/esp32: Add support for hardware accelerated SHA
This enables the use of the cryptographic accelerator within
the ESP32. The support algorithms are: SHA1, SHA256, SHA384
and SHA512.

Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
2025-05-26 15:23:51 +08:00
raiden00pl
6a0a01a4e9 nrf5340-dk/rpmsghci_nimble_cpuapp: fix make build
fix make build for nrf5340-dk/rpmsghci_nimble_cpuapp

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-23 15:04:16 -03:00
raiden00pl
cbe0c0a825 boards/thingy53: add RPMSG HCI example with nimble
add RPMSG HCI example with nimble demo for thingy53 board

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-23 15:04:16 -03:00
Lars Kruse
3dc53adb28 arch | boards | drivers: fix whitespace issues for switch case statements 2025-05-23 10:48:41 +08:00
Lars Kruse
3ce85ca54e style: fix spelling in code comments and strings 2025-05-23 10:48:41 +08:00
Lwazi Dube
bb97e14101 boards/sama5d3-xplained: Add knsh configuration 2025-05-20 09:16:27 -03:00
Lwazi Dube
2a7174601f boards/sama5d3-xplained: Use common usb host waiter.
Delete the board-specific usb host waiters and use the common code.
2025-05-20 09:32:22 +02:00
Kerogit
8126a8119f arch/avr: reworked eliminating unused sections with GCC
After a mailing list suggestion, the indirection that enabled
ARCH_TOOLCHAIN_GCC only when user requested it is removed.

The indirection was a safety measure for chips and boards with linker
scripts that (possibly) do not handle keeping for example .vectors
section even if the linker considers it unreferenced.

Instead, all existing configurations now disable
CONFIG_DEBUG_OPT_UNUSED_SECTIONS to prevent the linker from removing
any code. (Preserving previous behaviour.) This can be removed again
at some point after making sure that corresponding linker script
only removes code that is truly unused.

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2025-05-19 22:29:58 +08:00
Kerogit
034d76f28f boards/avr/avrdx/breadxavr: fix dependency in Kconfig
Button input driver support depends on AVRDx GPIO ISR multiplexer
but the configuration option did not enforce it.

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2025-05-19 22:29:58 +08:00
Kerogit
6196327155 boards/avr/avrdx/breadxavr: replace board hello configuration with NSH
Unlike the Hello, world example, the NSH configuration can serve
as a starting point for testing other examples.

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2025-05-19 22:29:58 +08:00
Lwazi Dube
accfb3609b boards/sama5d3-xplained: Fix mmc card detection.
Use the pins specified in the SAMA5D3 Xplained User Guide.
Rename config macros from SAMA5D4EK to SAMA5D3XPLAINED.
Add SDMMC support to defconfig. Boot mount is disabled by default.
2025-05-18 00:56:46 +08:00
raiden00pl
fb901e3bda boards/thingy53: add BME688 sensor support
add BME688 sensor support to thingy53
2025-05-17 12:16:54 +08:00
Martin Vajnar
68b22fee3c Update defconfigs
Remove SENSORS and SENSORS_QENCODER as it is selected by ESP_PCNT_AS_QE.
2025-05-16 11:10:29 -03:00
Martin Vajnar
3e100e3c86 esp32[c6|h2|s2|s3]: Assign Edge/Level GPIO pin numbers when in Quadrature Encoder mode
Only 2 pins are needed in this mode for both channels. The wiring
is such that Edge and Level pins are cross-connected for both
channels.
2025-05-16 11:10:29 -03:00
Martin Vajnar
51a75e622f esp32[c6|h2|s3|s2]: Fix assignment of Edge/Level GPIO pins in PCNT 2025-05-16 11:10:29 -03:00
p-szafonimateusz
54510c5f94 boards/x86_64/qemu-intel64: add xHCI support to jumbo configs
add xHCI support for qemu-intel64 jumbo config

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2025-05-15 21:58:57 +08:00