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arch/xtensa: update lower-half drivers for ESP32|S2|S3

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This commit is contained in:
Filipe Cavalcanti
2025-06-13 16:13:34 -03:00
committed by Xiang Xiao
parent 0a71cbe542
commit 187a386cc7
59 changed files with 1574 additions and 2028 deletions
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arch/xtensa/src/common/espressif/Kconfig
+17 -1
View File
@@ -153,6 +153,15 @@ config ESPRESSIF_DEDICATED_GPIO_IRQ
---help---
Enable dedicated GPIO IRQ support
menu "Bootloader and Image Configuration"
config ESPRESSIF_BOOTLOADER_MCUBOOT
bool
---help---
Enables the Espressif port of MCUboot to be used as 2nd stage bootloader.
endmenu # Bootloader and Image Configuration
menu "Pulse Counter (PCNT) Configuration"
depends on ESP_PCNT
@@ -1031,12 +1040,19 @@ config ESPRESSIF_WIFI_STATION_SOFTAP
endchoice # ESP Wi-Fi mode
config ESP_WIFI_ENABLE_SAE_PK
config ESPRESSIF_WIFI_ENABLE_SAE_PK
bool "Enable SAE-PK"
default y
depends on ESP_WIFI_ENABLE_SAE_H2E
---help---
Select this option to enable SAE-PK
config ESPRESSIF_WIFI_ENABLE_SAE_H2E
bool "Enable SAE-H2E"
default y
---help---
Select this option to enable SAE-H2E
config ESP_WIFI_ENABLE_WPA3_OWE_STA
bool "Enable OWE STA"
default y
arch/xtensa/src/common/espressif/Wireless.mk
+22 -3
View File
@@ -52,21 +52,23 @@ endif
EXTRA_LIBS += -lphy
ifeq ($(CONFIG_ESPRESSIF_WIFI),y)
EXTRA_LIBS += -lcore -lnet80211 -lpp
EXTRA_LIBS += -lcore -lnet80211 -lpp -lespnow
endif
ifeq ($(CONFIG_WPA_WAPI_PSK),y)
EXTRA_LIBS += -lwapi
endif
ifeq ($(CONFIG_ESPRESSIF_WIFI),y)
## ESP-IDF's mbedTLS
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
### Define Espressif's configs for mbedTLS
@@ -138,10 +140,14 @@ CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
ifeq ($(CONFIG_ESP_WIFI_ENABLE_SAE_PK),y)
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
endif
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_H2E),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_H2E
endif
ifeq ($(CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_OWE_STA
endif
@@ -176,7 +182,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)
CHIP_CSRCS += dragonfly.c
CHIP_CSRCS += sae.c
CHIP_CSRCS += wpa_common.c
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y)
CHIP_CSRCS += sae_pk.c
endif
CHIP_CSRCS += bss.c
CHIP_CSRCS += scan.c
CHIP_CSRCS += ieee802_11_common.c
@@ -263,3 +271,14 @@ CHIP_CSRCS += crypto_mbedtls-rsa.c
CHIP_CSRCS += crypto_mbedtls.c
CHIP_CSRCS += tls_mbedtls.c
CHIP_CSRCS += aes-siv.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)regulatory$(DELIM)esp_wifi_regulatory.c
endif
# Linker scripts
ifeq ($(CONFIG_ARCH_CHIP_ESP32S3),y)
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.bt_funcs.ld
endif
arch/xtensa/src/common/espressif/esp_espnow_pktradio.c
+3 -3
View File
@@ -778,15 +778,15 @@ static void espnow_recv_cb(const esp_now_recv_info_t * esp_now_info,
* Callback after data is send over espnow, just cancel the watchdog.
*
* Input Parameters:
* mac_address - The mac address of the destination node,
* status - The send result
* tx_info - Sending information for ESPNOW data
* status - The send result
*
* Returned Value:
* None
*
****************************************************************************/
static void espnow_send_cb(const uint8_t *mac_address,
static void espnow_send_cb(const esp_now_send_info_t *tx_info,
esp_now_send_status_t status)
{
FAR struct espnow_driver_s *priv = &g_espnow;
arch/xtensa/src/common/espressif/esp_i2s.c
+20 -6
View File
@@ -298,12 +298,18 @@
cfg.sinc_scale = I2S_PDM_SIG_SCALING_MUL_1, \
cfg.line_mode = I2S_PDM_TX_ONE_LINE_CODEC, \
cfg.hp_en = true, \
cfg.hp_cut_off_freq_hz = 35.5, \
cfg.hp_cut_off_freq_hzx10 = 355, \
cfg.sd_dither = 0, \
cfg.sd_dither2 = 1 \
#endif /* CONFIG_ARCH_CHIP_ESP32S3 */
#if !SOC_RCC_IS_INDEPENDENT
# define I2S_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
# define I2S_RCC_ATOMIC()
#endif
#define MIN(x,y) ((x)<(y)?(x):(y))
/****************************************************************************
@@ -337,6 +343,7 @@ typedef enum
struct esp_i2s_config_s
{
uint32_t port; /* I2S port */
periph_module_t module; /* I2S peripheral module */
uint32_t role; /* I2S port role (master or slave) */
uint8_t data_width; /* I2S sample data width */
uint32_t rate; /* I2S sample-rate */
@@ -581,6 +588,7 @@ i2s_hal_clock_info_t clk_info_i2s0 =
static const struct esp_i2s_config_s esp_i2s0_config =
{
.port = 0,
.module = PERIPH_I2S0_MODULE,
#ifdef CONFIG_ESPRESSIF_I2S0_ROLE_MASTER
.role = I2S_ROLE_MASTER,
#else
@@ -654,6 +662,7 @@ i2s_hal_clock_info_t clk_info_i2s1 =
static const struct esp_i2s_config_s esp_i2s1_config =
{
.port = 1,
.module = PERIPH_I2S1_MODULE,
#ifdef CONFIG_ESPRESSIF_I2S1_ROLE_MASTER
.role = I2S_ROLE_MASTER,
#else
@@ -1575,10 +1584,13 @@ static void i2s_configure(struct esp_i2s_s *priv)
/* Set peripheral clock and clear reset */
periph_module_enable(i2s_periph_signal[priv->config->port].module);
periph_module_enable(priv->config->module);
i2s_hal_init(priv->config->ctx, priv->config->port);
i2s_ll_enable_clock(priv->config->ctx->dev);
I2S_RCC_ATOMIC()
{
i2s_ll_enable_core_clock(priv->config->ctx->dev, true);
}
/* Configure multiplexed pins as connected on the board */
@@ -1758,7 +1770,7 @@ static void i2s_configure(struct esp_i2s_s *priv)
#ifdef CONFIG_ARCH_CHIP_ESP32S3
else
{
i2s_ll_tx_enable_pdm(priv->config->ctx->dev);
i2s_ll_tx_enable_pdm(priv->config->ctx->dev, true);
I2S_PDM_TX_SLOT_DEFAULT_CONFIG(tx_slot_cfg.pdm_tx);
i2s_hal_pdm_set_tx_slot(priv->config->ctx,
priv->config->role == I2S_ROLE_SLAVE,
@@ -2054,13 +2066,15 @@ static void i2s_set_clock(struct esp_i2s_s *priv)
#ifdef I2S_HAVE_TX
i2s_hal_set_tx_clock(priv->config->ctx,
priv->config->clk_info,
priv->config->tx_clk_src);
priv->config->tx_clk_src,
NULL);
#endif /* I2S_HAVE_TX */
#ifdef I2S_HAVE_RX
i2s_hal_set_rx_clock(priv->config->ctx,
priv->config->clk_info,
priv->config->rx_clk_src);
priv->config->rx_clk_src,
NULL);
#endif /* I2S_HAVE_RX */
}
arch/xtensa/src/common/espressif/esp_loader.c
+2 -2
View File
@@ -285,7 +285,7 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
cache_read_enable(APP_CPU_NUM);
# endif
#else
cache_hal_disable(CACHE_TYPE_ALL);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
/* Clear the MMU entries that are already set up,
@@ -341,7 +341,7 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
#ifdef CONFIG_ARCH_CHIP_ESP32
cache_read_enable(0);
#else
cache_hal_enable(CACHE_TYPE_ALL);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#endif
return (int)rc;
}
arch/xtensa/src/common/espressif/esp_pcnt.c
+4 -4
View File
@@ -862,7 +862,7 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit(
return NULL;
}
if (config->low_limit >= 0 && config->low_limit < PCNT_LL_MIN_LIN)
if (config->low_limit >= 0 && config->low_limit < PCNT_LL_MIN_LIM)
{
cperr("Configuration low limit is out of range!\n");
return NULL;
@@ -878,8 +878,8 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit(
if (g_pcnt_refs++ == 0)
{
periph_module_enable(pcnt_periph_signals.groups[0].module);
periph_module_reset(pcnt_periph_signals.groups[0].module);
periph_module_enable(PERIPH_PCNT_MODULE);
periph_module_reset(PERIPH_PCNT_MODULE);
pcnt_hal_init(&ctx, 0);
}
@@ -1009,7 +1009,7 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev)
g_pcnt_refs--;
if (g_pcnt_refs == 0)
{
periph_module_disable(pcnt_periph_signals.groups[0].module);
periph_module_disable(PERIPH_PCNT_MODULE);
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
cpu,
arch/xtensa/src/common/espressif/esp_rmt.c
+2 -2
View File
@@ -455,8 +455,8 @@ static void rmt_module_enable(void)
if (g_rmtdev_common.rmt_module_enabled == false)
{
periph_module_reset(rmt_periph_signals.groups[0].module);
periph_module_enable(rmt_periph_signals.groups[0].module);
periph_module_reset(PERIPH_RMT_MODULE);
periph_module_enable(PERIPH_RMT_MODULE);
g_rmtdev_common.rmt_module_enabled = true;
}
arch/xtensa/src/common/espressif/esp_spiflash.c
+1 -1
View File
@@ -324,7 +324,7 @@ static IRAM_ATTR void esp_spi_trans(uint32_t command,
/* Start transmission */
spi_flash_ll_user_start(dev);
spi_flash_ll_user_start(dev, false);
/* Wait until transmission is done */
arch/xtensa/src/common/espressif/esp_temperature_sensor.c
+42 -8
View File
@@ -63,6 +63,7 @@
#include "hal/temperature_sensor_types.h"
#include "soc/temperature_sensor_periph.h"
#include "esp_efuse_rtc_calib.h"
#include "hal/adc_ll.h"
/****************************************************************************
* Pre-processor Definitions
@@ -70,6 +71,18 @@
#define ESP_TEMP_MIN_INTERVAL 30000
#if !SOC_RCC_IS_INDEPENDENT
# define TSENS_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
# define TSENS_RCC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
# define ADC_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
# define ADC_BUS_CLK_ATOMIC()
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@@ -364,8 +377,6 @@ static float temperature_sensor_parse_raw_value(uint32_t tsens_raw,
static void esp_temperature_sensor_enable(struct esp_temp_priv_s *priv)
{
temperature_sensor_ll_clk_enable(true);
temperature_sensor_ll_clk_sel(priv->clk_src);
temperature_sensor_ll_enable(true);
priv->tempstate = TEMP_SENSOR_ENABLE;
}
@@ -410,6 +421,7 @@ static void esp_temp_sensor_register(struct esp_temp_priv_s *priv)
register_driver(CONFIG_ESPRESSIF_TEMP_PATH, &g_esp_temp_sensor_fops,
0666, priv);
#else
priv->lower.type = SENSOR_TYPE_TEMPERATURE;
sensor_register(&priv->lower, CONFIG_ESPRESSIF_TEMP_PATH_DEVNO);
#endif /* CONFIG_ESPRESSIF_TEMP_UORB */
}
@@ -422,7 +434,7 @@ static void esp_temp_sensor_register(struct esp_temp_priv_s *priv)
*
* Input Parameters:
* priv - Pointer to the internal driver state structure.
* cfg - Configuration of measurement range for the temperature sensor
* cfg - Configuration of measurement range for the temperature sensor
*
* Returned Value:
* Returns OK on success; a negated errno value on failure
@@ -433,8 +445,28 @@ static int esp_temperature_sensor_install(struct esp_temp_priv_s *priv,
struct esp_temp_sensor_config_t cfg)
{
int ret;
periph_module_enable(priv->module);
periph_module_reset(priv->module);
regi2c_saradc_enable();
ADC_BUS_CLK_ATOMIC()
{
#if !SOC_TSENS_IS_INDEPENDENT_FROM_ADC
adc_ll_enable_bus_clock(true);
# if SOC_RCC_IS_INDEPENDENT
adc_ll_enable_func_clock(true);
# endif
adc_ll_reset_register();
#endif
}
TSENS_RCC_ATOMIC()
{
temperature_sensor_ll_bus_clk_enable(true);
temperature_sensor_ll_reset_module();
}
temperature_sensor_ll_enable(true);
temperature_sensor_ll_clk_sel(priv->clk_src);
ret = temperature_sensor_attribute_table_sort();
if (ret < 0)
@@ -452,7 +484,6 @@ static int esp_temperature_sensor_install(struct esp_temp_priv_s *priv,
goto err;
}
regi2c_saradc_enable();
temperature_sensor_ll_set_range(priv->tsens_attribute->reg_val);
esp_temperature_sensor_disable(priv); /* Disable the sensor by default */
@@ -481,8 +512,11 @@ err:
static void esp_temperature_sensor_uninstall(struct esp_temp_priv_s *priv)
{
regi2c_saradc_disable();
periph_module_disable(priv->module);
temperature_sensor_ll_enable(false);
TSENS_RCC_ATOMIC()
{
temperature_sensor_ll_bus_clk_enable(false);
}
}
/****************************************************************************
arch/xtensa/src/common/espressif/esp_wifi_utils.c
+581 -1
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_wifi_utils.h
+97 -5
View File
@@ -30,11 +30,12 @@
#include <nuttx/config.h>
#include <nuttx/net/netdev.h>
#include "esp_private/wifi.h"
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif /* __ASSEMBLY__ */
#include <stdint.h>
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
@@ -97,10 +98,101 @@ int esp_wifi_get_scan_results(struct iwreq *iwr);
void esp_wifi_scan_event_parse(void);
/****************************************************************************
* Name: esp_evt_work_cb
*
* Description:
* Process the cached event
*
* Input Parameters:
* arg - No mean
*
* Returned Value:
* None
*
****************************************************************************/
void esp_evt_work_cb(void *arg);
/****************************************************************************
* Name: esp_event_post
*
* Description:
* Active work queue and let the work to process the cached event
*
* Input Parameters:
* event_base - Event set name
* event_id - Event ID
* event_data - Event private data
* event_data_size - Event data size
* ticks - Waiting system ticks
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_event_post(const char *event_base,
int32_t event_id,
void *event_data,
size_t event_data_size,
uint32_t ticks);
/****************************************************************************
* Name: esp_init_event_queue
*
* Description:
* Initialize the Wi-Fi event queue that holds pending events to be
* processed. This queue is used to store Wi-Fi events like scan
* completion, station connect/disconnect etc. before they are handled by
* the event work callback.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp_init_event_queue(void);
/****************************************************************************
* Name: esp_wifi_lock
*
* Description:
* Lock or unlock the event process
*
* Input Parameters:
* lock - true: Lock event process, false: unlock event process
*
* Returned Value:
* The result of lock or unlock the event process
*
****************************************************************************/
int esp_wifi_lock(bool lock);
/****************************************************************************
* Name: esp_wifi_notify_subscribe
*
* Description:
* Enable event notification
*
* Input Parameters:
* pid - Task PID
* event - Signal event data pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_WIFI_UTILS_H */
arch/xtensa/src/common/espressif/esp_wireless.c
-150
View File
@@ -132,9 +132,6 @@ struct esp_wireless_priv_s
static inline void phy_digital_regs_store(void);
static inline void phy_digital_regs_load(void);
static int esp_swi_irq(int irq, void *context, void *arg);
# if defined(CONFIG_ARCH_CHIP_ESP32) && defined(CONFIG_ESPRESSIF_WIFI)
static void esp_wifi_set_log_level(void);
#endif
/****************************************************************************
* Extern Functions declaration
@@ -364,41 +361,6 @@ static int esp_swi_irq(int irq, void *context, void *arg)
return OK;
}
#ifdef CONFIG_ESPRESSIF_WIFI
/****************************************************************************
* Name: esp_wifi_set_log_level
*
* Description:
* Sets the log level for the ESP32 WiFi module based on preprocessor
* definitions. The log level can be verbose, warning, or error.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_wifi_set_log_level(void)
{
wifi_log_level_t wifi_log_level = WIFI_LOG_NONE;
/* set WiFi log level */
#if defined(CONFIG_DEBUG_WIRELESS_INFO)
wifi_log_level = WIFI_LOG_VERBOSE;
#elif defined(CONFIG_DEBUG_WIRELESS_WARN)
wifi_log_level = WIFI_LOG_WARNING;
#elif defined(CONFIG_LOG_MAXIMUM_LEVEL)
wifi_log_level = WIFI_LOG_ERROR;
#endif
esp_wifi_internal_set_log_level(wifi_log_level);
}
#endif /* CONFIG_ESPRESSIF_WIFI */
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -1482,115 +1444,3 @@ int esp_wireless_deinit(void)
return OK;
}
#ifdef CONFIG_ESPRESSIF_WIFI
/****************************************************************************
* Name: esp_wifi_init
*
* Description:
* Initialize Wi-Fi
*
* Input Parameters:
* config - Initialization config parameters
*
* Returned Value:
* 0 if success or others if fail
*
****************************************************************************/
int esp_wifi_init(const wifi_init_config_t *config)
{
int32_t ret;
#ifdef CONFIG_ARCH_CHIP_ESP32S3
uint32_t min_active_time_us =
CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME * 1000;
uint32_t keep_alive_time_us =
CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME * 1000 * 1000;
uint32_t wait_broadcast_data_time_us =
CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME * 1000;
esp_wifi_set_sleep_min_active_time(min_active_time_us);
esp_wifi_set_keep_alive_time(keep_alive_time_us);
esp_wifi_set_sleep_wait_broadcast_data_time(wait_broadcast_data_time_us);
#endif
#if defined(CONFIG_ESPRESSIF_WIFI_BT_COEXIST)
ret = coex_init();
if (ret)
{
wlerr("ERROR: Failed to initialize coex error=%ld\n", ret);
return ret;
}
#endif
/* WARN: Verify if power domain should go on before or after BT coexist */
esp_wifi_power_domain_on();
esp_wifi_set_log_level();
ret = esp_wifi_init_internal(config);
if (ret)
{
wlerr("Failed to initialize Wi-Fi error=%ld\n", ret);
return ret;
}
#if defined(CONFIG_MAC_BB_P) && defined(CONFIG_ARCH_CHIP_ESP32)
esp_mac_bb_pd_mem_init();
esp_wifi_internal_set_mac_sleep(true);
#endif
esp_phy_modem_init();
#ifdef CONFIG_ARCH_CHIP_ESP32
g_wifi_mac_time_update_cb = esp_wifi_internal_update_mac_time;
#endif
ret = esp_supplicant_init();
if (ret)
{
wlerr("Failed to initialize WPA supplicant error=%ld\n", ret);
esp_wifi_deinit_internal();
return ret;
}
return 0;
}
/****************************************************************************
* Name: esp_wifi_deinit
*
* Description:
* Deinitialize Wi-Fi and free resource
*
* Input Parameters:
* None
*
* Returned Value:
* 0 if success or others if fail
*
****************************************************************************/
int esp_wifi_deinit(void)
{
int ret;
ret = esp_supplicant_deinit();
if (ret)
{
wlerr("Failed to deinitialize supplicant\n");
return ret;
}
ret = esp_wifi_deinit_internal();
if (ret != 0)
{
wlerr("Failed to deinitialize Wi-Fi\n");
return ret;
}
return ret;
}
#endif /* CONFIG_ESPRESSIF_WIFI */
arch/xtensa/src/common/espressif/esp_wireless.h
+3
View File
@@ -44,6 +44,9 @@
#include "esp32s3_rt_timer.h"
#endif
#ifdef CONFIG_ESPRESSIF_WIFI
# include "os.h"
#endif
#include "esp_log.h"
#include "esp_mac.h"
#include "esp_private/phy.h"
arch/xtensa/src/common/espressif/esp_wlan.c
+36
View File
@@ -201,6 +201,42 @@ struct wlan_priv_s
spinlock_t lock;
};
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef ESPRESSIF_WLAN_HAS_STA
/* If reconnect automatically */
volatile bool g_sta_reconnect;
/* If Wi-Fi sta starts */
volatile bool g_sta_started;
/* If Wi-Fi sta connected */
volatile bool g_sta_connected;
/* Wi-Fi interface configuration */
wifi_config_t g_sta_wifi_cfg;
#endif /* ESPRESSIF_WLAN_HAS_STA */
#ifdef ESPRESSIF_WLAN_HAS_SOFTAP
/* If Wi-Fi SoftAP starts */
volatile bool g_softap_started;
/* Wi-Fi interface configuration */
wifi_config_t g_softap_wifi_cfg;
#endif /* ESPRESSIF_WLAN_HAS_SOFTAP */
/****************************************************************************
* Private Data
****************************************************************************/
arch/xtensa/src/common/espressif/esp_wlan.h
+47 -6
View File
@@ -56,14 +56,58 @@ extern "C"
* Pre-processor Definitions
****************************************************************************/
#
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ESPRESSIF_WIFI_STATION)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_SOFTAP)
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 1
# define ESPRESSIF_WLAN_DEVS 2
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef ESPRESSIF_WLAN_HAS_STA
/* If reconnect automatically */
extern volatile bool g_sta_reconnect;
/* If Wi-Fi sta starts */
extern volatile bool g_sta_started;
/* If Wi-Fi sta connected */
extern volatile bool g_sta_connected;
#endif /* ESPRESSIF_WLAN_HAS_STA */
#ifdef ESPRESSIF_WLAN_HAS_SOFTAP
/* If Wi-Fi SoftAP starts */
extern volatile bool g_softap_started;
#endif /* ESPRESSIF_WLAN_HAS_SOFTAP */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef ESPRESSIF_WLAN_HAS_STA
/****************************************************************************
* Name: esp_wlan_sta_set_linkstatus
*
@@ -97,7 +141,6 @@ int esp_wlan_sta_set_linkstatus(bool linkstatus);
****************************************************************************/
int esp_wlan_sta_initialize(void);
#endif /* ESPRESSIF_WLAN_HAS_STA */
/****************************************************************************
* Name: esp_wlan_softap_initialize
@@ -113,9 +156,7 @@ int esp_wlan_sta_initialize(void);
*
****************************************************************************/
#ifdef ESPRESSIF_WLAN_HAS_SOFTAP
int esp_wlan_softap_initialize(void);
#endif /* ESPRESSIF_WLAN_HAS_SOFTAP */
#endif /* CONFIG_ESPRESSIF_WIFI */
#ifdef __cplusplus
arch/xtensa/src/esp32/Bootloader.mk
+7
View File
@@ -73,6 +73,7 @@ ifeq ($(CONFIG_ESP32_SECURE_BOOT),y)
endif
$(Q) echo "Creating Bootloader configuration"
$(Q) { \
$(call cfg_en,NON_OS_BUILD) \
$(if $(CONFIG_ESP32_FLASH_2M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_2MB)) \
$(if $(CONFIG_ESP32_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \
$(if $(CONFIG_ESP32_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \
@@ -89,6 +90,7 @@ endif
} > $(BOOTLOADER_CONFIG)
ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
$(Q) { \
$(call cfg_en,CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) \
$(if $(CONFIG_ESP32_SECURE_BOOT),$(call cfg_en,CONFIG_SECURE_BOOT)$(call cfg_en,CONFIG_SECURE_BOOT_V2_ENABLED)$(call cfg_val,CONFIG_ESP_SIGN_KEY_FILE,$(abspath $(TOPDIR)/$(ESPSEC_KEYDIR)/$(subst ",,$(CONFIG_ESP32_SECURE_BOOT_APP_SIGNING_KEY))))) \
$(if $(CONFIG_ESP32_SECURE_SIGNED_APPS_SCHEME_RSA_2048),$(call cfg_en,CONFIG_ESP_USE_MBEDTLS)$(call cfg_en,CONFIG_ESP_SIGN_RSA)$(call cfg_val,CONFIG_ESP_SIGN_RSA_LEN,2048)) \
$(if $(CONFIG_ESP32_SECURE_SIGNED_APPS_SCHEME_RSA_3072),$(call cfg_en,CONFIG_ESP_USE_MBEDTLS)$(call cfg_en,CONFIG_ESP_SIGN_RSA)$(call cfg_val,CONFIG_ESP_SIGN_RSA_LEN,3072)) \
@@ -117,6 +119,11 @@ ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
$(call cfg_en,CONFIG_ESP_CONSOLE_UART) \
$(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,0)) \
$(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,1)) \
$(call cfg_en,CONFIG_LIBC_NEWLIB) \
$(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM,0)) \
$(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM,1)) \
$(call cfg_en,CONFIG_IDF_TARGET_ARCH_XTENSA) \
$(call cfg_val,CONFIG_BOOTLOADER_LOG_LEVEL,3) \
} >> $(BOOTLOADER_CONFIG)
else ifeq ($(CONFIG_ESP32_APP_FORMAT_LEGACY),y)
$(Q) { \
arch/xtensa/src/esp32/Kconfig
+1
View File
@@ -2761,6 +2761,7 @@ config ESP32_APP_FORMAT_LEGACY
config ESP32_APP_FORMAT_MCUBOOT
bool "Enable MCUboot-bootable format"
depends on !MCUBOOT_BOOTLOADER
select ESPRESSIF_BOOTLOADER_MCUBOOT
default n
select ESP32_HAVE_OTA_PARTITION
---help---
arch/xtensa/src/esp32/Make.defs
+3 -2
View File
@@ -228,7 +228,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 3f02f2139e79ddc60f98ca35ed65c62c6914f079
ESP_HAL_3RDPARTY_VERSION = e9a78c811578545e2bc673862d885a15bd6cbf67
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -278,12 +278,13 @@ include chip/hal.mk
include common/espressif/Make.defs
context:: chip/$(ESP_HAL_3RDPARTY_REPO)
ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y)
$(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..."
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32 components/esp_coex/lib
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard
$(Q) echo "Applying patches..."
$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y)
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32 components/esp_coex/lib
endif
distclean::
arch/xtensa/src/esp32/esp32_ble_adapter.c
+2 -2
View File
@@ -3262,7 +3262,7 @@ int esp32_bt_controller_disable(void)
}
/****************************************************************************
* Name: esp32_bt_controller_get_status
* Name: esp_bt_controller_get_status
*
* Description:
* Returns the status of the BT Controller
@@ -3275,7 +3275,7 @@ int esp32_bt_controller_disable(void)
*
****************************************************************************/
esp_bt_controller_status_t esp32_bt_controller_get_status(void)
esp_bt_controller_status_t esp_bt_controller_get_status(void)
{
return g_btdm_controller_status;
}
arch/xtensa/src/esp32/esp32_ble_adapter.h
+1 -1
View File
@@ -109,7 +109,7 @@ int esp32_bt_controller_disable(void);
*
****************************************************************************/
esp_bt_controller_status_t esp32_bt_controller_get_status(void);
esp_bt_controller_status_t esp_bt_controller_get_status(void);
/****************************************************************************
* Name: esp32_vhci_host_check_send_available
arch/xtensa/src/esp32/esp32_pm.c
+4 -4
View File
@@ -75,7 +75,7 @@
#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */
#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */
@@ -810,7 +810,7 @@ static void RTC_IRAM_ATTR esp32_wake_deep_sleep(void)
putreg32(getreg32(DPORT_PRO_CACHE_CTRL1_REG) &
(~DPORT_PRO_CACHE_MMU_IA_CLR), DPORT_PRO_CACHE_CTRL1_REG);
#if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
#if ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
/* ROM code has not started yet, so we need to set delay factor
* used by ets_delay_us first.
*/
@@ -821,7 +821,7 @@ static void RTC_IRAM_ATTR esp32_wake_deep_sleep(void)
* the flash chip some time to become ready.
*/
ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
ets_delay_us(ESP32_DEEP_SLEEP_WAKEUP_DELAY);
#endif
}
@@ -892,7 +892,7 @@ int esp32_light_sleep_start(uint64_t *sleep_time)
*/
flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
+ CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
+ ESP32_DEEP_SLEEP_WAKEUP_DELAY;
#ifndef CONFIG_ESP32_SPIRAM
vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
arch/xtensa/src/esp32/esp32_tickless.c
-1
View File
@@ -60,7 +60,6 @@
#include <arch/xtensa/core_macros.h>
#include <arch/board/board.h>
#include "xtensa_timer.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "xtensa_counter.h"
arch/xtensa/src/esp32/esp32_wifi_adapter.c
+64 -508
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_wifi_adapter.h
-56
View File
@@ -45,22 +45,6 @@ extern "C"
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ESPRESSIF_WIFI_STATION)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_SOFTAP)
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 1
# define ESPRESSIF_WLAN_DEVS 2
#endif
#define SSID_MAX_LEN (32)
#define PWD_MAX_LEN (64)
@@ -70,23 +54,6 @@ extern "C"
typedef int esp_err_t;
/* Wi-Fi event ID */
enum wifi_adpt_evt_e
{
WIFI_ADPT_EVT_SCAN_DONE = 0,
WIFI_ADPT_EVT_STA_START,
WIFI_ADPT_EVT_STA_CONNECT,
WIFI_ADPT_EVT_STA_DISCONNECT,
WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE,
WIFI_ADPT_EVT_STA_STOP,
WIFI_ADPT_EVT_AP_START,
WIFI_ADPT_EVT_AP_STOP,
WIFI_ADPT_EVT_AP_STACONNECTED,
WIFI_ADPT_EVT_AP_STADISCONNECTED,
WIFI_ADPT_EVT_MAX,
};
enum coex_log_level_e
{
COEX_LOG_NONE = 0,
@@ -143,25 +110,6 @@ int esp_wifi_adapter_init(void);
void esp_wifi_free_eb(void *eb);
/****************************************************************************
* Name: esp_wifi_notify_subscribe
*
* Description:
* Enable event notification
*
* Input Parameters:
* pid - Task PID
* event - Signal event data pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event);
#ifdef ESPRESSIF_WLAN_HAS_STA
/****************************************************************************
* Name: esp_wifi_sta_start
*
@@ -496,9 +444,6 @@ int esp_wifi_sta_country(struct iwreq *iwr, bool set);
****************************************************************************/
int esp_wifi_sta_rssi(struct iwreq *iwr, bool set);
#endif /* ESPRESSIF_WLAN_HAS_STA */
#ifdef ESPRESSIF_WLAN_HAS_SOFTAP
/****************************************************************************
* Name: esp_wifi_softap_start
@@ -834,7 +779,6 @@ int esp_wifi_softap_country(struct iwreq *iwr, bool set);
****************************************************************************/
int esp_wifi_softap_rssi(struct iwreq *iwr, bool set);
#endif /* ESPRESSIF_WLAN_HAS_SOFTAP */
/****************************************************************************
* Name: esp32_wifi_bt_coexist_init
arch/xtensa/src/esp32/hal.mk
+39 -8
View File
@@ -35,14 +35,20 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private
@@ -54,10 +60,15 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
@@ -65,14 +76,17 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
# Linker scripts
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libc-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-data.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-reent-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.syscalls.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
@@ -89,22 +103,29 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
@@ -129,9 +150,16 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)dport_access_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list$(DELIM)log_linked_list.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_lock.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
@@ -141,6 +169,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
@@ -152,6 +183,7 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c
@@ -160,10 +192,9 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c
arch/xtensa/src/esp32s2/Bootloader.mk
+8
View File
@@ -78,6 +78,8 @@ ifeq ($(CONFIG_ESP32S2_SECURE_BOOT),y)
endif
$(Q) echo "Creating Bootloader configuration"
$(Q) { \
$(call cfg_en,NON_OS_BUILD) \
$(call cfg_en,CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) \
$(if $(CONFIG_ESP32S2_FLASH_2M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_2MB)) \
$(if $(CONFIG_ESP32S2_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \
$(if $(CONFIG_ESP32S2_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \
@@ -113,11 +115,17 @@ endif
$(call cfg_val,CONFIG_ESP_APPLICATION_SIZE,$(CONFIG_ESPRESSIF_OTA_SLOT_SIZE)) \
$(call cfg_val,CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS,$(CONFIG_ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET)) \
$(call cfg_en,CONFIG_ESP_MCUBOOT_WDT_ENABLE) \
$(call cfg_en,CONFIG_LIBC_NEWLIB) \
$(call cfg_val,CONFIG_ESP_SCRATCH_OFFSET,$(CONFIG_ESPRESSIF_OTA_SCRATCH_OFFSET)) \
$(call cfg_val,CONFIG_ESP_SCRATCH_SIZE,$(CONFIG_ESPRESSIF_OTA_SCRATCH_SIZE)) \
$(call cfg_en,CONFIG_ESP_CONSOLE_UART) \
$(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,0)) \
$(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,1)) \
$(call cfg_en,CONFIG_LIBC_NEWLIB) \
$(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM,0)) \
$(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM,1)) \
$(call cfg_en,CONFIG_IDF_TARGET_ARCH_XTENSA) \
$(call cfg_val,CONFIG_BOOTLOADER_LOG_LEVEL,3) \
} >> $(BOOTLOADER_CONFIG)
endif
arch/xtensa/src/esp32s2/Kconfig
+1
View File
@@ -1371,6 +1371,7 @@ config ESPRESSIF_SIMPLE_BOOT
config ESP32S2_APP_FORMAT_MCUBOOT
bool "Enable MCUboot-bootable format"
depends on !MCUBOOT_BOOTLOADER
select ESPRESSIF_BOOTLOADER_MCUBOOT
default n
select ESPRESSIF_HAVE_OTA_PARTITION
---help---
arch/xtensa/src/esp32s2/Make.defs
+4 -3
View File
@@ -143,7 +143,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 3f02f2139e79ddc60f98ca35ed65c62c6914f079
ESP_HAL_3RDPARTY_VERSION = e9a78c811578545e2bc673862d885a15bd6cbf67
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -184,12 +184,13 @@ include common/espressif/Make.defs
include chip/Bootloader.mk
context:: chip/$(ESP_HAL_3RDPARTY_REPO)
ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y)
$(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..."
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard
$(Q) echo "Applying patches..."
$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y)
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/esp_phy/lib components/esp_wifi/lib
endif
distclean::
arch/xtensa/src/esp32s2/esp32s2_start.c
+1 -84
View File
@@ -52,6 +52,7 @@
#include "hal/cache_hal.h"
#include "hal/sar_ctrl_ll.h"
#include "rom/spi_flash.h"
#include "esp_private/cache_utils.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
@@ -100,34 +101,6 @@ extern uint8_t _image_drom_lma[];
extern uint8_t _image_drom_size[];
#endif
typedef enum
{
CACHE_MEMORY_INVALID = 0,
CACHE_MEMORY_ICACHE_LOW = 1 << 0,
CACHE_MEMORY_ICACHE_HIGH = 1 << 1,
CACHE_MEMORY_DCACHE_LOW = 1 << 2,
CACHE_MEMORY_DCACHE_HIGH = 1 << 3,
} cache_layout_t;
typedef enum
{
CACHE_SIZE_HALF = 0, /* 8KB for icache and dcache */
CACHE_SIZE_FULL = 1, /* 16KB for icache and dcache */
} cache_size_t;
typedef enum
{
CACHE_4WAYS_ASSOC = 0, /* 4 way associated cache */
CACHE_8WAYS_ASSOC = 1, /* 8 way associated cache */
} cache_ways_t;
typedef enum
{
CACHE_LINE_SIZE_16B = 0, /* 16 Byte cache line size */
CACHE_LINE_SIZE_32B = 1, /* 32 Byte cache line size */
CACHE_LINE_SIZE_64B = 2, /* 64 Byte cache line size */
} cache_line_size_t;
#define CACHE_SIZE_8KB CACHE_SIZE_HALF
#define CACHE_SIZE_16KB CACHE_SIZE_FULL
@@ -186,62 +159,6 @@ uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp_config_data_cache_mode
*
* Description:
* Configure the data cache mode to use with PSRAM.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
IRAM_ATTR void esp_config_data_cache_mode(void)
{
cache_size_t cache_size;
cache_ways_t cache_ways;
cache_line_size_t cache_line_size;
#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)
#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_16KB;
#endif
#else
#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
cache_size = CACHE_SIZE_16KB;
#endif
#endif
cache_ways = CACHE_4WAYS_ASSOC;
#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)
cache_line_size = CACHE_LINE_SIZE_16B;
#else
cache_line_size = CACHE_LINE_SIZE_32B;
#endif
merr("Data cache \t\t: size %dKB, %dWays, cache line size %dByte",
cache_size == CACHE_SIZE_8KB ? 8 : 16, 4,
cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
cache_set_dcache_mode(cache_size, cache_ways, cache_line_size);
cache_invalidate_dcache_all();
}
/****************************************************************************
* Name: configure_cpu_caches
*
arch/xtensa/src/esp32s2/esp32s2_touch.h
+2 -1
View File
@@ -28,8 +28,9 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/bits.h>
#include "esp32s2_touch_lowerhalf.h"
#include "hardware/esp32s2_touch.h"
/****************************************************************************
* Pre-processor Definitions
arch/xtensa/src/esp32s2/esp32s2_twai.c
+1
View File
@@ -47,6 +47,7 @@
#include "hardware/esp32s2_system.h"
#include "hardware/esp32s2_gpio_sigmap.h"
#include "hardware/esp32s2_twai.h"
#if defined(CONFIG_ESP32S2_TWAI)
arch/xtensa/src/esp32s2/esp32s2_twai.h
-1
View File
@@ -27,7 +27,6 @@
#include <nuttx/config.h>
#include <nuttx/can/can.h>
#include "hardware/esp32s2_twai.h"
/****************************************************************************
* Pre-processor Definitions
arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c
+65 -484
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.h
-56
View File
@@ -45,22 +45,6 @@ extern "C"
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ESPRESSIF_WIFI_STATION)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_SOFTAP)
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 1
# define ESPRESSIF_WLAN_DEVS 2
#endif
#define SSID_MAX_LEN (32)
#define PWD_MAX_LEN (64)
@@ -70,23 +54,6 @@ extern "C"
typedef int esp_err_t;
/* Wi-Fi event ID */
enum wifi_adpt_evt_e
{
WIFI_ADPT_EVT_SCAN_DONE = 0,
WIFI_ADPT_EVT_STA_START,
WIFI_ADPT_EVT_STA_CONNECT,
WIFI_ADPT_EVT_STA_DISCONNECT,
WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE,
WIFI_ADPT_EVT_STA_STOP,
WIFI_ADPT_EVT_AP_START,
WIFI_ADPT_EVT_AP_STOP,
WIFI_ADPT_EVT_AP_STACONNECTED,
WIFI_ADPT_EVT_AP_STADISCONNECTED,
WIFI_ADPT_EVT_MAX,
};
/* Wi-Fi event callback function */
typedef void (*wifi_evt_cb_t)(void *p);
@@ -131,25 +98,6 @@ int esp_wifi_adapter_init(void);
void esp_wifi_free_eb(void *eb);
/****************************************************************************
* Name: esp_wifi_notify_subscribe
*
* Description:
* Enable event notification
*
* Input Parameters:
* pid - Task PID
* event - Signal event data pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event);
#ifdef ESPRESSIF_WLAN_HAS_STA
/****************************************************************************
* Name: esp_wifi_sta_start
*
@@ -484,9 +432,6 @@ int esp_wifi_sta_country(struct iwreq *iwr, bool set);
****************************************************************************/
int esp_wifi_sta_rssi(struct iwreq *iwr, bool set);
#endif /* ESPRESSIF_WLAN_HAS_STA */
#ifdef ESPRESSIF_WLAN_HAS_SOFTAP
/****************************************************************************
* Name: esp_wifi_softap_start
@@ -822,7 +767,6 @@ int esp_wifi_softap_country(struct iwreq *iwr, bool set);
****************************************************************************/
int esp_wifi_softap_rssi(struct iwreq *iwr, bool set);
#endif /* ESPRESSIF_WLAN_HAS_SOFTAP */
/****************************************************************************
* Name: esp_wifi_stop_callback
arch/xtensa/src/esp32s2/hal.mk
+47 -8
View File
@@ -35,14 +35,21 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)rom
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private
@@ -52,10 +59,22 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
@@ -68,10 +87,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libc-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-data.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.spiflash.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-reent-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.spiflash_legacy.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
# Source files
@@ -80,6 +100,22 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_cali_line_fitting.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_table.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list$(DELIM)log_linked_list.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_lock.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c
@@ -92,7 +128,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
@@ -123,8 +161,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
@@ -136,6 +172,8 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)flash_ops.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)cache_utils.c
# Bootloader files
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
@@ -151,13 +189,14 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
arch/xtensa/src/esp32s3/Bootloader.mk
+7
View File
@@ -60,6 +60,7 @@ cfg_val = echo "$(1)=$(2)";
$(BOOTLOADER_CONFIG): $(TOPDIR)/.config $(BOOTLOADER_DIR)
$(Q) echo "Creating Bootloader configuration"
$(Q) { \
$(call cfg_en,NON_OS_BUILD) \
$(if $(CONFIG_ESP32S3_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \
$(if $(CONFIG_ESP32S3_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \
$(if $(CONFIG_ESP32S3_FLASH_16M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_16MB)) \
@@ -76,18 +77,24 @@ $(BOOTLOADER_CONFIG): $(TOPDIR)/.config $(BOOTLOADER_DIR)
} > $(BOOTLOADER_CONFIG)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
$(Q) { \
$(call cfg_en,CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) \
$(call cfg_val,CONFIG_ESP_BOOTLOADER_OFFSET,0x0000) \
$(call cfg_val,CONFIG_ESP_BOOTLOADER_SIZE,0xF000) \
$(call cfg_val,CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS,$(CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET)) \
$(call cfg_val,CONFIG_ESP_APPLICATION_SIZE,$(CONFIG_ESP32S3_OTA_SLOT_SIZE)) \
$(call cfg_val,CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS,$(CONFIG_ESP32S3_OTA_SECONDARY_SLOT_OFFSET)) \
$(call cfg_en,CONFIG_ESP_MCUBOOT_WDT_ENABLE) \
$(call cfg_en,CONFIG_LIBC_NEWLIB) \
$(call cfg_val,CONFIG_ESP_SCRATCH_OFFSET,$(CONFIG_ESP32S3_OTA_SCRATCH_OFFSET)) \
$(call cfg_val,CONFIG_ESP_SCRATCH_SIZE,$(CONFIG_ESP32S3_OTA_SCRATCH_SIZE)) \
$(call cfg_en,CONFIG_ESP_CONSOLE_UART) \
$(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,0)) \
$(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,1)) \
$(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM,0)) \
$(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM,1)) \
$(call cfg_en,CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT) \
$(call cfg_en,CONFIG_IDF_TARGET_ARCH_XTENSA) \
$(call cfg_val,CONFIG_BOOTLOADER_LOG_LEVEL,3) \
} >> $(BOOTLOADER_CONFIG)
else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y)
$(Q) { \
arch/xtensa/src/esp32s3/Kconfig
+1
View File
@@ -2680,6 +2680,7 @@ config ESPRESSIF_SIMPLE_BOOT
config ESP32S3_APP_FORMAT_MCUBOOT
bool "Enable MCUboot-bootable format"
depends on !MCUBOOT_BOOTLOADER
select ESPRESSIF_BOOTLOADER_MCUBOOT
default n
select ESP32S3_HAVE_OTA_PARTITION
---help---
arch/xtensa/src/esp32s3/Make.defs
+4 -3
View File
@@ -217,7 +217,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 65d20bfeed8dc22ff6eb096cea4486f925b92f1e
ESP_HAL_3RDPARTY_VERSION = e9a78c811578545e2bc673862d885a15bd6cbf67
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -270,12 +270,13 @@ include chip/hal.mk
include common/espressif/Make.defs
context:: chip/$(ESP_HAL_3RDPARTY_REPO)
ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y)
$(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..."
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32c3_family components/esp_coex/lib
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard
$(Q) echo "Applying patches..."
$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y)
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32c3_family components/esp_coex/lib
endif
distclean::
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
+192 -9
View File
@@ -96,9 +96,11 @@
#define BTDM_LPCLK_SEL_8M (3)
#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
#define OSI_VERSION 0x00010009
#define OSI_VERSION 0x0001000a
#define OSI_MAGIC_VALUE 0xfadebead
#define BLE_PWR_HDL_INVL 0xffff
#ifdef CONFIG_ESP32S3_SPIFLASH
# define BLE_TASK_EVENT_QUEUE_ITEM_SIZE 8
# define BLE_TASK_EVENT_QUEUE_LEN 8
@@ -228,6 +230,8 @@ struct osi_funcs_s
void (* _btdm_rom_table_ready)(void);
bool (* _coex_bt_wakeup_request)(void);
void (* _coex_bt_wakeup_request_end)(void);
int64_t (*_get_time_us)(void);
void (* _assert)(void);
};
/* BLE message queue private data */
@@ -395,6 +399,8 @@ static void btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr,
static void btdm_funcs_table_ready_wrapper(void);
static bool coex_bt_wakeup_request(void);
static void coex_bt_wakeup_request_end(void);
static int64_t get_time_us_wrapper(void);
static void assert_wrapper(void);
/****************************************************************************
* Other functions
@@ -473,10 +479,9 @@ extern int api_vhci_host_register_callback(const vhci_host_callback_t
/* TX power */
extern int ble_txpwr_set(int power_type, int power_level);
extern int ble_txpwr_get(int power_type);
extern int ble_txpwr_set(int power_type, uint16_t handle, int power_level);
extern int ble_txpwr_get(int power_type, uint16_t handle);
extern uint16_t l2c_ble_link_get_tx_buf_num(void);
extern int coex_core_ble_conn_dyn_prio_get(bool *low, bool *high);
extern void coex_pti_v2(void);
@@ -494,6 +499,25 @@ extern void ets_backup_dma_copy(uint32_t reg, uint32_t mem_addr,
#endif
extern void btdm_cca_feature_enable(void);
extern void btdm_aa_check_enhance_enable(void);
#if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
extern void scan_stack_enable_adv_flow_ctrl_vs_cmd(bool en);
extern void adv_stack_enable_clear_legacy_adv_vs_cmd(bool en);
extern void adv_filter_stack_enable_dup_exc_list_vs_cmd(bool en);
extern void chan_sel_stack_enable_set_csa_vs_cmd(bool en);
#endif
extern void ble_dtm_funcs_reset(void);
extern void ble_scan_funcs_reset(void);
extern void ble_42_adv_funcs_reset(void);
extern void ble_init_funcs_reset(void);
extern void ble_con_funcs_reset(void);
extern void ble_cca_funcs_reset(void);
extern void ble_ext_adv_funcs_reset(void);
extern void ble_ext_scan_funcs_reset(void);
extern void ble_base_funcs_reset(void);
extern void ble_enc_funcs_reset(void);
extern uint8_t _bt_bss_start[];
extern uint8_t _bt_bss_end[];
@@ -573,6 +597,8 @@ static struct osi_funcs_s g_osi_funcs =
._btdm_rom_table_ready = btdm_funcs_table_ready_wrapper,
._coex_bt_wakeup_request = coex_bt_wakeup_request,
._coex_bt_wakeup_request_end = coex_bt_wakeup_request_end,
._get_time_us = get_time_us_wrapper,
._assert = assert_wrapper,
};
static DRAM_ATTR struct osi_funcs_s *g_osi_funcs_p;
@@ -738,7 +764,7 @@ static int interrupt_alloc_wrapper(int cpu_id,
void **ret_handle)
{
btdm_isr_alloc_t *p;
intr_handle_data_t *handle;
struct intr_handle_data_t *handle;
vector_desc_t *vd;
int ret = OK;
int cpuint;
@@ -753,7 +779,7 @@ static int interrupt_alloc_wrapper(int cpu_id,
return ESP_ERR_NOT_FOUND;
}
handle = kmm_calloc(1, sizeof(intr_handle_data_t));
handle = kmm_calloc(1, sizeof(struct intr_handle_data_t));
if (handle == NULL)
{
free(p);
@@ -2905,6 +2931,51 @@ static void btdm_funcs_table_ready_wrapper(void)
{
#if BT_BLE_CCA_MODE == 2
btdm_cca_feature_enable();
#endif
#if BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED
btdm_aa_check_enhance_enable();
#endif
#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
/* Do nothing */
#else
wlinfo("Feature Config, ADV:%d, BLE_50:%d, DTM:%d, SCAN:%d, CCA:%d, "
"SMP:%d, CONNECT:%d", BT_CTRL_BLE_ADV, BT_CTRL_50_FEATURE_SUPPORT,
BT_CTRL_DTM_ENABLE, BT_CTRL_BLE_SCAN, BT_BLE_CCA_MODE,
BLE_SECURITY_ENABLE, BT_CTRL_BLE_MASTER);
ble_base_funcs_reset();
# if CONFIG_BT_CTRL_BLE_ADV
ble_42_adv_funcs_reset();
# if (BT_CTRL_50_FEATURE_SUPPORT == 1)
ble_ext_adv_funcs_reset();
# endif
# endif
# if CONFIG_BT_CTRL_DTM_ENABLE
ble_dtm_funcs_reset();
# endif
# if CONFIG_BT_CTRL_BLE_SCAN
ble_scan_funcs_reset();
# if (BT_CTRL_50_FEATURE_SUPPORT == 1)
ble_ext_scan_funcs_reset();
# endif
# endif
# if (BT_BLE_CCA_MODE != 0)
ble_cca_funcs_reset();
# endif
# if CONFIG_BT_CTRL_BLE_SECURITY_ENABLE
ble_enc_funcs_reset();
# endif
# if CONFIG_BT_CTRL_BLE_MASTER
ble_init_funcs_reset();
ble_con_funcs_reset();
# endif
#endif
}
@@ -2993,10 +3064,105 @@ static void coex_bt_wakeup_request_end(void)
return;
}
/****************************************************************************
* Name: get_time_us_wrapper
*
* Description:
* Wrapper function to get the current system time in microseconds. This
* function is placed in IRAM for faster execution and calls the underlying
* esp32s3_rt_timer_time_us() function.
*
* Input Parameters:
* None
*
* Returned Value:
* The current system time in microseconds as a 64-bit integer
*
****************************************************************************/
static IRAM_ATTR int64_t get_time_us_wrapper(void)
{
return (int64_t)esp32s3_rt_timer_time_us();
}
/****************************************************************************
* Name: assert_wrapper
*
* Description:
* Empty wrapper function for assertions. This function is placed in IRAM
* for faster execution. Currently implemented as a no-op function.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static IRAM_ATTR void assert_wrapper(void)
{
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Functions to be called by libbt
****************************************************************************/
/****************************************************************************
* Name: malloc_ble_controller_mem
*
* Description:
* Allocates memory for the BLE controller using the kernel memory manager.
* If allocation fails, an error message is logged.
*
* Input Parameters:
* size - The number of bytes to allocate
*
* Returned Value:
* A pointer to the allocated memory on success, NULL on failure
*
****************************************************************************/
void *malloc_ble_controller_mem(size_t size)
{
void *p = kmm_malloc(size);
if (p == NULL)
{
wlerr("Malloc failed");
}
return p;
}
/****************************************************************************
* Name: get_ble_controller_free_heap_size
*
* Description:
* Returns the amount of free heap memory available for the BLE controller.
* This function queries the user heap to determine available memory.
*
* Input Parameters:
* None
*
* Returned Value:
* The number of free bytes in the user heap
*
****************************************************************************/
uint32_t get_ble_controller_free_heap_size(void)
{
return mm_heapfree(USR_HEAP);
}
/****************************************************************************
* Other Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_bt_controller_init
*
@@ -3121,12 +3287,22 @@ int esp32s3_bt_controller_init(void)
periph_module_enable(PERIPH_BT_MODULE);
periph_module_reset(PERIPH_BT_MODULE);
if (btdm_controller_init(cfg) != 0)
err = btdm_controller_init(cfg);
if (err != OK)
{
wlerr("%s %d\n", __func__, err);
err = -ENOMEM;
goto error;
}
#if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
scan_stack_enable_adv_flow_ctrl_vs_cmd(true);
adv_stack_enable_clear_legacy_adv_vs_cmd(true);
adv_filter_stack_enable_dup_exc_list_vs_cmd(true);
chan_sel_stack_enable_set_csa_vs_cmd(true);
#endif
g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
#ifdef CONFIG_ESP32S3_SPIFLASH
@@ -3166,6 +3342,13 @@ int esp32s3_bt_controller_deinit(void)
return ERROR;
}
#if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED)
scan_stack_enable_adv_flow_ctrl_vs_cmd(false);
adv_stack_enable_clear_legacy_adv_vs_cmd(false);
adv_filter_stack_enable_dup_exc_list_vs_cmd(false);
chan_sel_stack_enable_set_csa_vs_cmd(false);
#endif
btdm_controller_deinit();
bt_controller_deinit_internal();
@@ -3375,7 +3558,7 @@ int esp32s3_bt_controller_disable(void)
}
/****************************************************************************
* Name: esp32s3_bt_controller_get_status
* Name: esp_bt_controller_get_status
*
* Description:
* Returns the status of the BT Controller
@@ -3388,7 +3571,7 @@ int esp32s3_bt_controller_disable(void)
*
****************************************************************************/
esp_bt_controller_status_t esp32s3_bt_controller_get_status(void)
esp_bt_controller_status_t esp_bt_controller_get_status(void)
{
return g_btdm_controller_status;
}
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.h
+1 -1
View File
@@ -121,7 +121,7 @@ int esp32s3_bt_controller_disable(void);
*
****************************************************************************/
esp_bt_controller_status_t esp32s3_bt_controller_get_status(void);
esp_bt_controller_status_t esp_bt_controller_get_status(void);
/****************************************************************************
* Name: esp32s3_vhci_host_check_send_available
arch/xtensa/src/esp32s3/esp32s3_dma.c
+3 -3
View File
@@ -472,11 +472,11 @@ int esp32s3_dma_get_interrupt(int chan, bool tx)
if (tx)
{
intr_status = gdma_ll_tx_get_interrupt_status(ctx.dev, chan);
intr_status = gdma_ll_tx_get_interrupt_status(ctx.dev, chan, false);
}
else
{
intr_status = gdma_ll_rx_get_interrupt_status(ctx.dev, chan);
intr_status = gdma_ll_rx_get_interrupt_status(ctx.dev, chan, false);
}
return intr_status;
@@ -694,7 +694,7 @@ void esp32s3_dma_init(void)
modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_DMA_CLK_EN_M);
modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST_M, 0);
gdma_hal_init(&ctx, 0);
ctx.dev = GDMA_LL_GET_HW(0);
/* enable DMA clock gating */
arch/xtensa/src/esp32s3/esp32s3_spiflash.c
+5 -4
View File
@@ -51,6 +51,7 @@
#include "spi_flash_defs.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "soc/extmem_reg.h"
#include "soc/spi_mem_reg.h"
#include "rom/opi_flash.h"
@@ -887,7 +888,7 @@ static inline void IRAM_ATTR spiflash_os_yield(void)
static void spi_flash_disable_cache(void)
{
cache_hal_suspend(CACHE_TYPE_ALL);
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
/****************************************************************************
@@ -907,7 +908,7 @@ static void spi_flash_disable_cache(void)
static void spi_flash_restore_cache(void)
{
cache_hal_resume(CACHE_TYPE_ALL);
cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
#ifdef CONFIG_SMP
@@ -1098,7 +1099,7 @@ int esp32s3_mmap(struct spiflash_map_req_s *req)
start_page < DROM0_PAGES_END;
++start_page)
{
if (MMU_TABLE[start_page] == MMU_INVALID)
if (MMU_TABLE[start_page] == SOC_MMU_INVALID)
{
break;
}
@@ -1165,7 +1166,7 @@ void esp32s3_ummap(const struct spiflash_map_req_s *req)
for (i = req->start_page; i < req->start_page + req->page_cnt; ++i)
{
MMU_TABLE[i] = MMU_INVALID;
MMU_TABLE[i] = SOC_MMU_INVALID;
}
spiflash_end();
arch/xtensa/src/esp32s3/esp32s3_spiram.c
+12 -12
View File
@@ -167,7 +167,7 @@ static inline uint32_t mmu_valid_space(uint32_t *start_address)
for (int i = (FLASH_MMU_TABLE_SIZE - 1); i >= 0; i--)
{
if (FLASH_MMU_TABLE[i] & MMU_INVALID)
if (FLASH_MMU_TABLE[i] & SOC_MMU_INVALID)
{
continue;
}
@@ -178,7 +178,7 @@ static inline uint32_t mmu_valid_space(uint32_t *start_address)
i++;
*start_address = DRAM0_CACHE_ADDRESS_LOW + (i) * MMU_PAGE_SIZE;
*start_address = SOC_DRAM0_CACHE_ADDRESS_LOW + (i) * MMU_PAGE_SIZE;
return (FLASH_MMU_TABLE_SIZE - i) * MMU_PAGE_SIZE;
}
@@ -228,11 +228,10 @@ static inline bool mmu_check_valid_ext_vaddr_region(uint32_t vaddr_start,
uint32_t len)
{
uint32_t vaddr_end = vaddr_start + len - 1;
bool valid = false;
valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) &&
ADDRESS_IN_IRAM0_CACHE(vaddr_end)) |
(ADDRESS_IN_DRAM0_CACHE(vaddr_start) &&
ADDRESS_IN_DRAM0_CACHE(vaddr_end));
bool valid = (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) &&
SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) |
(SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) &&
SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
return valid;
}
@@ -272,7 +271,7 @@ static int IRAM_ATTR esp_mmu_map_region(uint32_t vaddr, uint32_t paddr,
{
entry_id = (vaddr & MMU_VADDR_MASK) >> 16;
DEBUGASSERT(entry_id < MMU_ENTRY_NUM);
if (write_back == false && FLASH_MMU_TABLE[entry_id] != MMU_INVALID)
if (!write_back && FLASH_MMU_TABLE[entry_id] != SOC_MMU_INVALID)
{
esp_spiram_writeback_cache();
write_back = true;
@@ -359,7 +358,8 @@ int IRAM_ATTR cache_dbus_mmu_map(int vaddr, int paddr, int num)
#endif
cache_state[cpu] = cache_suspend_dcache();
esp_mmu_map_region(vaddr, paddr, num * MMU_PAGE_SIZE, MMU_ACCESS_SPIRAM);
esp_mmu_map_region(vaddr, paddr, num * MMU_PAGE_SIZE,
SOC_MMU_ACCESS_SPIRAM);
regval = getreg32(EXTMEM_DCACHE_CTRL1_REG);
regval &= ~EXTMEM_DCACHE_SHUT_CORE0_BUS;
@@ -414,7 +414,7 @@ int IRAM_ATTR esp_spiram_init_cache(void)
{
ASSERT(SPIRAM_VADDR_OFFSET % MMU_PAGE_SIZE == 0);
ASSERT(SPIRAM_VADDR_MAP_SIZE % MMU_PAGE_SIZE == 0);
target_mapped_vaddr_start = DRAM0_CACHE_ADDRESS_LOW +
target_mapped_vaddr_start = SOC_DRAM0_CACHE_ADDRESS_LOW +
SPIRAM_VADDR_OFFSET;
target_mapped_vaddr_end = target_mapped_vaddr_start +
SPIRAM_VADDR_MAP_SIZE;
@@ -439,7 +439,7 @@ int IRAM_ATTR esp_spiram_init_cache(void)
}
ASSERT(target_mapped_vaddr_end > target_mapped_vaddr_start);
ASSERT(target_mapped_vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH);
ASSERT(target_mapped_vaddr_end <= SOC_DRAM0_CACHE_ADDRESS_HIGH);
mapped_vaddr_size = target_mapped_vaddr_end -
target_mapped_vaddr_start;
g_mapped_vaddr_start = target_mapped_vaddr_start;
@@ -468,7 +468,7 @@ int IRAM_ATTR esp_spiram_init_cache(void)
cache_suspend_dcache();
cache_dbus_mmu_set(MMU_ACCESS_SPIRAM, g_mapped_vaddr_start,
cache_dbus_mmu_set(SOC_MMU_ACCESS_SPIRAM, g_mapped_vaddr_start,
0, 64, g_mapped_size >> 16, 0);
regval = getreg32(EXTMEM_DCACHE_CTRL1_REG);
arch/xtensa/src/esp32s3/esp32s3_start.c
+11
View File
@@ -52,6 +52,7 @@
#include "rom/esp32s3_spiflash.h"
#include "espressif/esp_loader.h"
#include "esp_app_desc.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_types.h"
#include "hal/cache_types.h"
@@ -476,6 +477,8 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void)
noinstrument_function void IRAM_ATTR __start(void)
{
const esp_app_desc_t *app_desc;
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined(CONFIG_ESPRESSIF_SIMPLE_BOOT)
size_t partition_offset = PRIMARY_SLOT_OFFSET;
@@ -504,6 +507,14 @@ noinstrument_function void IRAM_ATTR __start(void)
}
#endif
app_desc = esp_app_get_description();
if (app_desc->magic_word != ESP_APP_DESC_MAGIC_WORD)
{
ets_printf("Magic Word check failed: %08" PRIx32 "\n",
app_desc->magic_word);
ets_printf("Trying to boot anyway...\n");
}
configure_cpu_caches();
if (efuse_ll_get_flash_type())
arch/xtensa/src/esp32s3/esp32s3_textheap.c
+4 -2
View File
@@ -32,6 +32,7 @@
#include <nuttx/kmalloc.h>
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hardware/esp32s3_soc.h"
#ifdef CONFIG_ESP32S3_RTC_HEAP
@@ -226,8 +227,9 @@ IRAM_ATTR void up_textheap_data_sync(void)
#ifdef CONFIG_ESP32S3_SPIRAM
esp_spiram_writeback_cache();
#endif
cache_hal_disable(CACHE_TYPE_INSTRUCTION);
cache_hal_enable(CACHE_TYPE_INSTRUCTION);
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
leave_critical_section(flags);
}
arch/xtensa/src/esp32s3/esp32s3_userspace.c
+3 -3
View File
@@ -383,14 +383,14 @@ static noinline_function IRAM_ATTR void configure_flash_mmu(void)
drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK;
drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK;
drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma);
ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned,
ASSERT(cache_dbus_mmu_set(SOC_MMU_ACCESS_FLASH, drom_vma_aligned,
drom_lma_aligned, 64,
(int)drom_page_count, 0) == 0);
irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK;
irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK;
irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma);
ASSERT(cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned,
ASSERT(cache_ibus_mmu_set(SOC_MMU_ACCESS_FLASH, irom_vma_aligned,
irom_lma_aligned, 64,
(int)irom_page_count, 0) == 0);
@@ -423,7 +423,7 @@ static noinline_function IRAM_ATTR const void *map_flash(uint32_t src_addr,
src_addr_aligned = src_addr & MMU_FLASH_MASK;
page_count = calc_mmu_pages(size, src_addr);
ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR,
ASSERT(cache_dbus_mmu_set(SOC_MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR,
src_addr_aligned, 64, (int)page_count, 0) == 0);
dcache_resume(cache_state);
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
+66 -506
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
-60
View File
@@ -45,22 +45,6 @@ extern "C"
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ESPRESSIF_WIFI_STATION)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_SOFTAP)
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 0
# define ESPRESSIF_WLAN_DEVS 1
#elif defined(CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP)
# define ESPRESSIF_WLAN_HAS_STA
# define ESPRESSIF_WLAN_HAS_SOFTAP
# define ESPRESSIF_WLAN_STA_DEVNO 0
# define ESPRESSIF_WLAN_SOFTAP_DEVNO 1
# define ESPRESSIF_WLAN_DEVS 2
#endif
#define SSID_MAX_LEN (32)
#define PWD_MAX_LEN (64)
@@ -70,27 +54,6 @@ extern "C"
typedef int esp_err_t;
/* Wi-Fi event ID */
enum wifi_adpt_evt_e
{
WIFI_ADPT_EVT_SCAN_DONE = 0,
WIFI_ADPT_EVT_STA_START,
WIFI_ADPT_EVT_STA_CONNECT,
WIFI_ADPT_EVT_STA_DISCONNECT,
WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE,
WIFI_ADPT_EVT_STA_STOP,
WIFI_ADPT_EVT_AP_START,
WIFI_ADPT_EVT_AP_STOP,
WIFI_ADPT_EVT_AP_STACONNECTED,
WIFI_ADPT_EVT_AP_STADISCONNECTED,
WIFI_ADPT_EVT_MAX,
};
/* Wi-Fi event callback function */
typedef void (*wifi_evt_cb_t)(void *p);
/* Wi-Fi TX done callback function */
typedef void (*wifi_txdone_cb_t)(uint8_t *data, uint16_t *len, bool status);
@@ -131,25 +94,6 @@ int esp_wifi_adapter_init(void);
void esp_wifi_free_eb(void *eb);
/****************************************************************************
* Name: esp_wifi_notify_subscribe
*
* Description:
* Enable event notification
*
* Input Parameters:
* pid - Task PID
* event - Signal event data pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event);
#ifdef ESPRESSIF_WLAN_HAS_STA
/****************************************************************************
* Name: esp_wifi_sta_start
*
@@ -484,9 +428,6 @@ int esp_wifi_sta_country(struct iwreq *iwr, bool set);
****************************************************************************/
int esp_wifi_sta_rssi(struct iwreq *iwr, bool set);
#endif /* ESPRESSIF_WLAN_HAS_STA */
#ifdef ESPRESSIF_WLAN_HAS_SOFTAP
/****************************************************************************
* Name: esp_wifi_softap_start
@@ -822,7 +763,6 @@ int esp_wifi_softap_country(struct iwreq *iwr, bool set);
****************************************************************************/
int esp_wifi_softap_rssi(struct iwreq *iwr, bool set);
#endif /* ESPRESSIF_WLAN_HAS_SOFTAP */
/****************************************************************************
* Name: esp_wifi_bt_coexist_init
arch/xtensa/src/esp32s3/hal.mk
+37 -9
View File
@@ -36,14 +36,20 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private
@@ -55,23 +61,32 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
# Linker scripts
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.wdt.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
# Source files
@@ -87,6 +102,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efus
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
@@ -103,12 +119,16 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c
@@ -121,7 +141,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
@@ -137,8 +156,15 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list$(DELIM)log_linked_list.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_lock.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c
@@ -156,6 +182,8 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_hpm_enable.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)${CHIP_SERIES}$(DELIM)spi_flash_oct_flash_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c
@@ -173,7 +201,7 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
boards/xtensa/esp32/common/scripts/esp32_sections.ld
+19 -1
View File
@@ -171,6 +171,7 @@ SECTIONS
*libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_init.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
*libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
@@ -200,6 +201,7 @@ SECTIONS
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
*libarch.a:esp_app_desc.*(.literal .text .literal.* .text.*)
*libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*)
@@ -207,8 +209,16 @@ SECTIONS
*libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*)
*libarch.a:*log.*(.text .text.* .literal .literal.*)
*libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
*libarch.a:*log_lock.*(.literal .literal.* .text .text.*)
*libarch.a:*log_print.*(.literal .literal.* .text .text.*)
*libarch.a:*log_timestamp.*(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
*libarch.a:*log_timestamp.*(.literal.esp_log_timestamp .text.esp_log_timestamp)
*libarch.a:*log_timestamp_common.*(.literal .literal.* .text .text.*)
*libarch.a:*log_write.*(.literal.esp_log_write .text.esp_log_write)
*libarch.a:*log_write.*(.literal.esp_log_writev .text.esp_log_writev)
*libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
*libarch.a:*flash_qio_mode.*(.text .text.* .literal .literal.*)
*libarch.a:*spi_flash_wrap.*(.text .text.* .literal .literal.*)
#ifdef CONFIG_STACK_CANARIES
*libc.a:lib_stackchk.*(.literal .text .literal.* .text.*)
@@ -450,6 +460,9 @@ SECTIONS
*libarch.a:*log.*(.rodata .rodata.*)
*libarch.a:*log_noos.*(.rodata .rodata.*)
*libarch.a:*cpu_region_protect.*(.rodata .rodata.*)
*libarch.a:*flash_qio_mode.*(.rodata .rodata.*)
*libarch.a:*spi_flash_wrap.*(.rodata .rodata.*)
_edata = ABSOLUTE(.);
_data_end = ABSOLUTE(.);
@@ -505,6 +518,11 @@ SECTIONS
.flash.rodata : ALIGN(0x10000)
{
_rodata_reserved_start = ABSOLUTE(.);
/* !DO NOT PUT ANYTHING BEFORE THIS! */
/* Should be the first. App version info. */
*(.rodata_desc .rodata_desc.*)
. = ALIGN(4);
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*

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