29ab603a66
Kinetis:Add LPUART for use with K66
...
Add LPUART made UART5 an uption as the K66 does not have UART5
2017-02-25 07:02:56 -10:00
61b10c5e58
Kinetis:Add LPUART to K66 chip
...
Add KINETIS_NLPUART setting it to 1 and adjust KINETIS_NUART
to removed UART5 as the K66 dioes not have UART5
2017-02-25 07:02:56 -10:00
f6fe9beeb3
Kinetis:Add LPUART to config
2017-02-25 07:02:56 -10:00
b280aef9c0
Kinetis:Add LPUART register definitions
2017-02-25 07:02:38 -10:00
9061a3fb64
Kinetis: UART add UART_BDH_SBNS definition
2017-02-25 07:02:38 -10:00
a43554decd
Kinetis:SIM add paramiterized SIM_CLKDIVx_xxFRAC|DIV macros
...
The makes for cleaner board definitions like:
Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1
#define BOARD_SIM_CLKDIV3_PLLFLLDIV 2
#define BOARD_SIM_CLKDIV3_FREQ (BOARD_SOPT2_FREQ * (BOARD_SIM_CLKDIV3_PLLFLLFRAC / BOARD_SIM_CLKDIV3_PLLFLLDIV))
2017-02-23 19:27:55 -10:00
e1278c0cb9
Kinetis:Fix typo in comment
2017-02-23 19:25:53 -10:00
41e3d9f174
Kinetis:Refactor you use SIM_SOPT2_PLLFLLSEL, added warning
...
The warning has been added because: SIM_SOPT2_PLLFLLSEL
is a clock selection that may feed many clock subsystem:
USB, TPM, SDHCSRC, LPUARTSRC. Therefore, there needs to
be a global board level setting to select the source for
SIM_SOPT2_PLLFLLSEL and then derive all the sub selections
and proper fractions/divisors for each modules clock.
2017-02-22 10:42:52 -10:00
12c24f2644
Kinetis:kinetis_clockconfig uses the correct ACKISO
...
ACKISO is located in the PMC_REGSC on the majority
of the Kinetis SoCs. With the exception of the
MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
2017-02-22 10:42:52 -10:00
1324b8c00a
Kinetis:Resolves issues where Freescale moved ACKISO
...
ACKISO is located in the PMC_REGSC on the majority
of the Kinetis SoCs. With the exception of the
MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS
2017-02-22 10:42:52 -10:00
a4b985f865
Kinetis:PMC defines are based on PMC feature configuration
2017-02-22 10:42:52 -10:00
1ba6eadcec
Kinetis:Include the PMC features
2017-02-22 10:42:52 -10:00
8525c266a1
Created a kinetis PMC versioning scheme pulled in by Kinetis chip.h
...
The motvations is to version the IP blocks of the Kinetis
K series family of parts.
This added versioning and configuration features for the
Kinetis PMC IP block.
It is envisioned that in the long term as a chip is added.
The author of the new chip definitions will either find
the exact configuration in an existing chip define and
add the new chip to it Or add the PMC fature configuration
#defines to the chip ifdef list in
arch/arm/include/kinetis/kinetis_pmc.h In either case the
author should mark it as "Verified to Document Number:"
taken from the reference manual.
The version KINETIS_PMC_VERSION_UKN has been applied to
most all the SoCs in the kinetis arch prior to this commit.
The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
CONFIG_ARCH_CHIP_MK20DXxxxVLH7 All K64 and K66 have ben
Verified PMC configurations.
2017-02-22 10:42:52 -10:00
381ffa3083
Kinetis:SIM defines are based on SIM feature configuration
2017-02-22 10:42:52 -10:00
5b550a37eb
Kinetis:Include the SIM features
2017-02-22 10:42:52 -10:00
d74f16ecb9
Kinetis:Created a kinetis SIM versioning scheme pulled in by Kinetis chip.h
...
The motvations is to version the IP blocks of the Kinetis
K series family of parts.
This added versioning and configuration features for the
Kinetis SIM IP block.
It is envisioned that in the long term as a chip is added.
The author of the new chip definitions will either find
the exact configuration in an existing chip define and
add the new chip to it Or add the SIM feature configuration
#defines to the chip ifdef list in
arch/arm/include/kinetis/kinetis_sim.h In either case the
author should mark it as "Verified to Document Number:"
taken from the reference manual.
The version KINETIS_SIM_VERSION_UKN has been applied to
most all the SoCs in the kinetis arch prior to this commit.
The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
All K64 and K66 which not have Verified SIM configurations.
2017-02-22 10:42:52 -10:00
14bdf3af22
Kinetis:Fixed Typo in kinetis_mcg header
2017-02-22 10:42:52 -10:00
bb059432ea
Move local variables to top of function for compliance with coding standard.
2017-02-20 17:54:04 -06:00
4dfb8268f3
stm32f7: stm32_allocateheap: allow use DTCM memory for heap
...
STM32F7 has up to 128KiB of DTCM memory that is currently left unused.
This patch adds DTCM to main heap if CONFIG_STM32F7_DTCMEXCLUDE is not enabled.
2017-02-20 08:42:51 -06:00
4b4f0dc4df
STM32L4 COMP: Remove some unused definitions
2017-02-20 08:41:43 -06:00
0fc226dd53
Changes from review of last PR
2017-02-19 14:58:37 -06:00
1838171d43
Add twr-k64f120m config and fix some ENET related problems
2017-02-19 21:20:56 +01:00
4033953878
STM32L4 COMP: Port from Motorola MDK.
2017-02-19 11:33:35 -06:00
e61ded4a14
STM32L4: Add Comparator register definition file.
2017-02-19 10:09:17 -06:00
d900e1fac0
STM32L4: Bring LPTIM driver in from the Motorola MDK.
2017-02-18 11:06:20 -06:00
6bafdb1cdc
Remove some dangling whitespace at the end of some lines.
2017-02-18 10:20:08 -06:00
085616d651
STM32L4: Bring power management logic from Motrola MDK into NuttX
2017-02-18 10:18:42 -06:00
6fe94b5724
Trivial cosmetic, alignement changes.
2017-02-17 17:50:56 -06:00
e4e7528b1a
Port STM32L4 SAI driver from MDK.
2017-02-17 15:13:36 -06:00
377fadc816
STM32L4: Add SAI register definition header file.
2017-02-17 13:52:22 -06:00
dd1aa2357b
Allow board to configure HSE clock in bypass-mode. This is needed to enable HSE with Nucleo-F746ZG board.
2017-02-17 07:15:22 -06:00
add2fbfa85
LM3S Ethernet: Fix interrupt work in the last big commit.
2017-02-17 17:40:58 +09:00
a49b349614
C library: Add swab()
2017-02-16 14:42:27 -06:00
3b351615be
Kinetis K66: Change necessary for correct build.
2017-02-16 11:33:36 -06:00
42e8b12ec3
Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any registers. This led to incorrect timings on the bus.
2017-02-16 07:42:37 -06:00
c3bfccf293
Kinetis PWM: Purely cosmetic changes from review.
2017-02-15 17:54:55 -06:00
c83af148b1
Kinetis:Add FTM3 to PWM
2017-02-15 13:42:36 -10:00
a95a6c43d3
Kinetis Support RMII clock source select
...
This defined the RMII clock source select bits and allows
the selection to be made via Kconfig
2017-02-15 13:42:36 -10:00
1474300276
LPC43: Rename HAVE_CONSOLE to HAVE_SERIAL_CONSOLE. We can, of course, always have a some console other than a serial console.
2017-02-15 07:23:18 -06:00
058f06cc94
Fix typos introduced in previous commit
2017-02-15 07:16:15 -06:00
077adf863e
Merge branch 'master' of bitbucket.org:nuttx/nuttx
2017-02-14 19:31:58 -06:00
1b996f1c7c
Add usbnsh config to Bambino 200E board
2017-02-14 19:31:39 -06:00
4043dd4aa0
LPC43 serial: Correct conditional logi that selects /dev/ttySN. Problem noted by Alan Carvalho de Assis.
2017-02-14 19:12:11 -06:00
3423a4ecc2
Kinetis: Add comment the Freedom-K66F uses KSZ8081 PHY
2017-02-14 09:15:23 -10:00
35fc713931
Kinetis K64 and K66 share mpu files
2017-02-14 09:15:23 -10:00
b4695c5ee9
hostfs: Add support for fstat().
2017-02-14 09:54:08 -06:00
84b206bf7e
Kinetis K66 FMC
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Added K66 FMC register definition
2017-02-13 14:35:52 -10:00
7d80db5919
Kinetis K66 Pin Mux
2017-02-13 14:35:51 -10:00
e28781ebeb
Include K66 memory map
2017-02-13 14:35:51 -10:00
6597e46ce7
Define Alternate addresses for IP blocks in both AIPS0 & AIPS1
...
Added ALT version of RNGA, FTM2, DAC0 as a facility to later
define secondary access via AIPS1 to these peripherals
2017-02-13 14:35:51 -10:00
David Sidrane
Gregory Nutt
Jussi Kivilinna
Marc Rechté
Masayuki Ishikawa
Spahlinger, Michael
Alan Carvalho de Assis