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STM32L4: Add SAI register definition header file.
This commit is contained in:
Gregory Nutt
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32l4_sai.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
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#define STM32L4_SAI_ACR1_OFFSET 0x0004 /* SAI Configuration Register 1 A */
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#define STM32L4_SAI_ACR2_OFFSET 0x0008 /* SAI Configuration Register 2 A */
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#define STM32L4_SAI_AFRCR_OFFSET 0x000c /* SAI Frame Configuration Register A */
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#define STM32L4_SAI_ASLOTR_OFFSET 0x0010 /* SAI Slot Register A */
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#define STM32L4_SAI_AIM_OFFSET 0x0014 /* SAI Interrupt Mask Register 2 A */
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#define STM32L4_SAI_ASR_OFFSET 0x0018 /* SAI Status Register A */
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#define STM32L4_SAI_ACLRFR_OFFSET 0x001c /* SAI Clear Flag Register A */
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#define STM32L4_SAI_ADR_OFFSET 0x0020 /* SAI Data Register A */
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#define STM32L4_SAI_BCR1_OFFSET 0x0024 /* SAI Configuration Register 1 B */
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#define STM32L4_SAI_BCR2_OFFSET 0x0028 /* SAI Configuration Register 2 B */
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#define STM32L4_SAI_BFRCR_OFFSET 0x002c /* SAI Frame Configuration Register B */
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#define STM32L4_SAI_BSLOTR_OFFSET 0x0030 /* SAI Slot Register B */
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#define STM32L4_SAI_BIM_OFFSET 0x0034 /* SAI Interrupt Mask Register 2 B */
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#define STM32L4_SAI_BSR_OFFSET 0x0038 /* SAI Status Register B */
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#define STM32L4_SAI_BCLRFR_OFFSET 0x003c /* SAI Clear Flag Register A */
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#define STM32L4_SAI_BDR_OFFSET 0x0040 /* SAI Data Register B */
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/* Register Addresses ***************************************************************/
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#define STM32L4_SAI1_GCR (STM32L4_SAI1_BASE+STM32L4_SAI_GCR_OFFSET)
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#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_BASE+STM32L4_SAI_ACR1_OFFSET)
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#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_BASE+STM32L4_SAI_ACR2_OFFSET)
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#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_BASE+STM32L4_SAI_AFRCR_OFFSET)
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#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_BASE+STM32L4_SAI_ASLOTR_OFFSET)
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#define STM32L4_SAI1_AIM (STM32L4_SAI1_BASE+STM32L4_SAI_AIM_OFFSET)
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#define STM32L4_SAI1_ASR (STM32L4_SAI1_BASE+STM32L4_SAI_ASR_OFFSET)
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#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_BASE+STM32L4_SAI_ACLRFR_OFFSET)
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#define STM32L4_SAI1_ADR (STM32L4_SAI1_BASE+STM32L4_SAI_ADR_OFFSET)
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#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_BASE+STM32L4_SAI_BCR1_OFFSET)
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#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_BASE+STM32L4_SAI_BCR2_OFFSET)
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#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_BASE+STM32L4_SAI_BFRCR_OFFSET)
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#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_BASE+STM32L4_SAI_BSLOTR_OFFSET)
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#define STM32L4_SAI1_BIM (STM32L4_SAI1_BASE+STM32L4_SAI_BIM_OFFSET)
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#define STM32L4_SAI1_BSR (STM32L4_SAI1_BASE+STM32L4_SAI_BSR_OFFSET)
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#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_BASE+STM32L4_SAI_BCLRFR_OFFSET)
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#define STM32L4_SAI1_BDR (STM32L4_SAI1_BASE+STM32L4_SAI_BDR_OFFSET)
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#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET)
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#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_BASE+STM32L4_SAI_ACR1_OFFSET)
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#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_BASE+STM32L4_SAI_ACR2_OFFSET)
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#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_BASE+STM32L4_SAI_AFRCR_OFFSET)
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#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_BASE+STM32L4_SAI_ASLOTR_OFFSET)
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#define STM32L4_SAI2_AIM (STM32L4_SAI2_BASE+STM32L4_SAI_AIM_OFFSET)
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#define STM32L4_SAI2_ASR (STM32L4_SAI2_BASE+STM32L4_SAI_ASR_OFFSET)
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#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_BASE+STM32L4_SAI_ACLRFR_OFFSET)
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#define STM32L4_SAI2_ADR (STM32L4_SAI2_BASE+STM32L4_SAI_ADR_OFFSET)
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#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_BASE+STM32L4_SAI_BCR1_OFFSET)
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#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_BASE+STM32L4_SAI_BCR2_OFFSET)
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#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_BASE+STM32L4_SAI_BFRCR_OFFSET)
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#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_BASE+STM32L4_SAI_BSLOTR_OFFSET)
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#define STM32L4_SAI2_BIM (STM32L4_SAI2_BASE+STM32L4_SAI_BIM_OFFSET)
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#define STM32L4_SAI2_BSR (STM32L4_SAI2_BASE+STM32L4_SAI_BSR_OFFSET)
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#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_BASE+STM32L4_SAI_BCLRFR_OFFSET)
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#define STM32L4_SAI2_BDR (STM32L4_SAI2_BASE+STM32L4_SAI_BDR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* SAI Global Configuration Register */
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#define SAI_GCR_SYNCIN_SHIFT (0) /* Bits 0-1: Synchronization inputs */
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#define SAI_GCR_SYNCIN_MASK (3 << SAI_GCR_SYNCIN_SHIFT)
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# define SAI_GCR_SYNCIN(n) ((uint32_t)(n) << SAI_GCR_SYNCIN_SHIFT)
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/* Bits 2-3: Reserved */
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#define SAI_GCR_SYNCOUT_SHIFT (4) /* Bits 4-5: Synchronization outputs */
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#define SAI_GCR_SYNCOUT_MASK (3 << SAI_GCR_SYNCOUT_SHIFT)
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# define SAI_GCR_SYNCOUT ((uint32_t)(n) << SAI_GCR_SYNCOUT_SHIFT)
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/* Bits 6-31: Reserved */
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/* SAI Configuration Register 1 */
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#define SAI_CR1_MODE_SHIFT (0) /* Bits 0-1: SAI audio block mode */
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#define SAI_CR1_MODE_MASK (3 << SAI_CR1_MODE_SHIFT)
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# define SAI_CR1_MODE_MXMIT (0 << SAI_CR1_MODE_SHIFT) /* Master transmitter */
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# define SAI_CR1_MODE_MRECV (1 << SAI_CR1_MODE_SHIFT) /* Master receiver */
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# define SAI_CR1_MODE_SXMIT (2 << SAI_CR1_MODE_SHIFT) /* Slave transmitter */
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# define SAI_CR1_MODE_SRECV (3 << SAI_CR1_MODE_SHIFT) /* Slave receiver */
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#define SAI_CR1_PRTCFG_SHIFT (2) /* Bits 2-3: Protocol configuration */
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#define SAI_CR1_PRTCFG_MASK (3 << SAI_CR1_PRTCFG_SHIFT)
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# define SAI_CR1_PRTCFG_FREE (0 << SAI_CR1_PRTCFG_SHIFT) /* Free protocol */
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# define SAI_CR1_PRTCFG_SPDIF (1 << SAI_CR1_PRTCFG_SHIFT) /* SPDIF protocol */
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# define SAI_CR1_PRTCFG_AC97 (2 << SAI_CR1_PRTCFG_SHIFT) /* AC97 protocol */
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/* Bit 4: Reserved */
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#define SAI_CR1_DS_SHIFT (5) /* Bits 5-7: Data size */
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#define SAI_CR1_DS_MASK (7 << SAI_CR1_DS_SHIFT)
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# define SAI_CR1_DS_8BITS (2 << SAI_CR1_DS_SHIFT) /* 8 bits */
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# define SAI_CR1_DS_10BITS (3 << SAI_CR1_DS_SHIFT) /* 10 bits */
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# define SAI_CR1_DS_16BITS (4 << SAI_CR1_DS_SHIFT) /* 16 bits */
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# define SAI_CR1_DS_20BITS (5 << SAI_CR1_DS_SHIFT) /* 20 bits */
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# define SAI_CR1_DS_24BITS (6 << SAI_CR1_DS_SHIFT) /* 24 bits */
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# define SAI_CR1_DS_32BITS (7 << SAI_CR1_DS_SHIFT) /* 32 bits */
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#define SAI_CR1_LSBFIRST (1 << 8) /* Bit 8: Least significant bit first */
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#define SAI_CR1_CKSTR (1 << 9) /* Bit 9: Clock strobing edge */
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#define SAI_CR1_SYNCEN_SHIFT (10) /* Bits 10-11: Synchronization enable */
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#define SAI_CR1_SYNCEN_MASK (3 << SAI_CR1_SYNCEN_SHIFT)
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# define SAI_CR1_SYNCEN_ASYNCH (0 << SAI_CR1_SYNCEN_SHIFT) /* Asynchronous mode */
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# define SAI_CR1_SYNCEN_INTERNAL (1 << SAI_CR1_SYNCEN_SHIFT) /* Synchronous with other internal sub-block */
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# define SAI_CR1_SYNCEN_EXTERNAL (2 << SAI_CR1_SYNCEN_SHIFT) /* Aynchronous with external SAI peripheral */
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#define SAI_CR1_MONO (1 << 12) /* Bit 12: Mono mode */
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#define SAI_CR1_OUTDRIV (1 << 13) /* Bit 13: Output drive */
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/* Bits 14-15: Reserved */
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#define SAI_CR1_SAIEN (1 << 16) /* Bit 16: Audio block enable */
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#define SAI_CR1_DMAEN (1 << 17) /* Bit 17: DMA enable */
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/* Bit 18: Reserved */
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#define SAI_CR1_NODIV (1 << 19) /* Bit 19: No divider */
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#define SAI_CR1_MCKDIV_SHIFT (20) /* Bits 20-23: Master clock divider */
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#define SAI_CR1_MCKDIV_MASK (15 << SAI_CR1_MCKDIV_SHIFT)
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# define SAI_CR1_MCKDIV(n) ((uint32_t)(n) << SAI_CR1_MCKDIV_SHIFT)
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/* Bits 24-31: Reserved */
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/* SAI Configuration Register 2 */
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#define SAI_CR2_FTH_SHIFT (x0x) /* Bits 0-2: FIFO threshold */
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#define SAI_CR2_FTH_MASK (7 << SAI_CR2_FTH_SHIFT)
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# define SAI_CR2_FTH_EMPTY (0 << SAI_CR2_FTH_SHIFT) /* FIFO empty */
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# define SAI_CR2_FTH_25PCT (1 << SAI_CR2_FTH_SHIFT) /* 25% FIFO */
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# define SAI_CR2_FTH_50PCT (2 << SAI_CR2_FTH_SHIFT) /* 50% FIFO */
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# define SAI_CR2_FTH_75PCT (3 << SAI_CR2_FTH_SHIFT) /* 75% FIFO */
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# define SAI_CR2_FTH_FULL (4 << SAI_CR2_FTH_SHIFT) /* FIFO full */
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#define SAI_CR2_FFLUSH (1 << 3) /* Bit 3: FIFO flush */
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#define SAI_CR2_TRIS (1 << 4) /* Bit 4: Tristate management on data line */
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#define SAI_CR2_MUTE (1 << 5) /* Bit 5: Mute */
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#define SAI_CR2_MUTEVAL (1 << 6) /* Bit 6: Mute value */
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#define SAI_CR2_MUTECNT_SHIFT (7) /* Bits 7-12: Mute counter */
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#define SAI_CR2_MUTECNT_MASK (0x3f << SAI_CR2_MUTECNT_SHIFT)
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# define SAI_CR2_MUTECNT(n) ((uint32_t)(n) << SAI_CR2_MUTECNT_SHIFT)
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#define SAI_CR2_CPL (1 << 13) /* Bit 13: Complement */
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#define SAI_CR2_COMP_SHIFT (14) /* Bits 14-15: Companding mode */
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#define SAI_CR2_COMP_MASK (3 << SAI_CR2_COMP_SHIFT)
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# define SAI_CR2_COMP_NONE (0 << SAI_CR2_COMP_SHIFT) /* No companding algorithm */
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# define SAI_CR2_COMP_ULAW (2 << SAI_CR2_COMP_SHIFT) /* μ-Law algorithm */
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# define SAI_CR2_COMP_ALAW (3 << SAI_CR2_COMP_SHIFT) /* A-Law algorithm */
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/* Bits 16-31: Reserved */
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/* SAI Frame Configuration Register */
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#define SAI_FRCR_FRL_SHIFT (0) /* Bits 0-7: Frame length */
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#define SAI_FRCR_FRL_MASK (0xff << SAI_FRCR_FRL_SHIFT)
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# define SAI_FRCR_FRL(n) ((uint32_t)(n) << SAI_FRCR_FRL_SHIFT)
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#define SAI_FRCR_FSALL_SHIFT (8) /* Bits 8-14: Frame synchronization active level length */
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#define SAI_FRCR_FSALL_MASK (0x7f << SAI_FRCR_FSALL_SHIFT)
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# define SAI_FRCR_FSALL(n) ((uint32_t)(n) << SAI_FRCR_FSALL_SHIFT)
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#define SAI_FRCR_FSDEF (1 << 16) /* Bit 16: Frame synchronization definition */
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#define SAI_FRCR_FSPOL (1 << 17) /* Bit 17: Frame synchronization polarity */
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#define SAI_FRCR_FSOFF (1 << 18) /* Bit 18: Frame synchronization offset */
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/* Bits 19-31: Reserved */
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/* SAI Slot Register */
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#define SAI_SLOTR_FBOFF_SHIFT (0) /* Bits 0-4: First bit offset */
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#define SAI_SLOTR_FBOFF_MASK (32 << SAI_SLOTR_FBOFF_SHIFT)
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# define SAI_SLOTR_FBOFF(n) ((uint32_t)(n) << SAI_SLOTR_FBOFF_SHIFT)
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/* Bit 5: Reserved */
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#define SAI_SLOTR_SLOTSZ_SHIFT (6) /* Bits 6-7: Slot size */
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#define SAI_SLOTR_SLOTSZ_MASK (3 << SAI_SLOTR_SLOTSZ_SHIFT)
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# define SAI_SLOTR_SLOTSZ_DATA (0 << SAI_SLOTR_SLOTSZ_SHIFT) /* Same as data size */
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# define SAI_SLOTR_SLOTSZ_16BIT (1 << SAI_SLOTR_SLOTSZ_SHIFT) /* 16-bit */
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# define SAI_SLOTR_SLOTSZ_32BIT (2 << SAI_SLOTR_SLOTSZ_SHIFT) /* 32-bit */
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#define SAI_SLOTR_NBSLOT_SHIFT (0) /* Bits 0-3: Number of slots in an audio frame */
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#define SAI_SLOTR_NBSLOT_MASK (15 << SAI_SLOTR_NBSLOT_SHIFT)
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# define SAI_SLOTR_NBSLOT(n) ((uint32_t)(n) << SAI_SLOTR_NBSLOT_SHIFT)
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/* Bits 12-15: Reserved */
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#define SAI_SLOTR_SLOTEN_SHIFT (16) /* Bits 16-31: Slot enable */
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#define SAI_SLOTR_SLOTEN_MASK (0xffff << SAI_SLOTR_SLOTEN_SHIFT)
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# define SAI_SLOTR_SLOTEN(n) ((uint32_t)(n) << SAI_SLOTR_SLOTEN_SHIFT)
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/* SAI Interrupt Mask Register 2, SAI Status Register, and SAI Clear Flag Register */
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#define SAI_INT_OVRUDR (1 << 0) /* Bit 0: Overrun/underrun interrupt */
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#define SAI_INT_MUTEDET (1 << 1) /* Bit 1: Mute detection interrupt */
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#define SAI_INT_WCKCFG (1 << 2) /* Bit 2: Wrong clock configuration interrupt */
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#define SAI_INT_FREQ (1 << 3) /* Bit 3: FIFO request interrupt (not CLRFFR) */
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#define SAI_INT_CNRDY (1 << 4) /* Bit 4: Codec not ready interrupt (AC97). */
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#define SAI_INT_AFSDET (1 << 5) /* Bit 5: Anticipated frame synchronization detection interrupt */
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#define SAI_INT_LFSDET (1 << 6) /* Bit 6: Late frame synchronization detection interrupt */
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/* Bits 7-31: Reserved */
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/* SAI Data Register (32-bit data) */
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_SAI_H */
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