Xiang Xiao
2166c98809
Add printflike and scanflike to all printf/scanf like functions
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com >
2022-07-18 14:14:36 +03:00
Gustavo Henrique Nihei
5805ad3954
risc-v/esp32c3: Disable access to invalid memory regions using MPU
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com >
2022-06-11 01:55:46 +08:00
Gustavo Henrique Nihei
c778f35f08
risc-v/esp32c3: Add support for Protected Mode
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com >
2022-05-18 11:43:52 +08:00
Huang Qi
10bb48b9b4
arch/risc-v: Merge rv32im and rv64gc into common
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com >
2022-01-11 23:24:33 +08:00
ChenWen
6d165506d5
risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts
2021-12-21 10:03:58 -03:00
Dong Heng
f5c5d77744
risc-v/esp32c3: Add hardware brownout check and reset
2021-11-12 16:50:19 -03:00
Gustavo Henrique Nihei
3c63cb522c
risc-v/esp32c3: Enable booting from MCUboot bootloader
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com >
2021-09-27 18:22:29 -07:00
Xiang Xiao
007adc7736
Replace all __attribute__((section(x)) with locate_data(x)
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com >
2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72
Replace all __attribute__((aligned(x)) with aligned_data(x)
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com >
2021-07-29 21:55:21 -03:00
Sara Souza
0794991a07
risc-v/esp32-c3: Disable wdt in the start function.
2021-07-26 19:44:30 -07:00
Xiang Xiao
3f67c67aaf
arch: Fix the stack boundary calculation and check
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All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com >
2021-04-10 08:39:54 -07:00
Sara Souza
0926e7c578
risc-v/esp32-c3: Fixes gargabe UART issue, refactors serial driver, changes default pins of UART 1 and fixes low baud rate issue.
2021-04-06 11:44:06 -03:00
Abdelatif Guettouche
44ada05549
arch/risc-v: Internal functions should be prefixed with riscv_ not up_
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com >
2021-03-13 19:07:02 -03:00
Abdelatif Guettouche
39016f6d68
risc-v/esp32c3: Configure clock and call board initialize at startup.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com >
2021-02-25 22:13:26 -08:00
Sara Souza
998f7e5d4c
risc-v/esp32c3: Add basic UART support for console
2021-02-18 01:21:53 -08:00
Dong Heng
b11a5ca8b2
risc-v/esp32c3: Add ESP32-C3 basic support
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Co-authored-by: Dong Heng <dongheng@espressif.com >
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com >
2021-02-18 01:21:53 -08:00
