arm64: fix FIQ mask initialization in task state

Add FIQ bit (DAIF_FIQ_BIT) initialization to SPSR register when creating new
ARM64 tasks. By default, FIQ interrupts are masked unless CONFIG_ARM64_DECODEFIQ
is enabled. Ensures consistent FIQ masking behavior across all task contexts.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
2025-04-23 16:24:49 +08:00
committed by Xiang Xiao
parent d369c92b17
commit ffb4c101d8
@@ -91,6 +91,10 @@ void arm64_new_task(struct tcb_s * tcb)
xcp->regs[REG_SCTLR_EL1] |= SCTLR_TCF1_BIT;
#endif
#ifndef CONFIG_ARM64_DECODEFIQ
xcp->regs[REG_SPSR] |= DAIF_FIQ_BIT;
#endif
#ifdef CONFIG_SUPPRESS_INTERRUPTS
xcp->regs[REG_SPSR] |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT);
#endif /* CONFIG_SUPPRESS_INTERRUPTS */