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SAMD21: Add build framework for DMA support. Nothing there yet except for skeletal logic taken from SAM3/4.
This commit is contained in:
Gregory Nutt
@@ -270,7 +270,7 @@
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 0 /* No TC control channels */
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# define SAMDL_NTCCOUT 0 /* No TCC output channels */
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# define SAMDL_NDMA 0 /* No DMA channels */
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# define SAMDL_NDMACHAN 0 /* No DMA channels */
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# define SAMDL_NUSBIF 0 /* No USB interface */
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# define SAMDL_NAES 0 /* No AES engine */
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# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
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@@ -293,7 +293,7 @@
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 0 /* No TC control channels */
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# define SAMDL_NTCCOUT 0 /* No TCC output channels */
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# define SAMDL_NDMA 0 /* No DMA channels */
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# define SAMDL_NDMACHAN 0 /* No DMA channels */
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# define SAMDL_NUSBIF 0 /* No USB interface */
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# define SAMDL_NAES 0 /* No AES engine */
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# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
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@@ -316,7 +316,7 @@
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 0 /* No TC control channels */
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# define SAMDL_NTCCOUT 0 /* No TCC output channels */
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# define SAMDL_NDMA 0 /* No DMA channels */
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# define SAMDL_NDMACHAN 0 /* No DMA channels */
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# define SAMDL_NUSBIF 0 /* No USB interface */
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# define SAMDL_NAES 0 /* No AES engine */
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# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
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@@ -556,7 +556,7 @@
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 3 /* 3 TC control channels */
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# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMDL_NDMA 16 /* 16 DMA channels */
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# define SAMDL_NDMACHAN 16 /* 16 DMA channels */
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# define SAMDL_NUSBIF 1 /* 1 USB interface */
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# define SAMDL_NAES 1 /* 1 AES engine */
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# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
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@@ -579,7 +579,7 @@
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 3 /* 3 TC control channels */
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# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMDL_NDMA 16 /* 16 DMA channels */
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# define SAMDL_NDMACHAN 16 /* 16 DMA channels */
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# define SAMDL_NUSBIF 1 /* 1 USB interface */
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# define SAMDL_NAES 1 /* 1 AES engine */
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# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
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@@ -602,7 +602,7 @@
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# define SAMDL_NTCOUT 2 /* 2 TC output channels */
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# define SAMDL_NTCC 3 /* 3 TC control channels */
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# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMDL_NDMA 16 /* 16 DMA channels */
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# define SAMDL_NDMACHAN 16 /* 16 DMA channels */
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# define SAMDL_NUSBIF 1 /* 1 USB interface */
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# define SAMDL_NAES 1 /* 1 AES engine */
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# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
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@@ -70,7 +70,7 @@
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#ifdef CONFIG_SAM34_DMAC0
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/* If AT90SAM3U support is enabled, then OS DMA support should also be enabled */
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/* If SAM3/4 support is enabled, then OS DMA support should also be enabled */
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#ifndef CONFIG_ARCH_DMA
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# warning "SAM3/4 DMA enabled but CONFIG_ARCH_DMA disabled"
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+26
-20
@@ -291,20 +291,38 @@ config SAMDL_HAVE_TC7
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menu "SAMD/L Peripheral Support"
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config SAMDL_WDT
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bool "Watchdog Timer"
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config SAMDL_AC
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bool "Analog Comparator"
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default n
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config SAMDL_RTC
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bool "Real Time Counter"
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config SAMDL_ADC
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bool "Analog-to-Digital Converter"
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default n
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config SAMDL_DAC
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bool "Digital-to-Analog Converter"
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default n
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config SAMDL_DMAC
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bool "DMA Controller"
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default n
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select ARCH_DMA
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depends on EXPERIMENTAL
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config SAMDL_EVSYS
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bool "Event System"
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default n
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config SAMDL_NVMCTRL
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bool "Non-Volatile Memory Controller"
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default n
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config SAMDL_EVSYS
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bool "Event System"
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config SAMDL_PTC
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bool "Peripheral Touch Controller"
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default n
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config SAMDL_RTC
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bool "Real Time Counter"
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default n
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config SAMDL_SERCOM0
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@@ -370,20 +388,8 @@ config SAMDL_TC7
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default n
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depends on SAMDL_HAVE_TC7
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config SAMDL_ADC
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bool "Analog-to-Digital Converter"
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default n
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config SAMDL_AC
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bool "Analog Comparator"
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default n
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config SAMDL_DAC
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bool "Digital-to-Analog Converter"
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default n
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config SAMDL_PTC
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bool "Peripheral Touch Controller"
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config SAMDL_WDT
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bool "Watchdog Timer"
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default n
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endmenu
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@@ -1,7 +1,7 @@
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############################################################################
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# arch/arm/src/samdl/Make.defs
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#
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# Copyright (C) 2014 Gregory Nutt. All rights reserved.
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# Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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# Author: Gregory Nutt <gnutt@nuttx.org>
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#
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# Redistribution and use in source and binary forms, with or without
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@@ -89,6 +89,10 @@ ifeq ($(CONFIG_ARCH_IRQPRIO),y)
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CHIP_CSRCS += sam_irqprio.c
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endif
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ifeq ($(CONFIG_SAMDL_DMAC),y)
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CHIP_CSRCS += sam_dmac.c
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endif
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ifeq ($(CONFIG_SAMDL_HAVE_SPI),y)
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CHIP_CSRCS += sam_spi.c
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endif
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@@ -133,8 +133,8 @@
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# define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */
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#define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */
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#define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT)
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# define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */
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# define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */
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# define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */
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# define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */
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#define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */
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#define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT)
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# define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */
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@@ -246,7 +246,7 @@ trigger */
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#define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */
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#define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */
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#define DMAC_CHCTRLB_LVL_MASK (3 << DMAC_CHCTRLB_LVL_SHIFT)
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# define DMAC_CHCTRLB_LVL(n) ((uint32_t)(n) << DMAC_CHCTRLB_LVL_SHIFT) /*
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# define DMAC_CHCTRLB_LVL(n) ((uint32_t)(n) << DMAC_CHCTRLB_LVL_SHIFT)
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# define DMAC_CHCTRLB_LVL_LVL0 (0 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 0 */
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# define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */
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# define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */
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@@ -261,9 +261,9 @@ trigger */
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# define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */
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#define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */
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#define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT)
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#d efine DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */
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#d efine DMAC_CHCTRLB_CMD_SUSPEND (1 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel suspend operation */
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#d efine DMAC_CHCTRLB_CMD_RESUME (2 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel resume operation */
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# define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */
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# define DMAC_CHCTRLB_CMD_SUSPEND (1 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel suspend operation */
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# define DMAC_CHCTRLB_CMD_RESUME (2 << DMAC_CHCTRLB_CMD_SHIFT) /* Channel resume operation */
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/* Values for use with the DMAC_CHCTRLB_TRIGSRC(n) macro: */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,330 @@
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/************************************************************************************
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* arch/arm/src/samdl/sam_dmac.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_SAM_DMAC_H
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#define __ARCH_ARM_SRC_SAMDL_SAM_DMAC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "chip.h"
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#include "chip/sam_dmac.h"
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#ifdef CONFIG_SAMDL_DMAC
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#if defined(CONFIG_ARCH_FAMILY_SAMD20)
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# error Missing support for the SAMD20 architecture
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#elif defined(CONFIG_ARCH_FAMILY_SAML21)
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# include "chip/saml_dmac.h"
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#else
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# error Unrecognized SAMD/L architecture
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#ifndef CONFIG_DEBUG
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# undef CONFIG_DEBUG_DMA
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#endif
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/* DMA ******************************************************************************/
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/* Flags used to characterize the desired DMA channel. The naming convention is that
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* one side is the peripheral and the other is memory (however, the interface could still
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* be used if, for example, both sides were memory although the naming would be awkward)
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*/
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/* Common characteristics */
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#define DMACH_FLAG_BEATSIZE_SHIFT (0) /* Bits 0-1: Beat size */
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#define DMACH_FLAG_BEATSIZE_MASK (3 << DMACH_FLAG_BEATSIZE_SHIFT)
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# define DMACH_FLAG_BEATSIZE_BYTE (0 << DMACH_FLAG_BEATSIZE_SHIFT) /* 8-bit bus transfer */
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# define DMACH_FLAG_BEATSIZE_HWORD (1 << DMACH_FLAG_BEATSIZE_SHIFT) /* 16-bit bus transfer */
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# define DMACH_FLAG_BEATSIZE_WORD (2 << DMACH_FLAG_BEATSIZE_SHIFT) /* 32-bit bus transfer */
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#define DMACH_FLAG_STEPSIZE_SHIFT (2) /* Bits 2-4: Address increment step */
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#define DMACH_FLAG_STEPSIZE_MASK (7 << DMACH_FLAG_STEPSIZE_SHIFT)
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# define DMACH_FLAG_STEPSIZE_X1 (0 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */
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# define DMACH_FLAG_STEPSIZE_X2 (1 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */
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# define DMACH_FLAG_STEPSIZE_X4 (2 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 4 */
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# define DMACH_FLAG_STEPSIZE_X8 (3 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 8 */
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# define DMACH_FLAG_STEPSIZE_X16 (4 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 16 */
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# define DMACH_FLAG_STEPSIZE_X32 (5 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */
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# define DMACH_FLAG_STEPSIZE_X64 (6 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */
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# define DMACH_FLAG_STEPSIZE_X128 (7 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */
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#define DMACH_FLAG_RUNINSTDBY (1 << 5) /* Bit 5: Run in standby */
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/* Peripheral endpoint characteristics */
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#define DMACH_FLAG_PERIPHTRIG_SHIFT (6) /* Bits 6-11: See DMAC_TRIGSRC_* */
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#define DMACH_FLAG_PERIPHTRIG_MASK (0x3f << DMACH_FLAG_PERIPHTRIG_SHIFT)
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# define DMACH_FLAG_PERIPHTRIG(n) ((uint32_t)(n) << DMACH_FLAG_PERIPHTRIG_SHIFT)
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#define DMACH_FLAG_PERIPHINCREMENT (1 << 12) /* Bit 12: Autoincrement peripheral address */
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#define DMACH_FLAG_PERIPHQOS_SHIFT (14) /* Bits 14-15: Peripheral quality of service */
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#define DMACH_FLAG_PERIPHQOS_MASK (3 << DMACH_FLAG_PERIPHQOS_SHIFT)
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# define DMACH_FLAG_PERIPHQOS_DISABLE (0 << DMACH_FLAG_PERIPHQOS_SHIFT) /* Background */
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# define DMACH_FLAG_PERIPHQOS_LOW (1 << DMACH_FLAG_PERIPHQOS_SHIFT) /* Sensitve bandwidth */
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# define DMACH_FLAG_PERIPHQOS_MEDIUM (2 << DMACH_FLAG_PERIPHQOS_SHIFT) /* Sensitive latency */
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# define DMACH_FLAG_PERIPHQOS_HIGH (3 << DMACH_FLAG_PERIPHQOS_SHIFT) /* Critical latency */
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/* Memory endpoint characteristics */
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#define DMACH_FLAG_MEMINCREMENT (1 << 16) /* Bit 16: Autoincrement memory address */
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#define DMACH_FLAG_MEMQOS_SHIFT (17) /* Bits 17-18: Memory quality of service */
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#define DMACH_FLAG_MEMQOS_MASK (3 << DMACH_FLAG_MEMQOS_SHIFT)
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# define DMACH_FLAG_MEMQOS_DISABLE (0 << DMACH_FLAG_MEMQOS_SHIFT) /* Background */
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# define DMACH_FLAG_MEMQOS_LOW (1 << DMACH_FLAG_MEMQOS_SHIFT) /* Sensitve bandwidth */
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# define DMACH_FLAG_MEMQOS_MEDIUM (2 << DMACH_FLAG_MEMQOS_SHIFT) /* Sensitive latency */
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# define DMACH_FLAG_MEMQOS_HIGH (3 << DMACH_FLAG_MEMQOS_SHIFT) /* Critical latency */
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/* Bits 19-31: Not used */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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typedef FAR void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
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/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
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#ifdef CONFIG_DEBUG_DMA
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struct sam_dmaregs_s
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{
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/* DMAC Registers */
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uint8_t crcstatus; /* CRC Status Register */
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uint8_t dbgctrl; /* Debug Control Register */
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uint8_t qosctrl; /* Quality of Service Control Register */
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uint8_t chid; /* Channel ID Register */
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uint8_t chctrla; /* Channel Control A Register */
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uint8_t chintflag; /* Channel Interrupt Flag Status and Clear Register */
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uint8_t chstatus; /* Channel Status Register */
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uint16_t ctrl; /* Control Register */
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uint16_t crcctrl; /* CRC Control Register */
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uint16_t intpend; /* Interrupt Pending Register */
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uint32_t crcdatain; /* CRC Data Input Register */
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uint32_t crcchksum; /* CRC Checksum Register */
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uint32_t swtrigctrl; /* Software Trigger Control Register */
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uint32_t prictrl0; /* Priority Control 0 Register */
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uint32_t intstatus; /* Interrupt Status Register */
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uint32_t busych; /* Busy Channels Register */
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uint32_t pendch; /* Pending Channels Register */
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uint32_t active; /* Active Channels and Levels Register */
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uint32_t baseaddr; /* Descriptor Memory Section Base Address Register */
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uint32_t wrbaddr; /* Write-Back Memory Section Base Address Register */
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uint32_t chctrlb; /* Channel Control B Register */
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/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
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uint16_t btctrl; /* Block Transfer Control Register */
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uint16_t btcnt; /* Block Transfer Count Register */
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uint32_t srcaddr; /* Block Transfer Source Address Register */
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uint32_t dstaddr; /* Block Transfer Destination Address Register */
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uint32_t descaddr; /* Next Address Descriptor Register */
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};
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#endif
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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/************************************************************************************
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* Name: sam_dmachannel
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*
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* Description:
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* Allocate a DMA channel. This function sets aside a DMA channel and gives the
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* caller exclusive access to the DMA channel.
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*
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* The naming convention in all of the DMA interfaces is that one side is the
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* 'peripheral' and the other is 'memory'. However, the interface could still be
|
||||
* used if, for example, both sides were memory although the naming would be
|
||||
* awkward.
|
||||
*
|
||||
* Returned Value:
|
||||
* If a DMA channel if the required FIFO size is available, this function returns
|
||||
* a non-NULL, void* DMA channel handle. NULL is returned on any failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
DMA_HANDLE sam_dmachannel(uint32_t chflags);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmaconfig
|
||||
*
|
||||
* Description:
|
||||
* There are two channel usage models: (1) The channel is allocated and
|
||||
* configured in one step. This is the typical case where a DMA channel performs
|
||||
* a constant role. The alternative is (2) where the DMA channel is reconfigured
|
||||
* on the fly. In this case, the chflags provided to sam_dmachannel are not used
|
||||
* and sam_dmaconfig() is called before each DMA to configure the DMA channel
|
||||
* appropriately.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be
|
||||
* used again until sam_dmachannel() is called again to re-gain a valid handle.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_dmafree(DMA_HANDLE handle);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmatxsetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA for transmit of one buffer (memory to peripheral). This function
|
||||
* may be called multiple times to handle large and/or non-contiguous transfers.
|
||||
* Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the
|
||||
* same transfer, however.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t nbytes);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmarxsetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA for receipt of one buffer (peripheral to memory). This function
|
||||
* may be called multiple times to handle large and/or non-contiguous transfers.
|
||||
* Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the
|
||||
* same transfer, however.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t nbytes);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After sam_dmastop() is called, the DMA channel is
|
||||
* reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
|
||||
#else
|
||||
# define sam_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
|
||||
const char *msg);
|
||||
#else
|
||||
# define sam_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_SAMDL_DMAC */
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_DMAC_H */
|
||||
@@ -49,7 +49,24 @@
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#define sam_ahb_enableperiph(s) modifyreg32(SAM_MCLK_AHBMASK,0,s)
|
||||
|
||||
#if 0 /* Not used, conflicting names */
|
||||
#define sam_apba_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_APBA)
|
||||
#define sam_apbb_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_APBB)
|
||||
#define sam_apbc_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_APBC)
|
||||
#define sam_apbd_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_APBD)
|
||||
#define sam_apbe_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_APBE)
|
||||
#define sam_dsu_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_DSU)
|
||||
#define sam_nvmctrl_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_NVMCTRL)
|
||||
#endif
|
||||
#define sam_dmac_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_DMAC)
|
||||
#if 0 /* Not used, conflicting names */
|
||||
#define sam_usb_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_USB)
|
||||
#define sam_pac_enableperiph() sam_ahb_enableperiph(MCLK_AHBMASK_PAC)
|
||||
#endif
|
||||
|
||||
#define sam_apba_enableperiph(s) modifyreg32(SAM_MCLK_APBAMASK,0,s)
|
||||
|
||||
#define sam_pm_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_PM)
|
||||
@@ -104,6 +121,23 @@
|
||||
|
||||
#define sam_pac_enableperiph() sam_apbe_enableperiph(MCLK_APBEMASK_PAC)
|
||||
|
||||
#define sam_ahb_disableperiph(s) modifyreg32(SAM_MCLK_AHBMASK,s,0)
|
||||
|
||||
#if 0 /* Not used, conflicting names */
|
||||
#define sam_apba_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_APBA)
|
||||
#define sam_apbb_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_APBB)
|
||||
#define sam_apbc_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_APBC)
|
||||
#define sam_apbd_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_APBD)
|
||||
#define sam_apbe_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_APBE)
|
||||
#define sam_dsu_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_DSU)
|
||||
#define sam_nvmctrl_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_NVMCTRL)
|
||||
#endif
|
||||
#define sam_dmac_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_DMAC)
|
||||
#if 0 /* Not used, conflicting names */
|
||||
#define sam_usb_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_USB)
|
||||
#define sam_pac_disableperiph() sam_ahb_disableperiph(MCLK_AHBMASK_PAC)
|
||||
#endif
|
||||
|
||||
#define sam_apba_disableperiph(s) modifyreg32(SAM_MCLK_APBAMASK,s,0)
|
||||
|
||||
#define sam_pm_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_PM)
|
||||
@@ -158,6 +192,23 @@
|
||||
|
||||
#define sam_pac_disableperiph() sam_apbe_disableperiph(MCLK_APBEMASK_PAC)
|
||||
|
||||
#define sam_ahb_isenabled(s) (getreg32(SAM_MCLK_AHBMASK) & (s)) != 0)
|
||||
|
||||
#if 0 /* Not used, conflicting names */
|
||||
#define sam_apba_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_APBA)
|
||||
#define sam_apbb_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_APBB)
|
||||
#define sam_apbc_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_APBC)
|
||||
#define sam_apbd_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_APBD)
|
||||
#define sam_apbe_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_APBE)
|
||||
#define sam_dsu_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_DSU)
|
||||
#define sam_nvmctrl_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_NVMCTRL)
|
||||
#endif
|
||||
#define sam_dmac_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_DMAC)
|
||||
#if 0 /* Not used, conflicting names */
|
||||
#define sam_usb_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_USB)
|
||||
#define sam_pac_isenabled() sam_ahb_isenabled(MCLK_AHBMASK_PAC)
|
||||
#endif
|
||||
|
||||
#define sam_apba_isenabled(s) (getreg32(SAM_MCLK_APBAMASK) & (s)) != 0)
|
||||
|
||||
#define sam_pm_isenabled() sam_apba_isenabled(MCLK_APBAMASK_PM)
|
||||
|
||||
@@ -157,10 +157,13 @@ CONFIG_SAMDL_HAVE_TC3=y
|
||||
#
|
||||
# SAMD/L Peripheral Support
|
||||
#
|
||||
# CONFIG_SAMDL_WDT is not set
|
||||
# CONFIG_SAMDL_RTC is not set
|
||||
# CONFIG_SAMDL_NVMCTRL is not set
|
||||
# CONFIG_SAMDL_AC is not set
|
||||
# CONFIG_SAMDL_ADC is not set
|
||||
# CONFIG_SAMDL_DAC is not set
|
||||
# CONFIG_SAMDL_EVSYS is not set
|
||||
# CONFIG_SAMDL_NVMCTRL is not set
|
||||
# CONFIG_SAMDL_PTC is not set
|
||||
# CONFIG_SAMDL_RTC is not set
|
||||
# CONFIG_SAMDL_SERCOM0 is not set
|
||||
# CONFIG_SAMDL_SERCOM1 is not set
|
||||
# CONFIG_SAMDL_SERCOM2 is not set
|
||||
@@ -173,10 +176,7 @@ CONFIG_SAMDL_SERCOM4=y
|
||||
# CONFIG_SAMDL_TC3 is not set
|
||||
# CONFIG_SAMDL_TC4 is not set
|
||||
# CONFIG_SAMDL_TC5 is not set
|
||||
# CONFIG_SAMDL_ADC is not set
|
||||
# CONFIG_SAMDL_AC is not set
|
||||
# CONFIG_SAMDL_DAC is not set
|
||||
# CONFIG_SAMDL_PTC is not set
|
||||
# CONFIG_SAMDL_WDT is not set
|
||||
# CONFIG_SAMDL_SERCOM3_ISI2C is not set
|
||||
# CONFIG_SAMDL_SERCOM3_ISSPI is not set
|
||||
CONFIG_SAMDL_SERCOM3_ISUSART=y
|
||||
@@ -532,6 +532,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
|
||||
# CONFIG_FS_SMARTFS is not set
|
||||
# CONFIG_FS_BINFS is not set
|
||||
# CONFIG_FS_PROCFS is not set
|
||||
# CONFIG_FS_UNIONFS is not set
|
||||
|
||||
#
|
||||
# System Logging
|
||||
@@ -654,7 +655,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_EXAMPLES_NX is not set
|
||||
# CONFIG_EXAMPLES_NXTERM is not set
|
||||
# CONFIG_EXAMPLES_NXFFS is not set
|
||||
# CONFIG_EXAMPLES_NXFLAT is not set
|
||||
# CONFIG_EXAMPLES_NXHELLO is not set
|
||||
# CONFIG_EXAMPLES_NXIMAGE is not set
|
||||
# CONFIG_EXAMPLES_NXLINES is not set
|
||||
@@ -674,7 +674,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_EXAMPLES_SMART is not set
|
||||
# CONFIG_EXAMPLES_TCPECHO is not set
|
||||
# CONFIG_EXAMPLES_TELNETD is not set
|
||||
# CONFIG_EXAMPLES_THTTPD is not set
|
||||
# CONFIG_EXAMPLES_TIFF is not set
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
|
||||
# CONFIG_EXAMPLES_WEBSERVER is not set
|
||||
@@ -706,7 +705,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_NETUTILS_FTPC is not set
|
||||
# CONFIG_NETUTILS_JSON is not set
|
||||
# CONFIG_NETUTILS_SMTP is not set
|
||||
# CONFIG_NETUTILS_THTTPD is not set
|
||||
|
||||
#
|
||||
# FreeModBus
|
||||
|
||||
Reference in New Issue
Block a user