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Merged in petekol/nuttxnsm (pull request #59)

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some stm32f7 files
This commit is contained in:
Gregory Nutt
2016-06-15 12:01:30 -06:00
parent f2cac0ceb7 5a8f395a9b
commit ff7be7cead
30 changed files with 11275 additions and 32 deletions
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.gitignore
+33 -30
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@@ -1,30 +1,33 @@
.depend
Make.dep
*.o
*.a
*.d
*.i
*~
.swp
.*.swp
core
.gdbinit
cscope.out
/.config
/.config.old
/.version
/Make.defs
/setenv.sh
/setenv.bat
/nuttx
/nuttx.*
/nuttx-*
/_SAVED_APPS_config
/*.map
/*.elf
/*.srec
/*.bin
/*.ihx
/*.hex
/pcode
/tags
.depend
Make.dep
*.o
*.a
*.d
*.i
*~
.swp
.*.swp
core
.gdbinit
cscope.out
/.config
/.config.old
/.version
/Make.defs
/setenv.sh
/setenv.bat
/nuttx
/nuttx.*
/nuttx-*
/_SAVED_APPS_config
/*.map
/*.elf
/*.srec
/*.bin
/*.ihx
/*.hex
/pcode
/tags
/.settings/
/.cproject
/.project
arch/arm/src/stm32f7/Make.defs
+6 -2
View File
@@ -51,7 +51,7 @@ CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c
CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_systemreset.c up_unblocktask.c up_usestack.c
CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
# Configuration-dependent common files
@@ -114,7 +114,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
CHIP_CSRCS += stm32_start.c
CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c stm32_tim.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
@@ -139,6 +139,10 @@ ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_exti_pwr.c
endif
ifeq ($(CONFIG_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_RTC),y)
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
arch/arm/src/stm32f7/chip.h
+1
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@@ -50,6 +50,7 @@
#include <arch/stm32f7/chip.h>
#include "chip/stm32_pinmap.h"
#include "chip/stm32_memorymap.h"
#include "chip/stm32_pinmap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
arch/arm/src/stm32f7/chip/stm32_adc.h
+495
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@@ -0,0 +1,495 @@
/****************************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_adc.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
/* Register Addresses *******************************************************************************/
#if STM32F7_NADC > 0
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
#endif
#if STM32F7_NADC > 1
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
#endif
#if STM32F7_NADC > 2
# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
#endif
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* ADC status register */
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
/* ADC control register 1 */
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
/* ADC control register 2 */
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
/* Bits 12-15: Reserved */
#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
/* 0110: NA */
#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
#define ADC_CR2_JEXTSEL_T3CC3 (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
#define ADC_CR2_JEXTSEL_T5TRGO (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
#define ADC_CR2_JEXTSEL_T3CC1 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
#define ADC_CR2_JEXTSEL_T6TRGO (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
/* 1111: NA */
#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
/* Bit 23: Reserved, must be kept at reset value. */
#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
#define ADC_CR2_EXTSEL_T1TRGO2 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
#define ADC_CR2_EXTSEL_T2TRGO (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
#define ADC_CR2_EXTSEL_T4TRGO (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
#define ADC_CR2_EXTSEL_T6TRGO (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
/* 1110: NA */
#define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
/* ADC sample time register 1 */
#define ADC_SMPR_3 0 /* 000: 3 cycles */
#define ADC_SMPR_15 1 /* 001: 15 cycles */
#define ADC_SMPR_28 2 /* 010: 28 cycles */
#define ADC_SMPR_56 3 /* 011: 56 cycles */
#define ADC_SMPR_84 4 /* 100: 84 cycles */
#define ADC_SMPR_112 5 /* 101: 112 cycles */
#define ADC_SMPR_144 6 /* 110: 144 cycles */
#define ADC_SMPR_480 7 /* 111: 480 cycles */
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
/* ADC sample time register 2 */
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
/* ADC injected channel data offset register 1-4 */
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
/* ADC watchdog high threshold register */
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
/* ADC watchdog low threshold register */
#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
/* ADC regular sequence register 1 */
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
#define ADC_SQR1_RESERVED (0xff000000)
#define ADC_SQR1_FIRST (13)
#define ADC_SQR1_LAST (16)
#define ADC_SQR1_SQ_OFFSET (0)
/* ADC regular sequence register 2 */
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
#define ADC_SQR2_RESERVED (0xc0000000)
#define ADC_SQR2_FIRST (7)
#define ADC_SQR2_LAST (12)
#define ADC_SQR2_SQ_OFFSET (0)
/* ADC regular sequence register 3 */
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
#define ADC_SQR3_RESERVED (0xc0000000)
#define ADC_SQR3_FIRST (1)
#define ADC_SQR3_LAST (6)
#define ADC_SQR3_SQ_OFFSET (0)
/* Offset between SQ bits */
#define ADC_SQ_OFFSET (5)
/* ADC injected sequence register */
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
/* ADC injected data register 1-4 */
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
/* ADC regular data register */
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
/* Common status register */
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
# /* Bits 14-15: Reserved, must be kept at reset value. */
#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
/* Common control register */
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
/* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
/* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
/* Bits 5-7: Reserved, must be kept at reset value. */
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
/* Bit 12 Reserved, must be kept at reset value. */
# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */
# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT)
# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
/* Bits 18-21: Reserved, must be kept at reset value. */
# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */
# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
/* Bits 24-31 Reserved, must be kept at reset value. */
/* Data register for dual and triple modes (32-bit data with no named fields) */
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Function Prototypes
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H */
arch/arm/src/stm32f7/chip/stm32_i2c.h
+52
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@@ -0,0 +1,52 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_i2c.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_i2c.h"
#else
# error "Unsupported STM32 F7 part"
#endif
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */
arch/arm/src/stm32f7/chip/stm32_tim.h
+1127
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arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
+249
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@@ -0,0 +1,249 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
#define __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32F7_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32F7_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define STM32F7_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define STM32F7_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define STM32F7_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
#define STM32F7_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define STM32F7_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
#define STM32F7_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
#define STM32F7_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
#define STM32F7_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define STM32F7_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses ***************************************************************/
#if STM32F7_NI2C > 0
# define STM32F7_I2C1_CR1 (STM32F7_I2C1_BASE+STM32F7_I2C_CR1_OFFSET)
# define STM32F7_I2C1_CR2 (STM32F7_I2C1_BASE+STM32F7_I2C_CR2_OFFSET)
# define STM32F7_I2C1_OAR1 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR1_OFFSET)
# define STM32F7_I2C1_OAR2 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR2_OFFSET)
# define STM32F7_I2C1_TIMINGR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMINGR_OFFSET)
# define STM32F7_I2C1_TIMEOUTR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
# define STM32F7_I2C1_ISR (STM32F7_I2C1_BASE+STM32F7_I2C_ISR_OFFSET)
# define STM32F7_I2C1_ICR (STM32F7_I2C1_BASE+STM32F7_I2C_ICR_OFFSET)
# define STM32F7_I2C1_PECR (STM32F7_I2C1_BASE+STM32F7_I2C_PECR_OFFSET)
# define STM32F7_I2C1_RXDR (STM32F7_I2C1_BASE+STM32F7_I2C_RXDR_OFFSET)
# define STM32F7_I2C1_TXDR (STM32F7_I2C1_BASE+STM32F7_I2C_TXDR_OFFSET)
#endif
#if STM32F7_NI2C > 1
# define STM32F7_I2C2_CR1 (STM32F7_I2C2_BASE+STM32F7_I2C_CR1_OFFSET)
# define STM32F7_I2C2_CR2 (STM32F7_I2C2_BASE+STM32F7_I2C_CR2_OFFSET)
# define STM32F7_I2C2_OAR1 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR1_OFFSET)
# define STM32F7_I2C2_OAR2 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR2_OFFSET)
# define STM32F7_I2C2_TIMINGR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMINGR_OFFSET)
# define STM32F7_I2C2_TIMEOUTR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
# define STM32F7_I2C2_ISR (STM32F7_I2C2_BASE+STM32F7_I2C_ISR_OFFSET)
# define STM32F7_I2C2_ICR (STM32F7_I2C2_BASE+STM32F7_I2C_ICR_OFFSET)
# define STM32F7_I2C2_PECR (STM32F7_I2C2_BASE+STM32F7_I2C_PECR_OFFSET)
# define STM32F7_I2C2_RXDR (STM32F7_I2C2_BASE+STM32F7_I2C_RXDR_OFFSET)
# define STM32F7_I2C2_TXDR (STM32F7_I2C2_BASE+STM32F7_I2C_TXDR_OFFSET)
#endif
#if STM32F7_NI2C > 2
# define STM32F7_I2C3_CR1 (STM32F7_I2C3_BASE+STM32F7_I2C_CR1_OFFSET)
# define STM32F7_I2C3_CR2 (STM32F7_I2C3_BASE+STM32F7_I2C_CR2_OFFSET)
# define STM32F7_I2C3_OAR1 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR1_OFFSET)
# define STM32F7_I2C3_OAR2 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR2_OFFSET)
# define STM32F7_I2C3_TIMINGR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMINGR_OFFSET)
# define STM32F7_I2C3_TIMEOUTR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
# define STM32F7_I2C3_ISR (STM32F7_I2C3_BASE+STM32F7_I2C_ISR_OFFSET)
# define STM32F7_I2C3_ICR (STM32F7_I2C3_BASE+STM32F7_I2C_ICR_OFFSET)
# define STM32F7_I2C3_PECR (STM32F7_I2C3_BASE+STM32F7_I2C_PECR_OFFSET)
# define STM32F7_I2C3_RXDR (STM32F7_I2C3_BASE+STM32F7_I2C_RXDR_OFFSET)
# define STM32F7_I2C3_TXDR (STM32F7_I2C3_BASE+STM32F7_I2C_TXDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* Control register 1 */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
/* Control register 2 */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
/* Own address register 1 */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
/* Own address register 2 */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
/* Timeout register */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
/* Fields unique to the Interrupt and Status register */
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
/* Packet error checking register */
#define I2C_PECR_MASK (0xff)
/* Receive data register */
#define I2C_RXDR_MASK (0xff)
/* Transmit data register */
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
+7
View File
@@ -82,6 +82,7 @@
#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */
#define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */
#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */
#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */
@@ -143,6 +144,10 @@
#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */
# define STM32_ADC1_BASE 0x40012000 /* ADC1 */
# define STM32_ADC2_BASE 0x40012100 /* ADC2 */
# define STM32_ADC3_BASE 0x40012200 /* ADC3 */
# define STM32_ADCCMN_BASE 0x40012300 /* Common */
#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */
@@ -204,5 +209,7 @@
* address range
*/
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */
arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
+207
View File
@@ -0,0 +1,207 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Maximum allowed speed as per specifications for all SPIs */
#define STM32F7_SPI_CLK_MAX 27000000UL
/* Register Offsets *****************************************************************/
#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
/* Register Addresses ***************************************************************/
#if STM32F7_NSPI > 0
# define STM32F7_SPI1_CR1 (STM32_SPI1_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI1_CR2 (STM32_SPI1_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI1_SR (STM32_SPI1_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI1_DR (STM32_SPI1_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI1_CRCPR (STM32_SPI1_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI1_RXCRCR (STM32_SPI1_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI1_TXCRCR (STM32_SPI1_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 1
# define STM32F7_SPI2_CR1 (STM32_SPI2_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI2_CR2 (STM32_SPI2_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI2_SR (STM32_SPI2_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI2_DR (STM32_SPI2_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI2_CRCPR (STM32_SPI2_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI2_RXCRCR (STM32_SPI2_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI2_TXCRCR (STM32_SPI2_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 2
# define STM32F7_SPI3_CR1 (STM32_SPI3_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI3_CR2 (STM32_SPI3_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI3_SR (STM32_SPI3_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI3_DR (STM32_SPI3_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI3_CRCPR (STM32_SPI3_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI3_RXCRCR (STM32_SPI3_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI3_TXCRCR (STM32_SPI3_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 3
# define STM32F7_SPI4_CR1 (STM32_SPI4_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI4_CR2 (STM32_SPI4_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI4_SR (STM32_SPI4_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI4_DR (STM32_SPI4_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI4_CRCPR (STM32_SPI4_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI4_RXCRCR (STM32_SPI4_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI4_TXCRCR (STM32_SPI4_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 4
# define STM32F7_SPI5_CR1 (STM32_SPI5_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI5_CR2 (STM32_SPI5_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI5_SR (STM32_SPI5_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI5_DR (STM32_SPI5_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI5_CRCPR (STM32_SPI5_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI5_RXCRCR (STM32_SPI5_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI5_TXCRCR (STM32_SPI5_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 5
# define STM32F7_SPI6_CR1 (STM32_SPI6_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI6_CR2 (STM32_SPI6_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI6_SR (STM32_SPI6_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI6_DR (STM32_SPI6_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI6_CRCPR (STM32_SPI6_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI6_RXCRCR (STM32_SPI6_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI6_TXCRCR (STM32_SPI6_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* SPI Control Register 1 */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
/* SPI Control Register 2 */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_VAL(bits) ( ((bits)-1) << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
/* SPI status register */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */
arch/arm/src/stm32f7/stm32_adc.c
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arch/arm/src/stm32f7/stm32_adc.h
+774
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arch/arm/src/stm32f7/stm32_i2c.c
+2717
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arch/arm/src/stm32f7/stm32_i2c.h
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/****************************************************************************
* arch/arm/src/stm32f7/stm32_i2c.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H
#define __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
#include "chip/stm32_i2c.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F7_I2C_DYNTIMEO
# endif
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameter:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on succcess; a NULL on failure
*
****************************************************************************/
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
/****************************************************************************
* Name: stm32_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the stm32_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H */
arch/arm/src/stm32f7/stm32_tim.c
+1099
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arch/arm/src/stm32f7/stm32_tim.h
+215
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@@ -0,0 +1,215 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_tim.h
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Uros Platise <uros.platise@isotel.eu>
*
* With modifications and updates by:
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F7_STM32_TIM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/stm32_tim.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helpers **************************************************************************/
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s))
#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* TIM Device Structure */
struct stm32_tim_dev_s
{
struct stm32_tim_ops_s *ops;
};
/* TIM Modes of Operation */
typedef enum
{
STM32_TIM_MODE_UNUSED = -1,
/* One of the following */
STM32_TIM_MODE_MASK = 0x0310,
STM32_TIM_MODE_DISABLED = 0x0000,
STM32_TIM_MODE_UP = 0x0100,
STM32_TIM_MODE_DOWN = 0x0110,
STM32_TIM_MODE_UPDOWN = 0x0200,
STM32_TIM_MODE_PULSE = 0x0300,
/* One of the following */
STM32_TIM_MODE_CK_INT = 0x0000,
//STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
//STM32_TIM_MODE_CK_EXT = 0x0800,
//STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00,
/* Clock sources, OR'ed with CK_EXT */
//STM32_TIM_MODE_CK_CHINVALID = 0x0000,
//STM32_TIM_MODE_CK_CH1 = 0x0001,
//STM32_TIM_MODE_CK_CH2 = 0x0002,
//STM32_TIM_MODE_CK_CH3 = 0x0003,
//STM32_TIM_MODE_CK_CH4 = 0x0004
/* Todo: external trigger block */
} stm32_tim_mode_t;
/* TIM Channel Modes */
typedef enum
{
STM32_TIM_CH_DISABLED = 0x00,
/* Common configuration */
STM32_TIM_CH_POLARITY_POS = 0x00,
STM32_TIM_CH_POLARITY_NEG = 0x01,
/* MODES: */
STM32_TIM_CH_MODE_MASK = 0x06,
/* Output Compare Modes */
STM32_TIM_CH_OUTPWM = 0x04, /** Enable standard PWM mode, active high when counter < compare */
//STM32_TIM_CH_OUTCOMPARE = 0x06,
// TODO other modes ... as PWM capture, ENCODER and Hall Sensor
//STM32_TIM_CH_INCAPTURE = 0x10,
//STM32_TIM_CH_INPWM = 0x20
//STM32_TIM_CH_DRIVE_OC -- open collector mode
} stm32_tim_channel_t;
/* TIM Operations */
struct stm32_tim_ops_s
{
/* Basic Timers */
int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
/* General and Advanced Timers Adds */
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode);
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare);
int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
/* Timer interrupts */
int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source);
void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
};
/************************************************************************************
* Public Functions
************************************************************************************/
/* Power-up timer and get its structure */
FAR struct stm32_tim_dev_s *stm32_tim_init(int timer);
/* Power-down timer, mark it as unused */
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
/****************************************************************************
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* timer - the timer number.
*
* Returned Values:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_TIMER
int stm32_timer_initialize(FAR const char *devpath, int timer);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_TIM_H */
configs/stm32f746-ws/Kconfig
+8
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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_STM32F746_WS
endif # ARCH_BOARD_STM32F746_WS
configs/stm32f746-ws/include/board.h
+252
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/************************************************************************************
* configs/stm32f746-ws/include/board.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Author: Mark Olsson <post@markolsson.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIG_STM32F746_WS_INCLUDE_BOARD_H
#define __CONFIG_STM32F746_WS_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#ifdef __KERNEL__
#include "stm32_rcc.h"
#ifdef CONFIG_STM32F7_SDMMC1
# include "stm32_sdmmc.h"
#endif
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocking *************************************************************************/
/* The STM32F7 Discovery board provides the following clock sources:
*
* X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board)
* X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY.
* X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC
*
* So we have these clock source available within the STM32
*
* HSI: 16 MHz RC factory-trimmed
* LSI: 32 KHz RC
* HSE: On-board crystal frequency is 25MHz
* LSE: 32.768 kHz
*/
#define STM32_BOARD_XTAL 8000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* Main PLL Configuration.
*
* PLL source is HSE = 8,000,000
*
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* Subject to:
*
* 2 <= PLLM <= 63
* 192 <= PLLN <= 432
* 192 MHz <= PLL_VCO <= 432MHz
*
* SYSCLK = PLL_VCO / PLLP
* Subject to
*
* PLLP = {2, 4, 6, 8}
* SYSCLK <= 216 MHz
*
* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
* Subject to
* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
* and the random number generator need a frequency lower than or equal
* to 48 MHz to work correctly.
*
* 2 <= PLLQ <= 15
*/
/* Highest SYSCLK with USB OTG FS clock <= 48MHz
*
* PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz
* SYSCLK = 432 MHz / 2 = 216 MHz
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432)
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
/* Several prescalers allow the configuration of the two AHB buses, the
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
* the low-speed APB domain is 54 MHz.
*/
/* AHB clock (HCLK) is SYSCLK (216 MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB2 will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1
*/
#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
/* FLASH wait states
*
* --------- ---------- -----------
* VDD MAX SYSCLK WAIT STATES
* --------- ---------- -----------
* 1.7-2.1 V 180 MHz 8
* 2.1-2.4 V 216 MHz 9
* 2.4-2.7 V 216 MHz 8
* 2.7-3.6 V 216 MHz 7
* --------- ---------- -----------
*/
#define BOARD_FLASH_WAITSTATES 7
/* Alternate function pin selections ************************************************/
/* USART6:
*
* These configurations assume that you are using a standard Arduio RS-232 shield
* with the serial interface with RX on pin D0 and TX on pin D1:
*
* -------- ---------------
* STM32F7
* ARDUIONO FUNCTION GPIO
* -- ----- --------- -----
* DO RX USART6_RX PC7
* D1 TX USART6_TX PC6
* -- ----- --------- -----
*/
#define GPIO_USART6_RX GPIO_USART6_RX_1
#define GPIO_USART6_TX GPIO_USART6_TX_1
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32_boardinitialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIG_STM32F746_WS_INCLUDE_BOARD_H */
configs/stm32f746-ws/nsh/Make.defs
+113
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@@ -0,0 +1,113 @@
############################################################################
# configs/stm32f746-ws/nsh/Make.defs
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = flash.ld
ifeq ($(WINTOOL),y)
# Windows-native toolchains
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
AR = $(ARCROSSDEV)ar rcs
NM = $(ARCROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ARCHCFLAGS = -fno-builtin
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHDEFINES =
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
ASMEXT = .S
OBJEXT = .o
LIBEXT = .a
EXEEXT =
ifneq ($(CROSSDEV),arm-nuttx-elf-)
LDFLAGS += -nostartfiles -nodefaultlibs
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =
configs/stm32f746-ws/nsh/defconfig
+930
View File
File diff suppressed because it is too large Load Diff
configs/stm32f746-ws/nsh/setenv.sh
+77
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@@ -0,0 +1,77 @@
#!/bin/bash
# configs/stm32f746-ws/nsh/setenv.sh
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
if [ "$_" = "$0" ] ; then
echo "You must source this script, not run it!" 1>&2
exit 1
fi
WD=`pwd`
if [ ! -x "setenv.sh" ]; then
echo "This script must be executed from the top-level NuttX build directory"
exit 1
fi
if [ -z "${PATH_ORIG}" ]; then
export PATH_ORIG="${PATH}"
fi
# This is the Cygwin path to the location where I installed the Atmel GCC
# toolchain under Windows. You will also have to edit this if you install
# this toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
# This is the Cygwin path to the location where I installed the CodeSourcery
# toolchain under windows. You will also have to edit this if you install
# the CodeSourcery toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
export TOOLCHAIN_BIN="/cygdrive/c/Users/Public/tools/bin"
# This is the path to the location where I installed the devkitARM toolchain
# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
# This is the Cygwin path to the location where I build the buildroot
# toolchain.
# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
# Add the path to the toolchain to the PATH varialble
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
echo "PATH : ${PATH}"
configs/stm32f746-ws/scripts/flash.ld
+147
View File
@@ -0,0 +1,147 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/flash.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Modified 11/4/2013 for STM32F429 support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
* be accessed from either the AXIM interface at address 0x0800:0000 or from
* the ITCM interface at address 0x0020:0000.
*
* Additional information, including the option bytes, is available at at
* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
*
* In the STM32F746NGH6, two different boot spaces can be selected through
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
* BOOT_ADD1 option bytes:
*
* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
* ST programmed value: Flash on ITCM at 0x0020:0000
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified STM32F746G
* DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
* to address 0x0020:0000 in ITCM FLASH.
*
* The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
* SRAM is split up into three blocks:
*
* 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
* 2) 240Kb of SRAM1 beginning at address 0x2001:0000
* 3) 16Kb of SRAM2 beginning at address 0x2004:c000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*/
MEMORY
{
itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K
sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : {
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram1 AT > flash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram1
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
configs/stm32f746-ws/scripts/kernel-space.ld
+109
View File
@@ -0,0 +1,109 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/kernel-space.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > kflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
configs/stm32f746-ws/scripts/memory.ld
+129
View File
@@ -0,0 +1,129 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/memory.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
* be accessed from either the AXIM interface at address 0x0800:0000 or from
* the ITCM interface at address 0x0020:0000.
*
* Additional information, including the option bytes, is available at at
* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
*
* In the STM32F746NGH6, two different boot spaces can be selected through
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
* BOOT_ADD1 option bytes:
*
* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
* ST programmed value: Flash on ITCM at 0x0020:0000
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified STM32F746G
* DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
* to address 0x0020:0000 in ITCM FLASH.
*
* The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
* SRAM is split up into three blocks:
*
* 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
* 2) 240Kb of SRAM1 beginning at address 0x2001:0000
* 3) 16Kb of SRAM2 beginning at address 0x2004:c000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*
* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
* FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
* should fit into 64KB and, of course, can be optimized as needed (See
* also configs/stm32f746g-disco/scripts/kernel-space.ld). Allowing the
* additional does permit addition debug instrumentation to be added to the
* kernel space without overflowing the partition.
*
* Alignment of the user space FLASH partition is also a critical factor:
* The user space FLASH partition will be spanned with a single region of
* size 2**n bytes. The alignment of the user-space region must be the same.
* As a consequence, as the user-space increases in size, the alignment
* requirement also increases.
*
* This alignment requirement means that the largest user space FLASH region
* you can have will be 512KB at it would have to be positioned at
* 0x08800000. If you change this address, don't forget to change the
* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
* the check in kernel/userspace.c.
*
* For the same reasons, the maximum size of the SRAM mapping is limited to
* 4KB. Both of these alignment limitations could be reduced by using
* multiple regions to map the FLASH/SDRAM range or perhaps with some
* clever use of subregions.
*
* A detailed memory map for the 112KB SRAM region is as follows:
*
* 0x20001 0000: Kernel .data region. Typical size: 0.1KB
* ------- ---- Kernel .bss region. Typical size: 1.8KB
* 0x20001 0800: Kernel IDLE thread stack (approximate). Size is
* determined by CONFIG_IDLETHREAD_STACKSIZE and
* adjustments for alignment. Typical is 1KB.
* ------- ---- Padded to 4KB
* 0x20001 1000: User .data region. Size is variable.
* ------- ---- User .bss region Size is variable.
* 0x20001 2000: Beginning of kernel heap. Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE.
* ------- ---- Beginning of user heap. Can vary with other settings.
* 0x20004 c000: End+1 of SRAM1
*/
MEMORY
{
/* ITCM boot address */
itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
/* 1024KB FLASH */
kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K
/* 240KB of contiguous SRAM1 */
ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K
usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K
xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K
/* DTCM SRAM */
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
}
configs/stm32f746-ws/scripts/user-space.ld
+111
View File
@@ -0,0 +1,111 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/user-space.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
SECTIONS
{
.userspace : {
*(.userspace)
} > uflash
.text : {
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > uflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > uflash
.ARM.extab : {
*(.ARM.extab*)
} > uflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > uflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > usram AT > uflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > usram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
configs/stm32f746-ws/src/.gitignore
+2
View File
@@ -0,0 +1,2 @@
/.depend
/Make.dep
configs/stm32f746-ws/src/Makefile
+45
View File
@@ -0,0 +1,45 @@
############################################################################
# configs/stm32f746-ws/src/Makefile
#
# Copyright (C) 2015 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = stm32_boot.c stm32_spi.c
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += stm32_appinitialize.c
endif
include $(TOPDIR)/configs/Board.mk
configs/stm32f746-ws/src/stm32_appinitialize.c
+97
View File
@@ -0,0 +1,97 @@
/****************************************************************************
* config/stm32f746-ws/src/stm32_appinitilaize.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Author: Mark Olsson <post@markolsson.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <syslog.h>
#include <debug.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/leds/userled.h>
#include "stm32f746-ws.h"
#include "stm32_i2c.h"
static void stm32_i2c_register(int bus)
{
FAR struct i2c_master_s *i2c;
int ret;
i2c = stm32_i2cbus_initialize(bus);
if (i2c == NULL)
{
serr("ERROR: Failed to get I2C%d interface\n", bus);
}
else
{
ret = i2c_register(i2c, bus);
if (ret < 0)
{
serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
stm32_i2cbus_uninitialize(i2c);
}
}
}
static void stm32_i2ctool(void)
{
stm32_i2c_register(1);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
****************************************************************************/
int board_app_initialize(void)
{
/* Register I2C drivers on behalf of the I2C tool */
stm32_i2ctool();
return OK;
}
configs/stm32f746-ws/src/stm32_boot.c
+106
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/************************************************************************************
* configs/stm32f746-ws/src/stm32_boot.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "stm32f746-ws.h"
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32_boardinitialize(void)
{
#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
* stm32_spidev_initialize() has been brought into the link.
*/
if (stm32_spidev_initialize)
{
stm32_spidev_initialize();
}
#endif
}
/************************************************************************************
* Name: board_initialize
*
* Description:
* If CONFIG_BOARD_INITIALIZE is selected, then an additional initialization call
* will be performed in the boot-up sequence to a function called
* board_initialize(). board_initialize() will be called immediately after
* up_initialize() is called and just before the initial application is started.
* This additional initialization phase may be used, for example, to initialize
* board-specific device drivers.
*
************************************************************************************/
#ifdef CONFIG_BOARD_INITIALIZE
void board_initialize(void)
{
#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
/* Perform NSH initialization here instead of from the NSH. This
* alternative NSH initialization is necessary when NSH is ran in user-space
* but the initialization function must run in kernel space.
*/
(void)board_app_initialize();
#endif
}
#endif
configs/stm32f746-ws/src/stm32_spi.c
+257
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/************************************************************************************
* configs/nucleo-144/src/stm32_spi.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/spi/spi.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_spi.h"
#include "stm32f746-ws.h"
#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef SPI_VERBOSE
# define spivdbg lldbg
# else
# define spivdbg(x...)
# endif
#else
# undef SPI_VERBOSE
# define spidbg(x...)
# define spivdbg(x...)
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the stm32f746g-disco board.
*
************************************************************************************/
void weak_function stm32_spidev_initialize(void)
{
}
/****************************************************************************
* Name: stm32_spi1-6 select and stm32_spi1-6 status
*
* Description:
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
* provided by board-specific logic. They are implementations of the select
* and status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize())
* are provided by common STM32 logic. To use this common SPI logic on your
* board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
* board-specific logic. These functions will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 3. Add a calls to stm32_spibus_initialize() in your low level application
* initialization logic
* 4. The handle returned by stm32_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_STM32F7_SPI1
void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI2
void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI3
void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI4
void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI5
void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI6
void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
/****************************************************************************
* Name: stm32_spi1cmddata
*
* Description:
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
* or command (false). This function must be provided by platform-specific
* logic. This is an implementation of the cmddata method of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
*
* Input Parameters:
*
* spi - SPI device that controls the bus the device that requires the CMD/
* DATA selection.
* devid - If there are multiple devices on the bus, this selects which one
* to select cmd or data. NOTE: This design restricts, for example,
* one one SPI display per SPI bus.
* cmd - true: select command; false: select data
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32F7_SPI1
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI2
int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI3
int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI4
int stm32_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI5
int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI6
int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */
configs/stm32f746-ws/src/stm32f746-ws.h
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/****************************************************************************************************
* configs/stm32f746-ws/src/stm32f746-ws.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Author: Mark Olsson <post@markolsson.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H
#define __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* procfs File System */
#ifdef CONFIG_FS_PROCFS
# ifdef CONFIG_NSH_PROC_MOUNTPOINT
# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
# else
# define STM32_PROCFS_MOUNTPOINT "/proc"
# endif
#endif
/* STM32F736G Discovery GPIOs ***********************************************************************/
/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the reset button, that
* can be controlled by software (LD2 is a power indicator, LD3-6 indicate USB status, LD7 is
* controlled by the ST-Link).
*
* LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface. One end of LD1 is
* grounded so a high output on PI1 will illuminate the LED.
*/
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN14)
#define LED_DRIVER_PATH "/dev/userleds"
/* Pushbutton B1, labelled "User", is connected to GPIO PC13. A high value will be sensed when the
* button is depressed. Note that the EXTI interrupt is configured.
*/
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
/****************************************************************************************************
* Public data
****************************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the stm32f746g-disco board.
*
****************************************************************************************************/
void weak_function stm32_spidev_initialize(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H */