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Merge branch 'master' into l432kc

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This commit is contained in:
Sebastien Lorquet
2017-05-09 08:42:13 +02:00
parent c597202ac7 407fed41ef
commit ff4f5fdba2
134 changed files with 22012 additions and 2707 deletions
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Documentation/NuttXCCodingStandard.html
+17 -3
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@@ -12,7 +12,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: April 18, 2017</p>
<p>Last Updated: May 6, 2017</p>
</td>
</tr>
</table>
@@ -405,8 +405,11 @@
<p>
<b>Line Spacing</b>
A single blank line should precede and follow each comment.
The only exception is for the file header block comment that begins on line one;
The only exceptions are (1) for the file header block comment that begins on line one;
there is no preceding blank line in that case.
And (2) for conditional compilation.
Conditional compilation should include the conditional logic <i>and</i> all comments associated with the conditional logic.
In this case, the blank line appears <i>before</i> the conditional, not after it.
</p>
<center><table width="60%" border=1>
<tr><td bgcolor="white">
@@ -416,6 +419,12 @@
a = b;
/* set b equal to c */
b = c;
/* Do the impossible */
#ifdef CONFIG_THE_IMPOSSIBLE
the_impossible();
#endif
</ul></pre></font>
</td></tr>
<tr><td bgcolor="white">
@@ -430,6 +439,11 @@
b = c;
#ifdef CONFIG_THE_IMPOSSIBLE
/* Do the impossible */
the_impossible();
#endif
</ul></pre></font>
</td></tr>
</table></center>
@@ -1611,7 +1625,7 @@ enum xyz_state_e
</li>
<li>
<b>Lowercase Exceptions</b>.
There are3 a few lower case values in NuttX macro names. Such as a lower-case <code>p</code> for a period or decimal point (such as <code>VOLTAGE_3p3V</code>).
There are a few lower case values in NuttX macro names. Such as a lower-case <code>p</code> for a period or decimal point (such as <code>VOLTAGE_3p3V</code>).
I have also used lower-case <code>v</code> for a version number (such as <code>CONFIG_NET_IPv6</code>).
However, these are exceptions to the rule rather than illustrating a rule.
</li>
Documentation/README.html
+2
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@@ -208,6 +208,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mx7mmb/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- pic32mz-starterkit/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mz-starterkit/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- photon/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/photon/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- qemu-i486/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/qemu-i486/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- sabre-6quad/
Kconfig
+1 -1
View File
@@ -756,7 +756,7 @@ config DEBUG_WIRELESS
default n
depends on WIRELESS || DRIVERS_WIRELESS
---help---
Enable DEBUG_WIRELESS debug features.
Enable wireless debug features.
if DEBUG_WIRELESS
README.txt
+2
View File
@@ -1580,6 +1580,8 @@ nuttx/
| | `- README.txt
| |- pic32mz-starterkit/
| | `- README.txt
| |- photon/
| | `- README.txt
| |- qemu-i486/
| | `- README.txt
| |- sabre-6quad/
arch/arm/Kconfig
+1
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@@ -76,6 +76,7 @@ config ARCH_CHIP_KINETIS
select ARCH_HAVE_FPU
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_I2CRESET
---help---
Freescale Kinetis Architectures (ARM Cortex-M4)
arch/arm/include/kinetis/chip.h
+3 -2
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@@ -1438,8 +1438,9 @@
# define KINETIS_NDAC6 4 /* Four 6-bit DAC */
# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
# define KINETIS_NVREF 1 /* Voltage reference */
# define KINETIS_NTIMERS8 2 /* ? Two 8 channel timers */
# define KINETIS_NTIMERS2 2 /* ? Two 2 channel timers */
# define KINETIS_NTIMERS8 2 /* Two 8 channel FTM timers */
# define KINETIS_NTIMERS2 2 /* Two 2 channel FTM timers */
# define KINETIS_NTPMTIMERS2 2 /* Two 2 channel TPM timers */
# define KINETIS_NRTC 1 /* Real time clock */
# define KINETIS_NRNG 1 /* Random number generator */
# define KINETIS_NMMCAU 1 /* Hardware encryption */
arch/arm/include/stm32l4/chip.h
+76 -1
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@@ -68,7 +68,7 @@
* Parts STM32L4x6xE have 512Kb of FLASH
* Parts STM32L4x6xG have 1024Kb of FLASH
*
* The correct FLASH size must be set with a CONFIG_STM32L4_FLASH_*KB
* The correct FLASH size must be set with a CONFIG_STM32L4_FLASH_CONFIG_*
* selection.
*/
@@ -78,10 +78,18 @@
#elif defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
defined(CONFIG_STM32L4_STM32L462XX)
# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
#elif defined(CONFIG_STM32L4_STM32L432XX)
# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
#else
# error "Unsupported STM32L4 chip"
#endif
#if defined(CONFIG_STM32L4_STM32L4X6)
# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
@@ -100,6 +108,7 @@
# define STM32L4_NI2C 3 /* I2C1-3 */
#endif
# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
# define STM32L4_NUSBFS 0 /* No USB FS */
#if defined(CONFIG_STM32L4_STM32L496XX)
# define STM32L4_NCAN 2 /* CAN1-2 */
#else
@@ -118,6 +127,72 @@
# define STM32L4_NCRC 1 /* CRC */
# define STM32L4_NCOMP 2 /* Comparators */
# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32L4_STM32L4X6 */
#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
defined(CONFIG_STM32L4_STM32L462XX)
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
# define STM32L4_NUART 1 /* UART 4 */
# define STM32L4_NUSART 3 /* USART 1-3 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_NSPI 3 /* SPI1-3 */
# define STM32L4_NI2C 4 /* I2C1-4 */
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
#if defined(CONFIG_STM32L4_STM32L451XX)
# define STM32L4_NUSBFS 0 /* No USB FS */
#else
# define STM32L4_NUSBFS 1 /* USB FS */
#endif
# define STM32L4_NCAN 1 /* CAN1 */
# define STM32L4_NSAI 1 /* SAI1 */
#if defined(CONFIG_STM32L4_HAVE_SDMMC1)
# define STM32L4_NSDMMC 1 /* SDMMC interface */
#else
# define STM32L4_NSDMMC 0 /* No SDMMC interface */
#endif
# define STM32L4_NDMA 2 /* DMA1-2 */
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */
# define STM32L4_NDAC 1 /* 12-bit DAC1 */
# define STM32L4_NCRC 1 /* CRC */
# define STM32L4_NCOMP 2 /* Comparators */
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
#endif /* CONFIG_STM32L4_STM32L451XX */
#if defined(CONFIG_STM32L4_STM32L432XX)
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
# define STM32L4_NUART 0 /* No UART */
# define STM32L4_NUSART 2 /* USART 1-2 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_NSPI 2 /* SPI1, SPI3 */
# define STM32L4_NI2C 2 /* I2C1, I2C3 */
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
# define STM32L4_NUSBFS 1 /* USB FS */
# define STM32L4_NCAN 1 /* CAN1 */
# define STM32L4_NSAI 1 /* SAI1 */
# define STM32L4_NSDMMC 0 /* No SDMMC interface */
# define STM32L4_NDMA 2 /* DMA1-2 */
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
# define STM32L4_NCRC 1 /* CRC */
# define STM32L4_NCOMP 2 /* Comparators */
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
#endif /* CONFIG_STM32L4_STM32L432XX */
/* NVIC priority levels *************************************************************/
/* 16 Programmable interrupt levels */
arch/arm/include/stm32l4/irq.h
+3 -2
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@@ -76,9 +76,10 @@
#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6)
# include <arch/stm32l4/stm32l4x6xx_irq.h>
#elif defined(CONFIG_STM32L4_STM32L4X3)
# include <arch/stm32l4/stm32l4x3xx_irq.h>
#else
# error "Unsupported STM32 L4 chip"
#endif
arch/arm/include/stm32l4/stm32l4x3xx_irq.h
+185
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@@ -0,0 +1,185 @@
/****************************************************************************************************
* arch/arm/include/stm32l4/stm32l4x3xx_irq.h
*
* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
* Authors: Sebastien Lorquet <sebastien@lorquet.fr>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32L4_STM32L4X3XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32L4_STM32L4X3XX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
*
* External interrupts (vectors >= 16)
*/
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 12: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 13: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 14: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 15: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 16: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 17: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST+18) /* 18: ADC1 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
/* Reserved */ /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
/* Reserved */ /* 42-48: reserved */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
/* Reserved */ /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST+52) /* 52: UART4 global interrupt */
/* Reserved */ /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST+56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST+57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST+58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST+59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST+60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST+61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST+62) /* 62: DFSDM1 global interrupt*/
/* Reserved */ /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST+64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST+65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST+66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST+67) /* 67: USB event interrupt through EXTI line 17 */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST+68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST+69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST+70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST+71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST+74) /* 74: SAI1 global interrupt */
/* Reserved */ /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST+76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST+77) /* 77: TSC global interrupt */
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST+78) /* 78: LCD global interrupt */
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST+79) /* 79: AES crypto global interrupt */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST+80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST+82) /* 82: CRS global interrupt */
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST+83) /* 83: I2C4 event interrupt */
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST+84) /* 84: I2C4 error interrupt */
#if defined(CONFIG_STM32L4_STM32L4X3)
# define NR_INTERRUPTS 85
#else
# error "Unsupported STM32L4 chip"
#endif
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32L4_STM32L4X3XX_IRQ_H */
arch/arm/src/kinetis/Kconfig
+88 -1
View File
@@ -239,6 +239,10 @@ config KINETIS_HAVE_LPUART1
# will automatically be selected and will represent the 'OR' of the
# instances selected.
config KINETIS_SERIALDRIVER
bool
default n
config KINETIS_LPUART
bool
default n
@@ -268,15 +272,23 @@ config ARCH_FAMILY_K60
config ARCH_FAMILY_K64
bool
default n
select KINETIS_HAVE_FTM3
select KINETIS_HAVE_UART5
config ARCH_FAMILY_K66
bool
default n
select KINETIS_HAVE_FTM3
select KINETIS_HAVE_LPUART0
select KINETIS_HAVE_TPM1
select KINETIS_HAVE_TPM2
menu "Kinetis Peripheral Support"
config KINETIS_HAVE_FTM3
bool
default n
config KINETIS_HAVE_I2C1
bool
default n
@@ -297,6 +309,14 @@ config KINETIS_HAVE_SPI2
bool
default n
config KINETIS_HAVE_TPM1
bool
default n
config KINETIS_HAVE_TPM2
bool
default n
config KINETIS_TRACE
bool "Trace"
default n
@@ -314,6 +334,8 @@ config KINETIS_UART0
default n
select UART0_SERIALDRIVER
select KINETIS_UART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support UART0
@@ -322,6 +344,8 @@ config KINETIS_UART1
default n
select UART1_SERIALDRIVER
select KINETIS_UART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support UART1
@@ -330,6 +354,8 @@ config KINETIS_UART2
default n
select UART2_SERIALDRIVER
select KINETIS_UART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support UART2
@@ -338,6 +364,8 @@ config KINETIS_UART3
default n
select UART3_SERIALDRIVER
select KINETIS_UART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support UART3
@@ -346,6 +374,8 @@ config KINETIS_UART4
default n
select UART4_SERIALDRIVER
select KINETIS_UART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support UART4
@@ -355,6 +385,8 @@ config KINETIS_UART5
depends on KINETIS_HAVE_UART5
select UART5_SERIALDRIVER
select KINETIS_UART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support UART5
@@ -364,6 +396,8 @@ config KINETIS_LPUART0
depends on KINETIS_HAVE_LPUART0
select OTHER_UART_SERIALDRIVER
select KINETIS_LPUART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support the low power UART0
@@ -373,6 +407,8 @@ config KINETIS_LPUART1
depends on KINETIS_HAVE_LPUART1
select OTHER_UART_SERIALDRIVER
select KINETIS_LPUART
select KINETIS_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Support the low power UART1
@@ -531,10 +567,24 @@ config KINETIS_FTM2
config KINETIS_FTM3
bool "FTM3"
default n
depends on ARCH_FAMILY_K64 || ARCH_FAMILY_K66
depends on KINETIS_HAVE_FTM3
---help---
Support FlexTimer 3
config KINETIS_TPM1
bool "TPM1"
default n
depends on KINETIS_HAVE_TPM1
---help---
Support TPM module 1
config KINETIS_TPM2
bool "TPM2"
default n
depends on KINETIS_HAVE_TPM2
---help---
Support TPM module 2
config KINETIS_LPTIMER
bool "Low power timer (LPTIMER)"
default n
@@ -903,6 +953,43 @@ endmenu # Kinetis SDHC Configuration
#
menu "Kinetis UART Configuration"
if KINETIS_SERIALDRIVER || OTHER_SERIALDRIVER
comment "Serial Driver Configuration"
config KINETIS_UART_BREAKS
bool "Add TIOxSBRK to support sending Breaks"
depends on KINETIS_UART || KINETIS_LPUART
default n
---help---
Add TIOCxBRK routines to send a line break per the Kinetis manual, the
break will be a pulse based on the value M. This is not a BSD compatible
break.
config KINETIS_UART_EXTEDED_BREAK
bool "Selects a longer transmitted break character length"
depends on KINETIS_UART_BREAKS
default n
---help---
Sets BRK13 to send a longer transmitted break character.
config KINETIS_SERIALBRK_BSDCOMPAT
bool "BSD compatible break the break asserted until released"
depends on (KINETIS_UART || KINETIS_LPUART) && KINETIS_UART_BREAKS
default n
---help---
Enable using a BSD compatible break: TIOCSBRK will start the break
and TIOCCBRK will end the break.
config KINETIS_UART_SINGLEWIRE
bool "Single Wire Support"
default n
depends on KINETIS_UART || KINETIS_LPUART
---help---
Enable single wire UART and LPUART support. The option enables support
for the TIOCSSINGLEWIRE ioctl in the Kineteis serial drivers.
endif # KINETIS_SERIALDRIVER || OTHER_SERIALDRIVER
config KINETIS_UARTFIFOS
bool "Enable UART0 FIFO"
arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
+11 -10
View File
@@ -1,8 +1,9 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -159,14 +160,14 @@
# define PIN_FTM2_QD_PHA (PIN_ALT6 | PIN_PORTB | PIN18)
# define PIN_FTM2_QD_PHB (PIN_ALT6 | PIN_PORTB | PIN19)
# define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
# define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2)
# define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1)
# define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3)
# define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10)
# define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1)
# define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11)
# define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0)
# define PIN_I2C0_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN0)
# define PIN_I2C0_SCL_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN2)
# define PIN_I2C0_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN1)
# define PIN_I2C0_SDA_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN3)
# define PIN_I2C1_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN10)
# define PIN_I2C1_SCL_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN1)
# define PIN_I2C1_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN11)
# define PIN_I2C1_SDA_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN0)
# define PIN_I2S0_MCLK_1 (PIN_ALT4 | PIN_PORTC | PIN8)
# define PIN_I2S0_MCLK_2 (PIN_ALT6 | PIN_PORTC | PIN6)
arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
+11 -10
View File
@@ -1,8 +1,9 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -160,7 +161,7 @@
#define PIN_ADC0_SE8 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_ADC1_SE8 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_TSI0_CH0 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN0)
#define PIN_FTM1_CH0_3 (PIN_ALT3 | PIN_PORTB | PIN0)
#define PIN_FTM1_QD_PHA_3 (PIN_ALT6 | PIN_PORTB | PIN0)
#define PIN_LCD_P0F (PIN_ALT7 | PIN_PORTB | PIN0)
@@ -168,21 +169,21 @@
#define PIN_ADC0_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
#define PIN_ADC1_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
#define PIN_TSI0_CH6 (PIN_ANALOG | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN1)
#define PIN_FTM1_CH1_3 (PIN_ALT3 | PIN_PORTB | PIN1)
#define PIN_FTM1_QD_PHB (PIN_ALT6 | PIN_PORTB | PIN1)
#define PIN_LCD_P1F (PIN_ALT7 | PIN_PORTB | PIN1)
#define PIN_LCD_P2 (PIN_ANALOG | PIN_PORTB | PIN2)
#define PIN_ADC0_SE12 (PIN_ANALOG | PIN_PORTB | PIN2)
#define PIN_TSI0_CH7 (PIN_ANALOG | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_2 (PIN_ALT2_OPENDRAIN| PIN_PORTB | PIN2)
#define PIN_UART0_RTS_3 (PIN_ALT3 | PIN_PORTB | PIN2)
#define PIN_FTM0_FLT3 (PIN_ALT6 | PIN_PORTB | PIN2)
#define PIN_LCD_P2F (PIN_ALT7 | PIN_PORTB | PIN2)
#define PIN_LCD_P3 (PIN_ANALOG | PIN_PORTB | PIN3)
#define PIN_ADC0_SE13 (PIN_ANALOG | PIN_PORTB | PIN3)
#define PIN_TSI0_CH8 (PIN_ANALOG | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN3)
#define PIN_UART0_CTS_3 (PIN_ALT3 | PIN_PORTB | PIN3)
#define PIN_FTM0_FLT0_1 (PIN_ALT6 | PIN_PORTB | PIN3)
#define PIN_LCD_P3F (PIN_ALT7 | PIN_PORTB | PIN3)
@@ -325,12 +326,12 @@
#define PIN_LCD_P30 (PIN_ANALOG | PIN_PORTC | PIN10)
#define PIN_ADC1_SE6B (PIN_ANALOG | PIN_PORTC | PIN10)
#define PIN_CMP0_IN4 (PIN_ANALOG | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN10)
#define PIN_I2S0_RX_FS_2 (PIN_ALT4 | PIN_PORTC | PIN10)
#define PIN_LCD_P30F (PIN_ALT7 | PIN_PORTC | PIN10)
#define PIN_LCD_P31 (PIN_ANALOG | PIN_PORTC | PIN11)
#define PIN_ADC1_SE7B (PIN_ANALOG | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN11)
#define PIN_I2S0_RXD_2 (PIN_ALT4 | PIN_PORTC | PIN11)
#define PIN_LCD_P31F (PIN_ALT7 | PIN_PORTC | PIN11)
#define PIN_LCD_P32 (PIN_ANALOG | PIN_PORTC | PIN12)
@@ -427,13 +428,13 @@
#define PIN_UART1_TX_2 (PIN_ALT3 | PIN_PORTE | PIN0)
#define PIN_SDHC0_D1 (PIN_ALT4 | PIN_PORTE | PIN0)
#define PIN_FB_AD27 (PIN_ALT5 | PIN_PORTE | PIN0)
#define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0)
#define PIN_I2C1_SDA_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN0)
#define PIN_ADC1_SE5A (PIN_ANALOG | PIN_PORTE | PIN1)
#define PIN_SPI1_SOUT_2 (PIN_ALT2 | PIN_PORTE | PIN1)
#define PIN_UART1_RX_2 (PIN_ALT3 | PIN_PORTE | PIN1)
#define PIN_SDHC0_D0 (PIN_ALT4 | PIN_PORTE | PIN1)
#define PIN_FB_AD26 (PIN_ALT5 | PIN_PORTE | PIN1)
#define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1)
#define PIN_I2C1_SCL_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN1)
#define PIN_ADC1_SE6A (PIN_ANALOG | PIN_PORTE | PIN2)
#define PIN_SPI1_SCK_2 (PIN_ALT2 | PIN_PORTE | PIN2)
#define PIN_UART1_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN2)
arch/arm/src/kinetis/chip/kinetis_k60pinmux.h
+13 -12
View File
@@ -1,8 +1,9 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k60pinset.h
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -172,7 +173,7 @@
#define PIN_ADC0_SE8 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_ADC1_SE8 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_TSI0_CH0 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN0)
#define PIN_FTM1_CH0_3 (PIN_ALT3 | PIN_PORTB | PIN0)
#ifdef CONFIG_KINETIS_ENET_MDIOPULLUP
# define PIN_RMII0_MDIO (PIN_ALT4_PULLUP | PIN_PORTB | PIN0)
@@ -184,20 +185,20 @@
#define PIN_ADC0_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
#define PIN_ADC1_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
#define PIN_TSI0_CH6 (PIN_ANALOG | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN1)
#define PIN_FTM1_CH1_3 (PIN_ALT3 | PIN_PORTB | PIN1)
#define PIN_RMII0_MDC (PIN_ALT4 | PIN_PORTB | PIN1)
#define PIN_MII0_MDC (PIN_ALT4 | PIN_PORTB | PIN1)
#define PIN_FTM1_QD_PHB_3 (PIN_ALT6 | PIN_PORTB | PIN1)
#define PIN_ADC0_SE12 (PIN_ANALOG | PIN_PORTB | PIN2)
#define PIN_TSI0_CH7 (PIN_ANALOG | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN2)
#define PIN_UART0_RTS_3 (PIN_ALT3 | PIN_PORTB | PIN2)
#define PIN_ENET0_1588_TMR0_1 (PIN_ALT4 | PIN_PORTB | PIN2)
#define PIN_FTM0_FLT3 (PIN_ALT6 | PIN_PORTB | PIN2)
#define PIN_ADC0_SE13 (PIN_ANALOG | PIN_PORTB | PIN3)
#define PIN_TSI0_CH8 (PIN_ANALOG | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN3)
#define PIN_UART0_CTS_3 (PIN_ALT3 | PIN_PORTB | PIN3)
#define PIN_ENET0_1588_TMR1_1 (PIN_ALT4 | PIN_PORTB | PIN3)
#define PIN_FTM0_FLT0_2 (PIN_ALT6 | PIN_PORTB | PIN3)
@@ -313,11 +314,11 @@
#define PIN_FTM2_FLT0_2 (PIN_ALT6 | PIN_PORTC | PIN9)
#define PIN_ADC1_SE6B (PIN_ANALOG | PIN_PORTC | PIN10)
#define PIN_CMP0_IN4 (PIN_ANALOG | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN10)
#define PIN_I2S0_RX_FS_2 (PIN_ALT4 | PIN_PORTC | PIN10)
#define PIN_FB_AD5 (PIN_ALT5 | PIN_PORTC | PIN10)
#define PIN_ADC1_SE7B (PIN_ANALOG | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN11)
#define PIN_I2S0_RXD_2 (PIN_ALT4 | PIN_PORTC | PIN11)
#define PIN_FB_RW (PIN_ALT5 | PIN_PORTC | PIN11)
#define PIN_UART4_RTS_1 (PIN_ALT3 | PIN_PORTC | PIN12)
@@ -387,10 +388,10 @@
#define PIN_UART0_TX_4 (PIN_ALT3 | PIN_PORTD | PIN7)
#define PIN_FTM0_CH7_2 (PIN_ALT4 | PIN_PORTD | PIN7)
#define PIN_FTM0_FLT1_2 (PIN_ALT6 | PIN_PORTD | PIN7)
#define PIN_I2C0_SCL_3 (PIN_ALT2 | PIN_PORTD | PIN8)
#define PIN_I2C0_SCL_3 (PIN_ALT2_OPENDRAIN | PIN_PORTD | PIN8)
#define PIN_UART5_RX_1 (PIN_ALT3 | PIN_PORTD | PIN8)
#define PIN_FB_A16 (PIN_ALT6 | PIN_PORTD | PIN8)
#define PIN_I2C0_SDA_3 (PIN_ALT2 | PIN_PORTD | PIN9)
#define PIN_I2C0_SDA_3 (PIN_ALT2_OPENDRAIN | PIN_PORTD | PIN9)
#define PIN_UART5_TX_1 (PIN_ALT3 | PIN_PORTD | PIN9)
#define PIN_FB_A17 (PIN_ALT6 | PIN_PORTD | PIN9)
#define PIN_UART5_RTS_1 (PIN_ALT3 | PIN_PORTD | PIN10)
@@ -416,12 +417,12 @@
#define PIN_SPI1_PCS1_2 (PIN_ALT2 | PIN_PORTE | PIN0)
#define PIN_UART1_TX_2 (PIN_ALT3 | PIN_PORTE | PIN0)
#define PIN_SDHC0_D1 (PIN_ALT4 | PIN_PORTE | PIN0)
#define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0)
#define PIN_I2C1_SDA_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN0)
#define PIN_ADC1_SE5A (PIN_ANALOG | PIN_PORTE | PIN1)
#define PIN_SPI1_SOUT_2 (PIN_ALT2 | PIN_PORTE | PIN1)
#define PIN_UART1_RX_2 (PIN_ALT3 | PIN_PORTE | PIN1)
#define PIN_SDHC0_D0 (PIN_ALT4 | PIN_PORTE | PIN1)
#define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1)
#define PIN_I2C1_SCL_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN1)
#define PIN_ADC1_SE6A (PIN_ANALOG | PIN_PORTE | PIN2)
#define PIN_SPI1_SCK_2 (PIN_ALT2 | PIN_PORTE | PIN2)
#define PIN_UART1_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN2)
arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
+21 -20
View File
@@ -1,8 +1,9 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -305,26 +306,26 @@
/* I2C */
#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_3 (PIN_ALT2 | PIN_PORTD | PIN8)
#define PIN_I2C0_SCL_4 (PIN_ALT5 | PIN_PORTE | PIN24)
#define PIN_I2C0_SCL_5 (PIN_ALT7 | PIN_PORTD | PIN2)
#define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_3 (PIN_ALT2 | PIN_PORTD | PIN9)
#define PIN_I2C0_SDA_4 (PIN_ALT5 | PIN_PORTE | PIN25)
#define PIN_I2C0_SDA_5 (PIN_ALT7 | PIN_PORTD | PIN3)
#define PIN_I2C0_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_3 (PIN_ALT2_OPENDRAIN | PIN_PORTD | PIN8)
#define PIN_I2C0_SCL_4 (PIN_ALT5_OPENDRAIN | PIN_PORTE | PIN24)
#define PIN_I2C0_SCL_5 (PIN_ALT7_OPENDRAIN | PIN_PORTD | PIN2)
#define PIN_I2C0_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_3 (PIN_ALT2_OPENDRAIN | PIN_PORTD | PIN9)
#define PIN_I2C0_SDA_4 (PIN_ALT5_OPENDRAIN | PIN_PORTE | PIN25)
#define PIN_I2C0_SDA_5 (PIN_ALT7_OPENDRAIN | PIN_PORTD | PIN3)
#define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1)
#define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0)
#define PIN_I2C1_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN1)
#define PIN_I2C1_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN0)
#define PIN_I2C2_SCL_1 (PIN_ALT5 | PIN_PORTA | PIN12)
#define PIN_I2C2_SCL_2 (PIN_ALT5 | PIN_PORTA | PIN14)
#define PIN_I2C2_SDA_1 (PIN_ALT5 | PIN_PORTA | PIN11)
#define PIN_I2C2_SDA_2 (PIN_ALT5 | PIN_PORTA | PIN13)
#define PIN_I2C2_SCL_1 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN12)
#define PIN_I2C2_SCL_2 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN14)
#define PIN_I2C2_SDA_1 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN11)
#define PIN_I2C2_SDA_2 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN13)
/* I2S */
arch/arm/src/kinetis/chip/kinetis_k66pinmux.h
+22 -22
View File
@@ -317,31 +317,31 @@
/* I2C */
#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_3 (PIN_ALT2 | PIN_PORTD | PIN8)
#define PIN_I2C0_SCL_4 (PIN_ALT5 | PIN_PORTE | PIN24)
#define PIN_I2C0_SCL_5 (PIN_ALT7 | PIN_PORTD | PIN2)
#define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_3 (PIN_ALT2 | PIN_PORTD | PIN9)
#define PIN_I2C0_SDA_4 (PIN_ALT5 | PIN_PORTE | PIN25)
#define PIN_I2C0_SDA_5 (PIN_ALT7 | PIN_PORTD | PIN3)
#define PIN_I2C0_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN2)
#define PIN_I2C0_SCL_3 (PIN_ALT2_OPENDRAIN | PIN_PORTD | PIN8)
#define PIN_I2C0_SCL_4 (PIN_ALT5_OPENDRAIN | PIN_PORTE | PIN24)
#define PIN_I2C0_SCL_5 (PIN_ALT7_OPENDRAIN | PIN_PORTD | PIN2)
#define PIN_I2C0_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN1)
#define PIN_I2C0_SDA_2 (PIN_ALT2_OPENDRAIN | PIN_PORTB | PIN3)
#define PIN_I2C0_SDA_3 (PIN_ALT2_OPENDRAIN | PIN_PORTD | PIN9)
#define PIN_I2C0_SDA_4 (PIN_ALT5_OPENDRAIN | PIN_PORTE | PIN25)
#define PIN_I2C0_SDA_5 (PIN_ALT7_OPENDRAIN | PIN_PORTD | PIN3)
#define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1)
#define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0)
#define PIN_I2C1_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN10)
#define PIN_I2C1_SCL_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN1)
#define PIN_I2C1_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTC | PIN11)
#define PIN_I2C1_SDA_2 (PIN_ALT6_OPENDRAIN | PIN_PORTE | PIN0)
#define PIN_I2C2_SCL_1 (PIN_ALT5 | PIN_PORTA | PIN12)
#define PIN_I2C2_SCL_2 (PIN_ALT5 | PIN_PORTA | PIN14)
#define PIN_I2C2_SDA_1 (PIN_ALT5 | PIN_PORTA | PIN11)
#define PIN_I2C2_SDA_2 (PIN_ALT5 | PIN_PORTA | PIN13)
#define PIN_I2C2_SCL_1 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN12)
#define PIN_I2C2_SCL_2 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN14)
#define PIN_I2C2_SDA_1 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN11)
#define PIN_I2C2_SDA_2 (PIN_ALT5_OPENDRAIN | PIN_PORTA | PIN13)
#define PIN_I2C3_SCL_1 (PIN_ALT2 | PIN_PORTE | PIN11)
#define PIN_I2C3_SCL_2 (PIN_ALT4 | PIN_PORTA | PIN2)
#define PIN_I2C3_SDA_1 (PIN_ALT2 | PIN_PORTE | PIN10)
#define PIN_I2C3_SDA_2 (PIN_ALT4 | PIN_PORTA | PIN1)
#define PIN_I2C3_SCL_1 (PIN_ALT2_OPENDRAIN | PIN_PORTE | PIN11)
#define PIN_I2C3_SCL_2 (PIN_ALT4_OPENDRAIN | PIN_PORTA | PIN2)
#define PIN_I2C3_SDA_1 (PIN_ALT2_OPENDRAIN | PIN_PORTE | PIN10)
#define PIN_I2C3_SDA_2 (PIN_ALT4_OPENDRAIN | PIN_PORTA | PIN1)
/* I2S */
arch/arm/src/kinetis/chip/kinetis_kx6tpm.h
+211
View File
@@ -0,0 +1,211 @@
/****************************************************************************
* arch/arm/src/kinetis/chip/kinetis_kx6tpm.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_KX6TPM_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_KX6TPM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Declarations
****************************************************************************/
#define KINETIS_TPM_SC_OFFSET 0x0000 /* Status and Control offset*/
#define KINETIS_TPM_CNT_OFFSET 0x0004 /* Counter offset */
#define KINETIS_TPM_MOD_OFFSET 0x0008 /* Modulo offset */
#define KINETIS_TPM_C0SC_OFFSET 0x000C /* Channel 0 Status and Control offset */
#define KINETIS_TPM_C0V_OFFSET 0x0010 /* Channel 0 Value offset */
#define KINETIS_TPM_C1SC_OFFSET 0x0014 /* Channel 1 Status and Control offset */
#define KINETIS_TPM_C1V_OFFSET 0x0018 /* Channel 1 Value offset */
#define KINETIS_TPM_STATUS_OFFSET 0x0050 /* Capture and Compare Status offset */
#define KINETIS_TPM_COMBINE_OFFSET 0x0064 /* Combine Channel Register offset */
#define KINETIS_TPM_POL_OFFSET 0x0070 /* Channel Polarity offset */
#define KINETIS_TPM_FILTER_OFFSET 0x0078 /* Filter Control offset */
#define KINETIS_TPM_QDCTRL_OFFSET 0x0080 /* Quadrature Decoder Control and Status offset */
#define KINETIS_TPM_CONF_OFFSET 0x0084 /* Configuration offset */
#define KINETIS_TPM1_SC (KINETIS_TPM1_BASE + KINETIS_TPM_SC_OFFSET) /* TPM1 Status and Control */
#define KINETIS_TPM1_CNT (KINETIS_TPM1_BASE + KINETIS_TPM_CNT_OFFSET) /* TPM1 Counter */
#define KINETIS_TPM1_MOD (KINETIS_TPM1_BASE + KINETIS_TPM_MOD_OFFSET) /* TPM1 Modulo */
#define KINETIS_TPM1_C0SC (KINETIS_TPM1_BASE + KINETIS_TPM_C0SC_OFFSET) /* TPM1 Channel 0 Status and Control */
#define KINETIS_TPM1_C0V (KINETIS_TPM1_BASE + KINETIS_TPM_C0V_OFFSET) /* TPM1 Channel 0 Value */
#define KINETIS_TPM1_C1SC (KINETIS_TPM1_BASE + KINETIS_TPM_C1SC_OFFSET) /* TPM1 Channel 1 Status and Control */
#define KINETIS_TPM1_C1V (KINETIS_TPM1_BASE + KINETIS_TPM_C1V_OFFSET) /* TPM1 Channel 1 Value */
#define KINETIS_TPM1_C2SC (KINETIS_TPM1_BASE + KINETIS_TPM_C2SC_OFFSET) /* TPM1 Channel 2 Status and Control */
#define KINETIS_TPM1_C2V (KINETIS_TPM1_BASE + KINETIS_TPM_C2V_OFFSET) /* TPM1 Channel 2 Value */
#define KINETIS_TPM1_STATUS (KINETIS_TPM1_BASE + KINETIS_TPM_STATUS_OFFSET) /* TPM1 Capture and Compare Status */
#define KINETIS_TPM1_COMBINE (KINETIS_TPM1_BASE + KINETIS_TPM_COMBINE_OFFSET) /* TPM1 Combine Channel Register offset */
#define KINETIS_TPM1_POL (KINETIS_TPM1_BASE + KINETIS_TPM_POL_OFFSET) /* TPM1 Channel Polarity offset */
#define KINETIS_TPM1_FILTER (KINETIS_TPM1_BASE + KINETIS_TPM_FILTER_OFFSET) /* TPM1 Filter Control offset */
#define KINETIS_TPM1_QDCTRL (KINETIS_TPM1_BASE + KINETIS_TPM_QDCTRL_OFFSET) /* TPM1 Quadrature Decoder Control and Status offset */
#define KINETIS_TPM1_CONF (KINETIS_TPM1_BASE + KINETIS_TPM_CONF_OFFSET) /* TPM1 Configuration */
#define KINETIS_TPM2_SC (KINETIS_TPM2_BASE + KINETIS_TPM_SC_OFFSET) /* TPM2 Status and Control */
#define KINETIS_TPM2_CNT (KINETIS_TPM2_BASE + KINETIS_TPM_CNT_OFFSET) /* TPM2 Counter */
#define KINETIS_TPM2_MOD (KINETIS_TPM2_BASE + KINETIS_TPM_MOD_OFFSET) /* TPM2 Modulo */
#define KINETIS_TPM2_C0SC (KINETIS_TPM2_BASE + KINETIS_TPM_C0SC_OFFSET) /* TPM2 Channel 0 Status and Control */
#define KINETIS_TPM2_C0V (KINETIS_TPM2_BASE + KINETIS_TPM_C0V_OFFSET) /* TPM2 Channel 0 Value */
#define KINETIS_TPM2_C1SC (KINETIS_TPM2_BASE + KINETIS_TPM_C1SC_OFFSET) /* TPM2 Channel 1 Status and Control */
#define KINETIS_TPM2_C1V (KINETIS_TPM2_BASE + KINETIS_TPM_C1V_OFFSET) /* TPM2 Channel 1 Value */
#define KINETIS_TPM2_C2SC (KINETIS_TPM2_BASE + KINETIS_TPM_C2SC_OFFSET) /* TPM2 Channel 2 Status and Control */
#define KINETIS_TPM2_C2V (KINETIS_TPM2_BASE + KINETIS_TPM_C2V_OFFSET) /* TPM2 Channel 2 Value */
#define KINETIS_TPM2_STATUS (KINETIS_TPM2_BASE + KINETIS_TPM_STATUS_OFFSET) /* TPM2 Capture and Compare Status */
#define KINETIS_TPM2_COMBINE (KINETIS_TPM2_BASE + KINETIS_TPM_COMBINE_OFFSET) /* TPM2 Combine Channel Register offset */
#define KINETIS_TPM2_POL (KINETIS_TPM2_BASE + KINETIS_TPM_POL_OFFSET) /* TPM2 Channel Polarity offset */
#define KINETIS_TPM2_FILTER (KINETIS_TPM2_BASE + KINETIS_TPM_FILTER_OFFSET) /* TPM2 Filter Control offset */
#define KINETIS_TPM2_QDCTRL (KINETIS_TPM2_BASE + KINETIS_TPM_QDCTRL_OFFSET) /* TPM2 Quadrature Decoder Control and Status offset */
#define KINETIS_TPM2_CONF (KINETIS_TPM2_BASE + KINETIS_TPM_CONF_OFFSET) /* TPM2 Configuration */
#define TPM_SC_PS_SHIFT 0 /* Bits 0-2: Prescale Factor Selection */
#define TPM_SC_PS_MASK (7 << TPM_SC_PS_SHIFT)
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
#define TPM_SC_CMOD_SHIFT 3 /* Bits 3-4: Clock Mode Selection */
#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT)
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
#define TPM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */
#define TPM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */
#define TPM_SC_TOF (1 << 7) /* Bit 7: Timer Overflow Flag*/
#define TPM_SC_DMA (1 << 8) /* Bit 8: DMA Enable*/
/* Bits 9-31: Reserved */
#define TPM_CNT_SHIFT 0 /* Bits 0-15: Counter value */
#define TPM_CNT_MASK (0xffff << TPM_COUNT_SHIFT) /* Any write clears Count */
/* Bits 16-31: Reserved */
#define TPM_MOD_SHIFT 0 /* Bits 0-15: Mod value */
#define TPM_MOD_MASK (0xffff << TPM_MOD_SHIFT) /* This field must be written with single 16 or 32-bit access */
/* Bits 16-31: Reserved */
#define TPM_CnSC_DMA (1 << 0) /* Bit 0: Enables DMA transfers for the channel */
/* Bit 1: Reserved*/
#define TPM_CnSC_ELSA (1 << 2) /* Bit 2: Edge or Level Select */
#define TPM_CnSC_ELSB (1 << 3) /* Bit 3: Edge or Level Select */
#define TPM_CnSC_MSA (1 << 4) /* Bit 4: Channel Mode Select */
#define TPM_CnSC_MSB (1 << 5) /* Bit 5: Channel Mode Select */
#define TPM_CnSC_CHIE (1 << 6) /* Bit 6: Channel Interrupt Enable */
#define TPM_CnSC_CHF (1 << 7) /* Bit 7: Channel Flag */
/* Bits 8-31: Reserved */
#define TPM_VAL_SHIFT 0 /* Bits 0-15: Channel value */
#define TPM_VAL_MASK (0xffff << TPM_VAL_SHIFT) /* Captured TPM counter value of the input modes or
* the match value for the output modes. This field
* must be written with single 16 or 32-bit access.*/
/* Bits 16-31: Reserved */
#define TPM_STATUS_CH0F (1 << 0) /* Bit 0: Channel 0 Flag */
#define TPM_STATUS_CH1F (1 << 1) /* Bit 1: Channel 1 Flag */
/* Bits 2-7: Reserved */
#define TPM_STATUS_TOF (1 << 8) /* Bit 8: Timer Overflow Flag */
/* Bits 9-31: Reserved */
#define TPM_COMBINE_COMBINE0 (1 << 0) /* Bit 0: Combine Channels 0 and 1 */
#define TPM_COMBINE_COMSWAP0 (1 << 1) /* Bit 1: Combine Channel 0 and 1 Swap */
/* Bits 2-7: Reserved */
/* Bits 8-31: Reserved */
#define TPM_POL_POL0 (1 << 0) /* Bit 0: Channel 0 Polarity */
#define TPM_POL_POL1 (1 << 1) /* Bit 1: Channel 1 Polarity */
/* Bits 2-31: Reserved */
#define TPM_FILTER_CH0FVAL_SHIFT 0 /* Bits 0-3: Channel 0 Filter Value */
#define TPM_FILTER_CH0FVAL_MASK (0xf << TPM_FILTER_CH0FVAL_SHIFT)
#define TPM_FILTER_CH1FVAL_SHIFT 4 /* Bits 4-7: Channel 1 Filter Value */
#define TPM_FILTER_CH1FVAL_MASK (0xf << TPM_FILTER_CH1FVAL_SHIFT)
#define TPM_QDCTRL_QDCTRL (1 << 0) /* Bit 0: Enables the quadrature decoder mode */
#define TPM_QDCTRL_TOFDIR (1 << 1) /* Bit 1: Indicates if the TOF bit was set (Read Only) */
#define TPM_QDCTRL_QUADIR (1 << 2) /* Bit 2: Counter Direction in Quadrature Decode Mode (Read Only) */
#define TPM_QDCTRL_QUADMODE (1 << 3) /* Bit 3: Quadrature Decoder Mode */
/* Bits 4-31: Reserved */
#define TPM_CONF_DOZEEN (1 << 5) /* Bit 5: Doze Enable */
#define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (3 << TPM_CONF_DBGMODE_SHIFT)
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
#define TPM_CONF_GTBSYNC (1 << 8) /* Bit 8: Global Time Base Synchronization */
#define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */
/* Bits 10-15: Reserved */
#define TPM_CONF_CSOT (1 << 16) /* Bit 16: Counter Start On Trigger */
#define TPM_CONF_CSOO (1 << 17) /* Bit 17: Counter Stop On Overflow */
#define TPM_CONF_CROT (1 << 18) /* Bit 18: Counter Reload On Trigger */
#define TPM_CONF_CPOT (1 << 19) /* Bit 19: Counter Pause On Trigger */
/* Bits 20-21: Reserved */
#define TPM_CONF_TRGPOL (1 << 22) /* Bit 22: Trigger Polarity */
#define TPM_CONF_TRGSRC (1 << 23) /* Bit 23: Trigger Source */
#define TPM_CONF_TRGSEL_SHIFT 24 /* Bits 24-27: Trigger Select */
#define TPM_CONF_TRGSEL_MASK (0xf << TPM_CONF_TRGSEL_SHIFT)
/* Internal TPM_CONF_TRGSRC set */
# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */
# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */
# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */
# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */
# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_KX6TPM_H */
arch/arm/src/kinetis/chip/kinetis_osc.h
+12 -1
View File
@@ -1,7 +1,7 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_osc.h
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -51,10 +51,12 @@
/* Register Offsets *************************************************************************/
#define KINETIS_OSC_CR_OFFSET 0x0000 /* OSC Control Register */
#define KINETIS_OSC_DIV_OFFSET 0x0002 /* OSC CLock divider register */
/* Register Addresses ***********************************************************************/
#define KINETIS_OSC_CR (KINETIS_OSC_BASE+KINETIS_OSC_CR_OFFSET)
#define KINETIS_OSC_DIV (KINETIS_OSC_BASE+KINETIS_OSC_DIV_OFFSET)
/* Register Bit Definitions *****************************************************************/
@@ -69,6 +71,15 @@
#define OSC_CR_SC8P (1 << 1) /* Bit 1: Oscillator 8 pF Capacitor Load Configure */
#define OSC_CR_SC16P (1 << 0) /* Bit 0: Oscillator 16 pF Capacitor Load Configure */
/* OSC Control Register (8-bit) */
/* Bits 0-5: Reserved */
#define OSC_DIV_ERPS_SHIFT 6 /* Bits 6-7: ERCLK prescaler */
#define OSC_DIV_ERPS_MASK (3 << OSC_DIV_ERPS_SHIFT)
# define OSC_DIV_ERPS_DIV1 (0 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 1 */
# define OSC_DIV_ERPS_DIV2 (1 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 2 */
# define OSC_DIV_ERPS_DIV3 (2 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 4 */
# define OSC_DIV_ERPS_DIV8 (3 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 8 */
/********************************************************************************************
* Public Types
********************************************************************************************/
arch/arm/src/kinetis/chip/kinetis_sim.h
+2 -2
View File
@@ -328,7 +328,7 @@
divided by the PLLFLLCLK fractional divider
as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
# define SIM_SOPT2_TPMSRC_OCSERCLK (2 << SIM_SOPT2_TPMSRC_SHIFT) /* OSCERCLK clock */
# define SIM_SOPT2_TPMSRC_EXTBYP (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */
# define SIM_SOPT2_TPMSRC_MCGIRCLK (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */
# endif
# if defined(KINETIS_SIM_HAS_SOPT2_I2SSRC)
# define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */
@@ -348,7 +348,7 @@
divided by the PLLFLLCLK fractional divider
as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
# define SIM_SOPT2_LPUARTSRC_OCSERCLK (2 << SIM_SOPT2_LPUARTSRC_SHIFT) /* OSCERCLK clock */
# define SIM_SOPT2_LPUARTSRC_EXTBYP (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */
# define SIM_SOPT2_LPUARTSRC_MCGIRCLK (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */
# endif
# if defined(KINETIS_SIM_HAS_SOPT2_SDHCSRC)
# define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select */
arch/arm/src/kinetis/kinetis.h
+4 -2
View File
@@ -468,7 +468,8 @@ void kinetis_lpuartreset(uintptr_t uart_base);
#ifdef HAVE_UART_DEVICE
void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock,
unsigned int parity, unsigned int nbits,
unsigned int stop2);
unsigned int stop2,
bool iflow, bool oflow);
#endif
/****************************************************************************
@@ -482,7 +483,8 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock,
#ifdef HAVE_LPUART_DEVICE
void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock,
unsigned int parity, unsigned int nbits,
unsigned int stop2);
unsigned int stop2,
bool iflow, bool oflow);
#endif
/************************************************************************************
arch/arm/src/kinetis/kinetis_clockconfig.c
+13
View File
@@ -49,6 +49,7 @@
#include "chip/kinetis_pmc.h"
#include "chip/kinetis_llwu.h"
#include "chip/kinetis_pinmux.h"
#include "chip/kinetis_osc.h"
#include <arch/board/board.h>
@@ -199,6 +200,18 @@ void kinetis_pllconfig(void)
#endif
uint8_t regval8;
#if defined(BOARD_OSC_CR)
/* Use complete BOARD_OSC_CR settings */
putreg8(BOARD_OSC_CR, KINETIS_OSC_CR);
#endif
#if defined(BOARD_OSC_DIV)
/* Use complete BOARD_OSC_DIV settings */
putreg8(BOARD_OSC_DIV, KINETIS_OSC_DIV);
#endif
#if defined(BOARD_MCG_C2)
/* Use complete BOARD_MCG_C2 settings */
arch/arm/src/kinetis/kinetis_lowputc.c
+165 -4
View File
@@ -41,6 +41,7 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/irq.h>
#include <arch/board/board.h>
@@ -59,6 +60,58 @@
* Pre-processor Definitions
****************************************************************************/
/* Default hardware flow control */
#if !defined(CONFIG_UART0_IFLOWCONTROL)
# define CONFIG_UART0_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART0_OFLOWCONTROL)
# define CONFIG_UART0_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART1_IFLOWCONTROL)
# define CONFIG_UART1_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART1_OFLOWCONTROL)
# define CONFIG_UART1_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART2_IFLOWCONTROL)
# define CONFIG_UART2_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART2_OFLOWCONTROL)
# define CONFIG_UART2_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART3_IFLOWCONTROL)
# define CONFIG_UART3_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART3_OFLOWCONTROL)
# define CONFIG_UART3_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART4_IFLOWCONTROL)
# define CONFIG_UART4_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART4_OFLOWCONTROL)
# define CONFIG_UART4_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART5_IFLOWCONTROL)
# define CONFIG_UART5_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_UART5_OFLOWCONTROL)
# define CONFIG_UART5_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_LPUART0_IFLOWCONTROL)
# define CONFIG_LPUART0_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_LPUART0_OFLOWCONTROL)
# define CONFIG_LPUART0_OFLOWCONTROL 0
#endif
#if !defined(CONFIG_LPUART1_IFLOWCONTROL)
# define CONFIG_LPUART1_IFLOWCONTROL 0
#endif
#if !defined(CONFIG_LPUART1_OFLOWCONTROL)
# define CONFIG_LPUART1_OFLOWCONTROL 0
#endif
/* Select UART parameters for the selected console */
#if defined(HAVE_UART_CONSOLE)
@@ -69,6 +122,8 @@
# define CONSOLE_BITS CONFIG_UART0_BITS
# define CONSOLE_2STOP CONFIG_UART0_2STOP
# define CONSOLE_PARITY CONFIG_UART0_PARITY
# define CONSOLE_IFLOW CONFIG_UART0_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_UART0_OFLOWCONTROL
# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE KINETIS_UART1_BASE
# define CONSOLE_FREQ BOARD_CORECLK_FREQ
@@ -76,6 +131,8 @@
# define CONSOLE_BITS CONFIG_UART1_BITS
# define CONSOLE_2STOP CONFIG_UART1_2STOP
# define CONSOLE_PARITY CONFIG_UART1_PARITY
# define CONSOLE_IFLOW CONFIG_UART1_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_UART1_OFLOWCONTROL
# elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE KINETIS_UART2_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
@@ -83,6 +140,8 @@
# define CONSOLE_BITS CONFIG_UART2_BITS
# define CONSOLE_2STOP CONFIG_UART2_2STOP
# define CONSOLE_PARITY CONFIG_UART2_PARITY
# define CONSOLE_IFLOW CONFIG_UART2_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_UART2_OFLOWCONTROL
# elif defined(CONFIG_UART3_SERIAL_CONSOLE)
# define CONSOLE_BASE KINETIS_UART3_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
@@ -90,6 +149,8 @@
# define CONSOLE_BITS CONFIG_UART3_BITS
# define CONSOLE_2STOP CONFIG_UART3_2STOP
# define CONSOLE_PARITY CONFIG_UART3_PARITY
# define CONSOLE_IFLOW CONFIG_UART3_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_UART3_OFLOWCONTROL
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define CONSOLE_BASE KINETIS_UART4_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
@@ -97,6 +158,8 @@
# define CONSOLE_BITS CONFIG_UART4_BITS
# define CONSOLE_2STOP CONFIG_UART4_2STOP
# define CONSOLE_PARITY CONFIG_UART4_PARITY
# define CONSOLE_IFLOW CONFIG_UART4_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_UART4_OFLOWCONTROL
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define CONSOLE_BASE KINETIS_UART5_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
@@ -104,6 +167,8 @@
# define CONSOLE_BITS CONFIG_UART5_BITS
# define CONSOLE_2STOP CONFIG_UART5_2STOP
# define CONSOLE_PARITY CONFIG_UART5_PARITY
# define CONSOLE_IFLOW CONFIG_UART5_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_UART5_OFLOWCONTROL
# elif defined(HAVE_UART_CONSOLE)
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
# endif
@@ -115,6 +180,8 @@
# define CONSOLE_PARITY CONFIG_LPUART0_PARITY
# define CONSOLE_BITS CONFIG_LPUART0_BITS
# define CONSOLE_2STOP CONFIG_LPUART0_2STOP
# define CONSOLE_IFLOW CONFIG_LPUART0_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_LPUART0_OFLOWCONTROL
# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define CONSOLE_BASE KINETIS_LPUART1_BASE
# define CONSOLE_FREQ BOARD_LPUART1_FREQ
@@ -122,6 +189,8 @@
# define CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define CONSOLE_BITS CONFIG_LPUART1_BITS
# define CONSOLE_2STOP CONFIG_LPUART1_2STOP
# define CONSOLE_IFLOW CONFIG_LPUART1_IFLOWCONTROL
# define CONSOLE_OFLOW CONFIG_LPUART1_OFLOWCONTROL
# else
# error "No LPUART console is selected"
# endif
@@ -271,26 +340,62 @@ void kinetis_lowsetup(void)
# ifdef CONFIG_KINETIS_UART0
kinetis_pinconfig(PIN_UART0_TX);
kinetis_pinconfig(PIN_UART0_RX);
# if CONFIG_UART0_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART0_RTS);
# endif
# if CONFIG_UART0_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART0_CTS);
# endif
# endif
# ifdef CONFIG_KINETIS_UART1
kinetis_pinconfig(PIN_UART1_TX);
kinetis_pinconfig(PIN_UART1_RX);
# if CONFIG_UART1_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART1_RTS);
# endif
# if CONFIG_UART1_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART1_CTS);
# endif
# endif
# ifdef CONFIG_KINETIS_UART2
kinetis_pinconfig(PIN_UART2_TX);
kinetis_pinconfig(PIN_UART2_RX);
# if CONFIG_UART2_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART2_RTS);
# endif
# if CONFIG_UART2_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART2_CTS);
# endif
# endif
# ifdef CONFIG_KINETIS_UART3
kinetis_pinconfig(PIN_UART3_TX);
kinetis_pinconfig(PIN_UART3_RX);
# if CONFIG_UART3_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART3_RTS);
# endif
# if CONFIG_UART3_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART3_CTS);
# endif
# endif
# ifdef CONFIG_KINETIS_UART4
kinetis_pinconfig(PIN_UART4_TX);
kinetis_pinconfig(PIN_UART4_RX);
# if CONFIG_UART4_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART4_RTS);
# endif
# if CONFIG_UART4_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART4_CTS);
# endif
# endif
# ifdef CONFIG_KINETIS_UART5
kinetis_pinconfig(PIN_UART5_TX);
kinetis_pinconfig(PIN_UART5_RX);
# if CONFIG_UART5_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART5_RTS);
# endif
# if CONFIG_UART5_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_UART5_CTS);
# endif
# endif
/* Configure the console (only) now. Other UARTs will be configured
@@ -300,7 +405,8 @@ void kinetis_lowsetup(void)
# if defined(HAVE_UART_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
kinetis_uartconfigure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \
CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP);
CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP, \
CONSOLE_IFLOW, CONSOLE_OFLOW);
# endif
#endif /* HAVE_UART_DEVICE */
@@ -327,17 +433,30 @@ void kinetis_lowsetup(void)
# ifdef CONFIG_KINETIS_LPUART0
kinetis_pinconfig(PIN_LPUART0_TX);
kinetis_pinconfig(PIN_LPUART0_RX);
# if CONFIG_LPUART0_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_LPUART0_RTS);
# endif
# if CONFIG_LPUART0_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_LOUART0_CTS);
# endif
# endif
# ifdef CONFIG_KINETIS_LPUART1
kinetis_pinconfig(PIN_LPUART1_TX);
kinetis_pinconfig(PIN_LPUART1_RX);
# if CONFIG_LPUART1_IFLOWCONTROL == 1
kinetis_pinconfig(PIN_LPUART1_RTS);
# endif
# if CONFIG_LPUART1_OFLOWCONTROL == 1
kinetis_pinconfig(PIN_LOUART1_CTS);
# endif
# endif
# if defined(HAVE_LPUART_CONSOLE) && !defined(CONFIG_SUPPRESS_LPUART_CONFIG)
kinetis_lpuartconfigure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \
CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP);
CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP, \
CONSOLE_IFLOW, CONSOLE_OFLOW);
# endif
#endif /* HAVE_LPUART_DEVICE */
}
@@ -395,7 +514,8 @@ void kinetis_lpuartreset(uintptr_t uart_base)
#ifdef HAVE_UART_DEVICE
void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
uint32_t clock, unsigned int parity,
unsigned int nbits, unsigned int stop2)
unsigned int nbits, unsigned int stop2,
bool iflow, bool oflow)
{
uint32_t sbr;
uint32_t brfa;
@@ -542,6 +662,27 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
putreg8(0, uart_base+KINETIS_UART_PFIFO_OFFSET);
#endif
/* Hardware flow control */
regval = getreg8(uart_base+KINETIS_UART_MODEM_OFFSET);
regval &= ~(UART_MODEM_TXCTSE | UART_MODEM_RXRTSE);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
if (iflow)
{
regval |= UART_MODEM_RXRTSE;
}
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
if (oflow)
{
regval |= UART_MODEM_TXCTSE;
}
#endif
putreg8(regval, uart_base+KINETIS_UART_MODEM_OFFSET);
/* Now we can (re-)enable the transmitter and receiver */
regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET);
@@ -561,7 +702,8 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
#ifdef HAVE_LPUART_DEVICE
void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
uint32_t clock, unsigned int parity,
unsigned int nbits, unsigned int stop2)
unsigned int nbits, unsigned int stop2,
bool iflow, bool oflow)
{
uint32_t sbrreg;
uint32_t osrreg;
@@ -711,6 +853,25 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
DEBUGASSERT(nbits == 8);
}
/* Hardware flow control */
regval = getreg32(uart_base+KINETIS_LPUART_MODIR_OFFSET);
regval &= ~(UART_MODEM_TXCTSE | UART_MODEM_RXRTSE);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
if (iflow)
{
regval |= LPUART_MODIR_RXRTSE;
}
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
if (oflow)
{
regval |= LPUART_MODIR_TXCTSE;
}
#endif
putreg32(regval, uart_base+KINETIS_LPUART_MODIR_OFFSET);
/* Now we can (re-)enable the transmitter and receiver */
regval |= (LPUART_CTRL_RE | LPUART_CTRL_TE);
arch/arm/src/kinetis/kinetis_lpserial.c
+348 -13
View File
@@ -53,6 +53,11 @@
#include <nuttx/arch.h>
#include <nuttx/serial/serial.h>
#ifdef CONFIG_SERIAL_TERMIOS
# include <termios.h>
#endif
#include <arch/serial.h>
#include <arch/board/board.h>
#include "up_arch.h"
@@ -61,6 +66,7 @@
#include "kinetis_config.h"
#include "chip.h"
#include "chip/kinetis_lpuart.h"
#include "chip/kinetis_pinmux.h"
#include "kinetis.h"
/****************************************************************************
@@ -153,6 +159,18 @@ struct kinetis_dev_s
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (8 or 9) */
uint8_t stop2; /* Use 2 stop bits */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
bool iflow; /* input flow control (RTS) enabled */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
bool oflow; /* output flow control (CTS) enabled */
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
uint32_t rts_gpio; /* UART RTS GPIO pin configuration */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
uint32_t cts_gpio; /* UART CTS GPIO pin configuration */
#endif
};
/****************************************************************************
@@ -168,6 +186,10 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg);
static int kinetis_receive(struct uart_dev_s *dev, uint32_t *status);
static void kinetis_rxint(struct uart_dev_s *dev, bool enable);
static bool kinetis_rxavailable(struct uart_dev_s *dev);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool kinetis_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
bool upper);
#endif
static void kinetis_send(struct uart_dev_s *dev, int ch);
static void kinetis_txint(struct uart_dev_s *dev, bool enable);
static bool kinetis_txready(struct uart_dev_s *dev);
@@ -187,7 +209,7 @@ static const struct uart_ops_s g_lpuart_ops =
.rxint = kinetis_rxint,
.rxavailable = kinetis_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
.rxflowcontrol = kinetis_rxflowcontrol,
#endif
.send = kinetis_send,
.txint = kinetis_txint,
@@ -219,6 +241,14 @@ static struct kinetis_dev_s g_lpuart0priv =
.parity = CONFIG_LPUART0_PARITY,
.bits = CONFIG_LPUART0_BITS,
.stop2 = CONFIG_LPUART0_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART0_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_LPUART0_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_LPUART0_RTS,
#endif
};
static uart_dev_t g_lpuart0port =
@@ -251,6 +281,14 @@ static struct kinetis_dev_s g_lpuart1priv =
.parity = CONFIG_LPUART1_PARITY,
.bits = CONFIG_LPUART1_BITS,
.stop2 = CONFIG_LPUART1_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_LPUART1_RTS,
#endif
};
static uart_dev_t g_lpuart1port =
@@ -360,11 +398,22 @@ static int kinetis_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv;
#ifdef CONFIG_SERIAL_IFLOWCONTROL
bool iflow = priv->iflow;
#else
bool iflow = false;
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
bool oflow = priv->oflow;
#else
bool oflow = false;
#endif
/* Configure the LPUART as an RS-232 UART */
kinetis_lpuartconfigure(priv->uartbase, priv->baud, priv->clock,
priv->parity, priv->bits, priv->stop2);
priv->parity, priv->bits, priv->stop2,
iflow, oflow);
#endif
/* Make sure that all interrupts are disabled */
@@ -564,23 +613,239 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if 0 /* Reserved for future growth */
struct inode *inode;
struct uart_dev_s *dev;
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || \
defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
struct inode *inode;
struct uart_dev_s *dev;
uint8_t regval;
#endif
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
struct kinetis_dev_s *priv;
int ret = OK;
bool iflow = false;
bool oflow = false;
#endif
int ret = OK;
DEBUGASSERT(filep, filep->f_inode);
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || \
defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
DEBUGASSERT(filep != NULL && filep->f_inode != NULL);
inode = filep->f_inode;
dev = inode->i_private;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
#endif
DEBUGASSERT(dev, dev->priv);
priv = (struct kinetis_dev_s *)dev->priv;
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
priv = (struct kinetis_dev_s *)dev->priv;
#endif
switch (cmd)
{
case xxx: /* Add commands here */
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
case TIOCSERGSTRUCT:
{
struct kinetis_dev_s *user = (struct kinetis_dev_s *)arg;
if (!user)
{
ret = -EINVAL;
}
else
{
memcpy(user, dev, sizeof(struct kinetis_dev_s));
}
}
break;
#endif
#ifdef CONFIG_KINETIS_UART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
/* Change to single-wire operation. the RXD pin is disconnected from
* the UART and the UART implements a half-duplex serial connection.
* The UART uses the TXD pin for both receiving and transmitting
*/
regval = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
if (arg == SER_SINGLEWIRE_ENABLED)
{
regval |= (LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC);
}
else
{
regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC);
}
kinetis_serialout(priv, KINETIS_LPUART_CTRL_OFFSET, regval);
}
break;
#endif
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
{
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
ret = -EINVAL;
break;
}
cfsetispeed(termiosp, priv->baud);
/* Note: CSIZE only supports 5-8 bits. The driver only support 8/9 bit
* modes and therefore is no way to report 9-bit mode, we always claim
* 8 bit mode.
*/
termiosp->c_cflag =
((priv->parity != 0) ? PARENB : 0) |
((priv->parity == 1) ? PARODD : 0) |
((priv->stop2) ? CSTOPB : 0) |
# ifdef CONFIG_SERIAL_OFLOWCONTROL
((priv->oflow) ? CCTS_OFLOW : 0) |
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
((priv->iflow) ? CRTS_IFLOW : 0) |
# endif
CS8;
/* TODO: CCTS_IFLOW, CCTS_OFLOW */
}
break;
case TCSETS:
{
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
ret = -EINVAL;
break;
}
/* Perform some sanity checks before accepting any changes */
if (((termiosp->c_cflag & CSIZE) != CS8)
# ifdef CONFIG_SERIAL_IFLOWCONTROL
|| ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0))
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
|| ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))
# endif
)
{
ret = -EINVAL;
break;
}
if (termiosp->c_cflag & PARENB)
{
priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
}
else
{
priv->parity = 0;
}
priv->stop2 = (termiosp->c_cflag & CSTOPB) != 0;
# ifdef CONFIG_SERIAL_OFLOWCONTROL
priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0;
oflow = priv->oflow;
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
iflow = priv->iflow;
# endif
/* Note that since there is no way to request 9-bit mode
* and no way to support 5/6/7-bit modes, we ignore them
* all here.
*/
/* Note that only cfgetispeed is used because we have knowledge
* that only one speed is supported.
*/
priv->baud = cfgetispeed(termiosp);
/* Effect the changes immediately - note that we do not implement
* TCSADRAIN / TCSAFLUSH
*/
kinetis_uartconfigure(priv->uartbase, priv->baud, priv->clock,
priv->parity, priv->bits, priv->stop2,
iflow, oflow);
}
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_KINETIS_UART_BREAKS
case TIOCSBRK:
{
irqstate_t flags;
flags = enter_critical_section();
/* Send a longer break signal */
regval = kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET);
regval &= ~LPUART_STAT_BRK13;
# ifdef CONFIG_KINETIS_UART_EXTEDED_BREAK
regval |= LPUART_STAT_BRK13;
# endif
kinetis_serialout(priv, LPUART_STAT_BRK13, regval);
/* Send a break signal */
regval = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
regval |= LPUART_CTRL_SBK;
kinetis_serialout(priv, KINETIS_LPUART_CTRL_OFFSET, regval);
# ifdef CONFIG_KINETIS_SERIALBRK_BSDCOMPAT
/* BSD compatibility: Turn break on, and leave it on */
kinetis_txint(dev, false);
# else
/* Send a single break character
* Toggling SBK sends one break character. Per the manual
* Toggling implies clearing the SBK field before the break
* character has finished transmitting.
*/
regval &= ~LPUART_CTRL_SBK;
kinetis_serialout(priv, KINETIS_LPUART_CTRL_OFFSET, regval);
#endif
leave_critical_section(flags);
}
break;
case TIOCCBRK:
{
irqstate_t flags;
flags = enter_critical_section();
/* Configure TX back to UART
* If non BSD compatible: This code has no effect, the SBRK
* was already cleared.
* but for BSD compatibility: Turn break off
*/
regval = kinetis_serialin(priv, KINETIS_LPUART_CTRL_OFFSET);
regval &= ~LPUART_CTRL_SBK;
kinetis_serialout(priv, KINETIS_LPUART_CTRL_OFFSET, regval);
# ifdef CONFIG_KINETIS_SERIALBRK_BSDCOMPAT
/* Enable further tx activity */
kinetis_txint(dev, true);
# endif
leave_critical_section(flags);
}
break;
#endif /* CONFIG_KINETIS_UART_BREAKS */
default:
ret = -ENOTTY;
@@ -588,9 +853,6 @@ static int kinetis_ioctl(struct file *filep, int cmd, unsigned long arg)
}
return ret;
#else
return -ENOTTY;
#endif
}
/****************************************************************************
@@ -696,6 +958,79 @@ static bool kinetis_rxavailable(struct uart_dev_s *dev)
return (kinetis_serialin(priv, KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_RDRF) != 0;
}
/****************************************************************************
* Name: kinetis_rxflowcontrol
*
* Description:
* Called when Rx buffer is full (or exceeds configured watermark levels
* if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined).
* Return true if UART activated RX flow control to block more incoming
* data
*
* Input parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
* not defined the value will be 0 for an empty buffer or the
* defined buffer size for a full buffer)
* upper - true indicates the upper watermark was crossed where
* false indicates the lower watermark has been crossed
*
* Returned Value:
* true if RX flow control activated.
*
****************************************************************************/
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool kinetis_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper)
{
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS)
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev->priv;
uint16_t ie;
if (priv->iflow)
{
/* Is the RX buffer full? */
if (upper)
{
/* Disable Rx interrupt to prevent more data being from
* peripheral. When hardware RTS is enabled, this will
* prevent more data from coming in.
*
* This function is only called when UART recv buffer is full,
* that is: "dev->recv.head + 1 == dev->recv.tail".
*
* Logic in "uart_read" will automatically toggle Rx interrupts
* when buffer is read empty and thus we do not have to re-
* enable Rx interrupts.
*/
ie = priv->ie;
ie &= ~LPUART_CTRL_RX_INTS;
kinetis_restoreuartint(priv, ie);
return true;
}
/* No.. The RX buffer is empty */
else
{
/* We might leave Rx interrupt disabled if full recv buffer was
* read empty. Enable Rx interrupt to make sure that more input is
* received.
*/
kinetis_rxint(dev, true);
}
}
#endif
return false;
}
#endif
/****************************************************************************
* Name: kinetis_send
*
arch/arm/src/kinetis/kinetis_serial.c
+379 -11
View File
@@ -53,6 +53,11 @@
#include <nuttx/arch.h>
#include <nuttx/serial/serial.h>
#ifdef CONFIG_SERIAL_TERMIOS
# include <termios.h>
#endif
#include <arch/serial.h>
#include <arch/board/board.h>
#include "up_arch.h"
@@ -61,6 +66,7 @@
#include "kinetis_config.h"
#include "chip.h"
#include "chip/kinetis_uart.h"
#include "chip/kinetis_pinmux.h"
#include "kinetis.h"
/****************************************************************************
@@ -242,6 +248,18 @@ struct up_dev_s
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (8 or 9) */
uint8_t stop2; /* Use 2 stop bits */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
bool iflow; /* input flow control (RTS) enabled */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
bool oflow; /* output flow control (CTS) enabled */
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
uint32_t rts_gpio; /* UART RTS GPIO pin configuration */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
uint32_t cts_gpio; /* UART CTS GPIO pin configuration */
#endif
};
/****************************************************************************
@@ -260,6 +278,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
bool upper);
#endif
static void up_send(struct uart_dev_s *dev, int ch);
static void up_txint(struct uart_dev_s *dev, bool enable);
static bool up_txready(struct uart_dev_s *dev);
@@ -282,7 +304,7 @@ static const struct uart_ops_s g_uart_ops =
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
.rxflowcontrol = up_rxflowcontrol,
#endif
.send = up_send,
.txint = up_txint,
@@ -337,6 +359,14 @@ static struct up_dev_s g_uart0priv =
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stop2 = CONFIG_UART0_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART0_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART0_RTS,
#endif
};
static uart_dev_t g_uart0port =
@@ -372,6 +402,14 @@ static struct up_dev_s g_uart1priv =
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stop2 = CONFIG_UART1_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART1_RTS,
#endif
};
static uart_dev_t g_uart1port =
@@ -407,6 +445,14 @@ static struct up_dev_s g_uart2priv =
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stop2 = CONFIG_UART2_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART2_RTS,
#endif
};
static uart_dev_t g_uart2port =
@@ -442,6 +488,14 @@ static struct up_dev_s g_uart3priv =
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
.stop2 = CONFIG_UART3_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART3_RTS,
#endif
};
static uart_dev_t g_uart3port =
@@ -477,6 +531,14 @@ static struct up_dev_s g_uart4priv =
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stop2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART4_RTS,
#endif
};
static uart_dev_t g_uart4port =
@@ -512,6 +574,14 @@ static struct up_dev_s g_uart5priv =
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stop2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART5_RTS,
#endif
};
static uart_dev_t g_uart5port =
@@ -621,11 +691,23 @@ static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#ifdef CONFIG_SERIAL_IFLOWCONTROL
bool iflow = priv->iflow;
#else
bool iflow = false;
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
bool oflow = priv->oflow;
#else
bool oflow = false;
#endif
/* Configure the UART as an RS-232 UART */
kinetis_uartconfigure(priv->uartbase, priv->baud, priv->clock,
priv->parity, priv->bits, priv->stop2);
priv->parity, priv->bits, priv->stop2,
iflow, oflow);
#endif
/* Make sure that all interrupts are disabled */
@@ -891,23 +973,239 @@ static int up_interrupts(int irq, void *context, FAR void *arg)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if 0 /* Reserved for future growth */
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || \
defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
struct inode *inode;
struct uart_dev_s *dev;
uint8_t regval;
#endif
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
struct up_dev_s *priv;
int ret = OK;
bool iflow = false;
bool oflow = false;
#endif
int ret = OK;
DEBUGASSERT(filep, filep->f_inode);
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || \
defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
DEBUGASSERT(filep != NULL && filep->f_inode != NULL);
inode = filep->f_inode;
dev = inode->i_private;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
#endif
DEBUGASSERT(dev, dev->priv);
priv = (struct up_dev_s *)dev->priv;
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_KINETIS_SERIALBRK_BSDCOMPAT)
priv = (struct up_dev_s *)dev->priv;
#endif
switch (cmd)
{
case xxx: /* Add commands here */
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
case TIOCSERGSTRUCT:
{
struct up_dev_s *user = (struct up_dev_s *)arg;
if (!user)
{
ret = -EINVAL;
}
else
{
memcpy(user, dev, sizeof(struct up_dev_s));
}
}
break;
#endif
#ifdef CONFIG_KINETIS_UART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
/* Change to single-wire operation. the RXD pin is disconnected from
* the UART and the UART implements a half-duplex serial connection.
* The UART uses the TXD pin for both receiving and transmitting
*/
regval = up_serialin(priv, KINETIS_UART_C1_OFFSET);
if (arg == SER_SINGLEWIRE_ENABLED)
{
regval |= (UART_C1_LOOPS | UART_C1_RSRC);
}
else
{
regval &= ~(UART_C1_LOOPS | UART_C1_RSRC);
}
up_serialout(priv, KINETIS_UART_C1_OFFSET, regval);
}
break;
#endif
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
{
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
ret = -EINVAL;
break;
}
cfsetispeed(termiosp, priv->baud);
/* Note: CSIZE only supports 5-8 bits. The driver only support 8/9 bit
* modes and therefore is no way to report 9-bit mode, we always claim
* 8 bit mode.
*/
termiosp->c_cflag =
((priv->parity != 0) ? PARENB : 0) |
((priv->parity == 1) ? PARODD : 0) |
((priv->stop2) ? CSTOPB : 0) |
# ifdef CONFIG_SERIAL_OFLOWCONTROL
((priv->oflow) ? CCTS_OFLOW : 0) |
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
((priv->iflow) ? CRTS_IFLOW : 0) |
# endif
CS8;
/* TODO: CCTS_IFLOW, CCTS_OFLOW */
}
break;
case TCSETS:
{
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
ret = -EINVAL;
break;
}
/* Perform some sanity checks before accepting any changes */
if (((termiosp->c_cflag & CSIZE) != CS8)
# ifdef CONFIG_SERIAL_IFLOWCONTROL
|| ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0))
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
|| ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))
# endif
)
{
ret = -EINVAL;
break;
}
if (termiosp->c_cflag & PARENB)
{
priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
}
else
{
priv->parity = 0;
}
priv->stop2 = (termiosp->c_cflag & CSTOPB) != 0;
# ifdef CONFIG_SERIAL_OFLOWCONTROL
priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0;
oflow = priv->oflow;
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
iflow = priv->iflow;
# endif
/* Note that since there is no way to request 9-bit mode
* and no way to support 5/6/7-bit modes, we ignore them
* all here.
*/
/* Note that only cfgetispeed is used because we have knowledge
* that only one speed is supported.
*/
priv->baud = cfgetispeed(termiosp);
/* Effect the changes immediately - note that we do not implement
* TCSADRAIN / TCSAFLUSH
*/
kinetis_uartconfigure(priv->uartbase, priv->baud, priv->clock,
priv->parity, priv->bits, priv->stop2,
iflow, oflow);
}
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_KINETIS_UART_BREAKS
case TIOCSBRK:
{
irqstate_t flags;
flags = enter_critical_section();
/* Send a longer break signal */
regval = up_serialin(priv, KINETIS_UART_S2_OFFSET);
regval &= ~UART_S2_BRK13;
# ifdef CONFIG_KINETIS_UART_EXTEDED_BREAK
regval |= UART_S2_BRK13;
# endif
up_serialout(priv, KINETIS_UART_S2_OFFSET, regval);
/* Send a break signal */
regval = up_serialin(priv, KINETIS_UART_C2_OFFSET);
regval |= UART_C2_SBK;
up_serialout(priv, KINETIS_UART_C2_OFFSET, regval);
# ifdef CONFIG_KINETIS_SERIALBRK_BSDCOMPAT
/* BSD compatibility: Turn break on, and leave it on */
up_txint(dev, false);
# else
/* Send a single break character
* Toggling SBK sends one break character. Per the manual
* Toggling implies clearing the SBK field before the break
* character has finished transmitting.
*/
regval &= ~(UART_C2_SBK);
up_serialout(priv, KINETIS_UART_C2_OFFSET, regval);
#endif
leave_critical_section(flags);
}
break;
case TIOCCBRK:
{
irqstate_t flags;
flags = enter_critical_section();
/* Configure TX back to UART
* If non BSD compatible: This code has no effect, the SBRK
* was already cleared.
* but for BSD compatibility: Turn break off
*/
regval = up_serialin(priv, KINETIS_UART_C2_OFFSET);
regval &= ~UART_C2_SBK;
up_serialout(priv, KINETIS_UART_C2_OFFSET, regval);
# ifdef CONFIG_KINETIS_SERIALBRK_BSDCOMPAT
/* Enable further tx activity */
up_txint(dev, true);
# endif
leave_critical_section(flags);
}
break;
#endif /* CONFIG_KINETIS_UART_BREAKS */
default:
ret = -ENOTTY;
@@ -915,9 +1213,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
}
return ret;
#else
return -ENOTTY;
#endif
}
/****************************************************************************
@@ -1030,6 +1325,79 @@ static bool up_rxavailable(struct uart_dev_s *dev)
#endif
}
/****************************************************************************
* Name: up_rxflowcontrol
*
* Description:
* Called when Rx buffer is full (or exceeds configured watermark levels
* if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined).
* Return true if UART activated RX flow control to block more incoming
* data
*
* Input parameters:
* dev - UART device instance
* nbuffered - the number of characters currently buffered
* (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
* not defined the value will be 0 for an empty buffer or the
* defined buffer size for a full buffer)
* upper - true indicates the upper watermark was crossed where
* false indicates the lower watermark has been crossed
*
* Returned Value:
* true if RX flow control activated.
*
****************************************************************************/
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool up_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper)
{
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS)
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint16_t ie;
if (priv->iflow)
{
/* Is the RX buffer full? */
if (upper)
{
/* Disable Rx interrupt to prevent more data being from
* peripheral. When hardware RTS is enabled, this will
* prevent more data from coming in.
*
* This function is only called when UART recv buffer is full,
* that is: "dev->recv.head + 1 == dev->recv.tail".
*
* Logic in "uart_read" will automatically toggle Rx interrupts
* when buffer is read empty and thus we do not have to re-
* enable Rx interrupts.
*/
ie = priv->ie;
ie &= ~UART_C2_RIE;
up_restoreuartint(priv, ie);
return true;
}
/* No.. The RX buffer is empty */
else
{
/* We might leave Rx interrupt disabled if full recv buffer was
* read empty. Enable Rx interrupt to make sure that more input is
* received.
*/
up_rxint(dev, true);
}
}
#endif
return false;
}
#endif
/****************************************************************************
* Name: up_send
*
arch/arm/src/kinetis/kinetis_tpm.h
+58
View File
@@ -0,0 +1,58 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_tpm.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_TPM_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_TPM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around tmp header files for the Kinetis family
* selected by the logic in chip.h.
*/
#if defined(KINETIS_K66)
# include "chip/kinetis_kx6tpm.h"
#else
# error "No TMP definitions for this Kinetis part"
#endif
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_TPM_H */
arch/arm/src/stm32/Kconfig
+13
View File
@@ -6165,6 +6165,19 @@ if STM32_SERIALDRIVER
comment "Serial Driver Configuration"
config STM32_SERIAL_RXDMA_BUFFER_SIZE
int "Rx DMA buffer size"
default 32
range 32 4096
depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA
---help---
The DMA buffer size when using RX DMA to emulate a FIFO.
When streaming data, the generic serial layer will be called
every time the FIFO receives half or this number of bytes.
Value given here will be rounded up to next multiple of 4 bytes.
config SERIAL_DISABLE_REORDERING
bool "Disable reordering of ttySx devices."
depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_UART4 || STM32_UART5 || STM32_USART6 || STM32_UART7 || STM32_UART8
arch/arm/src/stm32/stm32_freerun.c
+4 -2
View File
@@ -137,6 +137,7 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
*/
freerun->chan = chan;
freerun->width = STM32_TIM_GETWIDTH(freerun->tch);
freerun->running = false;
#ifdef CONFIG_CLOCK_TIMEKEEPING
@@ -153,7 +154,7 @@ int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan,
/* Set timer period */
STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX);
STM32_TIM_SETPERIOD(freerun->tch, (uint32_t)((1ull << freerun->width) - 1));
/* Start the counter */
@@ -248,7 +249,8 @@ int stm32_freerun_counter(struct stm32_freerun_s *freerun,
* usecs = (ticks * USEC_PER_SEC) / frequency;
*/
usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) /
usec = ((((uint64_t)overflow << freerun->width) +
(uint64_t)counter) * USEC_PER_SEC) /
freerun->frequency;
/* And return the value of the timer */
arch/arm/src/stm32/stm32_freerun.h
+1
View File
@@ -63,6 +63,7 @@
struct stm32_freerun_s
{
uint8_t chan; /* The timer/counter in use */
uint8_t width; /* Width of timer (16- or 32-bits) */
bool running; /* True: the timer is running */
FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */
uint32_t frequency;
arch/arm/src/stm32/stm32_serial.c
+8 -2
View File
@@ -182,8 +182,14 @@
* When streaming data, the generic serial layer will be called
* every time the FIFO receives half this number of bytes.
*/
# define RXDMA_BUFFER_SIZE 32
# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE)
# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE 32
# endif
# define RXDMA_MUTIPLE 4
# define RXDMA_MUTIPLE_MASK (RXDMA_MUTIPLE -1)
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \
+ RXDMA_MUTIPLE_MASK) \
& ~RXDMA_MUTIPLE_MASK)
/* DMA priority */
arch/arm/src/stm32/stm32_tim.c
+47 -10
View File
@@ -334,22 +334,23 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode);
/* Timer methods */
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
uint32_t period);
static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev);
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
stm32_tim_channel_t mode);
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
void *arg, int source);
static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev);
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
stm32_tim_channel_t mode);
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
void *arg, int source);
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source);
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source);
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source);
static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source);
static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source);
/************************************************************************************
* Private Data
@@ -361,6 +362,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops =
.setclock = stm32_tim_setclock,
.setperiod = stm32_tim_setperiod,
.getcounter = stm32_tim_getcounter,
.getwidth = stm32_tim_getwidth,
.setchannel = stm32_tim_setchannel,
.setcompare = stm32_tim_setcompare,
.getcapture = stm32_tim_getcapture,
@@ -904,6 +906,41 @@ static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev)
return stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET);
}
/************************************************************************************
* Name: stm32_tim_getwidth
************************************************************************************/
static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev)
{
/* Only TIM2 and TIM5 timers may be 32-bits in width
*
* Reference Table 2 of en.DM00042534.pdf
*/
switch (((struct stm32_tim_priv_s *)dev)->base)
{
/* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */
#if defined(CONFIG_STM32_TIM2) && !defined(STM32_STM32F10XX) && \
!defined(STM32_STM32L15XX)
case STM32_TIM2_BASE:
return 32;
#endif
/* TIM5 is 32-bits on all except F10x lines */
#if defined(CONFIG_STM32_TIM5) && !defined(STM32_STM32F10XX)
case STM32_TIM5_BASE:
return 32;
#endif
/* All others are 16-bit times */
default:
return 16;
}
}
/************************************************************************************
* Name: stm32_tim_setchannel
************************************************************************************/
arch/arm/src/stm32/stm32_tim.h
+2
View File
@@ -61,6 +61,7 @@
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
@@ -166,6 +167,7 @@ struct stm32_tim_ops_s
/* General and Advanced Timers Adds */
int (*getwidth)(FAR struct stm32_tim_dev_s *dev);
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
stm32_tim_channel_t mode);
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
arch/arm/src/stm32l4/Kconfig
+565 -73
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l4/Make.defs
+4
View File
@@ -212,3 +212,7 @@ ifeq ($(CONFIG_STM32L4_CAN),y)
CHIP_CSRCS += stm32l4_can.c
endif
ifeq ($(CONFIG_STM32L4_FIREWALL),y)
CHIP_CSRCS += stm32l4_firewall.c
endif
arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h → arch/arm/src/stm32l4/chip/stm32l4_gpio.h
+4 -4
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h
* arch/arm/src/stm32l4/chip/stm32l4_gpio.h
*
* Copyright (C) 2016, Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_GPIO_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_GPIO_H
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_GPIO_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_GPIO_H
/************************************************************************************
* Included Files
@@ -371,5 +371,5 @@
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_GPIO_H */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_GPIO_H */
arch/arm/src/stm32l4/chip/stm32l4_memorymap.h
+20 -7
View File
@@ -40,7 +40,7 @@
* Pre-processor Definitions
************************************************************************************/
/* STM32F40XXX Address Blocks *******************************************************/
/* STM32L4XXX Address Blocks ********************************************************/
#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (96k or 256k) */
@@ -50,7 +50,7 @@
# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI*/
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0000000-0xbfffffff: QSPI register block */
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
@@ -68,10 +68,13 @@
/* 0x08100000-0x0fffffff: Reserved */
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 32Kb or 64Kb SRAM2 */
/* 0x10010000-0x1ffeffff: Reserved */
#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff7a0f: System memory */
/* 0x1fff7a10-0x1fff7fff: Reserved */
#define STM32L4_OPTION_BASE 0x1fffc000 /* 0x1fffc000-0x1fffc007: Option bytes */
/* 0x1fffc008-0x1fffffff: Reserved */
#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
/* 0x1fff7400-0x1fff77ff: Reserved */
#define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */
/* 0x1fff7810-0x1ffff7ff: Reserved */
#define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */
/* 0x1ffff810-0x1fffffff: Reserved */
/* System Memory Addresses **********************************************************/
@@ -84,9 +87,13 @@
#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
* type.
* 0: LQFP64
* 1: WLCSP64
* 2: LQFP100
* 3: UFBGA132
* 4: LQFP144, WLCSP81 or WLCSP72
* 10: WLCSP49
* 11: UFBGA64
* 12: UFBGA100
* 16: UFBGA169
* 17: WLCSP100
*/
@@ -124,8 +131,14 @@
#define STM32L4_OPAMP_BASE 0x40007800
#define STM32L4_DAC_BASE 0x40007400
#define STM32L4_PWR_BASE 0x40007000
#define STM32L4_CAN2_BASE 0x40006800
#if defined(CONFIG_STM32L4_STM32L4X2)
# define STM32L4_USB_SRAM_BASE 0x40006c00
# define STM32L4_USB_FS_BASE 0x40006800
#else
# define STM32L4_CAN2_BASE 0x40006800
#endif
#define STM32L4_CAN1_BASE 0x40006400
#define STM32L4_CRS_BASE 0x40006000
#define STM32L4_I2C3_BASE 0x40005c00
#define STM32L4_I2C2_BASE 0x40005800
#define STM32L4_I2C1_BASE 0x40005400
arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
+3 -2
View File
@@ -43,9 +43,10 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_pinmap.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_pinmap.h"
#else
# error "Unsupported STM32 L4 pin map"
#endif
arch/arm/src/stm32l4/chip/stm32l4_syscfg.h
+13 -150
View File
@@ -1,8 +1,8 @@
/****************************************************************************************************
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4_syscfg.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,162 +31,25 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H
/****************************************************************************************************
/************************************************************************************
* Included Files
****************************************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_syscfg.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_syscfg.h"
#else
# error "Unsupported STM32 L4 chip"
#endif
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
/* Register Addresses *******************************************************************************/
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SYSCFG memory remap register */
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_MEMRMP_MASK (7 << SYSCFG_MEMRMP_SHIFT)
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_FMC (2 << SYSCFG_MEMRMP_SHIFT) /* 010: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 (112kB) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_QSPI (6 << SYSCFG_MEMRMP_SHIFT) /* 110: QUADSPI mapped at 0x0000 0000 */
#define SYSCFG_FBMODE (1 << 8) /* Bit 8: Flash Bank mode selection */
/* SYSCFG configuration register 1 */
#define SYSCFG_CFGR1_FWDIS (1 << 0) /* Bit 0: Firewall disable */
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
/* SYSCFG external interrupt configuration register 1-4 */
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin (only on STM32L496xx/4A6xx) */
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin (only on STM32L496xx/4A6xx) */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* SYSCFG SRAM2 control and status register */
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable (same) */
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable (same) */
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
/* SYSCFG SRAM2 write protection register */
/* There is one bit per SRAM2 page (0 to 31) */
/* SYSCFG SRAM2 key register */
#define SYSCFG_SKR_SHIFT 0
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
/* SYSCFG SRAM2 write protection register 2 (only on STM32L496xx/4A6xx) */
/* There is one bit per SRAM2 page (32 to 63) */
#endif /* CONFIG_STM32L4_STM32L476XX || CONFIG_STM32L4_STM32L486XX || CONFIG_STM32L4_STM32L496XX */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H */
arch/arm/src/stm32l4/chip/stm32l4x6xx_uart.h → arch/arm/src/stm32l4/chip/stm32l4_uart.h
+9 -9
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x6xx_uart.h
* arch/arm/src/stm32l4/chip/stm32l4_uart.h
*
* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_UART_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_UART_H
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_UART_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_UART_H
/************************************************************************************
* Included Files
@@ -57,7 +57,7 @@
#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupot and status register */
#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
@@ -139,7 +139,7 @@
/* Control register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
@@ -150,7 +150,7 @@
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M0 (1 << 12) /* Bit 12: word length */
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
@@ -163,7 +163,7 @@
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
USART_CR1_TCIE|USART_CR1_TXEIE|USART_CR1_PEIE|USART_CR1_CMIE| \
@@ -171,7 +171,7 @@
/* Control register 2 */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
@@ -314,5 +314,5 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4X6XX_UART_H */
#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_UART_H */
arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h
+461
View File
@@ -0,0 +1,461 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_DMA_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_DMA_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* 14 Channels Total: 7 DMA1 Channels(1-7) and 7 DMA2 channels (1-7) */
#define DMA1 0
#define DMA2 1
#define DMA3 2
#define DMA4 3
#define DMA5 4
#define DMA6 5
#define DMA7 6
/* Register Offsets *****************************************************************/
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
#define STM32L4_DMACHAN1_OFFSET 0x0000
#define STM32L4_DMACHAN2_OFFSET 0x0014
#define STM32L4_DMACHAN3_OFFSET 0x0028
#define STM32L4_DMACHAN4_OFFSET 0x003c
#define STM32L4_DMACHAN5_OFFSET 0x0050
#define STM32L4_DMACHAN6_OFFSET 0x0064
#define STM32L4_DMACHAN7_OFFSET 0x0078
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
/* Register Addresses ***************************************************************/
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define DMA_CHAN_SHIFT(n) ((n) << 2)
#define DMA_CHAN_MASK 0x0f
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
/* DMA interrupt status register */
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
/* DMA interrupt flag clear register */
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
/* DMA channel configuration register */
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
/* DMA channel number of data register */
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
/* DMA Channel mapping. Each DMA channel has a mapping to one of several
* possible sources/sinks of data. The requests from peripherals assigned to a
* channel are multiplexed together before entering the DMA block. This means
* that only one request on a given channel can be enabled at once.
*
* Alternative DMA channel selections are provided with a numeric suffix like _1,
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file.
*/
#define STM32L4_DMA1_CHAN1 (0)
#define STM32L4_DMA1_CHAN2 (1)
#define STM32L4_DMA1_CHAN3 (2)
#define STM32L4_DMA1_CHAN4 (3)
#define STM32L4_DMA1_CHAN5 (4)
#define STM32L4_DMA1_CHAN6 (5)
#define STM32L4_DMA1_CHAN7 (6)
#define STM32L4_DMA2_CHAN1 (7)
#define STM32L4_DMA2_CHAN2 (8)
#define STM32L4_DMA2_CHAN3 (9)
#define STM32L4_DMA2_CHAN4 (10)
#define STM32L4_DMA2_CHAN5 (11)
#define STM32L4_DMA2_CHAN6 (12)
#define STM32L4_DMA2_CHAN7 (13)
/* DMA Channel settings include a channel and an alternative function.
* Channel is in bits 0..7
* Request number is in bits 8..15
*/
#define DMACHAN_SETTING(chan, req) ((((req) & 0xff) << 8) | ((chan) & 0xff))
#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF
#define DMACHAN_SETTING_CHANNEL_SHIFT (0)
#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00
#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
/* ADC */
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
/* AES */
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6)
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6)
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6)
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6)
/* DAC */
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
/* DCMI */
#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4)
#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0)
/* DFSDM */
#define DMACHAN_DFSDM1_FLT0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
#define DMACHAN_DFSDM1_FLT1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
/* I2C */
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0)
#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0)
/* QUADSPI */
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
/* SAI */
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
/* SDMMC */
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
/* SPI */
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
/* SWPMI */
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
/* TIM */
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
/* UART */
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_DMA_H */
arch/arm/src/stm32l4/chip/stm32l4x3xx_firewall.h
+103
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/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x3xx_firewall.h
*
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_FIREWALL_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_FIREWALL_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
/* Register Addresses ***************************************************************/
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Code Segment Start Address */
#define FIREWALL_CSSADD_SHIFT 8
#define FIREWALL_CSSADD_MASK (0xFFFF << FIREWALL_CSSADD_SHIFT)
/* Code Segment Length */
#define FIREWALL_CSSLENG_SHIFT 8
#define FIREWALL_CSSLENG_MASK (0x3FFF << FIREWALL_CSSLENG_SHIFT)
/* Non-volatile Data Segment Start Address */
#define FIREWALL_NVDSADD_SHIFT 8
#define FIREWALL_NVDSADD_MASK (0xFFFF << FIREWALL_NVDSADD_SHIFT)
/* Non-volatile Data Segment Length */
#define FIREWALL_NVDSLENG_SHIFT 8
#define FIREWALL_NVDSLENG_MASK (0x3FFF << FIREWALL_NVDSLENG_SHIFT)
/* Volatile Data Segment Start Address */
#define FIREWALL_VDSADD_SHIFT 6
#define FIREWALL_VDSADD_MASK (0x07FF << FIREWALL_VDSADD_SHIFT)
/* Volatile Data Segment Length */
#define FIREWALL_VDSLENG_SHIFT 6
#define FIREWALL_VDSLENG_MASK (0x07FF << FIREWALL_VDSLENG_SHIFT)
/* Configuration Register */
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
#define FIREWALL_CR_VDS (1 << 1) /* Bit 1: Volatile data shared */
#define FIREWALL_CR_VDE (1 << 2) /* Bit 2: Volatile data execution */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_FIREWALL_H */
arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h
+559
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arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
+789
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l4/chip/stm32l4x3xx_syscfg.h
+182
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@@ -0,0 +1,182 @@
/****************************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x3xx_syscfg.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_SYSCFG_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X3)
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
/* Register Addresses *******************************************************************************/
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SYSCFG memory remap register */
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_MEMRMP_MASK (7 << SYSCFG_MEMRMP_SHIFT)
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 (112kB) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_QSPI (6 << SYSCFG_MEMRMP_SHIFT) /* 110: QUADSPI mapped at 0x0000 0000 */
/* SYSCFG configuration register 1 */
#define SYSCFG_CFGR1_FWDIS (1 << 0) /* Bit 0: Firewall disable */
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
/* SYSCFG external interrupt configuration register 1-4 */
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
/* No PORTF or PORTG on these chips */
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
#define SYSCFG_EXTICR_PORT_MASK (7)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* SYSCFG SRAM2 control and status register */
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable (same) */
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable (same) */
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
/* SYSCFG SRAM2 write protection register */
/* There is one bit per SRAM2 page (0 to 31) */
/* SYSCFG SRAM2 key register */
#define SYSCFG_SKR_SHIFT 0
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
#endif /* CONFIG_STM32L4_STM32L4X3 */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_SYSCFG_H */
arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h
+8
View File
@@ -89,11 +89,19 @@
/* Volatile Data Segment Start Address */
#define FIREWALL_VDSADD_SHIFT 6
#if defined(CONFIG_STM32L4_STM32L496XX)
#define FIREWALL_VDSADD_MASK (0x0FFF << FIREWALL_VDSADD_SHIFT)
#else
#define FIREWALL_VDSADD_MASK (0x07FF << FIREWALL_VDSADD_SHIFT)
#endif
/* Volatile Data Segment Length */
#define FIREWALL_VDSLENG_SHIFT 6
#if defined(CONFIG_STM32L4_STM32L496XX)
#define FIREWALL_VDSLENG_MASK (0x0FFF << FIREWALL_VDSLENG_SHIFT)
#else
#define FIREWALL_VDSLENG_MASK (0x07FF << FIREWALL_VDSLENG_SHIFT)
#endif
/* Configuration Register */
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
+2 -3
View File
@@ -44,8 +44,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6)
/****************************************************************************************************
* Pre-processor Definitions
@@ -807,5 +806,5 @@
# define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT)
# define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT)
#endif /* CONFIG_STM32L4_STM32L476XX || CONFIG_STM32L4_STM32L486XX || CONFIG_STM32L4_STM32L496XX */
#endif /* CONFIG_STM32L4_STM32L4X6 */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H */
arch/arm/src/stm32l4/chip/stm32l4x6xx_syscfg.h
+191
View File
@@ -0,0 +1,191 @@
/****************************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x6xx_syscfg.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_SYSCFG_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6)
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
/* Register Addresses *******************************************************************************/
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SYSCFG memory remap register */
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_MEMRMP_MASK (7 << SYSCFG_MEMRMP_SHIFT)
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_FMC (2 << SYSCFG_MEMRMP_SHIFT) /* 010: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 (112kB) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_QSPI (6 << SYSCFG_MEMRMP_SHIFT) /* 110: QUADSPI mapped at 0x0000 0000 */
#define SYSCFG_FBMODE (1 << 8) /* Bit 8: Flash Bank mode selection */
/* SYSCFG configuration register 1 */
#define SYSCFG_CFGR1_FWDIS (1 << 0) /* Bit 0: Firewall disable */
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
/* SYSCFG external interrupt configuration register 1-4 */
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin (only on STM32L496xx/4A6xx) */
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin (only on STM32L496xx/4A6xx) */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* SYSCFG SRAM2 control and status register */
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable (same) */
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable (same) */
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
/* SYSCFG SRAM2 write protection register */
/* There is one bit per SRAM2 page (0 to 31) */
/* SYSCFG SRAM2 key register */
#define SYSCFG_SKR_SHIFT 0
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
/* SYSCFG SRAM2 write protection register 2 (only on STM32L496xx/4A6xx) */
/* There is one bit per SRAM2 page (32 to 63) */
#endif /* CONFIG_STM32L4_STM32L4X6 */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_SYSCFG_H */
arch/arm/src/stm32l4/stm32l4_dma.c
+3 -22
View File
@@ -41,34 +41,15 @@
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/* This file is only a thin shell that includes the correct DMA implementation
* for the selected STM32 family. The correct file cannot be selected by
* the make system because it needs the intelligence that only exists in
* chip.h that can associate an STM32 part number with an STM32 family.
*
* TODO: do we need separate implementation for STM32L4X3?
*/
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#include "stm32l4x6xx_dma.c"
#else
# error "Unsupported STM32L4 chip"
arch/arm/src/stm32l4/stm32l4_dma.h
+3 -2
View File
@@ -49,9 +49,10 @@
/* Include the correct DMA register definitions for this STM32 family */
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_dma.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_dma.h"
#else
# error "Unsupported STM32L4 chip"
#endif
arch/arm/src/stm32l4/stm32l4_firewall.c
+4
View File
@@ -38,6 +38,10 @@
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include "up_arch.h"
#include "chip/stm32l4_syscfg.h"
#include "stm32l4_firewall.h"
arch/arm/src/stm32l4/stm32l4_firewall.h
+6 -5
View File
@@ -47,9 +47,10 @@
/* Include the correct firewall register definitions for this STM32L4 family */
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \
defined(CONFIG_STM32L4_STM32L496XX)
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_firewall.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_firewall.h"
#else
# error "Unsupported STM32L4 chip"
#endif
@@ -60,11 +61,11 @@
struct stm32l4_firewall_t
{
uintptr_t *codestart;
uintptr_t codestart;
size_t codelen;
uintptr_t *nvdatastart;
uintptr_t nvdatastart;
size_t nvdatalen;
uintptr_t *datastart;
uintptr_t datastart;
size_t datalen;
uint8_t datashared:1;
uint8_t dataexec :1;
arch/arm/src/stm32l4/stm32l4_flash.h
+54 -24
View File
@@ -41,42 +41,72 @@
* Pre-processor Definitions
************************************************************************************/
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based on the chip
* part number. This value can be overridden with CONFIG_STM32L4_FLASH_OVERRIDE_x
*
* Parts STM32L4xxE have 512Kb of FLASH
* Parts STM32L4xxG have 1024Kb of FLASH
*
* N.B. Only Single bank mode is supported
*/
#define _K(x) ((x)*1024)
#if !defined(CONFIG_STM32L4_FLASH_CONFIG_DEFAULT) && \
#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32L4_FLASH_CONFIG_G)
# define CONFIG_STM32L4_FLASH_CONFIG_DEFAULT
# define CONFIG_STM32L4_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
#if defined(CONFIG_STM32L4_FLASH_CONFIG_DEFAULT)
# define STM32L4_FLASH_NPAGES 512
# define STM32L4_FLASH_PAGESIZE 2048
#endif /* CONFIG_STM32L4_FLASH_CONFIG_DEFAULT */
/* Override of the Flash has been chosen */
/* Override of the Flash Has been Chosen */
#if !defined(CONFIG_STM32L4_FLASH_CONFIG_DEFAULT)
/* Define the Valid Configuration the F1 and F3 */
# if defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
# define STM32L4_FLASH_NPAGES 128
# define STM32L4_FLASH_PAGESIZE 2048
# elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */
# define STM32L4_FLASH_NPAGES 256
# define STM32L4_FLASH_PAGESIZE 2048
# elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
# define STM32L4_FLASH_NPAGES 512
# define STM32L4_FLASH_PAGESIZE 2048
# else
#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32L4_FLASH_CONFIG_B
# undef CONFIG_STM32L4_FLASH_CONFIG_C
# undef CONFIG_STM32L4_FLASH_CONFIG_E
# undef CONFIG_STM32L4_FLASH_CONFIG_G
# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
# define CONFIG_STM32L4_FLASH_CONFIG_B
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C)
# define CONFIG_STM32L4_FLASH_CONFIG_C
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_E)
# define CONFIG_STM32L4_FLASH_CONFIG_E
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G)
# define CONFIG_STM32L4_FLASH_CONFIG_G
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
# define STM32L4_FLASH_NPAGES 64
# define STM32L4_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
# define STM32L4_FLASH_NPAGES 128
# define STM32L4_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */
# define STM32L4_FLASH_NPAGES 256
# define STM32L4_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
# define STM32L4_FLASH_NPAGES 512
# define STM32L4_FLASH_PAGESIZE 2048
#else
# error "unknown flash configuration!"
#endif
#ifdef STM32L4_FLASH_PAGESIZE
# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE)
#endif /* def STM32L4_FLASH_PAGESIZE */
#endif
/* Register Offsets *****************************************************************/
@@ -128,7 +158,7 @@
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states <=64 <=26 */
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states <=80 <=26 */
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Pprefetch enable */
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */

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