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arch/arm/src/stm32l4 and boards/arm/stm32l4/nucleo-l476rg: Add support for LPTIM timers on the STM32L4 as PWM outputs.
This commit is contained in:
Matias N
Gregory Nutt
@@ -1810,6 +1810,74 @@ config STM32L4_ONESHOT_MAXTIMERS
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of the timers and places an upper limit on the number of oneshot
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timers that you can use.
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config STM32L4_LPTIM1_PWM
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bool "LPTIM1 PWM"
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default n
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depends on STM32L4_LPTIM1
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select PWM
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---help---
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Reserve low-power timer 1 for use by PWM
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Timer devices may be used for different purposes. One special purpose is
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to generate modulated outputs for such things as motor control. If STM32L4_LPTIM1
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is defined then THIS following may also be defined to indicate that
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the timer is intended to be used for pulsed output modulation.
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if STM32L4_LPTIM1_PWM
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choice
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prompt "LPTIM1 clock source"
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default STM32L4_LPTIM1_CLK_APB1
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config STM32L4_LPTIM1_CLK_APB1
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bool "Clock LPTIM1 from APB1"
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config STM32L4_LPTIM1_CLK_LSE
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bool "Clock LPTIM1 from LSE"
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config STM32L4_LPTIM1_CLK_LSI
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bool "Clock LPTIM1 from LSI"
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config STM32L4_LPTIM1_CLK_HSI
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bool "Clock LPTIM1 from HSI"
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endchoice
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endif # STM32L4_LPTIM1_PWM
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config STM32L4_LPTIM2_PWM
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bool "LPTIM2 PWM"
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default n
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depends on STM32L4_LPTIM2
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select PWM
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---help---
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Reserve low-power timer 2 for use by PWM
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Timer devices may be used for different purposes. One special purpose is
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to generate modulated outputs for such things as motor control. If STM32L4_LPTIM2
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is defined then THIS following may also be defined to indicate that
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the timer is intended to be used for pulsed output modulation.
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if STM32L4_LPTIM2_PWM
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choice
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prompt "LPTIM2 clock source"
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default STM32L4_LPTIM2_CLK_APB1
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config STM32L4_LPTIM2_CLK_APB1
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bool "Clock LPTIM2 from APB1"
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config STM32L4_LPTIM2_CLK_LSE
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bool "Clock LPTIM2 from LSE"
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config STM32L4_LPTIM2_CLK_LSI
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bool "Clock LPTIM2 from LSI"
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config STM32L4_LPTIM2_CLK_HSI
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bool "Clock LPTIM2 from HSI"
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endchoice
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endif # STM32L4_LPTIM2_PWM
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config STM32L4_TIM1_PWM
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bool "TIM1 PWM"
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default n
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@@ -114,4 +114,12 @@
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#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Single Mode */
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#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Continuous Mode */
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#define LPTIM_ISR_CMPM (1 << 0) /* Bit 0: Compare match */
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#define LPTIM_ISR_ARRM (1 << 1) /* Bit 1: Autoreload match */
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#define LPTIM_ISR_EXTTRIG (1 << 2) /* Bit 2: External trigger edge event */
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#define LPTIM_ISR_CMPOK (1 << 3) /* Bit 3: Compare register update OK */
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#define LPTIM_ISR_ARROK (1 << 4) /* Bit 4: Autoreload register update OK */
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#define LPTIM_ISR_UP (1 << 5) /* Bit 5: Counter direction change down to up */
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#define LPTIM_ISR_DOWN (1 << 6) /* Bit 6: Counter direction change up to down */
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#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H */
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@@ -116,18 +116,6 @@
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#define STM32L4_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */
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#define STM32L4_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */
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/* Low-Power Timers - LPTIM1 and LPTIM2 */
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#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status register */
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#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt clear register */
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#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt enable register */
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#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration register */
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#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control register */
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#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare register */
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#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Auto-reloud register (16-bit) */
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#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter (16-bit) */
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#define STM32L4_LPTIM_OR_OFFSET 0x001c /* Options Register */
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/* Register Addresses ***************************************************************/
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/* Advanced Timers - TIM1 and TIM8 */
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@@ -715,40 +703,40 @@
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#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
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#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */
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#define ATIM_BDTR_BKF_MASK (15 << ATIM_BDTR_BKF_SHIFT)
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# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */
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# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
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# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
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# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
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# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
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# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
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# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
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# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
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# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
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# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
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# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
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# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
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# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
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# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
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# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
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# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
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# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */
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# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
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# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
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# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
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# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
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# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
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# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
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# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
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# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
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# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
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# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
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# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
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# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
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# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
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# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
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# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
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#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */
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#define ATIM_BDTR_BK2F_MASK (15 << ATIM_BDTR_BK2F_SHIFT)
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# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */
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# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
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# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
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# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
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# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
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# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
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# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */
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# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
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# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
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# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
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# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
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# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
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# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
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# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
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#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */
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#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */
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+560
-155
File diff suppressed because it is too large
Load Diff
@@ -55,11 +55,14 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is
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* to generate modulated outputs for such things as motor control. If CONFIG_STM32L4_TIMn
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* is defined then the CONFIG_STM32L4_TIMn_PWM must also be defined to indicate that
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* timer "n" is intended to be used for pulsed output signal generation.
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* to generate modulated outputs for such things as motor control. If
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* CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM must also be
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* defined to indicate that timer "n" is intended to be used for pulsed output
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* signal generation.
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*/
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#ifndef CONFIG_STM32L4_TIM1
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@@ -97,14 +100,16 @@
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/* Check if PWM support for any channel is enabled. */
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#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \
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defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \
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defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \
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defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \
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defined(CONFIG_STM32L4_TIM17_PWM)
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#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \
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defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \
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defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \
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defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \
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defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \
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defined(CONFIG_STM32L4_LPTIM2_PWM)
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#include <arch/board/board.h>
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#include "hardware/stm32l4_tim.h"
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#include "hardware/stm32l4_lptim.h"
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#ifdef CONFIG_PWM_MULTICHAN
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@@ -677,6 +682,40 @@
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# endif
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#endif
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/* REVISIT: any other LPTIM implementations have more than one channel? */
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#define CONFIG_STM32L4_LPTIM1_CHANNEL 1
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#ifdef CONFIG_STM32L4_LPTIM1_PWM
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# if !defined(CONFIG_STM32L4_LPTIM1_CHANNEL)
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# error "CONFIG_STM32L4_LPTIM1_CHANNEL must be provided"
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# elif CONFIG_STM32L4_LPTIM1_CHANNEL == 1
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# define CONFIG_STM32L4_LPTIM1_CHANNEL1 1
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# define CONFIG_STM32L4_LPTIM1_CH1MODE CONFIG_STM32L4_LPTIM1_CHMODE
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# define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT
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# define PWM_LPTIM1_CH1NCFG 0
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# else
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# error "Unsupported value of CONFIG_STM32L4_LPTIM1_CHANNEL"
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# endif
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#endif
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/* REVISIT: any other LPTIM implementations have more than one channel? */
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#define CONFIG_STM32L4_LPTIM2_CHANNEL 1
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#ifdef CONFIG_STM32L4_LPTIM2_PWM
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# if !defined(CONFIG_STM32L4_LPTIM2_CHANNEL)
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# error "CONFIG_STM32L4_LPTIM2_CHANNEL must be provided"
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# elif CONFIG_STM32L4_LPTIM2_CHANNEL == 1
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# define CONFIG_STM32L4_LPTIM2_CHANNEL1 1
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# define CONFIG_STM32L4_LPTIM2_CH1MODE CONFIG_STM32L4_LPTIM2_CHMODE
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# define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT
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# define PWM_LPTIM2_CH1NCFG 0
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# else
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# error "Unsupported value of CONFIG_STM32L4_LPTIM2_CHANNEL"
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# endif
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#endif
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#define PWM_NCHANNELS 1
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#endif
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@@ -723,6 +762,25 @@ extern "C"
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FAR struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer);
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/****************************************************************************
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* Name: stm32l4_lp_pwminitialize
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*
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* Description:
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* Initialize one low-power timer for use with the upper_level PWM driver.
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*
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* Input Parameters:
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* timer - A number identifying the timer use. The number of valid timer
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* IDs varies with the STM32 MCU and MCU family but is somewhere in
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* the range of {1,..,2}.
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*
|
||||
* Returned Value:
|
||||
* On success, a pointer to the STM32 lower half PWM driver is returned.
|
||||
* NULL is returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
@@ -261,6 +261,9 @@
|
||||
#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1
|
||||
#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1
|
||||
|
||||
#define GPIO_LPTIM1_CH1OUT GPIO_LPTIM1_OUT_1
|
||||
#define GPIO_LPTIM2_CH1OUT GPIO_LPTIM2_OUT_2
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
@@ -202,8 +202,9 @@
|
||||
* DFSDM
|
||||
*/
|
||||
|
||||
/* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
|
||||
as per comment above HSI) */
|
||||
/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
|
||||
* as per comment above HSI) .
|
||||
*/
|
||||
|
||||
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
||||
|
||||
@@ -271,24 +272,26 @@
|
||||
/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
|
||||
|
||||
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
||||
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||||
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
|
||||
/* REVISIT : this can be configured */
|
||||
|
||||
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (80MHz) */
|
||||
|
||||
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
||||
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||||
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
|
||||
/* REVISIT : this can be configured */
|
||||
|
||||
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||||
@@ -301,6 +304,7 @@
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8,15,16,17 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
/* REVISIT : this can be configured */
|
||||
|
||||
/* TODO SDMMC */
|
||||
@@ -488,8 +492,8 @@
|
||||
#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||||
#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||||
#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||||
#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||||
#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||||
#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
||||
@@ -42,6 +42,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
@@ -262,6 +263,43 @@ int stm32l4_pwm_setup(void)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_LPTIM1_PWM)
|
||||
pwm = stm32l4_lp_pwminitialize(1);
|
||||
if (!pwm)
|
||||
{
|
||||
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the PWM driver at "/dev/lppwm1" */
|
||||
|
||||
ret = pwm_register("/dev/lppwm1", pwm);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: pwm_register failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_LPTIM2_PWM)
|
||||
pwm = stm32l4_lp_pwminitialize(2);
|
||||
if (!pwm)
|
||||
{
|
||||
aerr("ERROR: Failed to get the STM32L4 PWM lower half\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the PWM driver at "/dev/lppwm2" */
|
||||
|
||||
ret = pwm_register("/dev/lppwm2", pwm);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: pwm_register failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Now we are initialized */
|
||||
|
||||
initialized = true;
|
||||
|
||||
Reference in New Issue
Block a user