boards/arm/stm32h7: Add support fpr nucleo-h753zi board

Add BSP for the NUCLEO-H753ZI board using nucleo-h743zi2 as base. Signed-off-by: Peter Barada <peter.barada@gmail.com>
2026-05-23 06:39:01 +08:00 · 2026-05-20 10:47:52 -04:00
parent ad182bcb4b
commit fc2f6c9fc5
28 changed files with 3964 additions and 0 deletions
@@ -0,0 +1,302 @@
+=================
+ST Nucleo H753ZI
+=================
+
+.. tags:: chip:stm32, chip:stm32h7, chip:stm32h753
+
+This page discusses issues unique to NuttX configurations for the
+STMicro NUCLEO-H753ZI development board featuring the STM32H753ZI
+MCU. The STM32H753ZI is a 400MHz Cortex-M7 operation with 2MBytes Flash
+memory and 1MByte SRAM. The board features:
+
+- On-board ST-LINK/V2 for programming and debugging,
+- 3 user LEDs
+- Two pushbuttons (user[B1] and reset)
+- 32.768 kHz crystal oscillator
+- USB OTG FS with Micro-AB connectors
+- Ethernet connector compliant with IEEE-802.3-2002
+- Board connectors:
+  - USB with Micro-AB
+  - SWD
+  - Ethernet RJ45
+  - ST Zio connector including Arduino Uno V3
+  - ST morpho
+
+Refer to the http://www.st.com website for further information about this
+board (search keyword: NUCLEO-H753ZI)
+
+Serial Console
+==============
+
+Many options are available for a serial console via the Morpho connector.
+Here two common serial console options are suggested:
+
+1. Arduino Serial Shield.
+
+   If you are using a standard Arduino RS-232 shield with the serial
+   interface with RX on pin D0 and TX on pin D1 from USART6:
+
+      ======== ========= =====
+      ARDUINO  FUNCTION  GPIO
+      ======== ========= =====
+      DO RX    USART6_RX PG9
+      D1 TX    USART6_TX PG14
+      ======== ========= =====
+
+2. Nucleo Virtual Console.
+
+   The virtual console uses Serial Port 3 (USART3) with TX on PD8 and RX on
+   PD9.
+
+      ================= ===
+      VCOM Signal       Pin
+      ================= ===
+      SERIAL_RX         PD9
+      SERIAL_TX         PD8
+      ================= ===
+
+   These signals are internally connected to the on board ST-Link.
+
+   The Nucleo virtual console is the default serial console in all
+   configurations unless otherwise stated in the description of the
+   configuration.
+
+Configurations
+==============
+
+nsh:
+----
+
+This configuration provides a basic NuttShell configuration (NSH)
+for the Nucleo-H753ZI.  The default console is the VCOM on USART3.
+
+jumbo:
+------
+
+This configuration enables many Apache NuttX features.  This is
+mostly to help provide additional code coverage in CI, but also
+allows for a users to see a wide range of features that are
+supported by the OS.
+
+Some highlights:
+  NSH:
+    - Readline with tab completion
+    - Readline command history
+
+  Performance and Monitoring:
+    - RAM backed syslog
+    - Syslog with process name, priority, and timestamp
+    - Process Snapshot with stack usage, cpu usage, and signal information
+    - Interrupt Statistics
+    - procfs filesystem (required for ifconfig, ifup/ifdown)
+
+  Networking:
+    - IPv4 Networking
+    - Ethernet
+    - DHCP Client
+    - iperf
+    - telnet daemon
+
+  File Systems:
+    - FAT filesystem
+    - LittleFS
+    - RAM MTD device
+
+  Testing:
+    - OS Test with FPU support
+    - Filesystem testing
+
+  USB Host:
+    - USB Hub support
+    - Mass Storage Device
+    - Trace Monitoring
+
+
+..
+   ADE
+   telnetd [7:100]
+
+   NuttShell (NSH) NuttX-12.13.0
+   nsh> uname -a
+   NuttX  12.13.0 81dc339415-dirty May 19 2026 13:07:19 arm nucleo-h753zi
+   nsh> help
+   help usage:  help [-v] [<cmd>]
+
+       .           cp          expr        mkrd        route       truncate    
+       [           cmp         false       mount       set         uname       
+       ?           dirname     fdinfo      mv          kill        umount      
+       addroute    date        free        nslookup    pkill       unset       
+       alias       delroute    help        pidof       sleep       uptime      
+       unalias     df          hexdump     printf      usleep      watch       
+       arp         dmesg       ifconfig    ps          source      wget        
+       basename    echo        irqinfo     pwd         test        xd          
+       break       env         ls          reboot      top         wait        
+       cat         exec        mkdir       rm          time        
+       cd          exit        mkfatfs     rmdir       true        
+
+   Builtin Apps:
+       buttons     getprime    netcat      ping        tc          
+       dd          hidkbd      nsh         renew       telnetd     
+       fstest      iperf       ostest      sh          
+   nsh> ls
+   /:
+    dev/
+    mnt/
+    proc/
+   nsh> free
+         total       used       free    maxused    maxfree  nused  nfree name
+        953572     158596     794976     158992     461520     64      5 Umem
+   nsh> irqinfo
+   IRQ HANDLER  ARGUMENT    COUNT    RATE    TIME
+    11 080012e5 00000000       1031   50.738    0
+    15 0800b00d 00000000       2032  100.000    1
+    55 080007d5 24000000       1455   71.604    5
+    77 0800cccd 00000000          8    0.393    1
+   117 0800bf85 00000000        205   10.168 21558
+   nsh> ifconfig
+   eth0	Link encap:Ethernet HWaddr ea:63:b9:20:1d:46 at RUNNING mtu 1486
+   	inet addr:10.0.0.2 DRaddr:10.0.0.1 Mask:255.255.255.0
+
+   lo	Link encap:Local Loopback at RUNNING mtu 1518
+   	inet addr:127.0.0.1 DRaddr:127.0.0.1 Mask:255.0.0.0
+
+                IPv4   TCP   UDP  ICMP
+   Received     0004  0000  0004  0000
+   Dropped      0000  0000  0000  0000
+     IPv4        VHL: 0000   Frg: 0000
+     Checksum   0000  0000  0000  ----
+     TCP         ACK: 0000   SYN: 0000
+                 RST: 0000  0000
+     Type       0000  ----  ----  0000
+   Sent         0000  0000  0000  0000
+     Rexmit     ----  0000  ----  ----
+   nsh> renew eth0
+   nsh> ifconfig eth0
+   eth0	Link encap:Ethernet HWaddr ea:63:b9:20:1d:46 at RUNNING mtu 1486
+   	inet addr:192.168.3.106 DRaddr:192.168.3.1 Mask:255.255.255.0
+
+   nsh> ifconfig eth0
+   eth0	Link encap:Ethernet HWaddr ea:63:b9:20:1d:46 at RUNNING mtu 1486
+   	inet addr:192.168.3.106 DRaddr:192.168.3.1 Mask:255.255.255.0
+
+   nsh> ifconfig eth0
+   eth0	Link encap:Ethernet HWaddr ea:63:b9:20:1d:46 at RUNNING mtu 1486
+   	inet addr:192.168.3.106 DRaddr:192.168.3.1 Mask:255.255.255.0
+
+   nsh> ifconfig
+   eth0	Link encap:Ethernet HWaddr ea:63:b9:20:1d:46 at RUNNING mtu 1486
+   	inet addr:192.168.3.106 DRaddr:192.168.3.1 Mask:255.255.255.0
+
+   lo	Link encap:Local Loopback at RUNNING mtu 1518
+   	inet addr:127.0.0.1 DRaddr:127.0.0.1 Mask:255.0.0.0
+
+                IPv4   TCP   UDP  ICMP
+   Received     004e  0033  001a  0001
+   Dropped      0000  0000  0000  0000
+     IPv4        VHL: 0000   Frg: 0000
+     Checksum   0000  0000  0000  ----
+     TCP         ACK: 0000   SYN: 0000
+                 RST: 0000  0000
+     Type       0000  ----  ----  0000
+   Sent         0035  0032  0002  0001
+     Rexmit     ----  0000  ----  ----
+   nsh> ping www.google.com
+   PING 142.251.155.119 56 bytes of data
+   56 bytes from 142.251.155.119: icmp_seq=0 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=1 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=2 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=3 time=20.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=4 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=5 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=6 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=7 time=20.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=8 time=10.0 ms
+   56 bytes from 142.251.155.119: icmp_seq=9 time=10.0 ms
+   10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
+   rtt min/avg/max/mdev = 10.000/12.000/20.000/4.000 ms
+   nsh> ls /dev
+   /dev:
+    buttons
+    console
+    kmsg
+    null
+    rammtd
+    sda
+    telnet
+    ttyS0
+    zero
+   nsh> ls /mnt
+   /mnt:
+    lfs/
+   nsh> echo "This will go away on reboot." > /mnt/lfs/afile
+   nsh> cat /mnet/lfs/afile
+   nsh: cat: open failed: 2
+   nsh> mount -t vfat /dev/sda /mnt/sda
+   nsh> echo "Thos will stay on the USB drive" > /mnt/sda/afile
+   nsh> ls /mnt/sda
+   /mnt/sda:
+    GARMIN/
+    afile
+   nsh> rebootADE
+   telnetd [7:100]
+
+   NuttShell (NSH) NuttX-12.13.0
+   nsh> ls /mnt/lfs
+   /mnt/lfs:
+    .
+    ..
+   nsh> mount -t vfat /dev/sda /mnt/sda
+   nsh> ls /mnt/sda
+   /mnt/sda:
+    GARMIN/
+    afile
+   nsh> cat /mnt/sda/afail
+   nsh: cat: open failed: 2
+   nsh> cat /mnt/sda/afile
+   Thos will stay on the USB drive
+   nsh> buttons
+   buttons_main: Starting the button_daemon
+   buttons_main: button_daemon started
+   button_daemon: Running
+   button_daemon: Opening /dev/buttons
+   button_daemon: Supported BUTTONs 0x01
+   nsh> B1 was pressed
+   B1 was released
+   B1 was pressed
+   B1 was released
+
+   nsh> ps
+     TID   PID  PPID PRI POLICY   TYPE    NPX STATE    EVENT     SIGMASK            STACK    USED FILLED    CPU COMMAND
+       0     0     0   0 FIFO     Kthread   - Ready              0000000000000000 0001000 0000552  55.2%  100.0% Idle_Task
+       1     0     0 224 RR       Kthread   - Waiting  Semaphore 0000000000000000 0001976 0000632  31.9%   0.0% hpwork 0x24000130 0x24000180
+       2     0     0 100 RR       Kthread   - Waiting  Semaphore 0000000000000000 0001976 0000632  31.9%   0.0% lpwork 0x240000c0 0x24000110
+       4     0     0 100 RR       Kthread   - Waiting  Semaphore 0000000000000000 0002008 0000896  44.6%   0.0% usbhost
+       5     0     0  50 RR       Kthread   - Waiting  Signal    0000000000000000 0004048 0000616  15.2%   0.0% USB_Monitor
+       6     6     0 100 RR       Task      - Running            0000000000000000 0004048 0001800  44.4%   0.0% nsh_main
+       7     7     0 100 RR       Task      - Waiting  Semaphore 0000000000000000 0002008 0000912  45.4%   0.0% telnetd
+       9     9     0 100 RR       Task      - Waiting  Signal    0000000000000000 0004048 0000720  17.7%   0.0% button_daemon
+   nsh> 
+   ```
+
+   ```
+   peter@legion:~$ telnet 192.168.3.106
+   Trying 192.168.3.106...
+   Connected to 192.168.3.106.
+   Escape character is '^]'.
+   
+   NuttShell (NSH) NuttX-12.13.0
+   nsh> ps
+     TID   PID  PPID PRI POLICY   TYPE    NPX STATE    EVENT     SIGMASK            STACK    USED FILLED    CPU COMMAND
+       0     0     0   0 FIFO     Kthread   - Ready              0000000000000000 0001000 0000552  55.2%  100.0% Idle_Task
+       1     0     0 224 RR       Kthread   - Waiting  Semaphore 0000000000000000 0001976 0000632  31.9%   0.0% hpwork 0x24000130 0x24000180
+       2     0     0 100 RR       Kthread   - Waiting  Semaphore 0000000000000000 0001976 0000632  31.9%   0.0% lpwork 0x240000c0 0x24000110
+       4     0     0 100 RR       Kthread   - Waiting  Semaphore 0000000000000000 0002008 0000896  44.6%   0.0% usbhost
+       5     0     0  50 RR       Kthread   - Waiting  Signal    0000000000000000 0004048 0000632  15.6%   0.0% USB_Monitor
+       6     6     0 100 RR       Task      - Waiting  Semaphore 0000000000000000 0004048 0001416  34.9%   0.0% nsh_main
+       7     7     0 100 RR       Task      - Waiting  Semaphore 0000000000000000 0002008 0000912  45.4%   0.0% telnetd
+       9     9     0 100 RR       Task      - Running            0000000000000000 0002000 0001896  94.8%!  0.0% Telnet_session
+   nsh> ^]
+   telnet> quit
+   Connection closed.
+   peter@legion:~$ 
+   ```
@@ -2019,6 +2019,15 @@ config ARCH_BOARD_LINUM_STM32H753BI
 	---help---
 		The Linum board is based on the STMicro STM32H753BI MCU.

+config ARCH_BOARD_NUCLEO_H753ZI
+	bool "STM32H753 Nucleo H753ZI"
+	depends on ARCH_CHIP_STM32H753ZI
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	---help---
+		STMicro Nucleo H753ZI board based on the STMicro STM32H753ZI MCU.
+
 config ARCH_BOARD_OPENH743I
 	bool "Waveshare OpenH743I board"
 	depends on ARCH_CHIP_STM32H743II
@@ -3786,6 +3795,7 @@ config ARCH_BOARD
 	default "stm32h745i-disco"             if ARCH_BOARD_STM32H745I_DISCO
 	default "stm32h750b-dk"                if ARCH_BOARD_STM32H750B_DK
 	default "linum-stm32h753bi"            if ARCH_BOARD_LINUM_STM32H753BI
+	default "nucleo-h753zi"                if ARCH_BOARD_NUCLEO_H753ZI
 	default "openh743i"                    if ARCH_BOARD_OPENH743I
 	default "portenta-h7"                  if ARCH_BOARD_PORTENTA_H7
 	default "nucleo-l073rz"                if ARCH_BOARD_NUCLEO_L073RZ
@@ -4540,6 +4550,9 @@ endif
 if ARCH_BOARD_LINUM_STM32H753BI
 source "boards/arm/stm32h7/linum-stm32h753bi/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_H753ZI
+source "boards/arm/stm32h7/nucleo-h753zi/Kconfig"
+endif
 if ARCH_BOARD_OPENH743I
 source "boards/arm/stm32h7/openh743i/Kconfig"
 endif
@@ -0,0 +1,23 @@
+# ##############################################################################
+# boards/arm/stm32h7/nucleo-h753zi/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_NUCLEO_H753ZI
+
+endif # ARCH_BOARD_NUCLEO_H753ZI
@@ -0,0 +1,144 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_DATE is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h753zi"
+CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753ZI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_USB=y
+CONFIG_DEBUG_USB_ERROR=y
+CONFIG_DEBUG_USB_WARN=y
+CONFIG_DEFAULT_TASK_STACKSIZE=4096
+CONFIG_DHCPC_RENEW_STACKSIZE=2048
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_EXAMPLES_BUTTONS=y
+CONFIG_EXAMPLES_BUTTONS_NAME0="B1"
+CONFIG_EXAMPLES_BUTTONS_NAMES=y
+CONFIG_EXAMPLES_BUTTONS_QTD=1
+CONFIG_EXAMPLES_HIDKBD=y
+CONFIG_EXAMPLES_TOUCHSCREEN=y
+CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/mouse0"
+CONFIG_EXAMPLES_TOUCHSCREEN_MOUSE=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FS_FAT=y
+CONFIG_FS_LITTLEFS=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INPUT_BUTTONS=y
+CONFIG_INPUT_BUTTONS_LOWER=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBM=y
+CONFIG_LINE_MAX=64
+CONFIG_MM_REGIONS=4
+CONFIG_MTD=y
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETUTILS_DISCOVER=y
+CONFIG_NETUTILS_IPERF=y
+CONFIG_NETUTILS_NETCAT=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NET_ARP_IPIN=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=1500
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_IGMP=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_ROUTE=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_MAXARGUMENTS=12
+CONFIG_NSH_READLINE=y
+CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+CONFIG_RAMLOG=y
+CONFIG_RAMLOG_BUFSIZE=10240
+CONFIG_RAMLOG_SYSLOG=y
+CONFIG_RAMMTD=y
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_CPULOAD_SYSCLK=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKSTACKSIZE=2048
+CONFIG_SCHED_IRQMONITOR=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPWORKSTACKSIZE=2048
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32H7_ETHMAC=y
+CONFIG_STM32H7_HSI48=y
+CONFIG_STM32H7_OTGFS=y
+CONFIG_STM32H7_PHYSR=31
+CONFIG_STM32H7_PHYSR_100FD=0x0018
+CONFIG_STM32H7_PHYSR_100HD=0x0008
+CONFIG_STM32H7_PHYSR_10FD=0x0014
+CONFIG_STM32H7_PHYSR_10HD=0x0004
+CONFIG_STM32H7_PHYSR_ALTCONFIG=y
+CONFIG_STM32H7_PHYSR_ALTMODE=0x001c
+CONFIG_STM32H7_USART3=y
+CONFIG_SYSLOG_INTBUFFER=y
+CONFIG_SYSLOG_PRIORITY=y
+CONFIG_SYSLOG_PROCESS_NAME=y
+CONFIG_SYSLOG_TIMESTAMP=y
+CONFIG_SYSTEM_CLE=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_STACKSIZE=2048
+CONFIG_SYSTEM_PING=y
+CONFIG_SYSTEM_PING_STACKSIZE=2048
+CONFIG_SYSTEM_TELNETD_STACKSIZE=2048
+CONFIG_TASK_NAME_SIZE=16
+CONFIG_TESTING_FSTEST=y
+CONFIG_TESTING_FSTEST_STACKSIZE=2048
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_GETPRIME_STACKSIZE=2048
+CONFIG_TESTING_OSTEST=y
+CONFIG_TESTING_OSTEST_FPUSTACKSIZE=2048
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USBHOST=y
+CONFIG_USBHOST_HIDKBD=y
+CONFIG_USBHOST_HIDMOUSE=y
+CONFIG_USBHOST_HUB=y
+CONFIG_USBHOST_MSC=y
+CONFIG_USBHOST_MSC_NOTIFIER=y
+CONFIG_USBHOST_TRACE=y
+CONFIG_USBHOST_TRACE_VERBOSE=y
+CONFIG_USBMONITOR=y
@@ -0,0 +1,86 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h753zi"
+CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753ZI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FS_FAT=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBM=y
+CONFIG_LINE_MAX=64
+CONFIG_MM_REGIONS=4
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETUTILS_DISCOVER=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NET_ARP_IPIN=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=1500
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_IGMP=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_ROUTE=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SPI=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32H7_ETHMAC=y
+CONFIG_STM32H7_HSI48=y
+CONFIG_STM32H7_OTGFS=y
+CONFIG_STM32H7_PHYSR=31
+CONFIG_STM32H7_PHYSR_100FD=0x0018
+CONFIG_STM32H7_PHYSR_100HD=0x0008
+CONFIG_STM32H7_PHYSR_10FD=0x0014
+CONFIG_STM32H7_PHYSR_10HD=0x0004
+CONFIG_STM32H7_PHYSR_ALTCONFIG=y
+CONFIG_STM32H7_PHYSR_ALTMODE=0x001c
+CONFIG_STM32H7_USART3=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USBHOST=y
+CONFIG_USBHOST_MSC=y
+CONFIG_USBHOST_MSC_NOTIFIER=y
@@ -0,0 +1,45 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h753zi"
+CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753ZI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LINE_MAX=64
+CONFIG_MM_REGIONS=4
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32H7_USART3=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y
@@ -0,0 +1,129 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ADC=y
+CONFIG_ANALOG=y
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h753zi"
+CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753ZI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_RAMVECTORS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEFAULT_TASK_STACKSIZE=4096
+CONFIG_DEV_GPIO=y
+CONFIG_DHCPC_RENEW_STACKSIZE=2048
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FS_FAT=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_IOEXPANDER=y
+CONFIG_LIBC_EXECFUNCS=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_LIBM=y
+CONFIG_LINE_MAX=64
+CONFIG_MM_REGIONS=4
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xc0a8b201
+CONFIG_NETUTILS_DISCOVER=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NET_ARP_IPIN=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=1500
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_IGMP=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_ROUTE=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_FILE_APPS=y
+CONFIG_NSH_READLINE=y
+CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PRIORITY_INHERITANCE=y
+CONFIG_PTHREAD_MUTEX_TYPES=y
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+CONFIG_PTHREAD_STACK_MIN=1024
+CONFIG_PWM=y
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=10
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKSTACKSIZE=2048
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPWORKSTACKSIZE=2048
+CONFIG_SCHED_WAITPID=y
+CONFIG_SENSORS=y
+CONFIG_SENSORS_QENCODER=y
+CONFIG_SERIAL_TERMIOS=y
+CONFIG_SPI=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32H7_ADC1=y
+CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000
+CONFIG_STM32H7_ADC1_TIMTRIG=1
+CONFIG_STM32H7_DMA1=y
+CONFIG_STM32H7_ETHMAC=y
+CONFIG_STM32H7_HSI48=y
+CONFIG_STM32H7_OTGFS=y
+CONFIG_STM32H7_PHYSR=31
+CONFIG_STM32H7_PHYSR_100FD=0x0018
+CONFIG_STM32H7_PHYSR_100HD=0x0008
+CONFIG_STM32H7_PHYSR_10FD=0x0014
+CONFIG_STM32H7_PHYSR_10HD=0x0004
+CONFIG_STM32H7_PHYSR_ALTCONFIG=y
+CONFIG_STM32H7_PHYSR_ALTMODE=0x001c
+CONFIG_STM32H7_PWM_MULTICHAN=y
+CONFIG_STM32H7_TIM1=y
+CONFIG_STM32H7_TIM1_QE=y
+CONFIG_STM32H7_TIM2=y
+CONFIG_STM32H7_TIM2_ADC=y
+CONFIG_STM32H7_TIM3=y
+CONFIG_STM32H7_TIM3_CH1OUT=y
+CONFIG_STM32H7_TIM3_CH2OUT=y
+CONFIG_STM32H7_TIM3_CHANNEL1=y
+CONFIG_STM32H7_TIM3_CHANNEL2=y
+CONFIG_STM32H7_TIM3_PWM=y
+CONFIG_STM32H7_USART3=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_SYSTEM_PING_STACKSIZE=2048
+CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=2048
+CONFIG_SYSTEM_TELNETD_STACKSIZE=2048
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TLS_NCLEANUP=1
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USBHOST=y
+CONFIG_USBHOST_MSC=y
+CONFIG_USBHOST_MSC_NOTIFIER=y
+CONFIG_USEC_PER_TICK=1000
@@ -0,0 +1,71 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NET_IPv4 is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ALLOW_BSD_COMPONENTS=y
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h753zi"
+CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753ZI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_CANUTILS_CANDUMP=y
+CONFIG_CANUTILS_CANSEND=y
+CONFIG_CANUTILS_LIBCANUTILS=y
+CONFIG_CAN_PREALLOC_CONNS=2
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_NET=y
+CONFIG_DEBUG_NET_ERROR=y
+CONFIG_DEBUG_NET_INFO=y
+CONFIG_DEBUG_NET_WARN=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_FS_PROCFS=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LINE_MAX=64
+CONFIG_MM_REGIONS=4
+CONFIG_NET=y
+CONFIG_NETDEV_CAN_BITRATE_IOCTL=y
+CONFIG_NETDEV_IFINDEX=y
+CONFIG_NETDEV_LATEINIT=y
+CONFIG_NET_CAN=y
+CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE=500
+CONFIG_NET_CAN_RAW_TX_DEADLINE=y
+CONFIG_NET_CAN_SOCK_OPTS=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAMLOG=y
+CONFIG_RAMLOG_SYSLOG=y
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32H7_FDCAN1=y
+CONFIG_STM32H7_FDCAN2=y
+CONFIG_STM32H7_USART3=y
+CONFIG_SYSLOG_TIMESTAMP=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y
@@ -0,0 +1,471 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/include/board.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/* Do not include STM32 H7 header files here */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* The Nucleo-144  board provides the following clock sources:
+ *
+ *   MCO: 8 MHz from MCO output of ST-LINK is used as input clock (default)
+ *   X2:  32.768 KHz crystal for LSE
+ *   X3:  HSE crystal oscillator (not provided)
+ *
+ * So we have these clock source available within the STM32
+ *
+ *   HSI: 16 MHz RC factory-trimmed
+ *   LSI: 32 KHz RC
+ *   HSE: 8 MHz from MCO output of ST-LINK
+ *   LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL        8000000ul /* ST-LINK MCO */
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 8,000,000
+ *
+ * To use HSE, configure the solder bridges on the board:
+ *
+ *  - SB148, SB8 and SB9 OFF
+ *  - SB112 and SB149 ON
+ *
+ * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected.
+ * Otherwise you must select VCOH.
+ *
+ * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ *     1 <= PLLM <= 63
+ *     4 <= PLLN <= 512
+ *   150 MHz <= PLL_VCOL <= 420MHz
+ *   192 MHz <= PLL_VCOH <= 836MHz
+ *
+ * SYSCLK  = PLL_VCO / PLLP
+ * CPUCLK  = SYSCLK / D1CPRE
+ * Subject to
+ *
+ *   PLLP1   = {2, 4, 6, 8, ..., 128}
+ *   PLLP2,3 = {2, 3, 4, ..., 128}
+ *   CPUCLK <= 400 MHz
+ */
+
+#define STM32_BOARD_USEHSE
+#define STM32_HSEBYP_ENABLE
+
+#define STM32_PLLCFG_PLLSRC      RCC_PLLCKSELR_PLLSRC_HSE
+
+/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
+ *
+ *   PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
+ *
+ *   PLL1P = PLL1_VCO/2  = 800 MHz / 2   = 400 MHz
+ *   PLL1Q = PLL1_VCO/4  = 800 MHz / 4   = 200 MHz
+ *   PLL1R = PLL1_VCO/8  = 800 MHz / 8   = 100 MHz
+ */
+
+#define STM32_PLLCFG_PLL1CFG     (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
+                                  RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
+                                  RCC_PLLCFGR_DIVP1EN | \
+                                  RCC_PLLCFGR_DIVQ1EN | \
+                                  RCC_PLLCFGR_DIVR1EN)
+#define STM32_PLLCFG_PLL1M       RCC_PLLCKSELR_DIVM1(2)
+#define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(200)
+#define STM32_PLLCFG_PLL1P       RCC_PLL1DIVR_P1(2)
+#define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(4)
+#define STM32_PLLCFG_PLL1R       RCC_PLL1DIVR_R1(8)
+
+#define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 2) * 200)
+#define STM32_PLL1P_FREQUENCY    (STM32_VCO1_FREQUENCY / 2)
+#define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 4)
+#define STM32_PLL1R_FREQUENCY    (STM32_VCO1_FREQUENCY / 8)
+
+/* PLL2 */
+
+#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
+                              RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
+                              RCC_PLLCFGR_DIVP2EN)
+#define STM32_PLLCFG_PLL2M       RCC_PLLCKSELR_DIVM2(2)
+#define STM32_PLLCFG_PLL2N       RCC_PLL2DIVR_N2(200)
+#define STM32_PLLCFG_PLL2P       RCC_PLL2DIVR_P2(40)
+#define STM32_PLLCFG_PLL2Q       0
+#define STM32_PLLCFG_PLL2R       0
+
+#define STM32_VCO2_FREQUENCY     ((STM32_HSE_FREQUENCY / 2) * 200)
+#define STM32_PLL2P_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
+#define STM32_PLL2Q_FREQUENCY
+#define STM32_PLL2R_FREQUENCY
+
+/* PLL3 */
+
+#define STM32_PLLCFG_PLL3CFG 0
+#define STM32_PLLCFG_PLL3M   0
+#define STM32_PLLCFG_PLL3N   0
+#define STM32_PLLCFG_PLL3P   0
+#define STM32_PLLCFG_PLL3Q   0
+#define STM32_PLLCFG_PLL3R   0
+
+#define STM32_VCO3_FREQUENCY
+#define STM32_PLL3P_FREQUENCY
+#define STM32_PLL3Q_FREQUENCY
+#define STM32_PLL3R_FREQUENCY
+
+/* SYSCLK = PLL1P = 400 MHz
+ * CPUCLK = SYSCLK / 1 = 400 MHz
+ */
+
+#define STM32_RCC_D1CFGR_D1CPRE  (RCC_D1CFGR_D1CPRE_SYSCLK)
+#define STM32_SYSCLK_FREQUENCY   (STM32_PLL1P_FREQUENCY)
+#define STM32_CPUCLK_FREQUENCY   (STM32_SYSCLK_FREQUENCY / 1)
+
+/* Configure Clock Assignments */
+
+/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max)
+ * HCLK1 = HCLK2 = HCLK3 = HCLK4
+ */
+
+#define STM32_RCC_D1CFGR_HPRE   RCC_D1CFGR_HPRE_SYSCLKd2        /* HCLK  = SYSCLK / 2 */
+#define STM32_ACLK_FREQUENCY    (STM32_SYSCLK_FREQUENCY / 2)    /* ACLK in D1, HCLK3 in D1 */
+#define STM32_HCLK_FREQUENCY    (STM32_SYSCLK_FREQUENCY / 2)    /* HCLK in D2, HCLK4 in D3 */
+
+/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
+
+#define STM32_RCC_D2CFGR_D2PPRE1  RCC_D2CFGR_D2PPRE1_HCLKd4       /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY     (STM32_HCLK_FREQUENCY/4)
+
+/* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */
+
+#define STM32_RCC_D2CFGR_D2PPRE2  RCC_D2CFGR_D2PPRE2_HCLKd4       /* PCLK2 = HCLK / 4 */
+#define STM32_PCLK2_FREQUENCY     (STM32_HCLK_FREQUENCY/4)
+
+/* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */
+
+#define STM32_RCC_D1CFGR_D1PPRE   RCC_D1CFGR_D1PPRE_HCLKd4        /* PCLK3 = HCLK / 4 */
+#define STM32_PCLK3_FREQUENCY     (STM32_HCLK_FREQUENCY/4)
+
+/* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */
+
+#define STM32_RCC_D3CFGR_D3PPRE   RCC_D3CFGR_D3PPRE_HCLKd4       /* PCLK4 = HCLK / 4 */
+#define STM32_PCLK4_FREQUENCY     (STM32_HCLK_FREQUENCY/4)
+
+/* Timer clock frequencies */
+
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM15_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM16_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM17_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+
+/* Kernel Clock Configuration
+ *
+ * Note: look at Table 54 in ST Manual
+ */
+
+/* I2C123 clock source - HSI */
+
+#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
+
+/* I2C4 clock source - HSI */
+
+#define STM32_RCC_D3CCIPR_I2C4SRC    RCC_D3CCIPR_I2C4SEL_HSI
+
+/* SPI123 clock source - PLL1Q */
+
+#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
+
+/* SPI45 clock source - APB (PCLK2?) */
+
+#define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_APB
+
+/* SPI6 clock source - APB (PCLK4) */
+
+#define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PCLK4
+
+/* USB 1 and 2 clock source - HSI48 */
+
+#define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_HSI48
+
+/* ADC 1 2 3 clock source - pll2_pclk */
+
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
+
+/* FDCAN 1 2 clock source - HSE (TODO: Not the best choice for this board?) */
+
+#define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
+
+/* FLASH wait states
+ *
+ *  ------------ ---------- -----------
+ *  Vcore        MAX ACLK   WAIT STATES
+ *  ------------ ---------- -----------
+ *  1.15-1.26 V     70 MHz    0
+ *  (VOS1 level)   140 MHz    1
+ *                 210 MHz    2
+ *  1.05-1.15 V     55 MHz    0
+ *  (VOS2 level)   110 MHz    1
+ *                 165 MHz    2
+ *                 220 MHz    3
+ *  0.95-1.05 V     45 MHz    0
+ *  (VOS3 level)    90 MHz    1
+ *                 135 MHz    2
+ *                 180 MHz    3
+ *                 225 MHz    4
+ *  ------------ ---------- -----------
+ */
+
+#define BOARD_FLASH_WAITSTATES 4
+
+/* SDMMC definitions ********************************************************/
+
+/* Init 400kHz, PLL1Q/(2*250) */
+
+#define STM32_SDMMC_INIT_CLKDIV     (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+
+/* Just set these to 25 MHz for now, PLL1Q/(2*4),
+ * for default speed 12.5MB/s
+ */
+
+#define STM32_SDMMC_MMCXFR_CLKDIV   (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_SDXFR_CLKDIV    (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+
+#define STM32_SDMMC_CLKCR_EDGE      STM32_SDMMC_CLKCR_NEGEDGE
+
+/* LED definitions **********************************************************/
+
+/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
+ * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
+ * The following definitions assume the default Solder Bridges are installed.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
+ * any way. The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED1        0
+#define BOARD_LED2        1
+#define BOARD_LED3        2
+#define BOARD_NLEDS       3
+
+#define BOARD_LED_GREEN   BOARD_LED1
+#define BOARD_LED_BLUE    BOARD_LED2
+#define BOARD_LED_RED     BOARD_LED3
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT    (1 << BOARD_LED1)
+#define BOARD_LED2_BIT    (1 << BOARD_LED2)
+#define BOARD_LED3_BIT    (1 << BOARD_LED3)
+
+/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
+ * include/board.h and src/stm32_leds.c. The LEDs are used to encode
+ * OS-related events as follows:
+ *
+ *
+ *   SYMBOL                     Meaning                      LED state
+ *                                                        Red   Green Blue
+ *   ----------------------  --------------------------  ------ ------ ----
+ */
+
+#define LED_STARTED        0 /* NuttX has been started   OFF    OFF   OFF  */
+#define LED_HEAPALLOCATE   1 /* Heap has been allocated  OFF    OFF   ON   */
+#define LED_IRQSENABLED    2 /* Interrupts enabled       OFF    ON    OFF  */
+#define LED_STACKCREATED   3 /* Idle stack created       OFF    ON    ON   */
+#define LED_INIRQ          4 /* In an interrupt          N/C    N/C   GLOW */
+#define LED_SIGNAL         5 /* In a signal handler      N/C    GLOW  N/C  */
+#define LED_ASSERTION      6 /* An assertion failed      GLOW   N/C   GLOW */
+#define LED_PANIC          7 /* The system has crashed   Blink  OFF   N/C  */
+#define LED_IDLE           8 /* MCU is in sleep mode     ON     OFF   OFF  */
+
+/* Thus if the Green LED is statically on, NuttX has successfully booted and
+ * is, apparently, running normally.  If the Red LED is flashing at
+ * approximately 2Hz, then a fatal error has been detected and the system
+ * has halted.
+ */
+
+/* Button definitions *******************************************************/
+
+/* The NUCLEO board supports one button:  Pushbutton B1, labeled "User", is
+ * connected to GPIO PI11.
+ * A high value will be sensed when the button is depressed.
+ */
+
+#define BUTTON_USER        0
+#define NUM_BUTTONS        1
+#define BUTTON_USER_BIT    (1 << BUTTON_USER)
+
+/* Alternate function pin selections ****************************************/
+
+/* ADC */
+
+#define GPIO_ADC12_INP5   GPIO_ADC12_INP5_0                      /* PB1 */
+#define GPIO_ADC123_INP10 GPIO_ADC123_INP10_0                    /* PC0 */
+#define GPIO_ADC123_INP12 GPIO_ADC123_INP12_0                    /* PC2 */
+#define GPIO_ADC12_INP13  GPIO_ADC12_INP13_0                     /* PC3 */
+#define GPIO_ADC12_INP15  GPIO_ADC12_INP15_0                     /* PA3 */
+
+/* USART3 (Nucleo Virtual Console) */
+
+#define GPIO_USART3_RX    (GPIO_USART3_RX_3|GPIO_SPEED_100MHz)   /* PD9 */
+#define GPIO_USART3_TX    (GPIO_USART3_TX_3|GPIO_SPEED_100MHz)   /* PD8 */
+
+/* USART6 (Arduino Serial Shield) */
+
+#define GPIO_USART6_RX    (GPIO_USART6_RX_2|GPIO_SPEED_100MHz)   /* PG9 */
+#define GPIO_USART6_TX    (GPIO_USART6_TX_2|GPIO_SPEED_100MHz)   /* PG14 */
+
+/* I2C1 Use Nucleo I2C1 pins */
+
+#define GPIO_I2C1_SCL     (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz)     /* PB8 - D15 */
+#define GPIO_I2C1_SDA     (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz)     /* PB9 - D14 */
+
+/* I2C2 Use Nucleo I2C2 pins */
+
+#define GPIO_I2C2_SCL     (GPIO_I2C2_SCL_2|GPIO_SPEED_50MHz)     /* PF1 - D69 */
+#define GPIO_I2C2_SDA     (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz)     /* PF0 - D68 */
+#define GPIO_I2C2_SMBA    (GPIO_I2C2_SMBA_2|GPIO_SPEED_50MHz)    /* PF2 - D70 */
+
+/* SPI3 */
+
+#define GPIO_SPI3_MISO    (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz)    /* PB4 */
+#define GPIO_SPI3_MOSI    (GPIO_SPI3_MOSI_4|GPIO_SPEED_50MHz)    /* PB5 */
+#define GPIO_SPI3_SCK     (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz)     /* PB3 */
+#define GPIO_SPI3_NSS     (GPIO_SPI3_NSS_2|GPIO_SPEED_50MHz)     /* PA4 */
+
+/* TIM1 */
+
+#define GPIO_TIM1_CH1OUT  (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz)  /* PE9  - D6 */
+#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3|GPIO_SPEED_50MHz) /* PE8  - D42 */
+#define GPIO_TIM1_CH2OUT  (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz)  /* PE11 - D5 */
+#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3|GPIO_SPEED_50MHz) /* PE10 - D40 */
+
+#define GPIO_TIM1_CH1IN   (GPIO_TIM1_CH1IN_2|GPIO_SPEED_50MHz)   /* PE9 */
+#define GPIO_TIM1_CH2IN   (GPIO_TIM1_CH2IN_2|GPIO_SPEED_50MHz)   /* PE11 */
+
+/* TIM3 */
+
+#define GPIO_TIM3_CH1OUT  (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz)  /* PB4  */
+#define GPIO_TIM3_CH2OUT  (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_50MHz)  /* PB5  */
+
+#define GPIO_TIM3_CH1IN   (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz)   /* PA4 */
+#define GPIO_TIM3_CH2IN   (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz)   /* PB5 */
+
+/* TIM4 */
+
+#define GPIO_TIM4_CH1IN   (GPIO_TIM4_CH1IN_2|GPIO_SPEED_50MHz)   /* PD12 */
+#define GPIO_TIM4_CH2IN   (GPIO_TIM4_CH2IN_2|GPIO_SPEED_50MHz)   /* PD13 */
+
+/* FDCAN1 */
+
+#define GPIO_CAN1_RX      (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz)      /* PD0 */
+#define GPIO_CAN1_TX      (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz)      /* PD1 */
+
+/* FDCAN2 */
+
+#define GPIO_CAN2_RX      (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz)      /* PB5 - D11 */
+#define GPIO_CAN2_TX      (GPIO_CAN2_TX_2|GPIO_SPEED_50MHz)      /* PB6 - D1 */
+
+/* OTG */
+
+#define GPIO_OTGFS_DM     (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)    /* PA11 */
+#define GPIO_OTGFS_DP     (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)    /* PA12 */
+#define GPIO_OTGFS_ID     (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)    /* PA10 */
+
+/* Ethernet */
+
+#define GPIO_ETH_MDC          (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz)
+#define GPIO_ETH_MDIO         (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_CRS_DV  (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_RXD0    (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_RXD1    (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_TXD0    (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_TXD1    (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz)
+#define GPIO_ETH_RMII_TX_EN   (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz)
+
+/* DMA **********************************************************************/
+
+#define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* DMA1 */
+#define DMAMAP_SPI3_TX DMAMAP_DMA12_SPI3TX_0 /* DMA1 */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H */
@@ -0,0 +1,41 @@
+############################################################################
+# boards/arm/stm32h7/nucleo-h753zi/scripts/Make.defs
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = flash.ld
+ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
+
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
@@ -0,0 +1,203 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/scripts/flash.ld
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* The STM32H753ZI has 2048Kb of main FLASH memory. The flash memory is
+ * partitioned into a User Flash memory and a System Flash memory. Each
+ * of these memories has two banks:
+ *
+ *   1) User Flash memory:
+ *
+ *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each
+ *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each
+ *
+ *   2) System Flash memory:
+ *
+ *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector
+ *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector
+ *
+ *   3) User option bytes for user configuration, only in Bank 1.
+ *
+ * In the STM32H753ZI, two different boot spaces can be selected through
+ * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
+ * BOOT_ADD1 option bytes:
+ *
+ *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
+ *      ST programmed value: Flash memory at 0x0800:0000
+ *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
+ *      ST programmed value: System bootloader at 0x1FF0:0000
+ *
+ * TODO: Check next paragraph with nucleo schematics
+ *
+ * NuttX does not modify these option bytes. On the unmodified NUCLEO-H753ZI
+ * board, the BOOT0 pin is at ground so by default, the STM32 will boot
+ * to address 0x0800:0000 in FLASH.
+ *
+ * The STM32H753ZI also has 1024Kb of data SRAM.
+ * SRAM is split up into several blocks and into three power domains:
+ *
+ *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
+ *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus
+ *
+ *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000
+ *
+ *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit
+ *           DTCM ports. The DTCM-RAM could be used for critical real-time
+ *           data, such as interrupt service routines or stack / heap memory.
+ *           Both DTCM-RAMs can be used in parallel (for load/store operations)
+ *           thanks to the Cortex-M7 dual issue capability.
+ *
+ *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000
+ *
+ *           This RAM is connected to ITCM 64-bit interface designed for
+ *           execution of critical real-times routines by the CPU.
+ *
+ *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA
+ *      through D1 domain AXI bus matrix
+ *
+ *      2.1) 512Kb of SRAM beginning at address 0x2400:0000
+ *
+ *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA
+ *      through D2 domain AHB bus matrix
+ *
+ *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000
+ *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000
+ *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000
+ *
+ *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000
+ *
+ *   4) AHB SRAM (D3 domain) accessible by most of system masters
+ *      through D3 domain AHB bus matrix
+ *
+ *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000
+ *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ */
+
+MEMORY
+{
+  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+  flash (rx)  : ORIGIN = 0x08000000, LENGTH = 2048K
+  dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+  dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+  sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
+  sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
+  sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
+  sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
+  sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
+  bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+SECTIONS
+{
+    .text :
+    {
+        _stext = ABSOLUTE(.);
+        *(.vectors)
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        _etext = ABSOLUTE(.);
+    } > flash
+
+    .init_section :
+    {
+        _sinit = ABSOLUTE(.);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
+        _einit = ABSOLUTE(.);
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab*)
+    } > flash
+
+    __exidx_start = ABSOLUTE(.);
+    .ARM.exidx :
+    {
+        *(.ARM.exidx*)
+    } > flash
+    __exidx_end = ABSOLUTE(.);
+
+    _eronly = ABSOLUTE(.);
+
+    .data :
+    {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        . = ALIGN(4);
+        _edata = ABSOLUTE(.);
+    } > sram AT > flash
+
+    .bss :
+    {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(8);
+        _ebss = ABSOLUTE(.);
+    } > sram
+
+    /* Emit the D3 power domain section for locating BDMA data
+     *
+     * Static data with locate_data(".sram4") will be located
+     * at start of SRAM4; the rest of SRAM4 will be added to the heap.
+     */
+
+    .sram4_reserve (NOLOAD) :
+    {
+        *(.sram4)
+        . = ALIGN(4);
+        _sram4_heap_start = ABSOLUTE(.);
+    } > sram4
+
+    /* Stabs debugging sections. */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/scripts/memory.ld
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* TODO: Add description for memory organisation */
+
+MEMORY
+{
+  /* ITCM boot address */
+
+  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
+
+  /* 2048Kb FLASH */
+
+  kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+  uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
+  xflash (rx) : ORIGIN = 0x08040000, LENGTH = 1792K
+
+  /* 288Kb SRAM123 */
+
+  ksram (rwx) : ORIGIN = 0x30000000, LENGTH = 16K
+  usram (rwx) : ORIGIN = 0x30004000, LENGTH = 16K
+  xsram (rwx) : ORIGIN = 0x30008000, LENGTH = 288K - 32K
+
+  /* 512Kb of contiguous AXI SRAM */
+
+  sram (rwx)  : ORIGIN = 0x24000000, LENGTH = 512K
+
+  /* DTCM SRAM */
+
+  dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+  dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
+
+  sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
+  bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
+}
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/scripts/user-space.ld
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* NOTE:  This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+    .userspace : {
+        *(.userspace)
+    } > uflash
+
+    .text : {
+        _stext = ABSOLUTE(.);
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        _etext = ABSOLUTE(.);
+    } > uflash
+
+    .init_section : {
+        _sinit = ABSOLUTE(.);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
+        _einit = ABSOLUTE(.);
+    } > uflash
+
+    .ARM.extab : {
+        *(.ARM.extab*)
+    } > uflash
+
+    __exidx_start = ABSOLUTE(.);
+    .ARM.exidx : {
+        *(.ARM.exidx*)
+    } > uflash
+
+    __exidx_end = ABSOLUTE(.);
+
+    _eronly = ABSOLUTE(.);
+
+    .data : {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        . = ALIGN(4);
+        _edata = ABSOLUTE(.);
+    } > usram AT > uflash
+
+    .bss : {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(8);
+        _ebss = ABSOLUTE(.);
+    } > usram
+
+    /* Stabs debugging sections */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}
@@ -0,0 +1,68 @@
+# ##############################################################################
+# boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS stm32_boot.c stm32_bringup.c)
+
+if(CONFIG_ADC)
+  list(APPEND SRCS stm32_adc.c)
+endif()
+
+if(CONFIG_ARCH_LEDS)
+  list(APPEND SRCS stm32_autoleds.c)
+else()
+  list(APPEND SRCS stm32_userleds.c)
+endif()
+
+if(CONFIG_STM32H7_OTGFS)
+  list(APPEND SRCS stm32_usb.c)
+endif()
+
+if(CONFIG_DEV_GPIO)
+  list(APPEND SRCS stm32_gpio.c)
+endif()
+
+if(CONFIG_PWM)
+  list(APPEND SRCS stm32_pwm.c)
+endif()
+
+if(CONFIG_SENSORS_QENCODER)
+  list(APPEND SRCS stm32_qencoder.c)
+endif()
+
+if(CONFIG_BOARDCTL_RESET)
+  list(APPEND SRCS stm32_reset.c)
+endif()
+
+if(CONFIG_ARCH_BUTTONS)
+  list(APPEND SRCS stm32_buttons.c)
+endif()
+
+target_sources(board PRIVATE ${SRCS})
+
+set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
+
+if(NOT CONFIG_BUILD_FLAT)
+  add_subdirectory(${NUTTX_BOARD_DIR}/kernel)
+  set_property(
+    GLOBAL PROPERTY LD_SCRIPT_USER ${NUTTX_BOARD_DIR}/scripts/memory.ld
+                    ${NUTTX_BOARD_DIR}/scripts/user-space.ld)
+endif()
@@ -0,0 +1,61 @@
+############################################################################
+# boards/arm/stm32h7/nucleo-h753zi/src/Makefile
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = stm32_boot.c stm32_bringup.c
+
+ifeq ($(CONFIG_ADC),y)
+CSRCS += stm32_adc.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += stm32_autoleds.c
+else
+CSRCS += stm32_userleds.c
+endif
+
+ifeq ($(CONFIG_ARCH_BUTTONS),y)
+CSRCS += stm32_buttons.c
+endif
+
+ifeq ($(CONFIG_STM32H7_OTGFS),y)
+CSRCS += stm32_usb.c
+endif
+
+ifeq ($(CONFIG_DEV_GPIO),y)
+CSRCS += stm32_gpio.c
+endif
+
+ifeq ($(CONFIG_PWM),y)
+CSRCS += stm32_pwm.c
+endif
+
+ifeq ($(CONFIG_SENSORS_QENCODER),y)
+CSRCS += stm32_qencoder.c
+endif
+
+ifeq ($(CONFIG_BOARDCTL_RESET),y)
+CSRCS += stm32_reset.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
@@ -0,0 +1,244 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H
+#define __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#define HAVE_USBDEV     1
+#define HAVE_USBHOST    1
+#define HAVE_USBMONITOR 1
+
+/* Can't support USB host or device features if USB OTG FS is not enabled */
+
+#ifndef CONFIG_STM32H7_OTGFS
+#  undef HAVE_USBDEV
+#  undef HAVE_USBHOST
+#endif
+
+/* Can't support USB device if USB device is not enabled */
+
+#ifndef CONFIG_USBDEV
+#  undef HAVE_USBDEV
+#endif
+
+/* Can't support USB host is USB host is not enabled */
+
+#ifndef CONFIG_USBHOST
+#  undef HAVE_USBHOST
+#endif
+
+/* Check if we should enable the USB monitor before starting NSH */
+
+#ifndef CONFIG_USBMONITOR
+#  undef HAVE_USBMONITOR
+#endif
+
+#ifndef HAVE_USBDEV
+#  undef CONFIG_USBDEV_TRACE
+#endif
+
+#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE)
+#  undef HAVE_USBMONITOR
+#endif
+
+/* LED */
+
+#define GPIO_LD1       (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                        GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_LD2       (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                        GPIO_OUTPUT_CLEAR | GPIO_PORTE | GPIO_PIN1)
+#define GPIO_LD3       (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                        GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN14)
+
+#define GPIO_LED_GREEN  GPIO_LD1
+#define GPIO_LED_YELLOW GPIO_LD2
+#define GPIO_LED_RED    GPIO_LD3
+
+/* BUTTONS
+ *
+ * The Blue pushbutton B1, labeled "User", is connected to GPIO PC13.
+ * A high value will be sensed when the button is depressed.
+ * Note:
+ *    1) That the EXTI is included in the definition to enable an interrupt
+ *       on this IO.
+ *    2) The following definitions assume the default Solder Bridges are
+ *       installed.
+ */
+
+#define GPIO_BTN_USER  (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
+
+#define GPIO_OTGFS_VBUS   (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
+                           GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+
+#define GPIO_OTGFS_PWRON  (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|  \
+                           GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10)
+
+#ifdef CONFIG_USBHOST
+#  define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \
+                           GPIO_SPEED_100MHz|GPIO_PUSHPULL| \
+                           GPIO_PORTG|GPIO_PIN7)
+#else
+#  define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
+                           GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
+#endif
+
+/* GPIO pins used by the GPIO Subsystem */
+
+#define BOARD_NGPIOIN     4 /* Amount of GPIO Input pins */
+#define BOARD_NGPIOOUT    8 /* Amount of GPIO Output pins */
+#define BOARD_NGPIOINT    1 /* Amount of GPIO Input w/ Interruption pins */
+
+/* Example, used free Ports on the board */
+
+#define GPIO_IN1          (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN7)
+#define GPIO_IN2          (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN12)
+#define GPIO_IN3          (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN14)
+#define GPIO_IN4          (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN15)
+
+#define GPIO_OUT1         (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                           GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN4)
+#define GPIO_OUT2         (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                           GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN5)
+#define GPIO_OUT3         (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                           GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN6)
+#define GPIO_OUT4         (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                           GPIO_OUTPUT_SET | GPIO_PORTA| GPIO_PIN5)
+#define GPIO_OUT5         (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
+                           GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN3)
+#define GPIO_INT1         (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN3)
+
+/* PWM */
+
+#if defined(CONFIG_STM32H7_TIM1_PWM)
+#  define NUCLEOH753ZI_PWMTIMER 1
+#else
+#  define NUCLEOH753ZI_PWMTIMER 3
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void);
+
+/****************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called from stm32_usbinitialize very early in initialization to setup
+ *   USB-related GPIO pins for the NUCLEO-H753ZI board.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_OTGFS
+void weak_function stm32_usbinitialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_adc_setup
+ *
+ * Description:
+ *   Initialize ADC and register the ADC driver.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ADC
+int stm32_adc_setup(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_gpio_initialize
+ *
+ * Description:
+ *   Initialize GPIO-Driver.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+int stm32_gpio_initialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the USB host
+ *   functionality. This function will start a thread that will monitor for
+ *   device connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST)
+int stm32_usbhost_initialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_pwm_setup
+ *
+ * Description:
+ *   Initialize PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PWM
+int stm32_pwm_setup(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_qencoder_initialize
+ *
+ * Description:
+ *   Initialize and register a qencoder
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SENSORS_QENCODER
+int stm32_qencoder_initialize(const char *devpath, int timer);
+#endif
+
+#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H */
@@ -0,0 +1,221 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <nuttx/debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/analog/adc.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "stm32_adc.h"
+#include "nucleo-h753zi.h"
+
+#ifdef CONFIG_ADC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Up to 3 ADC interfaces are supported */
+
+#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \
+    defined(CONFIG_STM32H7_ADC3)
+#ifndef CONFIG_STM32H7_ADC1
+#  warning "Channel information only available for ADC1"
+#endif
+
+/* The number of ADC channels in the conversion list */
+
+#define ADC1_NCHANNELS 5
+#define ADC3_NCHANNELS 1
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_ADC1
+/* Identifying number of each ADC channel: Variable Resistor.
+ *
+ * ADC1: {5, 10, 12, 13, 15};
+ */
+
+static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] =
+{
+  5, 10, 12, 13, 15
+};
+
+/* Configurations of pins used by each ADC channels
+ *
+ * ADC1:
+ * {GPIO_ADC12_INP5, GPIO_ADC123_INP10, GPIO_ADC123_INP12, GPIO_ADC12_INP13,
+ *  GPIO_ADC12_INP15};
+ */
+
+static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] =
+{
+  GPIO_ADC12_INP5,
+  GPIO_ADC123_INP10,
+  GPIO_ADC123_INP12,
+  GPIO_ADC12_INP13,
+  GPIO_ADC12_INP15
+};
+#endif
+
+#ifdef CONFIG_STM32H7_ADC3
+/* Identifying number of each ADC channel: Variable Resistor.
+ *
+ * ADC3: {6,};
+ */
+
+static const uint8_t  g_adc3_chanlist[ADC1_NCHANNELS] =
+{
+  6
+};
+
+/* Configurations of pins used by each ADC channels
+ *
+ *
+ * ADC3: {GPIO_ADC3_INP6}
+ */
+
+static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] =
+{
+  GPIO_ADC3_INP6
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adc_setup
+ *
+ * Description:
+ *   Initialize ADC and register the ADC driver.
+ *
+ ****************************************************************************/
+
+int stm32_adc_setup(void)
+{
+#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3)
+  static bool initialized = false;
+  struct adc_dev_s *adc;
+  int ret;
+  int i;
+  char devname[] = "/dev/adc0";
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+#endif
+#if defined(CONFIG_STM32H7_ADC1)
+      /* Configure the pins as analog inputs for the selected channels */
+
+      for (i = 0; i < ADC1_NCHANNELS; i++)
+        {
+          if (g_adc1_pinlist[i] != 0)
+            {
+              stm32_configgpio(g_adc1_pinlist[i]);
+            }
+        }
+
+      /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+      adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS);
+      if (adc == NULL)
+        {
+          aerr("ERROR: Failed to get ADC1 interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the ADC driver at "/dev/adc0" */
+
+      ret = adc_register(devname, adc);
+      if (ret < 0)
+        {
+          aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret);
+          return ret;
+        }
+
+      devname[8]++;
+#endif
+#if defined(CONFIG_STM32H7_ADC3)
+      /* Configure the pins as analog inputs for the selected channels */
+
+      for (i = 0; i < ADC3_NCHANNELS; i++)
+        {
+          if (g_adc3_pinlist[i] != 0)
+            {
+              stm32_configgpio(g_adc3_pinlist[i]);
+            }
+        }
+
+      /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+      adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS);
+      if (adc == NULL)
+        {
+          aerr("ERROR: Failed to get ADC3 interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the ADC driver at "/dev/adc0 or 1" */
+
+      ret = adc_register(devname, adc);
+      if (ret < 0)
+        {
+          aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret);
+          return ret;
+        }
+#endif
+
+#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3)
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */
+#endif /* CONFIG_ADC */
@@ -0,0 +1,171 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_autoleds.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <nuttx/debug.h>
+
+#include <sys/param.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "stm32_gpio.h"
+#include "nucleo-h753zi.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Indexed by BOARD_LED_<color> */
+
+static const uint32_t g_ledmap[BOARD_NLEDS] =
+{
+  GPIO_LED_GREEN,
+  GPIO_LED_YELLOW,
+  GPIO_LED_RED,
+};
+
+static bool g_initialized;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void phy_set_led(int led, bool state)
+{
+  /* Active High */
+
+  stm32_gpiowrite(g_ledmap[led], state);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+  int i;
+
+  /* Configure the LD1 GPIO for output. Initial state is OFF */
+
+  for (i = 0; i < nitems(g_ledmap); i++)
+    {
+      stm32_configgpio(g_ledmap[i]);
+    }
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+  switch (led)
+    {
+    default:
+      break;
+
+    case LED_HEAPALLOCATE:
+      phy_set_led(BOARD_LED_BLUE, true);
+      break;
+
+    case LED_IRQSENABLED:
+      phy_set_led(BOARD_LED_BLUE, false);
+      phy_set_led(BOARD_LED_GREEN, true);
+      break;
+
+    case LED_STACKCREATED:
+      phy_set_led(BOARD_LED_GREEN, true);
+      phy_set_led(BOARD_LED_BLUE, true);
+      g_initialized = true;
+      break;
+
+    case LED_INIRQ:
+      phy_set_led(BOARD_LED_BLUE, true);
+      break;
+
+    case LED_SIGNAL:
+      phy_set_led(BOARD_LED_GREEN, true);
+      break;
+
+    case LED_ASSERTION:
+      phy_set_led(BOARD_LED_RED, true);
+      phy_set_led(BOARD_LED_BLUE, true);
+      break;
+
+    case LED_PANIC:
+      phy_set_led(BOARD_LED_RED, true);
+      break;
+
+    case LED_IDLE : /* IDLE */
+      phy_set_led(BOARD_LED_RED, true);
+    break;
+    }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+  switch (led)
+    {
+    default:
+      break;
+
+    case LED_SIGNAL:
+      phy_set_led(BOARD_LED_GREEN, false);
+      break;
+
+    case LED_INIRQ:
+      phy_set_led(BOARD_LED_BLUE, false);
+      break;
+
+    case LED_ASSERTION:
+      phy_set_led(BOARD_LED_RED, false);
+      phy_set_led(BOARD_LED_BLUE, false);
+      break;
+
+    case LED_PANIC:
+      phy_set_led(BOARD_LED_RED, false);
+      break;
+
+    case LED_IDLE : /* IDLE */
+      phy_set_led(BOARD_LED_RED, false);
+    break;
+    }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
@@ -0,0 +1,87 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "arm_internal.h"
+#include "stm32_start.h"
+#include "nucleo-h753zi.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.
+ *   This entry point is called early in the initialization -- after all
+ *   memory has been configured and mapped but before any devices have been
+ *   initialized.
+ *
+ ****************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+  /* Configure on-board LEDs if LED support has been selected. */
+
+  board_autoled_initialize();
+#endif
+
+#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST)
+  /* Initialize USB */
+
+  stm32_usbinitialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_late_initialize().  board_late_initialize()
+ *   will be called immediately after up_initialize() is called and just
+ *   before the initial application is started.  This additional
+ *   initialization phase may be used, for example, to initialize board-
+ *   specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+  stm32_bringup();
+}
+#endif
@@ -0,0 +1,287 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <syslog.h>
+#include <errno.h>
+
+#include <nuttx/fs/fs.h>
+#include <nuttx/mtd/mtd.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/usb/usbmonitor.h>
+#include <nuttx/leds/userled.h>
+
+#ifdef CONFIG_STM32H7_OTGFS
+#include "stm32_usbhost.h"
+#endif
+
+#ifdef CONFIG_STM32H7_FDCAN
+#include "stm32_fdcan_sock.h"
+#endif
+
+#ifdef CONFIG_SYSTEMTICK_HOOK
+#include <semaphore.h>
+#endif
+
+#include "nucleo-h753zi.h"
+
+#ifdef CONFIG_INPUT_BUTTONS
+#  include <nuttx/input/buttons.h>
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void)
+{
+  int ret;
+#ifdef CONFIG_RAMMTD
+  uint8_t *ramstart;
+#endif
+
+  UNUSED(ret);
+
+#ifdef CONFIG_FS_PROCFS
+  /* Mount the procfs file system */
+
+  ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to mount the PROC filesystem: %d\n",  ret);
+    }
+#endif /* CONFIG_FS_PROCFS */
+
+#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
+  /* Register the LED driver */
+
+  ret = userled_lower_initialize("/dev/userleds");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_RAMMTD
+  /* Create a RAM MTD device if configured */
+
+  ramstart = kmm_malloc(128 * 1024);
+  if (ramstart == NULL)
+    {
+      syslog(LOG_ERR, "ERROR: Allocation for RAM MTD failed\n");
+    }
+  else
+    {
+      /* Initialized the RAM MTD */
+
+      struct mtd_dev_s *mtd = rammtd_initialize(ramstart, 128 * 1024);
+      if (mtd == NULL)
+        {
+          syslog(LOG_ERR, "ERROR: rammtd_initialize failed\n");
+          kmm_free(ramstart);
+        }
+      else
+        {
+          /* Erase the RAM MTD */
+
+          ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0);
+          if (ret < 0)
+            {
+              syslog(LOG_ERR, "ERROR: IOCTL MTDIOC_BULKERASE failed\n");
+            }
+
+#ifdef CONFIG_FS_LITTLEFS
+          /* Register the MTD driver so that it can be accessed from the
+           * VFS.
+           */
+
+          ret = register_mtddriver("/dev/rammtd", mtd, 0755, NULL);
+          if (ret < 0)
+            {
+              syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n",
+                     ret);
+            }
+
+          /* Mount the LittleFS file system */
+
+          ret = nx_mount("/dev/rammtd", "/mnt/lfs", "littlefs", 0,
+                         "forceformat");
+          if (ret < 0)
+            {
+              syslog(LOG_ERR,
+                     "ERROR: Failed to mount LittleFS at /mnt/lfs: %d\n",
+                     ret);
+            }
+#endif
+        }
+    }
+#endif
+
+#if defined(CONFIG_INPUT_BUTTONS_LOWER)
+  /* Register the BUTTON driver */
+
+  ret = btn_lower_initialize("/dev/buttons");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
+    }
+#endif /* CONFIG_INPUT_BUTTONS */
+
+#ifdef HAVE_USBHOST
+  /* Initialize USB host operation.  stm32_usbhost_initialize()
+   * starts a thread will monitor for USB connection and
+   * disconnection events.
+   */
+
+  ret = stm32_usbhost_initialize();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to initialize USB host: %d\n",
+             ret);
+    }
+#endif
+
+#ifdef HAVE_USBMONITOR
+  /* Start the USB Monitor */
+
+  ret = usbmonitor_start();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to start USB monitor: %d\n",
+             ret);
+    }
+#endif
+
+#ifdef CONFIG_ADC
+  /* Initialize ADC and register the ADC driver. */
+
+  ret = stm32_adc_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
+    }
+#endif /* CONFIG_ADC */
+
+#ifdef CONFIG_DEV_GPIO
+  /* Register the GPIO driver */
+
+  ret = stm32_gpio_initialize();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_NETDEV_LATEINIT
+
+#  ifdef CONFIG_STM32H7_FDCAN1
+  stm32_fdcansockinitialize(0);
+#  endif
+
+#  ifdef CONFIG_STM32H7_FDCAN2
+  stm32_fdcansockinitialize(1);
+#  endif
+
+#endif
+
+#ifdef CONFIG_SENSORS_QENCODER
+#ifdef CONFIG_STM32H7_TIM1_QE
+  ret = stm32_qencoder_initialize("/dev/qe0", 1);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to register the qencoder: %d\n",
+             ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3_QE
+  ret = stm32_qencoder_initialize("/dev/qe2", 3);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to register the qencoder: %d\n",
+             ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4_QE
+  ret = stm32_qencoder_initialize("/dev/qe3", 4);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to register the qencoder: %d\n",
+             ret);
+      return ret;
+    }
+#endif
+#endif
+
+#ifdef CONFIG_PWM
+  /* Initialize PWM and register the PWM device. */
+
+  ret = stm32_pwm_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret);
+    }
+#endif
+
+  return OK;
+}
+
+#ifdef CONFIG_SYSTEMTICK_HOOK
+
+sem_t g_waitsem;
+
+void board_timerhook(void)
+{
+  (void)sem_post(&g_waitsem);
+}
+#endif
@@ -0,0 +1,107 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_buttons.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stddef.h>
+#include <errno.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/board.h>
+
+#include "stm32_gpio.h"
+#include "nucleo-h753zi.h"
+#include <arch/board/board.h>
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_button_initialize
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.
+ *   After that, board_buttons() may be called to collect the current state
+ *   of all buttons or board_button_irq() may be called to register button
+ *   interrupt handlers.
+ *
+ ****************************************************************************/
+
+uint32_t board_button_initialize(void)
+{
+  stm32_configgpio(GPIO_BTN_USER);
+  return NUM_BUTTONS;
+}
+
+/****************************************************************************
+ * Name: board_buttons
+ ****************************************************************************/
+
+uint32_t board_buttons(void)
+{
+  return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0;
+}
+
+/****************************************************************************
+ * Button support.
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.
+ *   After that, board_buttons() may be called to collect the current state
+ *   of all buttons or board_button_irq() may be called to register button
+ *   interrupt handlers.
+ *
+ *   After board_button_initialize() has been called, board_buttons() may be
+ *   called to collect the state of all buttons.  board_buttons() returns a
+ *   32-bit bit set with each bit associated with a button.  See the
+ *   BUTTON_*_BIT definitions in board.h for the meaning of each bit.
+ *
+ *   board_button_irq() may be called to register an interrupt handler that
+ *   will be called when a button is depressed or released.  The ID value is
+ *   a button enumeration value that uniquely identifies a button resource.
+ *   See the BUTTON_* definitions in board.h for the meaning of enumeration
+ *   value.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, void *arg)
+{
+  int ret = -EINVAL;
+
+  if (id == BUTTON_USER)
+    {
+      ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true,
+                               irqhandler, arg);
+    }
+
+  return ret;
+}
+#endif
+#endif /* CONFIG_ARCH_BUTTONS */
@@ -0,0 +1,333 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_gpio.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <assert.h>
+#include <nuttx/debug.h>
+
+#include <nuttx/clock.h>
+#include <nuttx/wdog.h>
+#include <nuttx/ioexpander/gpio.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "nucleo-h753zi.h"
+
+#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct stm32gpio_dev_s
+{
+  struct gpio_dev_s gpio;
+  uint8_t id;
+};
+
+struct stm32gpint_dev_s
+{
+  struct stm32gpio_dev_s stm32gpio;
+  pin_interrupt_t callback;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int gpin_read(struct gpio_dev_s *dev, bool *value);
+static int gpout_read(struct gpio_dev_s *dev, bool *value);
+static int gpout_write(struct gpio_dev_s *dev, bool value);
+static int gpint_read(struct gpio_dev_s *dev, bool *value);
+static int gpint_attach(struct gpio_dev_s *dev,
+                        pin_interrupt_t callback);
+static int gpint_enable(struct gpio_dev_s *dev, bool enable);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct gpio_operations_s gpin_ops =
+{
+  .go_read   = gpin_read,
+  .go_write  = NULL,
+  .go_attach = NULL,
+  .go_enable = NULL,
+};
+
+static const struct gpio_operations_s gpout_ops =
+{
+  .go_read   = gpout_read,
+  .go_write  = gpout_write,
+  .go_attach = NULL,
+  .go_enable = NULL,
+};
+
+static const struct gpio_operations_s gpint_ops =
+{
+  .go_read   = gpint_read,
+  .go_write  = NULL,
+  .go_attach = gpint_attach,
+  .go_enable = gpint_enable,
+};
+
+#if BOARD_NGPIOIN > 0
+/* This array maps the GPIO pins used as INPUT */
+
+static const uint32_t g_gpioinputs[BOARD_NGPIOIN] =
+{
+  GPIO_IN1,
+  GPIO_IN2,
+  GPIO_IN3,
+  GPIO_IN4,
+};
+
+static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN];
+#endif
+
+#if BOARD_NGPIOOUT
+/* This array maps the GPIO pins used as OUTPUT */
+
+static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
+{
+  GPIO_LD1,
+  GPIO_LD2,
+  GPIO_LD3,
+  GPIO_OUT1,
+  GPIO_OUT2,
+  GPIO_OUT3,
+  GPIO_OUT4,
+  GPIO_OUT5,
+};
+
+static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT];
+#endif
+
+#if BOARD_NGPIOINT > 0
+/* This array maps the GPIO pins used as INTERRUPT INPUTS */
+
+static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] =
+{
+  GPIO_INT1,
+};
+
+static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT];
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int stm32gpio_interrupt(int irq, void *context, void *arg)
+{
+  struct stm32gpint_dev_s *stm32gpint =
+    (struct stm32gpint_dev_s *)arg;
+
+  DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL);
+  gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback);
+
+  stm32gpint->callback(&stm32gpint->stm32gpio.gpio,
+                       stm32gpint->stm32gpio.id);
+  return OK;
+}
+
+static int gpin_read(struct gpio_dev_s *dev, bool *value)
+{
+  struct stm32gpio_dev_s *stm32gpio =
+    (struct stm32gpio_dev_s *)dev;
+
+  DEBUGASSERT(stm32gpio != NULL && value != NULL);
+  DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN);
+  gpioinfo("Reading...\n");
+
+  *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]);
+  return OK;
+}
+
+static int gpout_read(struct gpio_dev_s *dev, bool *value)
+{
+  struct stm32gpio_dev_s *stm32gpio =
+    (struct stm32gpio_dev_s *)dev;
+
+  DEBUGASSERT(stm32gpio != NULL && value != NULL);
+  DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT);
+  gpioinfo("Reading...\n");
+
+  *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]);
+  return OK;
+}
+
+static int gpout_write(struct gpio_dev_s *dev, bool value)
+{
+  struct stm32gpio_dev_s *stm32gpio =
+    (struct stm32gpio_dev_s *)dev;
+
+  DEBUGASSERT(stm32gpio != NULL);
+  DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT);
+  gpioinfo("Writing %d\n", (int)value);
+
+  stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value);
+  return OK;
+}
+
+static int gpint_read(struct gpio_dev_s *dev, bool *value)
+{
+  struct stm32gpint_dev_s *stm32gpint =
+    (struct stm32gpint_dev_s *)dev;
+
+  DEBUGASSERT(stm32gpint != NULL && value != NULL);
+  DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT);
+  gpioinfo("Reading int pin...\n");
+
+  *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]);
+  return OK;
+}
+
+static int gpint_attach(struct gpio_dev_s *dev,
+                        pin_interrupt_t callback)
+{
+  struct stm32gpint_dev_s *stm32gpint =
+    (struct stm32gpint_dev_s *)dev;
+
+  gpioinfo("Attaching the callback\n");
+
+  /* Make sure the interrupt is disabled */
+
+  stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false,
+                     false, false, NULL, NULL);
+
+  gpioinfo("Attach %p\n", callback);
+  stm32gpint->callback = callback;
+  return OK;
+}
+
+static int gpint_enable(struct gpio_dev_s *dev, bool enable)
+{
+  struct stm32gpint_dev_s *stm32gpint =
+    (struct stm32gpint_dev_s *)dev;
+
+  if (enable)
+    {
+      if (stm32gpint->callback != NULL)
+        {
+          gpioinfo("Enabling the interrupt\n");
+
+          /* Configure the interrupt for rising edge */
+
+          stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id],
+                             true, false, false, stm32gpio_interrupt,
+                             &g_gpint[stm32gpint->stm32gpio.id]);
+        }
+    }
+  else
+    {
+      gpioinfo("Disable the interrupt\n");
+      stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id],
+                         false, false, false, NULL, NULL);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_gpio_initialize
+ *
+ * Description:
+ *   Initialize GPIO drivers for use with /apps/examples/gpio
+ *
+ ****************************************************************************/
+
+int stm32_gpio_initialize(void)
+{
+  int i;
+  int pincount = 0;
+
+#if BOARD_NGPIOIN > 0
+  for (i = 0; i < BOARD_NGPIOIN; i++)
+    {
+      /* Setup and register the GPIO pin */
+
+      g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN;
+      g_gpin[i].gpio.gp_ops     = &gpin_ops;
+      g_gpin[i].id              = i;
+      gpio_pin_register(&g_gpin[i].gpio, pincount);
+
+      /* Configure the pin that will be used as input */
+
+      stm32_configgpio(g_gpioinputs[i]);
+
+      pincount++;
+    }
+#endif
+
+#if BOARD_NGPIOOUT > 0
+  for (i = 0; i < BOARD_NGPIOOUT; i++)
+    {
+      /* Setup and register the GPIO pin */
+
+      g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN;
+      g_gpout[i].gpio.gp_ops     = &gpout_ops;
+      g_gpout[i].id              = i;
+      gpio_pin_register(&g_gpout[i].gpio, pincount);
+
+      /* Configure the pin that will be used as output */
+
+      stm32_gpiowrite(g_gpiooutputs[i], 0);
+      stm32_configgpio(g_gpiooutputs[i]);
+
+      pincount++;
+    }
+#endif
+
+#if BOARD_NGPIOINT > 0
+  for (i = 0; i < BOARD_NGPIOINT; i++)
+    {
+      /* Setup and register the GPIO pin */
+
+      g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN;
+      g_gpint[i].stm32gpio.gpio.gp_ops     = &gpint_ops;
+      g_gpint[i].stm32gpio.id              = i;
+      gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount);
+
+      /* Configure the pin that will be used as interrupt input */
+
+      stm32_configgpio(g_gpiointinputs[i]);
+
+      pincount++;
+    }
+#endif
+
+  return 0;
+}
+#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */
@@ -0,0 +1,114 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <errno.h>
+#include <nuttx/debug.h>
+
+#include <nuttx/timers/pwm.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_internal.h"
+#include "stm32_pwm.h"
+#include "nucleo-h753zi.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#define HAVE_PWM 1
+
+#ifndef CONFIG_PWM
+#  undef HAVE_PWM
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_pwm_setup
+ *
+ * Description:
+ *   Initialize PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+int stm32_pwm_setup(void)
+{
+#ifdef HAVE_PWM
+  static bool initialized = false;
+  struct pwm_lowerhalf_s *pwm;
+  int ret;
+
+  /* Have we already initialized? */
+
+  if (!initialized)
+    {
+      /* Get an instance of the PWM interface */
+
+      pwm = stm32_pwminitialize(NUCLEOH753ZI_PWMTIMER);
+      if (pwm == NULL)
+        {
+          tmrerr("ERROR: Failed to get the STM32 PWM lower half\n");
+          return -ENODEV;
+        }
+
+      /* Register the PWM driver at "/dev/pwm0" */
+
+ #if defined(CONFIG_STM32H7_TIM1_PWM)
+      ret = pwm_register("/dev/pwm0", pwm);
+      if (ret < 0)
+        {
+          tmrerr("ERROR: pwm_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+
+#if defined(CONFIG_STM32H7_TIM3_PWM)
+      ret = pwm_register("/dev/pwm2", pwm);
+      if (ret < 0)
+        {
+          tmrerr("ERROR: pwm_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+#else
+  return -ENODEV;
+#endif
+}
@@ -0,0 +1,67 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_qencoder.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <nuttx/debug.h>
+
+#include <nuttx/sensors/qencoder.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_internal.h"
+#include "stm32_qencoder.h"
+#include "nucleo-h753zi.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: qe_devinit
+ *
+ * Description:
+ *   All STM32H7 architectures must provide the following interface to work
+ *   with examples/qencoder.
+ *
+ ****************************************************************************/
+
+int stm32_qencoder_initialize(const char *devpath, int timer)
+{
+  int ret;
+
+  /* Initialize a quadrature encoder interface. */
+
+  sninfo("Initializing the quadrature encoder using TIM%d\n", timer);
+  ret = stm32_qeinitialize(devpath, timer);
+  if (ret < 0)
+    {
+      snerr("ERROR: stm32_qeinitialize failed: %d\n", ret);
+    }
+
+  return ret;
+}
@@ -0,0 +1,64 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#ifdef CONFIG_BOARDCTL_RESET
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_reset
+ *
+ * Description:
+ *   Reset board.  Support for this function is required by board-level
+ *   logic if CONFIG_BOARDCTL_RESET is selected.
+ *
+ * Input Parameters:
+ *   status - Status information provided with the reset event.  This
+ *            meaning of this status information is board-specific.  If not
+ *            used by a board, the value zero may be provided in calls to
+ *            board_reset().
+ *
+ * Returned Value:
+ *   If this function returns, then it was not possible to power-off the
+ *   board due to some constraints.  The return value int this case is a
+ *   board-specific reason for the failure to shutdown.
+ *
+ ****************************************************************************/
+
+int board_reset(int status)
+{
+  up_systemreset();
+  return 0;
+}
+
+#endif /* CONFIG_BOARDCTL_RESET */
@@ -0,0 +1,322 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <errno.h>
+#include <assert.h>
+#include <nuttx/debug.h>
+
+#include <nuttx/kthread.h>
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbhost.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "arm_internal.h"
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "stm32_otg.h"
+#include "nucleo-h753zi.h"
+
+#ifdef CONFIG_STM32H7_OTGFS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
+#  define HAVE_USB 1
+#else
+#  warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
+#  undef HAVE_USB
+#endif
+
+#ifndef CONFIG_USBHOST_DEFPRIO
+#  define CONFIG_USBHOST_DEFPRIO 100
+#endif
+
+#ifndef CONFIG_USBHOST_STACKSIZE
+#  define CONFIG_USBHOST_STACKSIZE 2048
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static struct usbhost_connection_s *g_usbconn;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: usbhost_waiter
+ *
+ * Description:
+ *   Wait for USB devices to be connected.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static int usbhost_waiter(int argc, char *argv[])
+{
+  struct usbhost_hubport_s *hport;
+
+  uinfo("Running\n");
+  for (; ; )
+    {
+      /* Wait for the device to change state */
+
+      DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
+      uinfo("%s\n", hport->connected ? "connected" : "disconnected");
+
+      /* Did we just become connected? */
+
+      if (hport->connected)
+        {
+          /* Yes.. enumerate the newly connected device */
+
+          CONN_ENUMERATE(g_usbconn, hport);
+        }
+    }
+
+  /* Keep the compiler from complaining */
+
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called from stm32_usbinitialize very early in initialization to setup
+ *   USB-related GPIO pins for the nucleo-144 board.
+ *
+ ****************************************************************************/
+
+void stm32_usbinitialize(void)
+{
+  /* The OTG FS has an internal soft pull-up.
+   * No GPIO configuration is required
+   */
+
+  /* Configure the OTG FS VBUS sensing GPIO,
+   * Power On, and Overcurrent GPIOs
+   */
+
+#ifdef CONFIG_STM32H7_OTGFS
+  stm32_configgpio(GPIO_OTGFS_VBUS);
+  stm32_configgpio(GPIO_OTGFS_PWRON);
+  stm32_configgpio(GPIO_OTGFS_OVER);
+#endif
+}
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the USB host
+ *   functionality.
+ *   This function will start a thread that will monitor for device
+ *   connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_usbhost_initialize(void)
+{
+  int ret;
+
+  /* First, register all of the class drivers needed to support the drivers
+   * that we care about:
+   */
+
+  uinfo("Register class drivers\n");
+
+#ifdef CONFIG_USBHOST_HUB
+  /* Initialize USB hub class support */
+
+  ret = usbhost_hub_initialize();
+  if (ret < 0)
+    {
+      uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_USBHOST_MSC
+  /* Register the USB mass storage class class */
+
+  ret = usbhost_msc_initialize();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_USBHOST_CDCACM
+  /* Register the CDC/ACM serial class */
+
+  ret = usbhost_cdcacm_initialize();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDKBD
+  /* Initialize the HID keyboard class */
+
+  ret = usbhost_kbdinit();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the HID keyboard class\n");
+    }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDMOUSE
+  /* Initialize the HID mouse class */
+
+  ret = usbhost_mouse_init();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the HID mouse class\n");
+    }
+#endif
+
+  /* Then get an instance of the USB host interface */
+
+  uinfo("Initialize USB host\n");
+  g_usbconn = stm32_otgfshost_initialize(0);
+  if (g_usbconn)
+    {
+      /* Start a thread to handle device connection. */
+
+      uinfo("Start usbhost_waiter\n");
+
+      ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+                           CONFIG_USBHOST_STACKSIZE,
+                           usbhost_waiter, NULL);
+      return ret < 0 ? -ENOEXEC : OK;
+    }
+
+  return -ENODEV;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_vbusdrive
+ *
+ * Description:
+ *   Enable/disable driving of VBUS 5V output. This function must be
+ *   provided be each platform that implements the STM32 OTG FS host
+ *   interface
+ *
+ *   "On-chip 5 V VBUS generation is not supported. For this reason, a
+ *    charge pump or, if 5 V are available on the application board, a
+ *    basic power switch, must be added externally to drive the 5 V VBUS
+ *    line. The external charge pump can be driven by any GPIO output.
+ *    When the application decides to power on VBUS using the chosen GPIO,
+ *    it must also set the port power bit in the host port control and status
+ *    register (PPWR bit in OTG_FS_HPRT).
+ *
+ *   "The application uses this field to control power to this port, and
+ *    the core clears this bit on an overcurrent condition."
+ *
+ * Input Parameters:
+ *   iface - For future growth to handle multiple USB host interface.
+ *           Should be zero.
+ *   enable - true: enable VBUS power; false: disable VBUS power
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+void stm32_usbhost_vbusdrive(int iface, bool enable)
+{
+  DEBUGASSERT(iface == 0);
+
+  /* Set the Power Switch by driving the active low enable pin */
+
+  stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_setup_overcurrent
+ *
+ * Description:
+ *   Setup to receive an interrupt-level callback if an overcurrent
+ *   condition is detected.
+ *
+ * Input Parameters:
+ *   handler - New overcurrent interrupt handler
+ *   arg     - The argument provided for the interrupt handler
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  Otherwise, a negated errno value
+ *   is returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_setup_overcurrent(xcpt_t handler, void *arg)
+{
+  return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
+}
+#endif
+
+/****************************************************************************
+ * Name:  stm32_usbsuspend
+ *
+ * Description:
+ *   Board logic must provide the stm32_usbsuspend logic if the USBDEV
+ *   driver is used. This function is called whenever the USB enters or
+ *   leaves suspend mode. This is an opportunity for the board logic to
+ *   shutdown clocks, power, etc. while the USB is suspended.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV
+void stm32_usbsuspend(struct usbdev_s *dev, bool resume)
+{
+  uinfo("resume: %d\n", resume);
+}
+#endif
+
+#endif /* CONFIG_STM32_OTGFS */
@@ -0,0 +1,127 @@
+/****************************************************************************
+ * boards/arm/stm32h7/nucleo-h753zi/src/stm32_userleds.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <nuttx/debug.h>
+
+#include <sys/param.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "stm32_gpio.h"
+#include "nucleo-h753zi.h"
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This array maps an LED number to GPIO pin configuration and is indexed by
+ * BOARD_LED_<color>
+ */
+
+static const uint32_t g_ledcfg[BOARD_NLEDS] =
+{
+  GPIO_LED_GREEN,
+  GPIO_LED_YELLOW,
+  GPIO_LED_RED,
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ *
+ * Description:
+ *   If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
+ *   LEDs.  If CONFIG_ARCH_LEDS is not defined, then the
+ *   board_userled_initialize() is available to initialize the LED from user
+ *   application logic.
+ *
+ ****************************************************************************/
+
+uint32_t board_userled_initialize(void)
+{
+  int i;
+
+  /* Configure LED1-3 GPIOs for output */
+
+  for (i = 0; i < nitems(g_ledcfg); i++)
+    {
+      stm32_configgpio(g_ledcfg[i]);
+    }
+
+  return BOARD_NLEDS;
+}
+
+/****************************************************************************
+ * Name: board_userled
+ *
+ * Description:
+ *   If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
+ *  LEDs.  If CONFIG_ARCH_LEDS is not defined, then the board_userled() is
+ *  available to control the LED from user application logic.
+ *
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+  if ((unsigned)led < nitems(g_ledcfg))
+    {
+      stm32_gpiowrite(g_ledcfg[led], ledon);
+    }
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ *
+ * Description:
+ *   If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
+ *  LEDs.  If CONFIG_ARCH_LEDS is not defined, then the board_userled_all()
+ *  is available to control the LED from user application logic. NOTE: since
+ *  there is only a single LED on-board, this is function is not very useful.
+ *
+ ****************************************************************************/
+
+void board_userled_all(uint32_t ledset)
+{
+  int i;
+
+  /* Configure LED1-3 GPIOs for output */
+
+  for (i = 0; i < nitems(g_ledcfg); i++)
+    {
+      stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0);
+    }
+}
+
+#endif /* !CONFIG_ARCH_LEDS */