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Beginng of support for GMII/RGMII PHYs

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This commit is contained in:
Gregory Nutt
2013-09-26 15:55:21 -06:00
parent 48f1227fbf
commit fbd09bd75f
5 changed files with 229 additions and 145 deletions
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arch/arm/src/sama5/Kconfig
+2 -2
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@@ -277,7 +277,7 @@ config SAMA5_GMAC_NRXBUFFERS
config SAMA5_GMAC_NTXBUFFERS
int "Number of TX buffers"
default 1
default 8
---help---
GMAC buffer memory is segmented into full Ethernet packets (size
NET_BUFSIZE bytes). This setting provides the number of such packets
@@ -471,7 +471,7 @@ config SAMA5_EMAC_NRXBUFFERS
config SAMA5_EMAC_NTXBUFFERS
int "Number of TX buffers"
default 1
default 8
---help---
EMAC buffer memory is segmented into full Ethernet packets (size
NET_BUFSIZE bytes). This setting provides the number of such packets
arch/arm/src/sama5/chip/sam_gmac.h
+1 -1
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@@ -483,7 +483,7 @@
# define GMAC_NCFGR_CLK_DIV32 (2 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 32 (MCK up to 80 MHz) */
# define GMAC_NCFGR_CLK_DIV48 (3 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */
# define GMAC_NCFGR_CLK_DIV64 (4 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
# define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 240 MHz) */
# define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */
#define GMAC_NCFGR_DBW_SHIFT (21) /* Bits 21-22: Data Bus Width */
#define GMAC_NCFGR_DBW_MASK (3 << GMAC_NCFGR_DBW_SHIFT)
# define GMAC_NCFGR_DBW_32 (0 << GMAC_NCFGR_DBW_SHIFT) /* 32-bit data bus width */
arch/arm/src/sama5/sam_emac.c
+5 -3
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@@ -94,7 +94,7 @@
/* Number of buffer for TX */
#ifndef CONFIG_SAMA5_EMAC_NTXBUFFERS
# define CONFIG_SAMA5_EMAC_NTXBUFFERS 32
# define CONFIG_SAMA5_EMAC_NTXBUFFERS 8
#endif
#undef CONFIG_SAMA5_EMAC_NBC
@@ -294,11 +294,13 @@ static struct sam_emac_s g_emac;
/* Preallocated data */
/* TX descriptors list */
static struct emac_txdesc_s g_txdesc[TX_BUFFERS] __attribute__((aligned(8)));
static struct emac_txdesc_s g_txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS]
__attribute__((aligned(8)));
/* RX descriptors list */
static struct emac_rxdesc_s g_rxdesc[RX_BUFFERS]__attribute__((aligned(8)));
static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS]
__attribute__((aligned(8)));
/* Transmit Buffers
*
arch/arm/src/sama5/sam_ethernet.h
+8
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@@ -75,6 +75,8 @@
# define SAMA5_GMAC_PHY_LAN8700 1
# elif defined(CONFIG_ETH0_PHY_KSZ8051)
# define SAMA5_GMAC_PHY_KSZ8051 1
# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
# define SAMA5_GMAC_PHY_KSZ90x1 1
# else
# error ETH0 PHY unrecognized
# endif
@@ -85,6 +87,8 @@
# define SAMA5_GMAC_PHY_LAN8700 1
# elif defined(CONFIG_ETH1_PHY_KSZ8051)
# define SAMA5_GMAC_PHY_KSZ8051 1
# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
# define SAMA5_GMAC_PHY_KSZ90x1 1
# else
# error ETH1 PHY unrecognized
# endif
@@ -97,6 +101,8 @@
# define SAMA5_EMAC_PHY_LAN8700 1
# elif defined(CONFIG_ETH0_PHY_KSZ8051)
# define SAMA5_EMAC_PHY_KSZ8051 1
# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
# define SAMA5_EMAC_PHY_KSZ90x1 1
# else
# error ETH0 PHY unrecognized
# endif
@@ -107,6 +113,8 @@
# define SAMA5_EMAC_PHY_LAN8700 1
# elif defined(CONFIG_ETH1_PHY_KSZ8051)
# define SAMA5_EMAC_PHY_KSZ8051 1
# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
# define SAMA5_EMAC_PHY_KSZ90x1 1
# else
# error ETH1 PHY unrecognized
# endif
arch/arm/src/sama5/sam_gmac.c
+213 -139
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