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arch: arm: kinetis: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-03-24 09:22:06 +01:00
committed by David Sidrane
parent d5beb72299
commit fafecbf107
77 changed files with 2894 additions and 2260 deletions
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arch/arm/src/kinetis/chip.h
+12 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,33 +16,34 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware files
* should then include this file for the proper setup.
/* Include the memory map and the chip definitions file.
* Other chip hardware files should then include this file for the proper
* setup.
*/
#include <arch/irq.h>
#include <arch/kinetis/chip.h>
#include "hardware/kinetis_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
* interrupts which, for this architecture, is provided in the arch/kinetis/chip.h
* header file.
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/kinetis/chip.h header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS KINETIS_IRQ_NEXTINTS
arch/arm/src/kinetis/hardware/kinetis_adc.h
+28 -16
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_ADC_SC1A_OFFSET 0x0000 /* ADC status and control registers 1 */
#define KINETIS_ADC_SC1B_OFFSET 0x0004 /* ADC status and control registers 1 */
@@ -66,7 +66,7 @@
#define KINETIS_ADC_CLM1_OFFSET 0x0068 /* ADC minus-side general calibration value register */
#define KINETIS_ADC_CLM0_OFFSET 0x006c /* ADC minus-side general calibration value register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_ADC0_SC1A (KINETIS_ADC0_BASE+KINETIS_ADC_SC1A_OFFSET)
#define KINETIS_ADC0_SC1B (KINETIS_ADC0_BASE+KINETIS_ADC_SC1B_OFFSET)
@@ -130,7 +130,7 @@
#define KINETIS_ADC1_CLM1 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM1_OFFSET)
#define KINETIS_ADC1_CLM0 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM0_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* ADC status and control registers 1 */
@@ -166,10 +166,12 @@
# define ADC_SC1_ADCH_VREFSH (29 << ADC_SC1_ADCH_SHIFT) /* VREFSH */
# define ADC_SC1_ADCH_VREFSL (30 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 VREFSL; DIFF=1 reserved */
# define ADC_SC1_ADCH_DISABLED (31 << ADC_SC1_ADCH_SHIFT) /* Module disabled */
#define ADC_SC1_DIFF (1 << 5) /* Bit 5: Differential mode enable */
#define ADC_SC1_AIEN (1 << 6) /* Bit 6: Interrupt enable */
#define ADC_SC1_COCO (1 << 7) /* Bit 7: Conversion complete flag */
/* Bits 8-31: Reserved */
/* ADC configuration register 1 */
#define ADC_CFG1_ADICLK_SHIFT (0) /* Bits 0-1: Input clock select */
@@ -178,12 +180,14 @@
# define ADC_CFG1_ADICLK_BUSDIV2 (1 << ADC_CFG1_ADICLK_SHIFT) /* Bus clock/ 2 */
# define ADC_CFG1_ADICLK_ALTCLK (2 << ADC_CFG1_ADICLK_SHIFT) /* Alternate clock */
# define ADC_CFG1_ADICLK_ADACK (3 << ADC_CFG1_ADICLK_SHIFT) /* Asynchronous clock */
#define ADC_CFG1_MODE_SHIFT (2) /* Bits 2-3: Conversion mode selection */
#define ADC_CFG1_MODE_MASK (3 << ADC_CFG1_MODE_SHIFT)
# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */
# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */
# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */
# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */
#define ADC_CFG1_ADLSMP (1 << 4) /* Bit 4: Sample time configuration */
#define ADC_CFG1_ADIV_SHIFT (5) /* Bits 5-6: Clock divide select */
#define ADC_CFG1_ADIV_MASK (3 << ADC_CFG1_ADIV_SHIFT)
@@ -191,8 +195,10 @@
# define ADC_CFG1_ADIV_DIV2 (1 << ADC_CFG1_ADIV_SHIFT) /* Divider=2 rate=input clock/2 */
# define ADC_CFG1_ADIV_DIV4 (2 << ADC_CFG1_ADIV_SHIFT) /* Divider=4 rate=input clock/4 */
# define ADC_CFG1_ADIV_DIV8 (3 << ADC_CFG1_ADIV_SHIFT) /* Divider=8 rate=input clock/8 */
#define ADC_CFG1_ADLPC (1 << 7) /* Bit 7: Low-power configuration */
/* Bits 8-31: Reserved */
/* Configuration register 2 */
#define ADC_CFG2_ADLSTS_SHIFT (0) /* Bits 0-1: Long sample time select */
@@ -201,10 +207,12 @@
# define ADC_CFG2_ADLSTS_PLUS12 (1 << ADC_CFG2_ADLSTS_SHIFT) /* 12 extra ADCK cycles */
# define ADC_CFG2_ADLSTS_PLUS6 (2 << ADC_CFG2_ADLSTS_SHIFT) /* 6 extra ADCK cycles */
# define ADC_CFG2_ADLSTS_PLUS2 (3 << ADC_CFG2_ADLSTS_SHIFT) /* 2 extra ADCK cycles */
#define ADC_CFG2_ADHSC (1 << 2) /* Bit 2: High speed configuration */
#define ADC_CFG2_ADACKEN (1 << 3) /* Bit 3: Asynchronous clock output enable */
#define ADC_CFG2_MUXSEL (1 << 4) /* Bit 4: ADC Mux select */
/* Bits 5-31: Reserved */
/* ADC data result register */
#define ADC_R_MASK (0xffff) /* 16-bit signed or unsigned data */
@@ -219,6 +227,7 @@
#define ADC_SC2_REFSEL_MASK (3 << ADC_SC2_REFSEL_SHIFT)
# define ADC_SC2_REFSEL_DEFAULT (0 << ADC_SC2_REFSEL_SHIFT) /* Default reference: V REFH and V REFL */
# define ADC_SC2_REFSEL_ALT (1 << ADC_SC2_REFSEL_SHIFT) /* Alternate reference: V ALTH and V ALTL */
#define ADC_SC2_DMAEN (1 << 2) /* Bit 2: DMA enable */
#define ADC_SC2_ACREN (1 << 3) /* Bit 3: Compare function range enable */
#define ADC_SC2_ACFGT (1 << 4) /* Bit 4: Compare function greater than enable */
@@ -226,6 +235,7 @@
#define ADC_SC2_ADTRG (1 << 6) /* Bit 6: Conversion trigger select */
#define ADC_SC2_ADACT (1 << 7) /* Bit 7: Conversion active */
/* Bits 8-31: Reserved */
/* Status and control register 3 */
#define ADC_SC3_AVGS_SHIFT (0) /* Bits 0-1: Hardware average select */
@@ -234,12 +244,14 @@
# define ADC_SC3_AVGS_8SMPLS (1 << ADC_SC3_AVGS_SHIFT) /* 8 samples averaged */
# define ADC_SC3_AVGS_16SMPLS (2 << ADC_SC3_AVGS_SHIFT) /* 18 samples averaged */
# define ADC_SC3_AVGS_32SMPLS (3 << ADC_SC3_AVGS_SHIFT) /* 32 samples averaged */
#define ADC_SC3_AVGE (1 << 2) /* Bit 2: Hardware average enable */
#define ADC_SC3_ADCO (1 << 3) /* Bit 3: Continuous conversion enable */
/* Bits 4-5: Reserved */
#define ADC_SC3_CALF (1 << 6) /* Bit 6: Calibration failed flag */
#define ADC_SC3_CAL (1 << 7) /* Bit 7: Calibration */
/* Bits 8-31: Reserved */
/* ADC offset correction register */
#define ADC_OFS_MASK (0xffff) /* Bits 0-15: Offset error correction value */
@@ -293,16 +305,16 @@
#define ADC_CLM1_MASK (0x7f) /* Bits 0-6: Calibration value */
#define ADC_CLM0_MASK (0x3f) /* Bits 0-5: Calibration value */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H */
arch/arm/src/kinetis/hardware/kinetis_aips.h
+19 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_aips.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_AIPS_MPRA_OFFSET 0x0000 /* Master Privilege Register A */
@@ -57,7 +58,7 @@
# define KINETIS_AIPS_PACRU_OFFSET 0x0080 /* Peripheral Access Control Register */
#endif
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_AIPS0_MPRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_MPRA_OFFSET)
#define KINETIS_AIPS0_PACRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRA_OFFSET)
@@ -101,7 +102,7 @@
# define KINETIS_AIPS1_PACRU (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRU_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Master Privilege Register A */
@@ -131,7 +132,8 @@
#define AIPS_MPRA_MTR0 (1 << 30) /* Bit 30: Master trusted for read */
/* Bit 31: Reserved */
/* Peripheral Access Control Register. Naming here is only accurate for PACRA.
/* Peripheral Access Control Register.
* Naming here is only accurate for PACRA.
* PACRA: PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
* PACRB: PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15
* PACRC: PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23
@@ -187,16 +189,16 @@
#define AIPS_PACR_SP0 (1 << 30) /* Bit 30: Supervisor protect */
/* Bit 31: Reserved */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H */
arch/arm/src/kinetis/hardware/kinetis_axbs.h
+29 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_axbs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_AXBS_PRS_OFFSET(n) (0x0000 + ((n) << 8))
#define KINETIS_AXBS_CRS_OFFSET(n) (0x0010 + ((n) << 8))
@@ -64,7 +64,7 @@
#define KINETIS_AXBS_MGPCR6_OFFSET 0x0e00 /* Master General Purpose Control Register */
#define KINETIS_AXBS_MGPCR7_OFFSET 0x0f00 /* Master General Purpose Control Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_AXBS_PRS(n) (KINETIS_XBAR_BASE+KINETIS_AXBS_PRS_OFFSET(n))
#define KINETIS_AXBS_CRS(n) (KINETIS_XBAR_BASE+KINETIS_AXBS_CRS_OFFSET(n))
@@ -95,7 +95,7 @@
#define KINETIS_AXBS_MGPCR6 (KINETIS_XBAR_BASE+KINETIS_AXBS_MGPCR6_OFFSET)
#define KINETIS_AXBS_MGPCR7 (KINETIS_XBAR_BASE+KINETIS_AXBS_MGPCR7_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Priority Registers Slave */
@@ -109,6 +109,7 @@
# define AXBS_PRS_M0_PRI6 (5 << AXBS_PRS_M0_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M0_PRI7 (6 << AXBS_PRS_M0_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M0_PRI8 (7 << AXBS_PRS_M0_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 3: Reserved */
#define AXBS_PRS_M1_SHIFT (4) /* Bits 4-6: Master 1 priority */
#define AXBS_PRS_M1_MASK (7 << AXBS_PRS_M1_SHIFT)
@@ -120,6 +121,7 @@
# define AXBS_PRS_M1_PRI6 (5 << AXBS_PRS_M1_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M1_PRI7 (6 << AXBS_PRS_M1_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M1_PRI8 (7 << AXBS_PRS_M1_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 7: Reserved */
#define AXBS_PRS_M2_SHIFT (8) /* Bits 8-10: Master 2 priority */
#define AXBS_PRS_M2_MASK (7 << AXBS_PRS_M2_SHIFT)
@@ -131,6 +133,7 @@
# define AXBS_PRS_M2_PRI6 (5 << AXBS_PRS_M2_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M2_PRI7 (6 << AXBS_PRS_M2_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M2_PRI8 (7 << AXBS_PRS_M2_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 11: Reserved */
#define AXBS_PRS_M3_SHIFT (12) /* Bits 12-14: Master 3 priority */
#define AXBS_PRS_M3_MASK (7 << AXBS_PRS_M3_SHIFT)
@@ -142,6 +145,7 @@
# define AXBS_PRS_M3_PRI6 (5 << AXBS_PRS_M3_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M3_PRI7 (6 << AXBS_PRS_M3_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M3_PRI8 (7 << AXBS_PRS_M3_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 15: Reserved */
#define AXBS_PRS_M4_SHIFT (16) /* Bits 16-18: Master 4 priority */
#define AXBS_PRS_M4_MASK (7 << AXBS_PRS_M4_SHIFT)
@@ -153,6 +157,7 @@
# define AXBS_PRS_M4_PRI6 (5 << AXBS_PRS_M4_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M4_PRI7 (6 << AXBS_PRS_M4_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M4_PRI8 (7 << AXBS_PRS_M4_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 19: Reserved */
#define AXBS_PRS_M5_SHIFT (20) /* Bits 20-22: Master 5 priority */
#define AXBS_PRS_M5_MASK (7 << AXBS_PRS_M5_SHIFT)
@@ -164,6 +169,7 @@
# define AXBS_PRS_M5_PRI6 (5 << AXBS_PRS_M5_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M5_PRI7 (6 << AXBS_PRS_M5_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M5_PRI8 (7 << AXBS_PRS_M5_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 23: Reserved */
#define AXBS_PRS_M6_SHIFT (24) /* Bits 24-26: Master 6 priority */
#define AXBS_PRS_M6_MASK (7 << AXBS_PRS_M6_SHIFT)
@@ -175,6 +181,7 @@
# define AXBS_PRS_M6_PRI6 (5 << AXBS_PRS_M6_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M6_PRI7 (6 << AXBS_PRS_M6_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M6_PRI8 (7 << AXBS_PRS_M6_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 27: Reserved */
#define AXBS_PRS_M7_SHIFT (28) /* Bits 28-30: Master 7 priority */
#define AXBS_PRS_M7_MASK (7 << AXBS_PRS_M7_SHIFT)
@@ -186,7 +193,9 @@
# define AXBS_PRS_M7_PRI6 (5 << AXBS_PRS_M7_SHIFT) /* Master has pri 6 access to slave port */
# define AXBS_PRS_M7_PRI7 (6 << AXBS_PRS_M7_SHIFT) /* Master has pri 7 access to slave port */
# define AXBS_PRS_M7_PRI8 (7 << AXBS_PRS_M7_SHIFT) /* Master has pri 8 (lowest) access to slave port */
/* Bit 31: Reserved */
/* Control Register */
#define AXBS_CRS_PARK_SHIFT (0) /* Bits 0-2: Park */
@@ -197,15 +206,18 @@
# define AXBS_CRS_PARK_M3 (3 << AXBS_CRS_PARK_SHIFT) /* Park on master port M3 */
# define AXBS_CRS_PARK_M4 (4 << AXBS_CRS_PARK_SHIFT) /* Park on master port M4 */
# define AXBS_CRS_PARK_M5 (5 << AXBS_CRS_PARK_SHIFT) /* Park on master port M5 */
#define AXBS_CRS_PCTL_SHIFT (4) /* Bits 4-5: Parking control */
#define AXBS_CRS_PCTL_MASK (2 << AXBS_CRS_PCTL_SHIFT)
# define AXBS_CRS_PCTL_PARK (0 << AXBS_CRS_PCTL_SHIFT) /* Defined by the PARK bit field */
# define AXBS_CRS_PCTL_LAST (1 << AXBS_CRS_PCTL_SHIFT) /* Last master in control of slave port */
# define AXBS_CRS_PCTL_NOT (2 << AXBS_CRS_PCTL_SHIFT) /* Not parked on a master */
#define AXBS_CRS_ARB_SHIFT (8) /* Bits 8-9: Arbitration mode */
#define AXBS_CRS_ARB_MASK (3 << AXBS_CRS_ARB_SHIFT)
# define AXBS_CRS_ARB_FIXED (0 << AXBS_CRS_ARB_SHIFT) /* Fixed priority */
# define AXBS_CRS_ARB_MASK (1 << AXBS_CRS_ARB_SHIFT) /* Round-robin (rotating) priority */
/* Bits 10-29: Reserved */
#define AXBS_CRS_HLP (1 < 30) /* Bit 30: Halt low priority */
#define AXBS_CRS_RO (1 < 31) /* Bit 31: Read only */
@@ -219,18 +231,19 @@
# define AXBS_MGPCR_AULB_4BEATS (2 << AXBS_MGPCR_AULB_SHIFT) /* Arbitration allowed after four beats */
# define AXBS_MGPCR_AULB_8BEATS (3 << AXBS_MGPCR_AULB_SHIFT) /* Arbitration allowed after eight beats */
# define AXBS_MGPCR_AULB_16BEATS (4 << AXBS_MGPCR_AULB_SHIFT) /* Arbitration allowed after 16 beats */
/* Bits 3-31: Reserved */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H */
arch/arm/src/kinetis/hardware/kinetis_cmp.h
+19 -17
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_cmp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINESIS_CMP_OFFSET(n) ((n) << 3)
#define KINESIS_CMP0_OFFSET 0x0000
@@ -47,7 +47,7 @@
#define KINETIS_CMP_DACCR_OFFSET 0x0004 /* DAC Control Register */
#define KINETIS_CMP_MUXCR_OFFSET 0x0005 /* MUX Control Register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINESIS_CMP_BASE(n) (KINETIS_CMP_BASE+KINESIS_CMP_OFFSET(n))
#define KINESIS_CMP0_BASE (KINETIS_CMP_BASE+KINESIS_CMP0_OFFSET)
@@ -82,7 +82,7 @@
#define KINETIS_CMP2_DACCR (KINETIS_CMP2_BASE+KINETIS_CMP_DACCR_OFFSET)
#define KINETIS_CMP2_MUXCR (KINETIS_CMP2_BASE+KINETIS_CMP_MUXCR_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* CMP Control Register 0 (8-bit) */
@@ -103,7 +103,9 @@
# define CMP_CR0_FILTER_CNT5 (5 << CMP_CR0_FILTER_CNT_SHIFT) /* 5 consecutive samples must agree */
# define CMP_CR0_FILTER_CNT6 (6 << CMP_CR0_FILTER_CNT_SHIFT) /* 6 consecutive samples must agree */
# define CMP_CR0_FILTER_CNT7 (7 << CMP_CR0_FILTER_CNT_SHIFT) /* 7 consecutive samples must agree */
/* Bit 7: Reserved */
/* CMP Control Register 1 (8-bit) */
#define CMP_CR1_EN (1 << 0) /* Bit 0: Comparator Module Enable */
@@ -117,7 +119,6 @@
/* CMP Filter Period Register (8-bit Filter Sample Period) */
/* CMP Status and Control Register (8-bit) */
#define CMP_SCR_COUT (1 << 0) /* Bit 0: Analog Comparator Output */
@@ -128,6 +129,7 @@
#define CMP_SCR_SMELB (1 << 5) /* Bit 5: Stop Mode Edge/Level Interrupt Control */
#define CMP_SCR_DMAEN (1 << 6) /* Bit 6: DMA Enable Control */
/* Bit 7: Reserved */
/* DAC Control Register (8-bit) */
#define CMP_DACCR_VOSEL_SHIFT (0) /* Bits 0-5: DAC Output Voltage Select */
@@ -162,16 +164,16 @@
#endif
#define CMP_MUXCR_PEN (1 << 7) /* Bit 7: PMUX Enable */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H */
arch/arm/src/kinetis/hardware/kinetis_cmt.h
+27 -22
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_cmt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_CMT_CGH1_OFFSET 0x0000 /* CMT Carrier Generator High Data Register 1 */
#define KINETIS_CMT_CGL1_OFFSET 0x0001 /* CMT Carrier Generator Low Data Register 1 */
@@ -48,7 +48,7 @@
#define KINETIS_CMT_PPS_OFFSET 0x000a /* CMT Primary Prescaler Register */
#define KINETIS_CMT_DMA_OFFSET 0x000b /* CMT Direct Memory Access */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_CMT_CGH1 (KINETIS_CMT_BASE+KINETIS_CMT_CGH1_OFFSET)
#define KINETIS_CMT_CGL1 (KINETIS_CMT_BASE+KINETIS_CMT_CGL1_OFFSET)
@@ -63,17 +63,18 @@
#define KINETIS_CMT_PPS (KINETIS_CMT_BASE+KINETIS_CMT_PPS_OFFSET)
#define KINETIS_CMT_DMA (KINETIS_CMT_BASE+KINETIS_CMT_DMA_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* CMT Carrier Generator High/Low Data Register 1 (8-bit Primary Carrier High Time
* Data Value)
/* CMT Carrier Generator High/Low Data Register 1
* (8-bit Primary Carrier High Time Data Value)
*/
/* CMT Carrier Generator High/Low Data Register 2 (8-bit Secondary Carrier High Time
* Data Value)
/* CMT Carrier Generator High/Low Data Register 2
* (8-bit Secondary Carrier High Time Data Value)
*/
/* CMT Output Control Register (8-bit) */
/* Bits 0-4: Reserved */
#define CMT_OC_IROPEN (1 << 5) /* Bit 5: IRO Pin Enable */
#define CMT_OC_CMTPOL (1 << 6) /* Bit 6: CMT Output Polarity */
@@ -92,32 +93,36 @@
# define CMT_MSC_CMTDIV_DIV2 (1 << CMT_MSC_CMTDIV_SHIFT) /* IF / 2 */
# define CMT_MSC_CMTDIV_DIV4 (2 << CMT_MSC_CMTDIV_SHIFT) /* IF / 4 */
# define CMT_MSC_CMTDIV_DIV8 (3 << CMT_MSC_CMTDIV_SHIFT) /* IF / 8 */
#define CMT_MSC_EOCF (1 << 7) /* Bit 7: End Of Cycle Status Flag */
/* CMT Modulator Data Register Mark High/Low (8-bit command data) */
/* CMT Modulator Data Register Space High/Low (8-bit command data)*/
/* CMT Modulator Data Register Space High/Low (8-bit command data) */
/* CMT Primary Prescaler Register (8-bit) */
#define CMT_PPS_SHIFT (0) /* Bits 0-3: Primary Prescaler Divider */
#define CMT_PPS_MASK (15 << CMT_PPS_SHIFT)
# define CMT_PPS_DIV(n) (((n)-1) << CMT_PPS_SHIFT) /* Bus clock / n, n=1..16 */
/* Bits 4-7: Reserved */
/* CMT Direct Memory Access (8-bit) */
#define CMT_DMA_ENABLE (1 << 0) /* Bit 0: DMA Enable
#define CMT_DMA_ENABLE (1 << 0) /* Bit 0: DMA Enable */
/* Bits 1-7: Reserved */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H */
arch/arm/src/kinetis/hardware/kinetis_crc.h
+18 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_crc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,23 +31,23 @@
#if defined(KINETIS_NCRC) && KINETIS_NCRC > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_CRC_DATA_OFFSET 0x0000 /* CRC Data Register */
#define KINETIS_CRC_GPOLY_OFFSET 0x0004 /* CRC Polynomial Register */
#define KINETIS_CRC_CTRL_OFFSET 0x0008 /* CRC Control Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_CRC_DATA (KINETIS_CRC_BASE+KINETIS_CRC_DATA_OFFSET)
#define KINETIS_CRC_GPOLY (KINETIS_CRC_BASE+KINETIS_CRC_GPOLY_OFFSET)
#define KINETIS_CRC_CTRL (KINETIS_CRC_BASE+KINETIS_CRC_CTRL_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* CRC Data Register (32-bit) */
@@ -68,6 +68,7 @@
#define CRC_GPOLY_HIGH_MASK (0xffff << CRC_GPOLY_HIGH_SHIFT)
/* CRC Control Register */
/* Bits 0-23: Reserved */
#define CRC_CTRL_TCRC (1 << 24) /* Bit 24: Width of CRC protocol */
#define CRC_CTRL_WAS (1 << 25) /* Bit 25: Write CRC data register as seed */
@@ -79,6 +80,7 @@
# define CRC_CTRL_TOTR_BITS (1 << CRC_CTRL_TOTR_SHIFT) /* Bits transposed; bytes are not */
# define CRC_CTRL_TOTR_BOTH (2 << CRC_CTRL_TOTR_SHIFT) /* Both bits bytes and bytes transposed */
# define CRC_CTRL_TOTR_BYTES (3 << CRC_CTRL_TOTR_SHIFT) /* Bytes transposed; bits in byte are not */
#define CRC_CTRL_TOT_SHIFT (30) /* Bits 30-31: Type of Transpose for Writes */
#define CRC_CTRL_TOT_MASK (3 << CRC_CTRL_TOT_SHIFT)
# define CRC_CTRL_TOT_NONE (0 << CRC_CTRL_TOT_SHIFT) /* No transposition */
@@ -86,17 +88,17 @@
# define CRC_CTRL_TOT_BOTH (2 << CRC_CTRL_TOT_SHIFT) /* Both bits bytes and bytes transposed */
# define CRC_CTRL_TOT_BYTES (3 << CRC_CTRL_TOT_SHIFT) /* Bytes transposed; bits in byte are not */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_NCRC && KINETIS_NCRC > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H */
arch/arm/src/kinetis/hardware/kinetis_dac.h
+20 -17
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_dac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_DAC_DATL_OFFSET(n) (0x0000+((n)<<1))
#define KINETIS_DAC_DATH_OFFSET(n) (0x0001+((n)<<1))
@@ -75,7 +75,7 @@
#define KINETIS_DAC_C1_OFFSET 0x0022 /* DAC Control Register 1 */
#define KINETIS_DAC_C2_OFFSET 0x0023 /* DAC Control Register 2 */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_DAC0_DATL(n) (KINETIS_DAC0_BASE+KINETIS_DAC_DATL_OFFSET(n))
#define KINETIS_DAC0_DATH(n) (KINETIS_DAC0_BASE+KINETIS_DAC_DATH_OFFSET(n))
@@ -157,9 +157,10 @@
#define KINETIS_DAC1_C1 (KINETIS_DAC1_BASE+KINETIS_DAC_C1_OFFSET)
#define KINETIS_DAC1_C2 (KINETIS_DAC1_BASE+KINETIS_DAC_C2_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* DAC Data Low Register (8-bits of data DATA[7:0]) */
/* DAC Data High Register */
#define DAC_DAT0H_MASK (0x0f) /* Bits 0-3: DATA[11:8] */
@@ -168,8 +169,9 @@
#define DAC_SR_DACBFRPBF (1 << 0) /* Bit 0: DAC buffer read pointer bottom position flag */
#define DAC_SR_DACBFRPTF (1 << 1) /* Bit 1: DAC buffer read pointer top position flag */
#define DAC_SR_DACBFWMF (1 << 2) /* Bit 2: DAC buffer watermark flag
#define DAC_SR_DACBFWMF (1 << 2) /* Bit 2: DAC buffer watermark flag */
/* Bits 3-7: Reserved */
/* DAC Control Register */
#define DAC_C0_DACBBIEN (1 << 0) /* Bit 0: DAC buffer read pointer bottom flag interrupt enable */
@@ -189,6 +191,7 @@
# define DAC_C1_DACBFMD_NORMAL (0 << DAC_C1_DACBFMD_SHIFT) /* Normal Mode */
# define DAC_C1_DACBFMD_SWING (1 << DAC_C1_DACBFMD_SHIFT) /* Swing Mode */
# define DAC_C1_DACBFMD_OTSCAN (2 << DAC_C1_DACBFMD_SHIFT) /* One-Time Scan Mode */
#define DAC_C1_DACBFWM_SHIFT (3) /* Bits 3-4: DAC buffer watermark select */
#define DAC_C1_DACBFWM_MASK (3 << DAC_C1_DACBFWM_SHIFT)
# define DAC_C1_DACBFWM_1WORD (0 << DAC_C1_DACBFWM_SHIFT)
@@ -205,16 +208,16 @@
#define DAC_C2_DACBFUP_SHIFT (0) /* Bits 0-3: DAC buffer upper limit */
#define DAC_C2_DACBFUP_MASK (15 << DAC_C2_DACBFUP_SHIFT)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H */
arch/arm/src/kinetis/hardware/kinetis_dma.h
+30 -21
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_DMA_CR_OFFSET 0x0000 /* Control Register */
#define KINETIS_DMA_ES_OFFSET 0x0004 /* Error Status Register */
@@ -68,7 +68,6 @@
#define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */
#define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */
#define KINETIS_DMA_DCHPRI_OFFSET(n) 0x0100 + (n - (n % 4)) + (3 - (n % 4)) /* Channel n Priority Register */
#define KINETIS_DMA_TCD_OFFSET(n) (0x0000 + ((n) << 5))
@@ -276,7 +275,7 @@
#define KINETIS_DMA_TCD15_CSR_OFFSET 0x01fc /* TCD Control and Status */
#define KINETIS_DMA_TCD15_BITER_OFFSET 0x01fe /* TCD Beginning Minor Loop Link, Major Loop Count */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_DMA_CR (KINETIS_DMAC_BASE + KINETIS_DMA_CR_OFFSET)
#define KINETIS_DMA_ES (KINETIS_DMAC_BASE + KINETIS_DMA_ES_OFFSET)
@@ -519,9 +518,10 @@
#define KINETIS_DMA_TCD15_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CSR_OFFSET)
#define KINETIS_DMA_TCD15_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_BITER_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* Control Register (32-bit) */
/* Bit 0: Reserved */
#define DMA_CR_EDBG (1 << 1) /* Bit 1: Enable debug */
#define DMA_CR_ERCA (1 << 2) /* Bit 2: Enable round robin channel arbitration */
@@ -565,8 +565,9 @@
/* Bits 17-30: Reserved */
#define DMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */
/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI), Interrupt Request Register (INT),
* Error Register (ERR), Hardware Request Status Register (HRS) common bit definitions
/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI),
* Interrupt Request Register (INT), Error Register (ERR),
* Hardware Request Status Register (HRS) common bit definitions
*/
#define DMA_REQ(n) (1 << (n)) /* Bit n: DMA Request n, n=0..<KINETIS_NDMACH */
@@ -652,6 +653,7 @@
#endif
/* TCD Source Address. 32-bit address value. */
/* TCD Signed Source Address Offset. 32-bit offset value. */
/* TCD Transfer Attributes (16-bit) */
@@ -662,6 +664,7 @@
# define DMA_TCD_ATTR_DSIZE_16BIT (1 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */
# define DMA_TCD_ATTR_DSIZE_32BIT (2 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
# define DMA_TCD_ATTR_DSIZE_16BYTE (4 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 16-byte */
#define DMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination address modulo */
#define DMA_TCD_ATTR_DMOD_MASK (31 << DMA_TCD_ATTR_DMOD_SHIFT)
#define DMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */
@@ -670,11 +673,13 @@
# define DMA_TCD_ATTR_SSIZE_16BIT (1 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define DMA_TCD_ATTR_SSIZE_32BIT (2 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
# define DMA_TCD_ATTR_SSIZE_16BYTE (4 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
#define DMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source address modulo */
#define DMA_TCD_ATTR_SMOD_MASK (31 << DMA_TCD_ATTR_SMOD_SHIFT)
/* TCD Minor Byte Count.
* Case 1: Minor Loop Disabled. In this case, the register holds a simple 32-bit count value.
* Case 1: Minor Loop Disabled.
* In this case, the register holds a simple 32-bit count value.
* Case 2: Minor Loop Enabled and Offset Disabled:
*/
@@ -693,7 +698,9 @@
/* Bit 31: Same as Case 2 */
/* TCD Last Source Address Adjustment. 32-bit address value. */
/* TCD Destination Address. 32-bit address value. */
/* TCD Signed Destination Address Offset. 32-bit offset value. */
/* TCD Current Minor Loop Link, Major Loop Count. 16-bit.
@@ -713,7 +720,9 @@
#define DMA_TCD_CITER2_MASK (0x7fff << DMA_TCD_CITER2_SHIFT)
/* Bits 15: Same as Case 1 */
/* TCD Last Destination Address Adjustment/Scatter Gather Address. 32-bit address value. */
/* TCD Last Destination Address Adjustment/Scatter Gather Address.
* 32-bit address value.
*/
/* TCD Control and Status (16-bit) */
@@ -752,16 +761,16 @@
#define DMA_TCD_BITER2_MASK (0x7fff << DMA_TCD_CITER2_SHIFT)
/* Bits 15: Same as Case 1 */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H */
arch/arm/src/kinetis/hardware/kinetis_dmamux.h
+18 -17
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_dmamux.h
*
* Copyright (C) 2011, 2016, 2018 Gregory Nutt. All rights reserved.
@@ -32,24 +32,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#if KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG == 0
@@ -63,11 +63,12 @@
# define KINETIS_DMAMUX_CHCFG_OFFSET(n) (n)
#endif
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_DMAMUX_CHCFG(n) (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG_OFFSET(n))
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* Channel n Configuration Register */
#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (slot) */
@@ -75,7 +76,7 @@
#define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable */
#define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable */
/* DMA Request sources*****************************************************************************/
/* DMA Request sources*******************************************************/
#ifdef KINETIS_K60
@@ -258,16 +259,16 @@
#endif /* KINETIS_K66 */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H */
arch/arm/src/kinetis/hardware/kinetis_dspi.h
+26 -19
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_dspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_SPI_MCR_OFFSET 0x0000 /* DSPI Module Configuration Register */
#define KINETIS_SPI_TCR_OFFSET 0x0008 /* DSPI Transfer Count Register */
@@ -52,7 +52,7 @@
#define KINETIS_SPI_RXFR2_OFFSET 0x0084 /* DSPI Receive FIFO Registers */
#define KINETIS_SPI_RXFR3_OFFSET 0x0088 /* DSPI Receive FIFO Registers */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_SPI0_MCR (KINETIS_SPI0_BASE+KINETIS_SPI_MCR_OFFSET)
#define KINETIS_SPI0_TCR (KINETIS_SPI0_BASE+KINETIS_SPI_TCR_OFFSET)
@@ -105,7 +105,7 @@
#define KINETIS_SPI2_RXFR2 (KINETIS_SPI2_BASE+KINETIS_SPI_RXFR2_OFFSET)
#define KINETIS_SPI2_RXFR3 (KINETIS_SPI2_BASE+KINETIS_SPI_RXFR3_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* DSPI Module Configuration Register */
@@ -116,6 +116,7 @@
# define SPI_MCR_SMPL_PT_0CLKS (0 << SPI_MCR_SMPL_PT_SHIFT) /* 0 clocks between edge and sample */
# define SPI_MCR_SMPL_PT_1CLKS (1 << SPI_MCR_SMPL_PT_SHIFT) /* 1 clock between edge and sample */
# define SPI_MCR_SMPL_PT_2CLKS (2 << SPI_MCR_SMPL_PT_SHIFT) /* 2 clocks between edge and sample */
#define SPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO */
#define SPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO */
#define SPI_MCR_DIS_RXF (1 << 12) /* Bit 12: Disable Receive FIFO */
@@ -137,6 +138,7 @@
#define SPI_MCR_MSTR (1 << 31) /* Bit 31: Master/Slave Mode Select */
/* DSPI Transfer Count Register */
/* Bits 0-15: Reserved */
#define SPI_TCR_SPI_TCNT_SHIFT (16) /* Bits 16-31: SPI Transfer Counter */
#define SPI_TCR_SPI_TCNT_MASK (0xffff << SPI_TCR_SPI_TCNT_SHIFT)
@@ -222,8 +224,12 @@
#define SPI_CTARM_DBR (1 << 31) /* Bit 31: Double Baud Rate */
/* DSPI Clock and Transfer Attributes Register (Slave Mode) */
/* Bits 0-24: Reserved */
/* Bits 25-26: See common bits above */
/* Bits 25-26:
* See common bits above
*/
#define SPI_CTARS_FMSZ_SHIFT (27) /* Bits 27-31: Frame Size */
#define SPI_CTARS_FMSZ_MASK (31 << SPI_CTARS_FMSZ_SHIFT)
@@ -251,6 +257,7 @@
#define SPI_SR_TCF (1 << 31) /* Bit 31: Transfer Complete Flag */
/* DSPI DMA/Interrupt Request Select and Enable Register */
/* Bits 0-15: Reserved */
#define SPI_RSER_RFDF_DIRS (1 << 16) /* Bit 16: Receive FIFO Drain DMA or Interrupt Request Select */
#define SPI_RSER_RFDF_RE (1 << 17) /* Bit 17: Receive FIFO Drain Request Enable */
@@ -265,7 +272,7 @@
/* Bits 29-30: Reserved */
#define SPI_RSER_TCF_RE (1 << 31) /* Bit 31: Transmission Complete Request Enable */
/* DSPI PUSH TX FIFO Register (Master Mode)*/
/* DSPI PUSH TX FIFO Register (Master Mode) */
#define SPI_PUSHR_TXDATA_SHIFT (0) /* Bits 0-15: Transmit Data */
#define SPI_PUSHR_TXDATA_MASK (0xffff << SPI_PUSHR_TXDATA_SHIFT)
@@ -282,7 +289,7 @@
# define SPI_PUSHR_CTAS_CTAR1 (1 << SPI_PUSHR_CTAS_SHIFT)
#define SPI_PUSHR_CONT (1 << 31) /* Bit 31: Continuous Peripheral Chip Select Enable */
/* DSPI PUSH TX FIFO Register (Slave Mode, 32-bits of RXDATA)*/
/* DSPI PUSH TX FIFO Register (Slave Mode, 32-bits of RXDATA) */
/* DSPI POP RX FIFO Register (32-bits of RXDATA) */
@@ -295,16 +302,16 @@
/* DSPI Receive FIFO Registers (32-bits of RXDATA) */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H */
arch/arm/src/kinetis/hardware/kinetis_enet.h
+69 -21
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_enet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,11 @@
#if defined(KINETIS_NENET) && KINETIS_NENET > 0
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */
#define KINETIS_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */
@@ -88,7 +88,7 @@
#define KINETIS_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */
#define KINETIS_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_ENET_EIR (KINETIS_EMAC_BASE+KINETIS_ENET_EIR_OFFSET)
#define KINETIS_ENET_EIMR (KINETIS_EMAC_BASE+KINETIS_ENET_EIMR_OFFSET)
@@ -141,9 +141,10 @@
#define KINETIS_ENET_TCSR3 (KINETIS_EMAC_BASE+KINETIS_ENET_TCSR3_OFFSET)
#define KINETIS_ENET_TCCR3 (KINETIS_EMAC_BASE+KINETIS_ENET_TCCR3_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* Interrupt Event Register, Interrupt Mask Register */
/* Bits 0-14: Reserved */
#define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */
#define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */
@@ -162,14 +163,19 @@
#define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */
#define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */
/* Bit 31: Reserved */
/* Receive Descriptor Active Register */
/* Bits 0-23: Reserved */
#define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */
/* Bits 25-31: Reserved */
/* Transmit Descriptor Active Register */
/* Bits 0-23: Reserved */
#define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */
/* Bits 25-31: Reserved */
/* Ethernet Control Register */
#define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */
@@ -184,6 +190,7 @@
#define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes */
#endif
/* Bits 9-31: Reserved */
/* MII Management Frame Register */
#define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */
@@ -200,10 +207,12 @@
# define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */
# define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */
# define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */
#define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */
#define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT)
/* MII Speed Control Register */
/* Bit 0: Reserved */
#define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */
#define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT)
@@ -214,8 +223,11 @@
# define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */
# define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */
# define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */
/* Bits 11-31: Reserved */
/* MIB Control Register */
/* Bits 0-28: Reserved */
#define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */
#define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */
@@ -253,9 +265,12 @@
#define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */
#define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT)
# define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */
#define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */
/* Bits 10-31: Reserved */
/* Physical Address Lower/Upper Register (32-bits of 48-address) */
/* Physical Address Upper Register */
#define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */
@@ -270,8 +285,13 @@
#define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */
#define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT)
/* Descriptor Individual Uupper/Lower Address Register (64-bit address in two 32-bit registers) */
/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */
/* Descriptor Individual Uupper/Lower Address Register
* (64-bit address in two 32-bit registers)
*/
/* Descriptor Group Upper/Lower Address Register
* (64-bit address in two 32-bit registers)
*/
/* Transmit FIFO Watermark Register */
@@ -280,22 +300,28 @@
#define ENET_TFWR_TFWR_MASK (63 << ENET_TFWR_TFWR_SHIFT)
#define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */
/* Bits 9-31: Reserved */
/* Receive Descriptor Ring Start Register */
/* Bits 0-2: Reserved */
#define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */
#define ENET_RDSR_MASK (0xfffffff8)
/* Transmit Buffer Descriptor Ring Start Register */
/* Bits 0-2: Reserved */
#define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */
#define ENET_TDSR_MASK (0xfffffff8)
/* Maximum Receive Buffer Size Register */
/* Bits 14-31: Reserved */
#define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */
#define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT)
/* Bits 0-3: Reserved */
/* Receive FIFO Section Full Threshold */
/* Bits 8-31: Reserved */
#define ENET_RSFL_SHIFT (0) /* Bits 0-7: Value of receive FIFO section full threshold */
#define ENET_RSFL_MASK (0xff << ENET_RSFL_SHIFT)
@@ -305,41 +331,49 @@
#define ENET_RSEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO section empty threshold */
#define ENET_RSEM_MASK (0xff << ENET_RSEM_SHIFT)
/* Bits 8-31: Reserved */
/* Receive FIFO Almost Empty Threshold */
#define ENET_RAEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost empty threshold */
#define ENET_RAEM_MASK (0xff << ENET_RAEM_SHIFT)
/* Bits 8-31: Reserved */
/* Receive FIFO Almost Full Threshold */
#define ENET_RAFL_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost full threshold */
#define ENET_RAFL_MASK (0xff << ENET_RAFL_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit FIFO Section Empty Threshold */
#define ENET_TSEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */
#define ENET_TSEM_MASK (0xff << ENET_TSEM_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit FIFO Almost Empty Threshold */
#define ENET_TAEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */
#define ENET_TAEM_MASK (0xff << ENET_TAEM_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit FIFO Almost Full Threshold */
#define ENET_TAFL_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */
#define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit Inter-Packet Gap */
#define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */
#define ENET_TIPG_MASK (31 << ENET_TIPG_SHIFT)
/* Bits 5-31: Reserved */
/* Frame Truncation Length */
#define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */
#define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT)
/* Bits 14-31: Reserved */
/* Transmit Accelerator Function Configuration */
#define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */
@@ -347,6 +381,7 @@
#define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */
#define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */
/* Bits 5-31: Reserved */
/* Receive Accelerator Function Configuration */
#define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */
@@ -356,6 +391,7 @@
#define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */
#define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */
/* Bits 8-31: Reserved */
/* Timer Control Register */
#define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */
@@ -372,14 +408,19 @@
/* Bit 12: Reserved */
#define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */
/* Bits 14-31: Reserved */
/* Timer Value Register (32-bit timer value) */
/* Timer Offset Register (32-bit offset value) */
/* Timer Period Register (32-bit timer period) */
/* Timer Correction Register */
#define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */
/* Bit 31: Reserved */
/* Bit 31: Reserved */
/* Time-Stamping Clock Period Register */
#define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */
@@ -388,6 +429,7 @@
#define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */
#define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT)
/* Bits 15-31: Reserved */
/* Timestamp of Last Transmitted Frame (32-bit timestamp) */
/* Timer Global Status Register */
@@ -397,6 +439,7 @@
#define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */
#define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */
/* Bits 14-31: Reserved */
/* Timer Control Status Register n */
#define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */
@@ -415,12 +458,15 @@
# define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */
# define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */
# define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */
#define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */
#define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */
/* Bits 8-31: Reserved */
/* Timer Compare Capture Register (32-bit compare value) */
/* Buffer Descriptors ***********************************************************************/
/* Buffer Descriptors *******************************************************/
/* Endian-independent descriptor offsets */
#define DESC_STATUS1_OFFSET (0)
@@ -566,10 +612,12 @@
# define RXDESC_BDU (1 << 7)
#endif
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
/* Buffer Descriptors ***********************************************************************/
****************************************************************************/
/* Buffer Descriptors *******************************************************/
/* Legacy Buffer Descriptor */
#ifdef CONFIG_ENET_ENHANCEDBD
@@ -625,13 +673,13 @@ struct enet_desc_s
#endif
#endif
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_NENET && KINETIS_NENET > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H */
arch/arm/src/kinetis/hardware/kinetis_ewm.h
+18 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_ewm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,38 +16,38 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_EWM_CTRL_OFFSET 0x0000 /* Control Register */
#define KINETIS_EWM_SERV_OFFSET 0x0001 /* Service Register */
#define KINETIS_EWM_CMPL_OFFSET 0x0002 /* Compare Low Register */
#define KINETIS_EWM_CMPH_OFFSET 0x0003 /* Compare High Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_EWM_CTRL (KINETIS_EWM_BASE+KINETIS_EWM_CTRL_OFFSET)
#define KINETIS_EWM_SERV (KINETIS_EWM_BASE+KINETIS_EWM_SERV_OFFSET)
#define KINETIS_EWM_CMPL (KINETIS_EWM_BASE+KINETIS_EWM_CMPL_OFFSET)
#define KINETIS_EWM_CMPH (KINETIS_EWM_BASE+KINETIS_EWM_CMPH_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Control Register (8-bit) */
@@ -57,19 +57,21 @@
/* Bits 7–3: Reserved */
/* Service Register (8-bit values: 0xb4 followed by 0x2c) */
/* Compare Low Register (8-bit compare low value) */
/* Compare High Register (8-bit compare high value) */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H */
arch/arm/src/kinetis/hardware/kinetis_flexbus.h
+28 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_flexbus.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_FB_CS_OFFSET(n) (0x0000+(12*(n)))
#define KINETIS_FB_CSAR_OFFSET 0x0000 /* Chip select n address register */
@@ -66,7 +66,8 @@
#define KINETIS_FB_CSPMCR_OFFSET 0x0060 /* Chip select port multiplexing control register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
# define 0x4000c000 /* FlexBus */
#define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n))
@@ -100,7 +101,7 @@
#define KINETIS_FB_CSPMCR (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CSPMCR_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Chip select address register (32-bit) */
@@ -112,12 +113,13 @@
#define FB_CSMR_V (1 << 0) /* Bit 0: Valid */
/* Bits 1-7: Reserved */
#define FB_CSMR_WP (1 << 8) /* Bit 8: Write protect
#define FB_CSMR_WP (1 << 8) /* Bit 8: Write protect */
/* Bits 9-15: Reserved */
#define FB_CSMR_BAM_SHIFT (16) /* Bits 16-31: Base address mask */
#define FB_CSMR_BAM_MASK (0xffff << FB_CSMR_BAM_SHIFT)
/* Chip select control register (32-bit) */
/* Bits 0-1: Reserved */
#define FB_CSCR_BSTW (1 << 3) /* Bit 3: Burst-write enable */
#define FB_CSCR_BSTR (1 << 4) /* Bit 4: Burst-read enable */
@@ -127,6 +129,7 @@
# define FB_CSCR_PS_32BIT (0 << FB_CSCR_PS_SHIFT) /* 32-bit port size */
# define FB_CSCR_PS_8BIT (1 << FB_CSCR_PS_SHIFT) /* 8-bit port size */
# define FB_CSCR_PS_16BIT (2 << FB_CSCR_PS_SHIFT) /* 16-bit port size */
#define FB_CSCR_AA (1 << 8) /* Bit 8: Auto-acknowledge enable */
#define FB_CSCR_BLS (1 << 9) /* Bit 9: Byte-lane shift */
#define FB_CSCR_WS_SHIFT (10) /* Bits 19-15: Wait states */
@@ -137,18 +140,21 @@
# define FB_CSCR_WRAH_HOLD2 (1 << FB_CSCR_WRAH_SHIFT) /* Hold two cycles after FB_CSn */
# define FB_CSCR_WRAH_HOLD3 (2 << FB_CSCR_WRAH_SHIFT) /* Hold three cycles after FB_CSn */
# define FB_CSCR_WRAH_HOLD4 (3 << FB_CSCR_WRAH_SHIFT) /* Hold four cycles after FB_CSn */
#define FB_CSCR_RDAH_SHIFT (18) /* Bits 18-19: Read address hold or deselect */
#define FB_CSCR_RDAH_MASK (3 << FB_CSCR_RDAH_SHIFT)
# define FB_CSCR_RDAH_10CYCLES (0 << FB_CSCR_RDAH_SHIFT) /* AA=0:1 cycle else 0 cycles */
# define FB_CSCR_RDAH_21CYCLES (1 << FB_CSCR_RDAH_SHIFT) /* AA=0:2 cycles else 1 cycle */
# define FB_CSCR_RDAH_32CYCLES (2 << FB_CSCR_RDAH_SHIFT) /* AA=0:3 cycles else 2 cycles */
# define FB_CSCR_RDAH_43CYCLES (3 << FB_CSCR_RDAH_SHIFT) /* AA=0:4 cycles else 3 cycles */
#define FB_CSCR_ASET_SHIFT (20) /* Bits 20-21: Address setup */
#define FB_CSCR_ASET_MASK (3 << FB_CSCR_ASET_SHIFT)
# define FB_CSCR_ASET_1STRISING (0 << FB_CSCR_ASET_SHIFT) /* Assert CR on first rising clock edge */
# define FB_CSCR_ASET_2NDRISING (1 << FB_CSCR_ASET_SHIFT) /* Assert CR on second rising clock edge */
# define FB_CSCR_ASET_3RDRISING (2 << FB_CSCR_ASET_SHIFT) /* Assert CR on third rising clock edge */
# define FB_CSCR_ASET_4thRISING (3 << FB_CSCR_ASET_SHIFT) /* Assert CR on fourth rising clock edge */
#define FB_CSCR_EXTS (1 << 22) /* Bit 22: Extended address latch enable */
#define FB_CSCR_SWSEN (1 << 23) /* Bit 23: Secondary wait state enable */
/* Bits 24-25: Reserved */
@@ -156,43 +162,48 @@
#define FB_CSCR_SWS_MASK (0x3f << FB_CSCR_SWS_SHIFT)
/* Chip select port multiplexing control register (32-bit) */
/* Bits 0-11: Reserved */
#define FB_CSPMCR_GROUP5_SHIFT (12) /* Bits 12-15: FlexBus signal group 5 multiplex control */
#define FB_CSPMCR_GROUP5_MASK (15 << FB_CSPMCR_GROUP5_SHIFT)
# define FB_CSPMCR_GROUP5_TA (0 << FB_CSPMCR_GROUP5_SHIFT) /* FB_TA */
# define FB_CSPMCR_GROUP5_CS3 (1 << FB_CSPMCR_GROUP5_SHIFT) /* FB_CS3 */
# define FB_CSPMCR_GROUP5_BE70 (2 << FB_CSPMCR_GROUP5_SHIFT) /* FB_BE_7_0 */
#define FB_CSPMCR_GROUP4_SHIFT (16) /* Bits 16-19: FlexBus signal group 4 multiplex control */
#define FB_CSPMCR_GROUP4_MASK (15 << FB_CSPMCR_GROUP4_SHIFT)
# define FB_CSPMCR_GROUP4_TBST (0 << FB_CSPMCR_GROUP4_SHIFT) /* FB_TBST */
# define FB_CSPMCR_GROUP4_CS2 (1 << FB_CSPMCR_GROUP4_SHIFT) /* FB_CS2 */
# define FB_CSPMCR_GROUP4_BE158 (2 << FB_CSPMCR_GROUP4_SHIFT) /* FB_BE_15_8 */
#define FB_CSPMCR_GROUP3_SHIFT (20) /* Bits 29-23: FlexBus signal group 3 multiplex control */
#define FB_CSPMCR_GROUP3_MASK (15 << FB_CSPMCR_GROUP3_SHIFT)
# define FB_CSPMCR_GROUP3_CS5 (0 << FB_CSPMCR_GROUP3_SHIFT) /* FB_CS5 */
# define FB_CSPMCR_GROUP3_TSIZ1 (1 << FB_CSPMCR_GROUP3_SHIFT) /* FB_TSIZ1 */
# define FB_CSPMCR_GROUP3_BE2316 (2 << FB_CSPMCR_GROUP3_SHIFT) /* FB_BE_23_16 */
#define FB_CSPMCR_GROUP2_SHIFT (24) /* Bits 24-27: FlexBus signal group 2 multiplex control */
#define FB_CSPMCR_GROUP2_MASK (15 << FB_CSPMCR_GROUP2_SHIFT)
# define FB_CSPMCR_GROUP2_CS4 (0 << FB_CSPMCR_GROUP2_SHIFT) /* FB_CS4 */
# define FB_CSPMCR_GROUP2_TSIZ0 (1 << FB_CSPMCR_GROUP2_SHIFT) /* FB_TSIZ0 */
# define FB_CSPMCR_GROUP2_BE3124 (2 << FB_CSPMCR_GROUP2_SHIFT) /* FB_BE_31_24 */
#define FB_CSPMCR_GROUP1_SHIFT (28) /* Bits 28-31: FlexBus signal group 1 multiplex control */
#define FB_CSPMCR_GROUP1_MASK (15 << FB_CSPMCR_GROUP1_MASK)
# define FB_CSPMCR_GROUP1_ALE (0 << FB_CSPMCR_GROUP1_MASK) /* FB_ALE */
# define FB_CSPMCR_GROUP1_CS1 (1 << FB_CSPMCR_GROUP1_MASK) /* FB_CS1 */
# define FB_CSPMCR_GROUP1_TS (2 << FB_CSPMCR_GROUP1_MASK) /* FB_TS */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H */
arch/arm/src/kinetis/hardware/kinetis_flexcan.h
+13 -13
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_flexcan.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_CAN_MCR_OFFSET 0x0000 /* Module Configuration Register */
#define KINETIS_CAN_CTRL1_OFFSET 0x0004 /* Control 1 Register */
@@ -73,7 +73,7 @@
#define KINETIS_CAN_RXIMR14_OFFSET 0x08b8 /* R14 Individual Mask Registers */
#define KINETIS_CAN_RXIMR15_OFFSET 0x08bc /* R15 Individual Mask Registers */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_CAN0_MCR (KINETIS_CAN0_BASE+KINETIS_CAN_MCR_OFFSET)
#define KINETIS_CAN0_CTRL1 (KINETIS_CAN0_BASE+KINETIS_CAN_CTRL1_OFFSET)
@@ -112,7 +112,7 @@
#define KINETIS_CAN0_RXIMR15 (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR15_OFFSET)
#define KINETIS_CAN0_RXIMR_COUNT 16 /* Individual Mask Registers Count */
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* Module Configuration Register */
@@ -320,12 +320,12 @@
/* an incoming Remote Request Frame. */
#define CAN_TXMB_NOTUSED 0xF /* Not used.*/
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H */
arch/arm/src/kinetis/hardware/kinetis_fmc.h
+15 -15
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around FMC header files for the Kinetis family selected by
* the logic in chip.h.
/* This file is just a wrapper around FMC header files for the Kinetis
* family selected by the logic in chip.h.
*/
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
@@ -43,20 +43,20 @@
# error "No FMC definitions for this Kinetis part"
#endif
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H */
arch/arm/src/kinetis/hardware/kinetis_ftfe.h
+23 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_ftfe.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_FTFE_FSTAT_OFFSET 0x0000 /* Flash Status Register */
#define KINETIS_FTFE_FCNFG_OFFSET 0x0001 /* Flash Configuration Register */
@@ -59,7 +59,7 @@
#define KINETIS_FTFE_FEPROT_OFFSET 0x0016 /* EEPROM Protection Register */
#define KINETIS_FTFE_FDPROT_OFFSET 0x0017 /* Data Flash Protection Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_FTFE_FSTAT (KINETIS_FTFE_BASE+KINETIS_FTFE_FSTAT_OFFSET)
#define KINETIS_FTFE_FCNFG (KINETIS_FTFE_BASE+KINETIS_FTFE_FCNFG_OFFSET)
@@ -84,7 +84,7 @@
#define KINETIS_FTFE_FEPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FEPROT_OFFSET)
#define KINETIS_FTFE_FDPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FDPROT_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Flash Status Register */
@@ -112,33 +112,40 @@
#define FTFE_FSEC_SEC_MASK (3 << FTFE_FSEC_SEC_SHIFT)
# define FTFE_FSEC_SEC_SECURE (0 << FTFE_FSEC_SEC_SHIFT) /* 00,01,11: status is secure */
# define FTFE_FSEC_SEC_UNSECURE (2 << FTFE_FSEC_SEC_SHIFT) /* 10: status is insecure */
#define FTFE_FSEC_FSLACC_SHIFT (2) /* Bits 2-3: Freescale Failure Analysis Access Code */
#define FTFE_FSEC_FSLACC_MASK (3 << FTFE_FSEC_FSLACC_SHIFT)
# define FTFE_FSEC_FSLACC_GRANTED (0 << FTFE_FSEC_FSLACC_SHIFT) /* 00 or 11: Access granted */
# define FTFE_FSEC_FSLACC_DENIED (1 << FTFE_FSEC_FSLACC_SHIFT) /* 01 or 10: Access denied */
#define FTFE_FSEC_MEEN_SHIFT (4) /* Bits 4-5: Mass Erase Enable Bits */
#define FTFE_FSEC_MEEN_MASK (3 << FTFE_FSEC_MEEN_SHIFT)
# define FTFE_FSEC_MEEN_ENABLED (0 << FTFE_FSEC_MEEN_SHIFT) /* All values are enabled */
#define FTFE_FSEC_KEYEN_SHIFT (6) /* Bits 6-7: Backdoor Key Security Enable */
#define FTFE_FSEC_KEYEN_MASK (3 << FTFE_FSEC_KEYEN_SHIFT)
# define FTFE_FSEC_KEYEN_DISABLED (1 << FTFE_FSEC_KEYEN_SHIFT) /* All values are disabled */
/* Flash Option Register (32-bits, see Chip Configuration details) */
/* Flash Common Command Object Registers (8-bit flash command data) */
/* Program Flash Protection Registers (8-bit flash protection data) */
/* EEPROM Protection Register (8-bit eeprom protection data) */
/* Data Flash Protection Register (8-bit data flash protection data) */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H */
arch/arm/src/kinetis/hardware/kinetis_ftm.h
+46 -20
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_ftm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_FTM_SC_OFFSET 0x0000 /* Status and Control */
#define KINETIS_FTM_CNT_OFFSET 0x0004 /* Counter */
@@ -41,6 +41,7 @@
#define KINETIS_FTM_CSC_OFFSET(n) (0x000c+((n)<<3)) /* Channel (n) Status and Control */
#define KINETIS_FTM_CV_OFFSET(n) (0x0010+((n)<<3)) /* Channel (n) Value */
#define KINETIS_FTM_C0SC_OFFSET 0x000c /* Channel 0 Status and Control */
#define KINETIS_FTM_C0V_OFFSET 0x0010 /* Channel 0 Value */
#define KINETIS_FTM_C1SC_OFFSET 0x0014 /* Channel 1 Status and Control */
@@ -79,7 +80,7 @@
#define KINETIS_FTM_SWOCTRL_OFFSET 0x0094 /* FTM Software Output Control */
#define KINETIS_FTM_PWMLOAD_OFFSET 0x0098 /* FTM PWM Load */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_FTM0_SC (KINETIS_FTM0_BASE+KINETIS_FTM_SC_OFFSET)
#define KINETIS_FTM0_CNT (KINETIS_FTM0_BASE+KINETIS_FTM_CNT_OFFSET)
@@ -257,7 +258,7 @@
#define KINETIS_FTM3_SWOCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_SWOCTRL_OFFSET)
#define KINETIS_FTM3_PWMLOAD (KINETIS_FTM3_BASE+KINETIS_FTM_PWMLOAD_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* Status and Control */
@@ -277,10 +278,12 @@
# define FTM_SC_CLKS_SYSCLK (1 << FTM_SC_CLKS_SHIFT) /* System clock */
# define FTM_SC_CLKS_FIXED (2 << FTM_SC_CLKS_SHIFT) /* Fixed frequency clock */
# define FTM_SC_CLKS_EXTCLK (3 << FTM_SC_CLKS_SHIFT) /* External clock */
#define FTM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */
#define FTM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */
#define FTM_SC_TOF (1 << 7) /* Bit 7: Timer Overflow Flag */
/* Bits 8-31: Reserved */
/* Counter */
#define FTM_CNT_SHIFT (0) /* Bits 0-15: Counter value */
@@ -304,20 +307,23 @@
#define FTM_CSC_CHIE (1 << 6) /* Bit 6: Channel Interrupt Enable */
#define FTM_CSC_CHF (1 << 7) /* Bit 7: Channel Flag */
/* Bits 8-31: Reserved */
/* Channel (n) Value */
#define FTM_CV_SHIFT (0) /* Bits 0-15: Channel Value */
#define FTM_CV_MASK (0xffff << FTM_CV_SHIFT)
/* Bits 16-31: Reserved */
/* Counter Initial Value */
#define FTM_CNTIN_SHIFT (0) /* Bits 0-15: Initial Value of the FTM Counter */
#define FTM_CNTIN_MASK (0xffff << FTM_CNTIN_SHIFT)
/* Bits 16-31: Reserved */
/* Capture and Compare Status */
#define FTM_STATUS(n) (1 << (n)) /* Channel (n) Flag, n=0..7 */
/* Bits 8-31: Reserved */
/* Bits 8-31: Reserved */
/* Features Mode Selection */
@@ -332,8 +338,10 @@
# define FTM_MODE_FAULTM_EVEN (1 << FTM_MODE_FAULTM_SHIFT) /* Enable even channels, manual fault clearing */
# define FTM_MODE_FAULTM_MANUAL (2 << FTM_MODE_FAULTM_SHIFT) /* Enable all channels, manual fault clearing */
# define FTM_MODE_FAULTM_AUTO (3 << FTM_MODE_FAULTM_SHIFT) /* Enable all channels, automatic fault clearing */
#define FTM_MODE_FAULTIE (1 << 7) /* Bit 7: Fault Interrupt Enable */
/* Bits 8-31: Reserved */
/* Synchronization */
#define FTM_SYNC_CNTMIN (1 << 0) /* Bit 0: Minimum loading point enable */
@@ -345,14 +353,17 @@
#define FTM_SYNC_TRIG2 (1 << 6) /* Bit 6: PWM Synchronization Hardware Trigger 2 */
#define FTM_SYNC_SWSYNC (1 << 7) /* Bit 7: PWM Synchronization Software Trigger */
/* Bits 8-31: Reserved */
/* Initial State for Channels Output */
#define FTM_OUTINIT(n) (1 << (n)) /* Channel (n) Output Initialization Value, n=0..7 */
/* Bits 8-31: Reserved */
/* Bits 8-31: Reserved */
/* Output Mask */
#define FTM_OUTMASK(n) (1 << (n)) /* Channel (n) Output Mask, n=0..7 */
/* Bits 8-31: Reserved */
/* Bits 8-31: Reserved */
/* Function for Linked Channels */
#define FTM_COMBINE_COMBINE0 (1 << 0) /* Bit 0: Combine Channels for n = 0 */
@@ -387,6 +398,7 @@
#define FTM_COMBINE_SYNCEN3 (1 << 29) /* Bit 29: Synchronization Enable for n = 6 */
#define FTM_COMBINE_FAULTEN3 (1 << 30) /* Bit 30: Fault Control Enable for n = 6 */
/* Bit 31: Reserved */
/* Deadtime Insertion Control */
#define FTM_DEADTIME_DTVAL_SHIFT (0) /* Bits 0-5: Deadtime Value */
@@ -397,6 +409,7 @@
# define FTM_DEADTIME_DTPS_DIV4 (2 << FTM_DEADTIME_DTPS_SHIFT)
# define FTM_DEADTIME_DTPS_DIV16 (3 << FTM_DEADTIME_DTPS_SHIFT)
/* Bits 8-31: Reserved */
/* FTM External Trigger */
#define FTM_EXTTRIG_CH2TRIG (1 << 0) /* Bit 0: Channel 2 Trigger Enable */
@@ -408,10 +421,11 @@
#define FTM_EXTTRIG_INITTRIGEN (1 << 6) /* Bit 6: Initialization Trigger Enable */
#define FTM_EXTTRIG_TRIGF (1 << 7) /* Bit 7: Channel Trigger Flag */
/* Bits 8-31: Reserved */
/* Channels Polarity */
#define FTM_POL(n) (1 << (n)) /* Channel (n) Polarity, n=0..7 */
/* Bits 8-31: Reserved */
/* Bits 8-31: Reserved */
/* Fault Mode Status */
@@ -424,6 +438,7 @@
#define FTM_FMS_WPEN (1 << 6) /* Bit 6: Write Protection Enable */
#define FTM_FMS_FAULTF (1 << 7) /* Bit 7: Fault Detection Flag */
/* Bits 8-31: Reserved */
/* Input Capture Filter Control */
#define FTM_FILTER_CH0FVAL_SHIFT (0) /* Bits 0-3: Channel 0 Input Filter */
@@ -435,6 +450,7 @@
#define FTM_FILTER_CH3FVAL_SHIFT (12) /* Bits 12-15: Channel 3 Input Filter */
#define FTM_FILTER_CH3FVAL_MASK (15 << FTM_FILTER_CH3FVAL_SHIFT)
/* Bits 16-31: Reserved */
/* Fault Control */
#define FTM_FLTCTRL_FAULT0EN (1 << 0) /* Bit 0: Fault Input 0 Enable */
@@ -448,6 +464,7 @@
#define FTM_FLTCTRL_FFVAL_SHIFT (8) /* Bits 8-11: Fault Input Filter */
#define FTM_FLTCTRL_FFVAL_MASK (15 << FTM_FLTCTRL_FFVAL_SHIFT)
/* Bits 12-31: Reserved */
/* Quadrature Decoder Control and Status */
#define FTM_QDCTRL_QUADEN (1 << 0) /* Bit 0: Quadrature Decoder Mode Enable */
@@ -459,6 +476,7 @@
#define FTM_QDCTRL_PHBFLTREN (1 << 6) /* Bit 6: Phase B Input Filter Enable */
#define FTM_QDCTRL_PHAFLTREN (1 << 7) /* Bit 7: Phase A Input Filter Enable */
/* Bits 8-31: Reserved */
/* Configuration */
#define FTM_CONF_NUMTOF_SHIFT (0) /* Bits 0-4: TOF Frequency */
@@ -470,6 +488,7 @@
#define FTM_CONF_GTBEEN (1 << 9) /* Bit 9: Global time base enable */
#define FTM_CONF_GTBEOUT (1 << 10) /* Bit 10: Global time base output */
/* Bits 11-31: Reserved */
/* FTM Fault Input Polarity */
#define FTM_FLTPOL_FLT0POL (1 << 0) /* Bit 0: Fault Input 0 Polarity */
@@ -477,6 +496,7 @@
#define FTM_FLTPOL_FLT2POL (1 << 2) /* Bit 2: Fault Input 2 Polarity */
#define FTM_FLTPOL_FLT3POL (1 << 3) /* Bit 3: Fault Input 3 Polarity */
/* Bits 4-31: Reserved */
/* Synchronization Configuration */
#define FTM_SYNCONF_HWTRIGMODE (1 << 0) /* Bit 0: Hardware Trigger Mode */
@@ -499,6 +519,7 @@
#define FTM_SYNCONF_HWINVC (1 << 19) /* Bit 19: Inverting control synchronization (H/W) */
#define FTM_SYNCONF_HWSOC (1 << 20) /* Bit 20: Software output control synchronization (H/W) */
/* Bits 21-31: Reserved */
/* FTM Inverting Control */
#define FTM_INVCTRL_INV0EN (1 << 0) /* Bit 0: Pair Channels 0 Inverting Enable */
@@ -506,9 +527,11 @@
#define FTM_INVCTRL_INV2EN (1 << 2) /* Bit 2: Pair Channels 2 Inverting Enable */
#define FTM_INVCTRL_INV3EN (1 << 3) /* Bit 3: Pair Channels 3 Inverting Enable */
/* Bits 4-31: Reserved */
/* FTM Software Output Control */
#define FTM_SWOCTRL_CHOC(n) (1 << (n)) /* Bits 0-7: Channel (n) Software Output Control Enable */
#define FTM_SWOCTRL_CH0OC (1 << 0) /* Bit 0: Channel 0 Software Output Control Enable */
#define FTM_SWOCTRL_CH1OC (1 << 1) /* Bit 1: Channel 1 Software Output Control Enable */
#define FTM_SWOCTRL_CH2OC (1 << 2) /* Bit 2: Channel 2 Software Output Control Enable */
@@ -517,7 +540,9 @@
#define FTM_SWOCTRL_CH5OC (1 << 5) /* Bit 5: Channel 5 Software Output Control Enable */
#define FTM_SWOCTRL_CH6OC (1 << 6) /* Bit 6: Channel 6 Software Output Control Enable */
#define FTM_SWOCTRL_CH7OC (1 << 7) /* Bit 7: Channel 7 Software Output Control Enable */
#define FTM_SWOCTRL_CHOCV(n) (1 << ((n)+8)) /* Bits 8-15: Channel (n) Software Output Control Value */
#define FTM_SWOCTRL_CH0OCV (1 << 8) /* Bit 8: Channel 0 Software Output Control Value */
#define FTM_SWOCTRL_CH1OCV (1 << 9) /* Bit 9: Channel 1 Software Output Control Value */
#define FTM_SWOCTRL_CH2OCV (1 << 10) /* Bit 10: Channel 2 Software Output Control Value */
@@ -527,6 +552,7 @@
#define FTM_SWOCTRL_CH6OCV (1 << 14) /* Bit 14: Channel 6 Software Output Control Value */
#define FTM_SWOCTRL_CH7OCV (1 << 15) /* Bit 15: Channel 7 Software Output Control Value */
/* Bits 16-31: Reserved */
/* FTM PWM Load */
#define FTM_PWMLOAD_CHSEL(n) (1 << (n)) /* Bits 0-7: Channel (n) Select */
@@ -542,16 +568,16 @@
#define FTM_PWMLOAD_LDOK (1 << 9) /* Bit 9: Load Enable */
/* Bits 10-31: Reserved */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H */
arch/arm/src/kinetis/hardware/kinetis_gpio.h
+16 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output Register */
#define KINETIS_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output Register */
@@ -42,7 +42,7 @@
#define KINETIS_GPIO_PDIR_OFFSET 0x0010 /* Port Data Input Register */
#define KINETIS_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_GPIO_PDOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PDOR_OFFSET)
#define KINETIS_GPIO_PSOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PSOR_OFFSET)
@@ -86,7 +86,7 @@
#define KINETIS_GPIOE_PDIR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDIR_OFFSET)
#define KINETIS_GPIOE_PDDR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDDR_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Port Data Output Register */
@@ -112,16 +112,16 @@
#define GPIO_PDDR(n) (1 << (n))
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H */
arch/arm/src/kinetis/hardware/kinetis_i2c.h
+25 -19
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_I2C_A1_OFFSET 0x0000 /* I2C Address Register 1 */
#define KINETIS_I2C_F_OFFSET 0x0001 /* I2C Frequency Divider register */
@@ -48,7 +48,7 @@
#define KINETIS_I2C_SLTH_OFFSET 0x000a /* I2C SCL Low Timeout Register High */
#define KINETIS_I2C_SLTL_OFFSET 0x000b /* I2C SCL Low Timeout Register Low */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_I2C0_A1 (KINETIS_I2C0_BASE+KINETIS_I2C_A1_OFFSET)
#define KINETIS_I2C0_F (KINETIS_I2C0_BASE+KINETIS_I2C_F_OFFSET)
@@ -93,9 +93,10 @@
# define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET)
#endif
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* I2C Address Register 1 (8-bit) */
/* Bit 0: Reserved */
#define I2C_A1_SHIFT (1) /* Bits 1-7: Address */
#define I2C_A1_MASK (0x7f << I2C_A1_SHIFT)
@@ -111,8 +112,9 @@
# define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT)
# define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT)
/* From Table 51-54. I2C divider and hold values. Duplicate divider values differ in hold
* times. Refer to the Table 51-54. in the K64 Sub-Family Reference Manual.
/* From Table 51-54. I2C divider and hold values.
* Duplicate divider values differ in hold times.
* Refer to the Table 51-54. in the K64 Sub-Family Reference Manual.
*/
#define I2C_F_DIV20 ((uint8_t)0x00)
@@ -243,6 +245,7 @@
#endif
/* I2C Range Address register (8-bit) */
/* Bit 0: Reserved */
#define I2C_RA_SHIFT (1) /* Bits 1-7: Range slave address */
#define I2C_RA_MASK (0x7f << I2C_RA_SHIFT)
@@ -259,22 +262,25 @@
#define I2C_SMB_FACK (1 << 7) /* Bit 7: Fast NACK/ACK enable */
/* I2C Address Register 2 (8-bit) */
/* Bit 0: Reserved */
#define I2C_A2_SHIFT (1) /* Bits 1-7: SMBus address */
#define I2C_A2_MASK (0x7f << I2C_A2_SHIFT)
/* I2C SCL Low Timeout Register High/Low (16-bit data in two 8-bit registers) */
/* I2C SCL Low Timeout Register High/Low
* (16-bit data in two 8-bit registers)
*/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H */
arch/arm/src/kinetis/hardware/kinetis_i2s.h
+45 -20
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_i2s.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_I2S_TX0_OFFSET 0x000 /* I2S Transmit Data Registers 0 */
#define KINETIS_I2S_TX1_OFFSET 0x004 /* I2S Transmit Data Registers 1 */
@@ -57,7 +57,7 @@
#define KINETIS_I2S_ACCEN_OFFSET 0x054 /* I2S AC97 Channel Enable Register */
#define KINETIS_I2S_ACCDIS_OFFSET 0x058 /* I2S AC97 Channel Disable Register */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_I2S0_TX0 (KINETIS_I2S0_BASE+KINETIS_I2S_TX0_OFFSET)
#define KINETIS_I2S0_TX1 (KINETIS_I2S0_BASE+KINETIS_I2S_TX1_OFFSET)
@@ -81,9 +81,11 @@
#define KINETIS_I2S0_ACCEN (KINETIS_I2S0_BASE+KINETIS_I2S_ACCEN_OFFSET)
#define KINETIS_I2S0_ACCDIS (KINETIS_I2S0_BASE+KINETIS_I2S_ACCDIS_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* I2S Transmit Data Registers 0/1 and I2S Receive Data Registers 0/1: 32-bit I2S data */
/* I2S Transmit Data Registers 0/1 and
* I2S Receive Data Registers 0/1: 32-bit I2S data
*/
/* I2S Control Register */
@@ -97,6 +99,7 @@
# define I2S_CR_I2SMODE_NORMAL (0 << I2S_CR_I2SMODE_SHIFT) /* Normal mode */
# define I2S_CR_I2SMODE_MASTER (1 << I2S_CR_I2SMODE_SHIFT) /* I2S master mode */
# define I2S_CR_I2SMODE_SLAVE (2 << I2S_CR_I2SMODE_SHIFT) /* I2S slave mode */
#define I2S_CR_SYSCLKEN (1 << 7) /* Bit 7: System Clock (Oversampling Clock) Enable */
#define I2S_CR_TCHEN (1 << 8) /* Bit 8: Two-Channel Operation Enable */
#define I2S_CR_CLKIST (1 << 9) /* Bit 9: Clock Idle */
@@ -104,7 +107,10 @@
#define I2S_CR_RFRCLKDIS (1 << 11) /* Bit 11: Receive Frame Clock Disable */
#define I2S_CR_SYNCTXFS (1 << 12) /* Bit 12: CR[TE] latched with FS occurrence */
/* Bits 13-31: Reserved */
/* I2S Interrupt Status Register and I2S Interrupt Enable Register common bit definitions */
/* I2S Interrupt Status Register and I2S Interrupt Enable Register
* common bit definitions
*/
#define I2S_INT_TFE0 (1 << 0) /* Bit 0: Transmit FIFO Empty 0 */
#define I2S_INT_TFE1 (1 << 1) /* Bit 1: Transmit FIFO Empty 1 */
@@ -129,15 +135,23 @@
#define I2S_INT_TRFC (1 << 23) /* Bit 23: Transmit Frame Complete */
#define I2S_INT_RFRC (1 << 24) /* Bit 24: Receive Frame Complete */
/* Bits 25-31: Reserved */
/* I2S Interrupt Status Register (see common definitions above) */
/* I2S Interrupt Enable Register (see common definitions above and unique definitions below)*/
/* Bits 0-18: See common definitions above */
/* I2S Interrupt Enable Register
* (see common definitions above and unique definitions below)
*/
/* Bits 0-18:
* See common definitions above
*/
#define I2S_IER_TIE (1 << 19) /* Bit 19: Transmit Interrupt Enable */
#define I2S_IER_TDMAE (1 << 20) /* Bit 20: Transmit DMA Enable */
#define I2S_IER_RIE (1 << 21) /* Bit 21: Receive Interrupt Enable */
#define I2S_IER_RDMAE (1 << 22) /* Bit 22: Receive DMA Enable */
/* Bits 23-24: See common definitions above */
/* Bits 25-31: Reserved */
/* I2S Transmit Configuration Register */
#define I2S_TCR_TEFS (1 << 0) /* Bit 0: Transmit Early Frame Sync */
@@ -151,6 +165,7 @@
#define I2S_TCR_TFEN1 (1 << 8) /* Bit 8: Transmit FIFO Enable 1 */
#define I2S_TCR_TXBIT0 (1 << 9) /* Bit 9: Transmit Bit 0 */
/* Bits 10-31: Reserved */
/* I2S Receive Configuration Register */
#define I2S_RCR_REFS (1 << 0) /* Bit 0: Receive Early Frame Sync */
@@ -165,6 +180,7 @@
#define I2S_RCR_RXBIT0 (1 << 9) /* Bit 9: Receive Bit 0 */
#define I2S_RCR_RXEXT (1 << 10) /* Bit 10: Receive Data Extension */
/* Bits 11-31: Reserved */
/* I2S Transmit Clock Control Registers */
#define I2S_TCCR_PM_SHIFT (0) /* Bits 0-7: Prescaler Modulus Select */
@@ -184,6 +200,7 @@
#define I2S_TCCR_PSR (1 << 17) /* Bit 17: Prescaler Range */
#define I2S_TCCR_DIV2 (1 << 18) /* Bit 18: Divide By 2 */
/* Bits 19-31: Reserved */
/* I2S Receive Clock Control Registers */
#define I2S_RCCR_PM_SHIFT (0) /* Bits 0-7: Prescaler Modulus Select */
@@ -203,6 +220,7 @@
#define I2S_RCCR_PSR (1 << 17) /* Bit 17: Prescaler Range */
#define I2S_RCCR_DIV2 (1 << 18) /* Bit 18: Divide By 2 */
/* Bits 19-31: Reserved */
/* I2S FIFO Control/Status Register */
#define I2S_FCSR_TFWM0_SHIFT (0) /* Bits 0-3: Transmit FIFO Empty WaterMark 0 */
@@ -232,22 +250,27 @@
#define I2S_ACNT_FRDIV_SHIFT (5) /* Bits 5-10: Frame Rate Divider */
#define I2S_ACNT_FRDIV_MASK (63 << I2S_ACNT_FRDIV_SHIFT)
/* Bits 11-31: Reserved */
/* I2S AC97 Command Address Register */
#define I2S_ACADD_ACADD_SHIFT (0) /* Bits 0-18: AC97 Command Address */
#define I2S_ACADD_ACADD_MASK (0x7ffff << I2S_ACADD_ACADD_SHIFT)
/* Bits 19-31: Reserved */
/* I2S AC97 Command Data Register */
#define I2S_ACDAT_ACADD_SHIFT (0) /* Bits 0-18: AC97 Command Data */
#define I2S_ACDAT_ACADD_MASK (0x7ffff << I2S_ACDAT_ACADD_SHIFT)
/* Bits 19-31: Reserved */
/* I2S AC97 Tag Register */
#define I2S_ATAG_ACADD_SHIFT (0) /* Bits 0-15: AC97 Tag Value */
#define I2S_ATAG_ACADD_MASK (0xffff << I2S_ACDAT_ACADD_SHIFT)
/* Bits 16-31: Reserved */
/* I2S Transmit Time Slot Mask Register (32-bit Transmit Mask) */
/* I2S Receive Time Slot Mask Register (32-bit Receive Mask) */
/* I2S AC97 Channel Status Register */
@@ -255,11 +278,13 @@
#define I2S_ACCST_ACCST_SHIFT (0) /* Bits 0-9: AC97 Channel Status */
#define I2S_ACCST_ACCST_MASK (0x3ff << I2S_ACCST_ACCST_SHIFT)
/* Bits 10-31: Reserved */
/* I2S AC97 Channel Enable Register */
#define I2S_ACCEN_ACCST_SHIFT (0) /* Bits 0-9: AC97 Channel Enable */
#define I2S_ACCEN_ACCST_MASK (0x3ff << I2S_ACCEN_ACCST_SHIFT)
/* Bits 10-31: Reserved */
/* I2S AC97 Channel Disable Register */
#define I2S__
@@ -267,16 +292,16 @@
#define I2S_ACCDIS_ACCST_MASK (0x3ff << I2S_ACCEN_ACCST_SHIFT)
/* Bits 10-31: Reserved */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H */
arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h
+23 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */
@@ -152,7 +152,7 @@
#define KINETIS_FMC_DATAW3S7U_OFFSET 0x02f8 /* Cache Data Storage (upper word) */
#define KINETIS_FMC_DATAW3S7L_OFFSET 0x02fc /* Cache Data Storage (lower word) */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET)
#define KINETIS_FMC_PFB0CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB0CR_OFFSET)
@@ -271,9 +271,10 @@
#define KINETIS_FMC_DATAW3S7U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S7U_OFFSET)
#define KINETIS_FMC_DATAW3S7L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S7L_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Flash Access Protection Register */
/* Access protection bits (all masters) */
#define FMC_PFAPR_NONE 0 /* No access may be performed by this master */
@@ -305,7 +306,9 @@
#define FMC_PFAPR_M5PFD (1 << 21) /* Bit 21: Master 5 Prefetch Disable */
#define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */
#define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */
/* Bits 24-31: Reserved */
/* Flash Bank 0 Control Register */
#define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */
@@ -318,11 +321,13 @@
# define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */
# define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */
# define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */
/* Bits 8-16: Reserved */
#define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */
#define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT)
# define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */
# define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */
#define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */
#define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */
#define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT)
@@ -343,6 +348,7 @@
#define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT)
# define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */
# define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */
/* Bits 19-27: Reserved */
#define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */
#define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT)
@@ -353,22 +359,23 @@
/* Bits 1-5: Reserved */
#define FMC_TAGVD_TAG_SHIFT (6) /* Bits 6-18: 13-bit tag for cache entry */
#define FMC_TAGVD_TAG_MASK (0x1fff << FMC_TAGVD_TAG_SHIFT)
/* Bits 19-31: Reserved */
/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7.
* 64-bit data in two 32-bit registers.
*/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H */
arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h
+22 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */
@@ -137,7 +137,7 @@
#define KINETIS_MPU_RGDAAC14_OFFSET 0x0838 /* Region Descriptor Alternate Access Control 14 */
#define KINETIS_MPU_RGDAAC15_OFFSET 0x083c /* Region Descriptor Alternate Access Control 15 */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET)
@@ -241,7 +241,7 @@
#define KINETIS_MPU_RGDAAC14 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC14_OFFSET)
#define KINETIS_MPU_RGDAAC15 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC15_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* Control/Error Status Register */
@@ -252,6 +252,7 @@
# define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */
# define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */
# define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */
#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */
#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT)
#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */
@@ -260,6 +261,7 @@
#define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */
#define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT)
# define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */
# define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */
# define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */
# define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */
@@ -277,6 +279,7 @@
# define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */
# define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */
# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */
#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */
#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT)
/* Bits 8-15: Reserved */
@@ -284,11 +287,13 @@
#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT)
/* Region Descriptor n, Word 0 */
/* Bits 0-4: Reserved */
#define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */
#define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0)
/* Region Descriptor n, Word 1 */
/* Bits 0-4: Reserved */
#define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */
#define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0)
@@ -337,6 +342,7 @@
#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */
/* Bits 1-31: Reserved */
/* Region Descriptor Alternate Access Control n */
#define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */
@@ -368,16 +374,16 @@
#define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */
#define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H */
arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h
+24 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,12 @@
#ifdef KINETIS_K20
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Memory Map ***************************************************************/
/* Memory Map ***********************************************************************/
/* K20 Family
*
* The memory map for the following parts is defined in Freescale document
@@ -49,13 +50,16 @@
# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
#endif
/* 0x18000000 * –0x1bffffff Reserved */
#define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * –0x21ffffff Reserved */
#define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * –0x3fffffff Reserved */
#define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
@@ -63,15 +67,18 @@
* bridge 1 (AIPS-Lite1) */
#define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * –0x41ffffff Reserved */
#define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * –0xdfffffff Reserved */
#define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
/* 0xe0100000 * –0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
/* Peripheral Bridge 0 Memory Map *******************************************/
#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
@@ -121,7 +128,7 @@
#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
/* Peripheral Bridge 1 Memory Map *******************************************/
#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
@@ -139,7 +146,7 @@
#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
/* Private Peripheral Bus (PPB) Memory Map **********************************/
#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
@@ -149,17 +156,17 @@
#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K20 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H */
arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h
+14 -14
View File
@@ -1,4 +1,4 @@
/******************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
******************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H
/******************************************************************************************
/****************************************************************************
* Included Files
******************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,11 @@
#ifdef KINETIS_K28
/******************************************************************************************
/****************************************************************************
* Pre-processor Definitions
******************************************************************************************/
****************************************************************************/
/* Memory Map *****************************************************************************/
/* Memory Map ***************************************************************/
/* K28 Family
*
@@ -90,7 +90,7 @@
* External Peripheral - Not executable) */
# define KINETIS_PERIPH_BASE 0xe0000000 /* Private peripherals */
/* Peripheral Bridge 0 Memory Map *********************************************************/
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
@@ -147,7 +147,7 @@
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
/* Peripheral Bridge 1 Memory Map *********************************************************/
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGA_BASE 0x400a0000 /* True Random Number Generator (TRNG) */
@@ -185,7 +185,7 @@
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ************************************************/
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
@@ -202,10 +202,10 @@
* of debug components */
#else
/* The memory map for other parts is defined in other documents and may or may not
* be the same as above (the family members are all very similar) This error just
* means that you have to look at the document and determine for yourself if the
* memory map is the same.
/* The memory map for other parts is defined in other documents and may or
* may not be the same as above (the family members are all very similar)
* This error just means that you have to look at the document and
* determine for yourself if the memory map is the same.
*/
# error "No memory map for this K28 part"
arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h
+21 -20
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,19 +31,20 @@
#ifdef KINETIS_K28
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* In most cases, there are alternative configurations for various pins. Those alternative
* pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
* the board.h file must select the correct pin configuration for the board by defining a pin
/* In most cases, there are alternative configurations for various pins.
* Those alternative pins are labeled with a suffix like _1, _2, etc. in
* order to distinguish them. Logic in the board.h file must select the
* correct pin configuration for the board by defining a pin
* configuration (with no suffix) that maps to the correct alternative.
*
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in the initial version of this file.
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in the initial version of this file.
*/
/* ADC */
@@ -802,17 +803,17 @@
#define PIN_USB1_ID (PIN_ALT7 | PIN_PORTA | PIN11)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K28 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H */
arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
+23 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,12 @@
#ifdef KINETIS_K40
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Memory Map ***************************************************************/
/* Memory Map ***********************************************************************/
/* K40 Family
*
* The memory map for the following parts is defined in Freescale document
@@ -53,8 +54,10 @@
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
@@ -62,10 +65,12 @@
* bridge 1 (AIPS-Lite1) */
#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
#define KINETIS_FLEXBUS_WBBASE 0x60000000 /* -0x7fffffff FlexBus (External Memory -
* Write-back) */
@@ -74,9 +79,10 @@
#define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* -0xdfffffff FlexBus (External Memory -
* Non-executable) */
#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
/* Peripheral Bridge 0 Memory Map *******************************************/
#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
@@ -131,7 +137,7 @@
#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
/* Peripheral Bridge 1 Memory Map *******************************************/
#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
@@ -155,7 +161,7 @@
#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
/* Private Peripheral Bus (PPB) Memory Map **********************************/
#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
@@ -168,17 +174,17 @@
#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K40 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H */
arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h
+24 -18
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,12 @@
#ifdef KINETIS_K60
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Memory Map ***************************************************************/
/* Memory Map ***********************************************************************/
/* K60 Family
*
* The memory map for the following parts is defined in Freescale document
@@ -53,25 +54,30 @@
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
#define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
/* Peripheral Bridge 0 Memory Map *******************************************/
#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
@@ -126,7 +132,7 @@
#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
/* Peripheral Bridge 1 Memory Map *******************************************/
#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
#define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
@@ -151,7 +157,7 @@
#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
/* Private Peripheral Bus (PPB) Memory Map **********************************/
#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
@@ -165,17 +171,17 @@
#define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K60 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H */
arch/arm/src/kinetis/hardware/kinetis_k64fmc.h
+21 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k64fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */
@@ -104,7 +104,7 @@
#define KINETIS_FMC_DATAW3S3U_OFFSET 0x0278 /* Cache Data Storage (upper word) */
#define KINETIS_FMC_DATAW3S3L_OFFSET 0x027c /* Cache Data Storage (lower word) */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET)
#define KINETIS_FMC_PFB0CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB0CR_OFFSET)
@@ -175,9 +175,10 @@
#define KINETIS_FMC_DATAW3S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3U_OFFSET)
#define KINETIS_FMC_DATAW3S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3L_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Flash Access Protection Register */
/* Access protection bits (all masters) */
#define FMC_PFAPR_NONE 0 /* No access may be performed by this master */
@@ -210,6 +211,7 @@
#define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */
#define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */
/* Bits 24-31: Reserved */
/* Flash Bank 0 Control Register */
#define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */
@@ -222,11 +224,13 @@
# define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */
# define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */
# define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */
/* Bits 8-16: Reserved */
#define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */
#define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT)
# define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */
# define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */
#define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */
#define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */
#define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT)
@@ -247,6 +251,7 @@
#define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT)
# define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */
# define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */
/* Bits 19-27: Reserved */
#define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */
#define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT)
@@ -263,16 +268,16 @@
* 64-bit data in two 32-bit registers.
*/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H */
arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
+27 -21
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,12 @@
#ifdef KINETIS_K64
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Memory Map ***************************************************************/
/* Memory Map ***********************************************************************/
/* K64 Family
*
* The memory map for the following parts is defined in NXP document
@@ -58,8 +59,10 @@
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
@@ -67,16 +70,19 @@
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
@@ -132,7 +138,7 @@
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
@@ -158,7 +164,7 @@
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
@@ -173,26 +179,26 @@
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or may not
* be the same as above (the family members are all very similar) This error just
* means that you have to look at the document and determine for yourself if the
* memory map is the same.
/* The memory map for other parts is defined in other documents and may or
* may not be the same as above (the family members are all very similar)
* This error just means that you have to look at the document and
* determine for yourself if the memory map is the same.
*/
# error "No memory map for this K64 part"
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K64 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H */
arch/arm/src/kinetis/hardware/kinetis_llwu.h
+28 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_llwu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_LLWU_PE1_OFFSET 0x0000 /* LLWU Pin Enable 1 Register */
#define KINETIS_LLWU_PE2_OFFSET 0x0001 /* LLWU Pin Enable 2 Register */
@@ -45,7 +45,7 @@
#define KINETIS_LLWU_F3_OFFSET 0x0007 /* LLWU Flag 3 Register */
#define KINETIS_LLWU_CS_OFFSET 0x0008 /* LLWU Control and Status Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_LLWU_PE1 (KINETIS_LLWU_BASE+KINETIS_LLWU_PE1_OFFSET)
#define KINETIS_LLWU_PE2 (KINETIS_LLWU_BASE+KINETIS_LLWU_PE2_OFFSET)
@@ -57,7 +57,7 @@
#define KINETIS_LLWU_F3 (KINETIS_LLWU_BASE+KINETIS_LLWU_F3_OFFSET)
#define KINETIS_LLWU_CS (KINETIS_LLWU_BASE+KINETIS_LLWU_CS_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* LLWU Pin Enable 1 Register */
@@ -67,18 +67,21 @@
# define LLWU_PE1_WUPE0_RISING (1 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE1_WUPE0_FALLING (2 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE1_WUPE0_BOTH (3 << LLWU_PE1_WUPE0_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE1_WUPE1_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P1 */
#define LLWU_PE1_WUPE1_MASK (3 << LLWU_PE1_WUPE1_SHIFT)
# define LLWU_PE1_WUPE1_DISABLED (0 << LLWU_PE1_WUPE1_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE1_WUPE1_RISING (1 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE1_WUPE1_FALLING (2 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE1_WUPE1_BOTH (3 << LLWU_PE1_WUPE1_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE1_WUPE2_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P2 */
#define LLWU_PE1_WUPE2_MASK (3 << LLWU_PE1_WUPE2_SHIFT)
# define LLWU_PE1_WUPE2_DISABLED (0 << LLWU_PE1_WUPE2_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE1_WUPE2_RISING (1 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE1_WUPE2_FALLING (2 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE1_WUPE2_BOTH (3 << LLWU_PE1_WUPE2_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE1_WUPE3_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P3 */
#define LLWU_PE1_WUPE3_MASK (3 << LLWU_PE1_WUPE3_SHIFT)
# define LLWU_PE1_WUPE3_DISABLED (0 << LLWU_PE1_WUPE3_SHIFT) /* Ext input disabled as wakeup input */
@@ -94,18 +97,21 @@
# define LLWU_PE2_WUPE4_RISING (1 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE2_WUPE4_FALLING (2 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE2_WUPE4_BOTH (3 << LLWU_PE2_WUPE4_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE2_WUPE5_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P5 */
#define LLWU_PE2_WUPE5_MASK (3 << LLWU_PE2_WUPE5_SHIFT)
# define LLWU_PE2_WUPE5_DISABLED (0 << LLWU_PE2_WUPE5_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE2_WUPE5_RISING (1 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE2_WUPE5_FALLING (2 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE2_WUPE5_BOTH (3 << LLWU_PE2_WUPE5_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE2_WUPE6_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P6 */
#define LLWU_PE2_WUPE6_MASK (3 << LLWU_PE2_WUPE6_SHIFT)
# define LLWU_PE2_WUPE6_DISABLED (0 << LLWU_PE2_WUPE6_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE2_WUPE6_RISING (1 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE2_WUPE6_FALLING (2 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE2_WUPE6_BOTH (3 << LLWU_PE2_WUPE6_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE2_WUPE7_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P7 */
#define LLWU_PE2_WUPE7_MASK (3 << LLWU_PE2_WUPE7_SHIFT)
# define LLWU_PE2_WUPE7_DISABLED (0 << LLWU_PE2_WUPE7_SHIFT) /* Ext input disabled as wakeup input */
@@ -121,18 +127,21 @@
# define LLWU_PE3_WUPE8_RISING (1 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE3_WUPE8_FALLING (2 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE3_WUPE8_BOTH (3 << LLWU_PE3_WUPE8_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE3_WUPE9_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P9 */
#define LLWU_PE3_WUPE9_MASK (3 << LLWU_PE3_WUPE9_SHIFT)
# define LLWU_PE3_WUPE9_DISABLED (0 << LLWU_PE3_WUPE9_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE3_WUPE9_RISING (1 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE3_WUPE9_FALLING (2 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE3_WUPE9_BOTH (3 << LLWU_PE3_WUPE9_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE3_WUPE10_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P10 */
#define LLWU_PE3_WUPE10_MASK (3 << LLWU_PE3_WUPE10_SHIFT)
# define LLWU_PE3_WUPE10_DISABLED (0 << LLWU_PE3_WUPE10_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE3_WUPE10_RISING (1 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE3_WUPE10_FALLING (2 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE3_WUPE10_BOTH (3 << LLWU_PE3_WUPE10_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE3_WUPE11_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P11 */
#define LLWU_PE3_WUPE11_MASK (3 << LLWU_PE3_WUPE11_SHIFT)
# define LLWU_PE3_WUPE11_DISABLED (0 << LLWU_PE3_WUPE11_SHIFT) /* Ext input disabled as wakeup input */
@@ -148,18 +157,21 @@
# define LLWU_PE4_WUPE12_RISING (1 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE4_WUPE12_FALLING (2 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE4_WUPE12_BOTH (3 << LLWU_PE4_WUPE12_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE4_WUPE13_SHIFT (2) /* Bits 2-3: Wakeup Pin Enable for LLWU_P13 */
#define LLWU_PE4_WUPE13_MASK (3 << LLWU_PE4_WUPE13_SHIFT)
# define LLWU_PE4_WUPE13_DISABLED (0 << LLWU_PE4_WUPE13_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE4_WUPE13_RISING (1 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE4_WUPE13_FALLING (2 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE4_WUPE13_BOTH (3 << LLWU_PE4_WUPE13_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE4_WUPE14_SHIFT (4) /* Bits 4-5: Wakeup Pin Enable for LLWU_P14 */
#define LLWU_PE4_WUPE14_MASK (3 << LLWU_PE4_WUPE14_SHIFT)
# define LLWU_PE4_WUPE14_DISABLED (0 << LLWU_PE4_WUPE14_SHIFT) /* Ext input disabled as wakeup input */
# define LLWU_PE4_WUPE14_RISING (1 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for rising edge */
# define LLWU_PE4_WUPE14_FALLING (2 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for falling edge */
# define LLWU_PE4_WUPE14_BOTH (3 << LLWU_PE4_WUPE14_SHIFT) /* Ext input enabled for any change */
#define LLWU_PE4_WUPE15_SHIFT (6) /* Bits 6-7: Wakeup Pin Enable for LLWU_P15 */
#define LLWU_PE4_WUPE15_MASK (3 << LLWU_PE4_WUPE15_SHIFT)
# define LLWU_PE4_WUPE15_DISABLED (0 << LLWU_PE4_WUPE15_SHIFT) /* Ext input disabled as wakeup input */
@@ -224,16 +236,16 @@
#define LLWU_CS_FLTEP (1 << 1) /* Bit 1: Digital Filter on External Pin */
#define LLWU_CS_FLTR (1 << 0) /* Bit 0: Digital Filter on RESET Pin */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H */
arch/arm/src/kinetis/hardware/kinetis_lptmr.h
+22 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_lptmr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,31 +16,31 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_LPTMR_CSR_OFFSET 0x0000 /* Low Power Timer Control Status Register */
#define KINETIS_LPTMR_PSR_OFFSET 0x0004 /* Low Power Timer Prescale Register */
#define KINETIS_LPTMR_CMR_OFFSET 0x0008 /* Low Power Timer Compare Register */
#define KINETIS_LPTMR_CNR_OFFSET 0x000c /* Low Power Timer Counter Register */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_LPTMR0_CSR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_CSR_OFFSET)
#define KINETIS_LPTMR0_PSR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_PSR_OFFSET)
@@ -52,7 +52,7 @@
#define KINETIS_LPTMR1_CMR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CMR_OFFSET)
#define KINETIS_LPTMR1_CNR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CNR_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* Low Power Timer Control Status Register (32-bit) */
@@ -66,6 +66,7 @@
# define LPTMR_CSR_TPS_INPUT1 (1 << LPTMR_CSR_TPS_SHIFT) /* Pulse counter input 1 selected */
# define LPTMR_CSR_TPS_INPUT2 (2 << LPTMR_CSR_TPS_SHIFT) /* Pulse counter input 2 selected */
# define LPTMR_CSR_TPS_INPUT3 (3 << LPTMR_CSR_TPS_SHIFT) /* Pulse counter input 3 selected */
#define LPTMR_CSR_TIE (1 << 6) /* Bit 6: Timer Interrupt Enable */
#define LPTMR_CSR_TCF (1 << 7) /* Bit 7: Timer Compare Flag */
@@ -77,8 +78,10 @@
# define LPTMR_PSR_PCS_CLOCK (1 << LPTMR_PSR_PCS_SHIFT) /* Prescaler/glitch filter clock 1 */
# define LPTMR_PSR_PCS_CLOCK (2 << LPTMR_PSR_PCS_SHIFT) /* Prescaler/glitch filter clock 2 */
# define LPTMR_PSR_PCS_CLOCK (3 << LPTMR_PSR_PCS_SHIFT) /* Prescaler/glitch filter clock 3 */
#define LPTMR_PSR_PBYP (1 << 2) /* Bit 2: Prescaler Bypass */
#define LPTMR_PSR_PRESCALE_SHIFT (6) /* Bits 3-6: Prescale Value */
#define LPTMR_PSR_PRESCALE_MASK (15 << LPTMR_PSR_PRESCALE_SHIFT) /* Prescale divider: Glitch filter after: */
# define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=2 N/S */
# define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=4 2 edges */
@@ -96,28 +99,31 @@
# define LPTMR_PSR_PRESCALE_DIV16K (13 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=16384 8192 edges */
# define LPTMR_PSR_PRESCALE_DIV32K (14 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=32768 16384 edges */
# define LPTMR_PSR_PRESCALE_DIV64K (15 << LPTMR_PSR_PRESCALE_SHIFT) /* Divider=65536 32768 edges */
/* Bits 7-31: Reserved */
/* Low Power Timer Compare Register */
#define LPTMR_CMR_SHIFT (0) /* Bits 0-15: Compare Value */
#define LPTMR_CMR_MASK (0xffff << LPTMR_CMR_COMPARE_SHIFT)
/* Bits 16-31: Reserved */
/* Low Power Timer Counter Register */
#define LPTMR_CNR_SHIFT (0) /* Bits 0-15: Counter Value */
#define LPTMR_CNR_MASK (0xffff << LPTMR_CNR_COMPARE_SHIFT)
/* Bits 16-31: Reserved */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H */
arch/arm/src/kinetis/hardware/kinetis_mcm.h
+25 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_mcm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_MCM_PLASC_OFFSET 0x0008 /* Crossbar switch (AXBS) slave configuration */
#define KINETIS_MCM_PLAMC_OFFSET 0x000a /* Crossbar switch (AXBS) master configuration */
@@ -46,7 +46,7 @@
# define KINETIS_MCM_PID_OFFSET 0x0030 /* Process ID register */
#endif
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_MCM_PLASC (KINETIS_MCM_BASE+KINETIS_MCM_PLASC_OFFSET)
#define KINETIS_MCM_PLAMC (KINETIS_MCM_BASE+KINETIS_MCM_PLAMC_OFFSET)
@@ -59,7 +59,7 @@
# define KINETIS_MCM_PID (KINETIS_MCM_BASE+KINETIS_MCM_PID_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Crossbar switch (AXBS) slave configuration */
@@ -81,6 +81,7 @@
/* Bits 8-15: Reserved */
/* SRAM arbitration and protection */
/* Bits 0-23: Reserved */
#define MCM_SRAMAP_SRAMUAP_SHIFT (24) /* Bits 24-25: SRAM_U arbitration priority */
#define MCM_SRAMAP_SRAMUAP_MASK (3 << MCM_SRAMAP_SRAMUAP_SHIFT)
@@ -88,6 +89,7 @@
# define MCM_SRAMAP_SRAMUAP_SRR (1 << MCM_SRAMAP_SRAMUAP_SHIFT) /* Special round robin */
# define MCM_SRAMAP_SRAMUAP_FIXED1 (2 << MCM_SRAMAP_SRAMUAP_SHIFT) /* Fixed pri. Proc highest/backdoor lowest */
# define MCM_SRAMAP_SRAMUAP_FIXED2 (3 << MCM_SRAMAP_SRAMUAP_SHIFT) /* Fixed pri. Backdoor highest/proc lowest */
#define MCM_SRAMAP_SRAMUWP (1 << 26) /* Bit 26: SRAM_U write protect */
/* Bit 27: Reserved */
#define MCM_SRAMAP_SRAMLAP_SHIFT (28) /* Bits 28-29: SRAM_L arbitration priority */
@@ -96,13 +98,17 @@
# define MCM_SRAMAP_SRAMLAP_SRR (1 << MCM_SRAMAP_SRAMLAP_SHIFT) /* Special round robin */
# define MCM_SRAMAP_SRAMLAP_FIXED1 (2 << MCM_SRAMAP_SRAMLAP_SHIFT) /* Fixed pri. Proc highest/backdoor lowest */
# define MCM_SRAMAP_SRAMLAP_FIXED2 (3 << MCM_SRAMAP_SRAMLAP_SHIFT) /* Fixed pri. Backdoor highest/proc lowest */
#define MCM_SRAMAP_SRAMLWP (1 << 30) /* Bit 30: SRAM_L write protect */
/* Bit 31: Reserved */
/* Interrupt status register */
/* Bit 0: Reserved */
#define MCM_ISR_IRQ (1 << 1) /* Bit 1: Normal interrupt pending */
#define MCM_ISR_NMI (1 << 2) /* Bit 2: Non-maskable interrupt pending */
/* Bits 3-31: Reserved */
/* ETB counter control register */
#define MCM_ETBCC_CNTEN (1 << 0) /* Bit 0: Counter enable */
@@ -112,31 +118,34 @@
# define MCM_ETBCC_RSPT_INT (1 << MCM_ETBCC_RSPT_SHIFT) /* Normal interrupt when ETB count expires */
# define MCM_ETBCC_RSPT_NMI (2 << MCM_ETBCC_RSPT_SHIFT) /* NMI when ETB count expires */
# define MCM_ETBCC_RSPT_HALT (3 << MCM_ETBCC_RSPT_SHIFT) /* Debug halt when ETB count expires */
#define MCM_ETBCC_RLRQ (1 << 3) /* Bit 3: Reload request */
#define MCM_ETBCC_ETDIS (1 << 4) /* Bit 4: ETM-to-TPIU disable */
#define MCM_ETBCC_ITDIS (1 << 5) /* Bit 5: ITM-to-TPIU disable */
/* Bits 6-31: Reserved */
/* ETB reload register */
#define MCM_ETBRL_RELOAD_SHIFT (0) /* Bits 0-10: Byte count reload value */
#define MCM_ETBRL_RELOAD_MASK (0x7ff << MCM_ETBRL_RELOAD_SHIFT)
/* Bits 11-31: Reserved */
/* ETB counter value register */
#define MCM_ETBCNT_COUNTER_SHIFT (0) /* Bits 0-10: Byte count counter value */
#define MCM_ETBCNT_COUNTER_MASK (0x7ff << MCM_ETBCNT_COUNTER_SHIFT)
/* Bits 11-31: Reserved */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H */
arch/arm/src/kinetis/hardware/kinetis_memorymap.h
+15 -15
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
* by the logic in chip.h.
/* This file is just a wrapper around pin muxing header files for the Kinetis
* family selected by the logic in chip.h.
*/
#if defined(KINETIS_K20)
@@ -49,20 +49,20 @@
# error "No memory map for this Kinetis part"
#endif
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H */
arch/arm/src/kinetis/hardware/kinetis_mmcau.h
+19 -18
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_mmcau.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,11 @@
#if defined(KINETIS_NMMCAU) && KINETIS_NMMCAU > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_CAU_CASR_OFFSET 0x0000 /* Status Register */
#define KINETIS_CAU_CAA_OFFSET 0x0001 /* Accumulator */
@@ -53,7 +53,7 @@
# define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */
#endif
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_CAU_CASR (KINETIS_MMCAU_BASE+KINETIS_CAU_CASR_OFFSET)
#define KINETIS_CAU_CAA (KINETIS_MMCAU_BASE+KINETIS_CAU_CAA_OFFSET)
@@ -71,7 +71,7 @@
# define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Status Register */
@@ -81,10 +81,11 @@
#define CAU_CASR_VER_SHIFT (28) /* Bits 28-31: CAU version */
#define CAU_CASR_VER_MASK (15 << CAU_CASR_VER_SHIFT)
/* Accumulator (32-bit accumulated value)*/
/* Accumulator (32-bit accumulated value) */
/* General Purpose Register n (32-bit value used by CAU commands) */
/* CAU Commands *********************************************************************/
/* CAU Commands *************************************************************/
/* Bits 4-8 of 9-bit commands (bits 0-3 may be arguments of the command) */
@@ -112,17 +113,17 @@
#define CAU_CMD_SHS2 0x150 /* Secure Hash Shift 2 */
#define CAU_CMD_ILL 0x1f0 /* Illegal Command */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H */
arch/arm/src/kinetis/hardware/kinetis_mpu.h
+15 -15
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_mpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around MPU header files for the Kinetis family selected by the
* in chip.h.
/* This file is just a wrapper around MPU header files for the Kinetis family
* selected by the in chip.h.
*/
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
@@ -41,20 +41,20 @@
# error "No MPU definitions for this Kinetis part"
#endif
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H */
arch/arm/src/kinetis/hardware/kinetis_osc.h
+17 -16
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_osc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,34 +16,34 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_OSC_CR_OFFSET 0x0000 /* OSC Control Register */
#define KINETIS_OSC_DIV_OFFSET 0x0002 /* OSC CLock divider register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_OSC_CR (KINETIS_OSC_BASE+KINETIS_OSC_CR_OFFSET)
#define KINETIS_OSC_DIV (KINETIS_OSC_BASE+KINETIS_OSC_DIV_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* OSC Control Register (8-bit) */
@@ -57,6 +57,7 @@
#define OSC_CR_SC16P (1 << 0) /* Bit 0: Oscillator 16 pF Capacitor Load Configure */
/* OSC Control Register (8-bit) */
/* Bits 0-5: Reserved */
#define OSC_DIV_ERPS_SHIFT 6 /* Bits 6-7: ERCLK prescaler */
#define OSC_DIV_ERPS_MASK (3 << OSC_DIV_ERPS_SHIFT)
@@ -65,16 +66,16 @@
# define OSC_DIV_ERPS_DIV3 (2 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 4 */
# define OSC_DIV_ERPS_DIV8 (3 << OSC_DIV_ERPS_SHIFT) /* The divisor ratio is 8 */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H */
arch/arm/src/kinetis/hardware/kinetis_pdb.h
+28 -16
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_pdb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_PDB_SC_OFFSET 0x0000 /* Status and Control Register */
#define KINETIS_PDB_MOD_OFFSET 0x0004 /* Modulus Register */
@@ -41,6 +41,7 @@
#define KINETIS_PDB_IDLY_OFFSET 0x000c /* Interrupt Delay Register */
#define KINETIS_PDB_CH_OFFSET(n) (0x0010+(0x28*(n)) /* Channel n */
#define KINETIS_PDB_CHC1_OFFSET 0x0000 /* Channel n Control Register 1 */
#define KINETIS_PDB_CHS_OFFSET 0x0004 /* Channel n Status Register */
#define KINETIS_PDB_CHDLY0_OFFSET 0x0008 /* Channel n Delay 0 Register */
@@ -57,6 +58,7 @@
#define KINETIS_PDB_CH1DLY1_OFFSET 0x0044 /* Channel 1 Delay 1 Register */
#define KINETIS_PDB_INT_OFFSET(n) (0x0150+((n)<<3) /* DAC Interval n offset */
#define KINETIS_PDB_DACINTC_OFFSET 0x0000 /* DAC Interval Trigger n Control Register */
#define KINETIS_PDB_DACINT_OFFSET 0x0004 /* DAC Interval n Register */
@@ -73,7 +75,7 @@
# define KINETIS_PDB_PO2DLY_OFFSET 0x019c /* Pulse-Out 2 Delay Register */
#endif
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_PDB0_SC (KINETIS_PDB0_BASE+KINETIS_PDB_SC_OFFSET)
#define KINETIS_PDB0_MOD (KINETIS_PDB0_BASE+KINETIS_PDB_MOD_OFFSET)
@@ -113,7 +115,7 @@
# define KINETIS_PDB0_PO2DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO2DLY_OFFSET)
#endif
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* Status and Control Register */
@@ -147,6 +149,7 @@
# define PDB_SC_TRGSEL_TRGIN13 (13 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 3 */
# define PDB_SC_TRGSEL_TRGIN14 (14 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 4 */
# define PDB_SC_TRGSEL_TRGSW (15 << PDB_SC_TRGSEL_SHIFT) /* Software trigger */
#define PDB_SC_PRESCALER_SHIFT (12) /* Bits 12-14: Prescaler Divider Select */
#define PDB_SC_PRESCALER_MASK (7 << PDB_SC_PRESCALER_SHIFT)
# define PDB_SC_PRESCALER_DIVM (0 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / MULT */
@@ -157,6 +160,7 @@
# define PDB_SC_PRESCALER_DIV32M (5 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 32*MULT */
# define PDB_SC_PRESCALER_DIV64M (6 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 64*MULT */
# define PDB_SC_PRESCALER_DIV128M (7 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 128*MULT */
#define PDB_SC_DMAEN (1 << 15) /* Bit 15: DMA Enable */
#define PDB_SC_SWTRIG (1 << 16) /* Bit 16: Software Trigger */
#define PDB_SC_PDBEIE (1 << 17) /* Bit 17: PDB Sequence Error Interrupt Enable */
@@ -166,7 +170,9 @@
# define PDB_SC_LDMOD_PDBCNT (1 << PDB_SC_LDMOD_SHIFT) /* Load when the PDB counter = MOD */
# define PDB_SC_LDMOD_TRIGGER (2 << PDB_SC_LDMOD_SHIFT) /* Load when trigger input event */
# define PDB_SC_LDMOD_EITHER (3 << PDB_SC_LDMOD_SHIFT) /* Load when either occurs */
/* Bits 20-31: Reserved */
/* Modulus Register */
/* Bits 16-31: Reserved */
@@ -194,6 +200,7 @@
#define PDB_CHC1_BB_MASK (0xff << PDB_CHC1_BB_SHIFT)
# define PDB_CHC1_BB_CHAN(n) ((1 << (n)) << PDB_CHC1_BB_SHIFT)
/* Bits 24-31: Reserved */
/* Channel n Status Register */
#define PDB_CHS_ERR_SHIFT (0) /* Bits 0-7: PDB Channel Sequence Error Flags */
@@ -204,11 +211,14 @@
#define PDB_CHS_CF_MASK (0xff << PDB_CHS_CF_SHIFT)
# define PDB_CHS_CF_CHAN(n) ((1 << (n)) << PDB_CHS_CF_SHIFT)
/* Bits 24-31: Reserved */
/* Channel n Delay 0 Register */
/* Bits 16-31: Reserved */
#define PDB_CHDLY0_MASK (0xffff) /* Bits 0-15: PDB Channel Delay */
/* Channel n Delay 1 Register */
/* Bits 16-31: Reserved */
#define PDB_CHDLY1_MASK (0xffff) /* Bits 0-15: PDB Channel Delay */
@@ -217,7 +227,9 @@
#define PDB_DACINTC_TOE (1 << 0) /* Bit 0: DAC Interval Trigger Enable */
#define PDB_DACINTC_EXT (1 << 1) /* Bit 1: DAC External Trigger Input Enable */
/* Bits 2-31: Reserved */
/* DAC Interval n Register */
/* Bits 16-31: Reserved */
#define PDB_DACINT_MASK (0xffff) /* Bits 0-15: DAC Interval */
@@ -233,16 +245,16 @@
#define PDB_PO0DLY_DLY2_SHIFT (0) /* Bits 0-15: PDB Pulse-Out Delay 2 */
#define PDB_PO0DLY_DLY2_MASK (0xffff << PDB_PO0DLY_DLY2_SHIFT)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H */
arch/arm/src/kinetis/hardware/kinetis_pinmux.h
+15 -15
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
* by the logic in chip.h.
/* This file is just a wrapper around pin muxing header files for the Kinetis
* family selected by the logic in chip.h.
*/
#if defined(KINETIS_K20)
@@ -49,20 +49,20 @@
# error "No pin multiplexing for this Kinetis part"
#endif
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H */
arch/arm/src/kinetis/hardware/kinetis_pit.h
+17 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_pit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,29 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#if defined(KINETIS_K66)
# define KINETIS_PIT_HAS_CHAIN
# define KINETIS_PIT_HAS_LIFETIME
#endif
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */
#if defined(KINETIS_PIT_HAS_LIFETIME)
@@ -62,7 +62,7 @@
#define KINETIS_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */
#define KINETIS_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_PIT_MCR (KINETIS_PIT_BASE+KINETIS_PIT_MCR_OFFSET)
#if defined(KINETIS_PIT_HAS_LIFETIME)
@@ -86,7 +86,7 @@
#define KINETIS_PIT_TCTRL3 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL3_OFFSET)
#define KINETIS_PIT_TFLG3 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG3_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* PIT Module Control Register */
@@ -95,6 +95,7 @@
/* Bits 2-31: Reserved */
/* Timer Load Value Register (32-bit Timer Start Value Bits) */
/* Current Timer Value Register (32-bit Current Timer Value) */
/* Timer Control Register */
@@ -111,16 +112,16 @@
#define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */
/* Bits 1-31: Reserved */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H */
arch/arm/src/kinetis/hardware/kinetis_pmc.h
+19 -17
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_pmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_PMC_LVDSC1_OFFSET 0x0000 /* Low Voltage Detect Status and Control 1 Register */
#define KINETIS_PMC_LVDSC2_OFFSET 0x0001 /* Low Voltage Detect Status and Control 2 Register */
@@ -45,7 +45,7 @@
# define KINETIS_PMC_SRAMCTL_OFFSET 0x000c /* SRAM VLLS2 Control register */
#endif
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_PMC_LVDSC1 (KINETIS_PMC_BASE + KINETIS_PMC_LVDSC1_OFFSET)
#define KINETIS_PMC_LVDSC2 (KINETIS_PMC_BASE + KINETIS_PMC_LVDSC2_OFFSET)
@@ -57,7 +57,7 @@
# define KINETIS_PMC_SRAMCTL (KINETIS_PMC_BASE + KINETIS_PMC_SRAMCTL_OFFSET)
#endif
/* Register Bit Definitions *****************************************************************/
/* Register Bit Definitions *************************************************/
/* Low Voltage Detect Status and Control 1 Register */
@@ -65,6 +65,7 @@
#define PMC_LVDSC1_LVDV_MASK (3 << PMC_LVDSC1_LVDV_SHIFT)
# define PMC_LVDSC1_LVDV_LOW (0 << PMC_LVDSC1_LVDV_SHIFT) /* Low trip point selected (VLVD = VLVDL) */
# define PMC_LVDSC1_LVDV_HIGH (1 << PMC_LVDSC1_LVDV_SHIFT) /* High trip point selected (VLVD = VLVDH) */
/* Bits 2-3: Reserved */
#define PMC_LVDSC1_LVDRE (1 << 4) /* Bit 4: Low-Voltage Detect Reset Enable */
#define PMC_LVDSC1_LVDIE (1 << 5) /* Bit 5: Low-Voltage Detect Interrupt Enable */
@@ -79,7 +80,8 @@
# define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */
# define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */
# define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */
/* Bits 2-4: Reserved */
/* Bits 2-4: Reserved */
#define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */
#define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */
#define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */
@@ -123,16 +125,16 @@
# define PMC_SRAMCTL_VLLS2PD (1 << (n)) /* Bits 0-7: SRAM VLLS2 Powerdown */
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H */
arch/arm/src/kinetis/hardware/kinetis_port.h
+22 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_port.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* General Definitions **************************************************************/
****************************************************************************/
/* General Definitions ******************************************************/
#define KINETIS_PORTA (0)
#define KINETIS_PORTB (1)
@@ -41,9 +42,10 @@
#define KINETIS_PORTE (4)
#define KINETIS_NPORTS (5)
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_PORT_PCR_OFFSET(n) ((n) << 2) /* Pin Control Register n, n=0..31 */
#define KINETIS_PORT_PCR0_OFFSET 0x0000 /* Pin Control Register 0 */
#define KINETIS_PORT_PCR1_OFFSET 0x0004 /* Pin Control Register 1 */
#define KINETIS_PORT_PCR2_OFFSET 0x0008 /* Pin Control Register 2 */
@@ -83,7 +85,7 @@
#define KINETIS_PORT_DFCR_OFFSET 0x00c4 /* Digital Filter Clock Register */
#define KINETIS_PORT_DFWR_OFFSET 0x00c8 /* Digital Filter Width Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_PORT_PCR(p,n) (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR_OFFSET(n)
#define KINETIS_PORT_PCR0(p) (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR0_OFFSET)
@@ -325,7 +327,8 @@
#define KINETIS_PORTE_DFCR (KINETIS_PORTE_BASE+KINETIS_PORT_DFCR_OFFSET)
#define KINETIS_PORTE_DFWR (KINETIS_PORTE_BASE+KINETIS_PORT_DFWR_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Pin Control Register n, n=0..31 */
#define PORT_PCR_PS (1 << 0) /* Bit 0: Pull Select */
@@ -347,6 +350,7 @@
# define PORT_PCR_MUX_ALT5 (5 << PORT_PCR_MUX_SHIFT) /* Alternative 5 (chip specific) */
# define PORT_PCR_MUX_ALT6 (6 << PORT_PCR_MUX_SHIFT) /* Alternative 6 (chip specific) */
# define PORT_PCR_MUX_ALT7 (7 << PORT_PCR_MUX_SHIFT) /* Alternative 7 (chip specific / JTAG / NMI) */
/* Bits 11-14: Reserved */
#define PORT_PCR_LK (1 << 15) /* Bit 15: Lock Register */
#define PORT_PCR_IRQC_SHIFT (16) /* Bits 16-19: Interrupt Configuration */
@@ -360,6 +364,7 @@
# define PORT_PCR_IRQC_FALLING (10 << PORT_PCR_IRQC_SHIFT) /* Interrupt on falling edge */
# define PORT_PCR_IRQC_BOTH (11 << PORT_PCR_IRQC_SHIFT) /* Interrupt on either edge */
# define PORT_PCR_IRQC_ONE (12 << PORT_PCR_IRQC_SHIFT) /* Interrupt when logic one */
/* Bits 20-23: Reserved */
#define PORT_PCR_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */
/* Bits 25-31: Reserved */
@@ -399,16 +404,16 @@
#define PORT_DFWR_FILT_SHIFT (0) /* Bits 0-4: Filter Length */
#define PORT_DFWR_FILT_MASK (31 << PORT_DFWR_FILT_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H */
arch/arm/src/kinetis/hardware/kinetis_rngb.h
+22 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_rngb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,11 @@
#if defined(KINETIS_NRNG) && KINETIS_NRNG > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_RNG_VER_OFFSET 0x0000 /* RNGB Version ID Register */
#define KINETIS_RNG_CMD_OFFSET 0x0004 /* RNGB Command Register */
@@ -44,7 +44,7 @@
#define KINETIS_RNG_ESR_OFFSET 0x0010 /* RNGB Error Status Register */
#define KINETIS_RNG_OUT_OFFSET 0x0014 /* RNGB Output FIFO */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_RNG_VER (KINETIS_RNGB_BASE+KINETIS_RNG_VER_OFFSET)
#define KINETIS_RNG_CMD (KINETIS_RNGB_BASE+KINETIS_RNG_CMD_OFFSET)
@@ -53,7 +53,7 @@
#define KINETIS_RNG_ESR (KINETIS_RNGB_BASE+KINETIS_RNG_ESR_OFFSET)
#define KINETIS_RNG_OUT (KINETIS_RNGB_BASE+KINETIS_RNG_OUT_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* RNGB Version ID Register */
@@ -77,6 +77,7 @@
#define RNG_CMD_CE (1 << 5) /* Bit 5: Clear error */
#define RNG_CMD_SR (1 << 6) /* Bit 6: Software reset */
/* Bits 7-31: Reserved */
/* RNGB Control Register */
#define RNG_CR_FUFMOD_SHIFT (0) /* Bits 0-1: FIFO underflow response mode */
@@ -84,12 +85,15 @@
# define RNG_CR_FUFMOD_ZEROS (0 << RNG_CR_FUFMOD_SHIFT) /* Return zeros, set RNG_ESR[FUFE] */
# define RNG_CR_FUFMOD_ERROR (2 << RNG_CR_FUFMOD_SHIFT) /* Generate bus transfer error */
# define RNG_CR_FUFMOD_INT (3 << RNG_CR_FUFMOD_SHIFT) /* Generate interrupt, return zeros */
/* Bits 2-3: Reserved */
#define RNG_CR_AR (1 << 4) /* Bit 4: Auto-reseed */
#define RNG_CR_MASKDONE (1 << 5) /* Bit 5: Mask done interrupt */
#define RNG_CR_MASKERR (1 << 6) /* Bit 6: Mask error interrupt */
/* Bits 7-31: Reserved */
/* RNGB Status Register */
/* Bit 0: Reserved */
#define RNG_SR_BUSY (1 << 1) /* Bit 1: Busy */
#define RNG_SR_SLP (1 << 2) /* Bit 2: Sleep */
@@ -109,6 +113,7 @@
# define RNG_SR_ST_PF_TRNG (4 << RNG_SR_ST_PF_SHIFT) /* TRNG self test pass/fail */
# define RNG_SR_ST_PF_PRNG (2 << RNG_SR_ST_PF_SHIFT) /* PRNG self test pass/fail */
# define RNG_SR_ST_PF_RESEED (1 << RNG_SR_ST_PF_SHIFT) /* RESEED self test pass/fail */
#define RNG_SR_STATPF_SHIFT (24) /* Bits 24-31: Statistics test pass fail */
#define RNG_SR_STATPF_MASK (0xff << RNG_SR_STATPF_SHIFT)
# define RNG_SR_STATPF_LONG (0x80 << RNG_SR_STATPF_SHIFT) /* Long run test (>34) */
@@ -128,19 +133,20 @@
#define RNG_ESR_SATE (1 << 3) /* Bit 3: Statistical test error */
#define RNG_ESR_FUFE (1 << 4) /* Bit 4: FIFO underflow error */
/* Bits 5-31: Reserved */
/* RNGB Output FIFO (32-bit random output) */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_NRNG && KINETIS_NRNG > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H */
arch/arm/src/kinetis/hardware/kinetis_rtc.h
+38 -26
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,16 +31,17 @@
#if defined(KINETIS_NRTC) && KINETIS_NRTC > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
/* NXP/Freescale has families and technology generations (sometimes seen as processor
* speed). These are organized into feature families, and faster speeds sometimes
* have extended features. Families are K02 K10 K20 K22 K24 K30 K40 K50 K60 K64 K65
* K66 K70 K80
/* NXP/Freescale has families and technology generations
* (sometimes seen as processor speed).
* These are organized into feature families, and faster speeds sometimes
* have extended features.
* Families are K02 K10 K20 K22 K24 K30 K40 K50 K60 K64 K65 K66 K70 K80
*
* So far only two variations/generations on the RTC have been discovered.
* GEN1 RTC_TSR TPR TAR TCR CR SR LR IER WAR RAR
@@ -68,9 +69,10 @@
#define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */
#ifdef KINETIS_K60
/* Haven't found a processor or nuttx file where KINETIS_RTC_CCR is in it
* from K60P100M100SF2V2RM this would be called KINETIS_RTC_IER_OFFSET.
*/
/* Haven't found a processor or nuttx file where KINETIS_RTC_CCR is in it
* from K60P100M100SF2V2RM this would be called KINETIS_RTC_IER_OFFSET.
*/
# define KINETIS_RTC_CCR_OFFSET 0x001c /* RTC Chip Configuration Register (K60) */
#endif
@@ -85,7 +87,7 @@
#define KINETIS_RTC_WAR_OFFSET 0x0800 /* RTC Write Access Register */
#define KINETIS_RTC_RAR_OFFSET 0x0804 /* RTC Read Access Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_RTC_TSR (KINETIS_RTC_BASE+KINETIS_RTC_TSR_OFFSET)
#define KINETIS_RTC_TPR (KINETIS_RTC_BASE+KINETIS_RTC_TPR_OFFSET)
@@ -112,7 +114,7 @@
#define KINETIS_RTC_WAR (KINETIS_RTC_BASE+KINETIS_RTC_WAR_OFFSET)
#define KINETIS_RTC_RAR (KINETIS_RTC_BASE+KINETIS_RTC_RAR_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* RTC Time Seconds Register (32-bits of time in seconds) */
@@ -121,6 +123,7 @@
#define RTC_TPR_SHIFT (0) /* Bits 0-15: Time Prescaler Register */
#define RTC_TPR_MASK (0xffff << RTC_TPR_SHIFT)
/* Bits 16-31: Reserved */
/* RTC Time Alarm Register (32-bits of time alarm) */
/* RTC Time Compensation Register (32-bits) */
@@ -148,6 +151,7 @@
#define RTC_CR_SC4P (1 << 12) /* Bit 12: Oscillator 4pF load configure */
#define RTC_CR_SC2P (1 << 13) /* Bit 13: Oscillator 2pF load configure */
/* Bits 14-31: Reserved */
/* RTC Status Register (32-bits) */
#define RTC_SR_TIF (1 << 0) /* Bit 0: Time Invalid Flag */
@@ -160,7 +164,9 @@
/* Bit 3: Reserved RTC_GEN1 */
#define RTC_SR_TCE (1 << 4) /* Bit 4: Time Counter Enable */
/* Bits 5-31: Reserved */
/* RTC Lock Register (32-bits) */
/* Bits 0-2: Reserved */
#define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */
#define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */
@@ -174,6 +180,7 @@
# define RTC_LR_MCHL (1 << 11) /* Bit 10: Monotoic Counter High Lock */
#endif
/* Bits 12-31: Reserved */
/* RTC Interrupt Enable Register (32-bits, K40) */
# define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */
@@ -189,7 +196,9 @@
# define RTC_IER_WPON (1 << 7) /* Bit 7: Wakeup Pin On */
#ifdef KINETIS_K60
/* RTC Chip Configuration Register (32-bits,K60) */
/* Haven't found this in K60P100M100SF2V2RM */
# define RTC_CCR_CONFIG_SHIFT (0) /* Bits 0-7: Chip Configuration */
@@ -209,11 +218,14 @@
#define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */
#ifdef KINETIS_K60
/* This looks like old name, from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERW */
/* This looks like old name,
* from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERW
*/
# define RTC_WAR_CCRW (1 << 7) /* Bit 7: Chip Config Register Write */
#endif
/* Bits 8-31: Reserved */
/* RTC Read Access Register */
#define RTC_RAR_TSRR (1 << 0) /* Bit 0: Time Seconds Register Read */
@@ -226,8 +238,8 @@
#define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */
#ifdef KINETIS_K60
/* This is possibly an old name, from K60P100M100SF2V2RM bit 7 would be called
* RTC_RAR_IERR.
/* This is possibly an old name,
* from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERR.
*/
# define RTC_RAR_CCRR (1 << 7) /* Bit 7: Chip Config Register Read */
@@ -246,17 +258,17 @@
# define CONFIG_RTC_MAGICH 0xef32a141
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_NRTC && KINETIS_NRTC > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H */
arch/arm/src/kinetis/hardware/kinetis_sdhc.h
+38 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_sdhc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_SDHC_DSADDR_OFFSET 0x0000 /* DMA System Address Register */
#define KINETIS_SDHC_BLKATTR_OFFSET 0x0004 /* Block Attributes Register */
@@ -60,7 +60,7 @@
#define KINETIS_SDHC_MMCBOOT_OFFSET 0x00c4 /* MMC Boot Register */
#define KINETIS_SDHC_HOSTVER_OFFSET 0x00fc /* Host Controller Version */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_SDHC_DSADDR (KINETIS_SDHC_BASE+KINETIS_SDHC_DSADDR_OFFSET)
#define KINETIS_SDHC_BLKATTR (KINETIS_SDHC_BASE+KINETIS_SDHC_BLKATTR_OFFSET)
@@ -87,13 +87,14 @@
#define KINETIS_SDHC_MMCBOOT (KINETIS_SDHC_BASE+KINETIS_SDHC_MMCBOOT_OFFSET)
#define KINETIS_SDHC_HOSTVER (KINETIS_SDHC_BASE+KINETIS_SDHC_HOSTVER_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* DMA System Address Register */
#define SDHC_DSADDR_SHIFT (1) /* Bits 1-31: DMA System Address */
#define SDHC_DSADDR_MASK (0xfffffffe)
/* Bits 0-1: Reserved */
/* Block Attributes Register */
#define SDHC_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */
@@ -119,6 +120,7 @@
# define SDHC_XFERTYP_RSPTYP_LEN136 (1 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
# define SDHC_XFERTYP_RSPTYP_LEN48 (2 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
# define SDHC_XFERTYP_RSPTYP_LEN48BSY (3 << SDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
/* Bit 18: Reserved */
#define SDHC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */
#define SDHC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */
@@ -129,9 +131,11 @@
# define SDHC_XFERTYP_CMDTYP_SUSPEND (1 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
# define SDHC_XFERTYP_CMDTYP_RESUME (2 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
# define SDHC_XFERTYP_CMDTYP_ABORT (3 << SDHC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
#define SDHC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */
#define SDHC_XFERTYP_CMDINX_MASK (63 << SDHC_XFERTYP_CMDINX_SHIFT)
/* Bits 30-31: Reserved */
/* Command Response 0-3 (32-bit response data) */
/* Buffer Data Port Register (32-bit data content) */
@@ -173,12 +177,14 @@
# define SDHC_PROCTL_DTW_1BIT (0 << SDHC_PROCTL_DTW_SHIFT) /* 1-bit mode */
# define SDHC_PROCTL_DTW_4BIT (1 << SDHC_PROCTL_DTW_SHIFT) /* 4-bit mode */
# define SDHC_PROCTL_DTW_8BIT (2 << SDHC_PROCTL_DTW_SHIFT) /* 8-bit mode */
#define SDHC_PROCTL_D3CD (1 << 3) /* Bit nn: DAT3 as Card Detection Pin */
#define SDHC_PROCTL_EMODE_SHIFT (4) /* Bits 4-5: Endian mode */
#define SDHC_PROCTL_EMODE_MASK (3 << SDHC_PROCTL_EMODE_SHIFT)
# define SDHC_PROCTL_EMODE_BE (0 << SDHC_PROCTL_EMODE_SHIFT) /* Big endian mode */
# define SDHC_PROCTL_EMODE_HWBE (1 << SDHC_PROCTL_EMODE_SHIFT) /* Half word big endian mode */
# define SDHC_PROCTL_EMODE_LE (2 << SDHC_PROCTL_EMODE_SHIFT) /* Little endian mode */
#define SDHC_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */
#define SDHC_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */
#define SDHC_PROCTL_DMAS_SHIFT (8) /* Bits 8-9: DMA Select */
@@ -186,6 +192,7 @@
# define SDHC_PROCTL_DMAS_NODMA (0 << SDHC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
# define SDHC_PROCTL_DMAS_ADMA1 (1 << SDHC_PROCTL_DMAS_SHIFT) /* ADMA1 is selected */
# define SDHC_PROCTL_DMAS_ADMA2 (2 << SDHC_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */
/* Bits 10-15: Reserved */
#define SDHC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */
#define SDHC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */
@@ -196,6 +203,7 @@
#define SDHC_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */
#define SDHC_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */
/* Bits 27-31: Reserved */
/* System Control Register */
#define SDHC_SYSCTL_IPGEN (1 << 0) /* Bit 0: IPG Clock Enable */
@@ -205,6 +213,7 @@
#define SDHC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */
#define SDHC_SYSCTL_DVS_MASK (15 << SDHC_SYSCTL_DVS_SHIFT)
# define SDHC_SYSCTL_DVS_DIV(n) (((n)-1) << SDHC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */
#define SDHC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */
#define SDHC_SYSCTL_SDCLKFS_MASK (0xff << SDHC_SYSCTL_SDCLKFS_SHIFT)
# define SDHC_SYSCTL_SDCLKFS_BYPASS (0x00 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */
@@ -216,16 +225,20 @@
# define SDHC_SYSCTL_SDCLKFS_DIV64 (0x20 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */
# define SDHC_SYSCTL_SDCLKFS_DIV128 (0x40 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */
# define SDHC_SYSCTL_SDCLKFS_DIV256 (0x80 << SDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */
#define SDHC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */
#define SDHC_SYSCTL_DTOCV_MASK (15 << SDHC_SYSCTL_DTOCV_SHIFT)
# define SDHC_SYSCTL_DTOCV_MUL(n) (((n)-213) << SDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
/* Bits 20-23: Reserved */
#define SDHC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */
#define SDHC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */
#define SDHC_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */
#define SDHC_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */
/* Bits 28-31: Reserved */
/* Interrupt Status Register, Interrupt Status Enable Register, and Interrupt Signal Enable Register
/* Interrupt Status Register, Interrupt Status Enable Register,
* and Interrupt Signal Enable Register
* Common interrupt bit definitions
*/
@@ -263,7 +276,9 @@
/* Bits 5-6: Reserved */
#define SDHC_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */
/* Bits 8-31: Reserved */
/* Host Controller Capabilities */
/* Bits 0-15: Reserved */
#define SDHC_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */
#define SDHC_HTCAPBLT_MBL_MASK (7 << SDHC_HTCAPBLT_MBL_SHIFT)
@@ -280,6 +295,7 @@
#define SDHC_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */
#define SDHC_HTCAPBLT_VS18 (1 << 26) /* Bit 26: Voltage Support 1.8 */
/* Bits 27-31: Reserved */
/* Watermark Level Register */
#define SDHC_WML_RD_SHIFT (0) /* Bits 0-7: Read Watermark Level */
@@ -288,6 +304,7 @@
#define SDHC_WML_WR_SHIFT (16) /* Bits 16-23: Write Watermark Level */
#define SDHC_WML_WR_MASK (0xff << SDHC_WML_WRWML_SHIFT)
/* Bits 24-31: Reserved */
/* Force Event Register */
#define SDHC_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */
@@ -320,9 +337,11 @@
# define SDHC_ADMAES_FDS (1 << SDHC_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */
# define SDHC_ADMAES_CADR (2 << SDHC_ADMAES_ADMAES_SHIFT) /* Change address */
# define SDHC_ADMAES_TFR (3 << SDHC_ADMAES_ADMAES_SHIFT) /* Transfer data */
#define SDHC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */
#define SDHC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */
/* Bits 4-31: Reserved */
/* ADMA System Address Register */
#define SDHC_ADSADDR_SHIFT (1) /* Bits 1-31: ADMA System Address */
@@ -337,11 +356,13 @@
#define SDHC_VENDOR_INTSTVAL_SHIFT (16) /* Bits 16-23: Internal State Value */
#define SDHC_VENDOR_INTSTVAL_MASK (0xff << SDHC_VENDOR_INTSTVAL_SHIFT)
/* Bits 24-31: Reserved */
/* MMC Boot Register */
#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0) /* Bits 0-3: Boot ACK time out counter value */
#define SDHC_MMCBOOT_DTOCVACK_MASK (15 << SDHC_MMCBOOT_DTOCVACK_SHIFT)
# define SDHC_MMCBOOT_DTOCVACK_MUL(n) ((n-8) << SDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^n, n=8..22 */
#define SDHC_MMCBOOT_BOOTACK (1 << 4) /* Bit 4: Boot ack mode select */
#define SDHC_MMCBOOT_BOOTMODE (1 << 5) /* Bit 5: Boot mode select */
#define SDHC_MMCBOOT_BOOTEN (1 << 6) /* Bit 6: Boot mode enable */
@@ -358,16 +379,16 @@
#define SDHC_HOSTVER_VVN_MASK (0xff << SDHC_HOSTVER_VVN_SHIFT)
/* Bits 16-31: Reserved */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H */
arch/arm/src/kinetis/hardware/kinetis_slcd.h
+74 -18
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_slcd.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_LCD_GCR_OFFSET 0x0000 /* LCD general control register */
#define KINETIS_LCD_AR_OFFSET 0x0004 /* LCD auxiliary register */
@@ -60,7 +60,7 @@
#define KINETIS_LCD_WF59TO56_OFFSET 0x0058 /* LCD waveform register */
#define KINETIS_LCD_WF63TO60_OFFSET 0x005C /* LCD waveform register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_LCD_GCR (KINETIS_SLCD_BASE+KINETIS_LCD_GCR_OFFSET)
#define KINETIS_LCD_AR (KINETIS_SLCD_BASE+KINETIS_LCD_AR_OFFSET)
@@ -87,13 +87,14 @@
#define KINETIS_LCD_WF59TO56 (KINETIS_SLCD_BASE+KINETIS_LCD_WF59TO56_OFFSET)
#define KINETIS_LCD_WF63TO60 (KINETIS_SLCD_BASE+KINETIS_LCD_WF63TO60_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* LCD general control register */
#define LCD_GCR_DUTYSHIFT (0) /* Bits 0-2: LCD duty select */
#define LCD_GCR_DUTY_MASK (7 << LCD_GCR_DUTYSHIFT)
# define LCD_GCR_DUTY_BP(n) (((n)-1) << LCD_GCR_DUTYSHIFT) /* Use n BP (1/n duty cycle) */
#define LCD_GCR_LCLK_SHIFT (3) /* Bits 3-5: LCD clock prescaler */
#define LCD_GCR_LCLK_MASK (7 << LCD_GCR_LCLK_SHIFT)
#define LCD_GCR_SOURCE (1 << 6) /* Bit 6: LCD clock source select */
@@ -107,6 +108,7 @@
# define LCD_GCR_ALTDIV_DIV (1 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 8 */
# define LCD_GCR_ALTDIV_DIV (2 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 64 */
# define LCD_GCR_ALTDIV_DIV (3 << LCD_GCR_ALTDIV_SHIFT) /* Divide factor = 512 */
#define LCD_GCR_FDCIEN (1 << 14) /* Bit 14: LCD fault detection complete interrupt enable */
#define LCD_GCR_LCDIEN (1 << 15) /* Bit 15: LCD frame frequency interrupt enable */
#define LCD_GCR_VSUPPLY_SHIFT (16) /* Bits 16-17: Voltage supply control */
@@ -115,6 +117,7 @@
#define LCD_GCR_VSUPPLY_INTVLL3 (1 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL3 internally from VDD */
#define LCD_GCR_VSUPPLY_EXTVLL3 (3 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL3 externally from VDD */
#define LCD_GCR_VSUPPLY_INTVLL1 (3 << LCD_GCR_VSUPPLY_SHIFT) /* Drive VLL1 internally from VIREG */
/* Bits 18-19: Reserved */
#define LCD_GCR_LADJ_SHIFT (20) /* Bits 20-21: Load adjust */
#define LCD_GCR_LADJ_MASK (3 << LCD_GCR_LADJ_SHIFT)
@@ -126,6 +129,7 @@
# define LCD_GCR_LADJ_MIDFAST (1 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=6000pF */
# define LCD_GCR_LADJ_MIDSLOW (2 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=4000pF */
# define LCD_GCR_LADJ_SLOW (3 << LCD_GCR_LADJ_SHIFT) /* For CPSEL=1, <=2000pF */
#define LCD_GCR_HREFSEL (1 << 22) /* Bit 22: High reference select */
#define LCD_GCR_CPSEL (1 << 23) /* Bit 23: Charge pump or resistor bias select */
#define LCD_GCR_RVTRIM_SHIFT (24) /* Bits 24-27: Regulated voltage trim */
@@ -139,12 +143,13 @@
#define LCD_AR_BRATE_MASK (7 << LCD_AR_BRATE_SHIFT)
#define LCD_AR_BMODE (1 << 3) /* Bit 3: Blink mode */
/* Bit 4: Reserved */
#define LCD_AR_BLANK (1 << 5) /* Bit 5: Blank display mode
#define LCD_AR_BLANK (1 << 5) /* Bit 5: Blank display mode */
#define LCD_AR_ALT (1 << 6) /* Bit 6: Alternate display mode */
#define LCD_AR_BLINK (1 << 7) /* Bit 7: Blink command */
/* Bits 8-14: Reserved */
#define LCD_AR_LCDIF (1 << 15) /* Bit 15: LCD frame frequency interrupt flag */
/* Bits 16-31: Reserved */
/* LCD fault detect control register */
#define LCD_FDCR_FDPINID_SHIFT (0) /* Bits 0-5: Fault detect pin ID */
@@ -164,7 +169,9 @@
# define LCD_FDCR_FDPRS_DIV32 (5 << LCD_FDCR_FDPRS_SHIFT) /* 1/32 bus clock */
# define LCD_FDCR_FDPRS_DIV64 (6 << LCD_FDCR_FDPRS_SHIFT) /* 1/64 bus clock */
# define LCD_FDCR_FDPRS_DIV128 (7 << LCD_FDCR_FDPRS_SHIFT) /* 1/128 bus clock */
/* Bits 15-31: Reserved */
/* LCD fault detect status register */
#define LCD_FDSR_FDCNT_SHIFT (0) /* Bits 0-7: Fault detect counter */
@@ -172,12 +179,13 @@
/* Bits 8-14: Reserved */
#define LCD_FDSR_FDCF (1 << 15) /* Bit 15: Fault detection complete flag */
/* Bits 16-31: Reserved */
/* LCD pin enable register low/high (64 pin bits in two 32-bit registers) */
/* LCD pin enable register low/high (64 pin bits in two 32-bit registers) */
/* LCD backplane enable register (64 pin bits in two 32-bit registers) */
#define LCD_BPENL(n) (1 << (n)) /* Bit n: Enable backplane operation pin n, n=0-31 */
#define LCD_BPENH(n) (1 << ((n)-32)) /* Bit n-32: Enable backplane operation pin n, n=32-63 */
/* LCD waveform registers */
@@ -185,12 +193,15 @@
#define LCD_WF3TO0_WF0_SHIFT (0) /* Bits 0-7: Waveform control field 0 segment bits */
#define LCD_WF3TO0_WF0_MASK (0xff << LCD_WF3TO0_WF0_SHIFT)
# define LCD_WF3TO0_WF0_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF0_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF3TO0_WF1_SHIFT (8) /* Bits 8-15: Waveform control field 1 segment bits */
#define LCD_WF3TO0_WF1_MASK (0xff << LCD_WF3TO0_WF1_SHIFT)
# define LCD_WF3TO0_WF1_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF1_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF3TO0_WF2_SHIFT (16) /* Bits 16-23: Waveform control field 2 segment bits */
#define LCD_WF3TO0_WF2_MASK (0xff << LCD_WF3TO0_WF2_SHIFT)
# define LCD_WF3TO0_WF2_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF2_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF3TO0_WF3_SHIFT (24) /* Bits 24-31: Waveform control field 3 segment bits */
#define LCD_WF3TO0_WF3_MASK (0xff << LCD_WF3TO0_WF3_SHIFT)
# define LCD_WF3TO0_WF3_SEGMENT(n) ((1 << (n)) << LCD_WF3TO0_WF3_SHIFT) /* Segment n, n=0..7 */
@@ -198,12 +209,15 @@
#define LCD_WF7TO4_WF4_SHIFT (0) /* Bits 0-7: Waveform control field 4 segment bits */
#define LCD_WF7TO4_WF4_MASK (0xff << LCD_WF7TO4_WF4_SHIFT)
# define LCD_WF7TO4_WF4_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF4_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF7TO4_WF5_SHIFT (8) /* Bits 8-15: Waveform control field 5 segment bits */
#define LCD_WF7TO4_WF5_MASK (0xff << LCD_WF7TO4_WF5_SHIFT)
# define LCD_WF7TO4_WF5_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF5_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF7TO4_WF6_SHIFT (16) /* Bits 16-23: Waveform control field 6 segment bits */
#define LCD_WF7TO4_WF6_MASK (0xff << LCD_WF7TO4_WF6_SHIFT)
# define LCD_WF7TO4_WF6_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF6_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF7TO4_WF7_SHIFT (24) /* Bits 24-31: Waveform control field 7 segment bits */
#define LCD_WF7TO4_WF7_MASK (0xff << LCD_WF7TO4_WF7_SHIFT)
# define LCD_WF7TO4_WF7_SEGMENT(n) ((1 << (n)) << LCD_WF7TO4_WF7_SHIFT) /* Segment n, n=0..7 */
@@ -211,12 +225,15 @@
#define LCD_WF11TO8_WF8_SHIFT (0) /* Bits 0-7: Waveform control field 8 segment bits */
#define LCD_WF11TO8_WF8_MASK (0xff << LCD_WF11TO8_WF8_SHIFT)
# define LCD_WF11TO8_WF8_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF8_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF11TO8_WF9_SHIFT (8) /* Bits 8-15: Waveform control field 9 segment bits */
#define LCD_WF11TO8_WF9_MASK (0xff << LCD_WF11TO8_WF9_SHIFT)
# define LCD_WF11TO8_WF9_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF9_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF11TO8_WF10_SHIFT (16) /* Bits 16-23: Waveform control field 10 segment bits */
#define LCD_WF11TO8_WF10_MASK (0xff << LCD_WF11TO8_WF10_SHIFT)
# define LCD_WF11TO8_WF10_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF10_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF11TO8_WF11_SHIFT (24) /* Bits 24-31: Waveform control field 11 segment bits */
#define LCD_WF11TO8_WF11_MASK (0xff << LCD_WF11TO8_WF11_SHIFT)
# define LCD_WF11TO8_WF11_SEGMENT(n) ((1 << (n)) << LCD_WF11TO8_WF11_SHIFT) /* Segment n, n=0..7 */
@@ -224,12 +241,15 @@
#define LCD_WF15TO12_WF12_SHIFT (0) /* Bits 0-7: Waveform control field 12 segment bits */
#define LCD_WF15TO12_WF12_MASK (0xff << LCD_WF15TO12_WF12_SHIFT)
# define LCD_WF15TO12_WF12_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF12_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF15TO12_WF13_SHIFT (8) /* Bits 8-15: Waveform control field 13 segment bits */
#define LCD_WF15TO12_WF13_MASK (0xff << LCD_WF15TO12_WF13_SHIFT)
# define LCD_WF15TO12_WF13_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF13_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF15TO12_WF14_SHIFT (16) /* Bits 16-23: Waveform control field 14 segment bits */
#define LCD_WF15TO12_WF14_MASK (0xff << LCD_WF15TO12_WF14_SHIFT)
# define LCD_WF15TO12_WF14_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF14_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF15TO12_WF15_SHIFT (24) /* Bits 24-31: Waveform control field 15 segment bits */
#define LCD_WF15TO12_WF15_MASK (0xff << LCD_WF15TO12_WF15_SHIFT)
# define LCD_WF15TO12_WF15_SEGMENT(n) ((1 << (n)) << LCD_WF15TO12_WF15_SHIFT) /* Segment n, n=0..7 */
@@ -237,12 +257,15 @@
#define LCD_WF19TO16_WF16_SHIFT (0) /* Bits 0-7: Waveform control field 16 segment bits */
#define LCD_WF19TO16_WF16_MASK (0xff << LCD_WF19TO16_WF16_SHIFT)
# define LCD_WF19TO16_WF16_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF16_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF19TO16_WF17_SHIFT (8) /* Bits 8-15: Waveform control field 17 segment bits */
#define LCD_WF19TO16_WF17_MASK (0xff << LCD_WF19TO16_WF17_SHIFT)
# define LCD_WF19TO16_WF17_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF17_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF19TO16_WF18_SHIFT (16) /* Bits 16-23: Waveform control field 18 segment bits */
#define LCD_WF19TO16_WF18_MASK (0xff << LCD_WF19TO16_WF18_SHIFT)
# define LCD_WF19TO16_WF18_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF18_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF19TO16_WF19_SHIFT (24) /* Bits 24-31: Waveform control field 19 segment bits */
#define LCD_WF19TO16_WF19_MASK (0xff << LCD_WF19TO16_WF19_SHIFT)
# define LCD_WF19TO16_WF19_SEGMENT(n) ((1 << (n)) << LCD_WF19TO16_WF19_SHIFT) /* Segment n, n=0..7 */
@@ -250,12 +273,15 @@
#define LCD_WF23TO20_WF20_SHIFT (0) /* Bits 0-7: Waveform control field 20 segment bits */
#define LCD_WF23TO20_WF20_MASK (0xff << LCD_WF23TO20_WF20_SHIFT)
# define LCD_WF23TO20_WF20_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF20_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF23TO20_WF21_SHIFT (8) /* Bits 8-15: Waveform control field 21 segment bits */
#define LCD_WF23TO20_WF21_MASK (0xff << LCD_WF23TO20_WF21_SHIFT)
# define LCD_WF23TO20_WF21_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF21_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF23TO20_WF22_SHIFT (16) /* Bits 16-23: Waveform control field 22 segment bits */
#define LCD_WF23TO20_WF22_MASK (0xff << LCD_WF23TO20_WF22_SHIFT)
# define LCD_WF23TO20_WF22_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF22_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF23TO20_WF23_SHIFT (24) /* Bits 24-31: Waveform control field 23 segment bits */
#define LCD_WF23TO20_WF23_MASK (0xff << LCD_WF23TO20_WF23_SHIFT)
# define LCD_WF23TO20_WF23_SEGMENT(n) ((1 << (n)) << LCD_WF23TO20_WF23_SHIFT) /* Segment n, n=0..7 */
@@ -263,12 +289,15 @@
#define LCD_WF27TO24_WF24_SHIFT (0) /* Bits 0-7: Waveform control field 24 segment bits */
#define LCD_WF27TO24_WF24_MASK (0xff << LCD_WF27TO24_WF24_SHIFT)
# define LCD_WF27TO24_WF24_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF24_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF27TO24_WF25_SHIFT (8) /* Bits 8-15: Waveform control field 25 segment bits */
#define LCD_WF27TO24_WF25_MASK (0xff << LCD_WF27TO24_WF25_SHIFT)
# define LCD_WF27TO24_WF25_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF25_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF27TO24_WF26_SHIFT (16) /* Bits 16-23: Waveform control field 26 segment bits */
#define LCD_WF27TO24_WF26_MASK (0xff << LCD_WF27TO24_WF26_SHIFT)
# define LCD_WF27TO24_WF26_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF26_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF27TO24_WF27_SHIFT (24) /* Bits 24-31: Waveform control field 27 segment bits */
#define LCD_WF27TO24_WF27_MASK (0xff << LCD_WF27TO24_WF27_SHIFT)
# define LCD_WF27TO24_WF27_SEGMENT(n) ((1 << (n)) << LCD_WF27TO24_WF27_SHIFT) /* Segment n, n=0..7 */
@@ -276,12 +305,15 @@
#define LCD_WF31TO28_WF28_SHIFT (0) /* Bits 0-7: Waveform control field 28 segment bits */
#define LCD_WF31TO28_WF28_MASK (0xff << LCD_WF31TO28_WF28_SHIFT)
# define LCD_WF31TO28_WF28_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF28_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF31TO28_WF29_SHIFT (8) /* Bits 8-15: Waveform control field 29 segment bits */
#define LCD_WF31TO28_WF29_MASK (0xff << LCD_WF31TO28_WF29_SHIFT)
# define LCD_WF31TO28_WF29_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF29_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF31TO28_WF30_SHIFT (16) /* Bits 16-23: Waveform control field 30 segment bits */
#define LCD_WF31TO28_WF30_MASK (0xff << LCD_WF31TO28_WF30_SHIFT)
# define LCD_WF31TO28_WF30_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF30_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF31TO28_WF31_SHIFT (24) /* Bits 24-31: Waveform control field 31 segment bits */
#define LCD_WF31TO28_WF31_MASK (0xff << LCD_WF31TO28_WF31_SHIFT)
# define LCD_WF31TO28_WF31_SEGMENT(n) ((1 << (n)) << LCD_WF31TO28_WF31_SHIFT) /* Segment n, n=0..7 */
@@ -289,12 +321,15 @@
#define LCD_WF35TO32_WF32_SHIFT (0) /* Bits 0-7: Waveform control field 32 segment bits */
#define LCD_WF35TO32_WF32_MASK (0xff << LCD_WF35TO32_WF32_SHIFT)
# define LCD_WF35TO32_WF32_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF32_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF35TO32_WF33_SHIFT (8) /* Bits 8-15: Waveform control field 33 segment bits */
#define LCD_WF35TO32_WF33_MASK (0xff << LCD_WF35TO32_WF33_SHIFT)
# define LCD_WF35TO32_WF33_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF33_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF35TO32_WF34_SHIFT (16) /* Bits 16-23: Waveform control field 34 segment bits */
#define LCD_WF35TO32_WF34_MASK (0xff << LCD_WF35TO32_WF34_SHIFT)
# define LCD_WF35TO32_WF34_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF34_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF35TO32_WF35_SHIFT (24) /* Bits 24-31: Waveform control field 35 segment bits */
#define LCD_WF35TO32_WF35_MASK (0xff << LCD_WF35TO32_WF35_SHIFT)
# define LCD_WF35TO32_WF35_SEGMENT(n) ((1 << (n)) << LCD_WF35TO32_WF35_SHIFT) /* Segment n, n=0..7 */
@@ -302,12 +337,15 @@
#define LCD_WF39TO36_WF36_SHIFT (0) /* Bits 0-7: Waveform control field 36 segment bits */
#define LCD_WF39TO36_WF36_MASK (0xff << LCD_WF39TO36_WF36_SHIFT)
# define LCD_WF39TO36_WF36_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF36_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF39TO36_WF37_SHIFT (8) /* Bits 8-15: Waveform control field 37 segment bits */
#define LCD_WF39TO36_WF37_MASK (0xff << LCD_WF39TO36_WF37_SHIFT)
# define LCD_WF39TO36_WF37_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF37_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF39TO36_WF38_SHIFT (16) /* Bits 16-23: Waveform control field 38 segment bits */
#define LCD_WF39TO36_WF38_MASK (0xff << LCD_WF39TO36_WF38_SHIFT)
# define LCD_WF39TO36_WF38_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF38_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF39TO36_WF39_SHIFT (24) /* Bits 24-31: Waveform control field 39 segment bits */
#define LCD_WF39TO36_WF39_MASK (0xff << LCD_WF39TO36_WF39_SHIFT)
# define LCD_WF39TO36_WF39_SEGMENT(n) ((1 << (n)) << LCD_WF39TO36_WF39_SHIFT) /* Segment n, n=0..7 */
@@ -315,12 +353,15 @@
#define LCD_WF43TO40_WF40_SHIFT (0) /* Bits 0-7: Waveform control field 40 segment bits */
#define LCD_WF43TO40_WF40_MASK (0xff << LCD_WF43TO40_WF40_SHIFT)
# define LCD_WF43TO40_WF40_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF40_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF43TO40_WF41_SHIFT (8) /* Bits 8-15: Waveform control field 41 segment bits */
#define LCD_WF43TO40_WF41_MASK (0xff << LCD_WF43TO40_WF41_SHIFT)
# define LCD_WF43TO40_WF41_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF41_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF43TO40_WF42_SHIFT (16) /* Bits 16-23: Waveform control field 42 segment bits */
#define LCD_WF43TO40_WF42_MASK (0xff << LCD_WF43TO40_WF42_SHIFT)
# define LCD_WF43TO40_WF42_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF42_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF43TO40_WF43_SHIFT (24) /* Bits 24-31: Waveform control field 43 segment bits */
#define LCD_WF43TO40_WF43_MASK (0xff << LCD_WF43TO40_WF43_SHIFT)
# define LCD_WF43TO40_WF43_SEGMENT(n) ((1 << (n)) << LCD_WF43TO40_WF43_SHIFT) /* Segment n, n=0..7 */
@@ -328,12 +369,15 @@
#define LCD_WF47TO44_WF44_SHIFT (0) /* Bits 0-7: Waveform control field 44 segment bits */
#define LCD_WF47TO44_WF44_MASK (0xff << LCD_WF47TO44_WF44_SHIFT)
# define LCD_WF47TO44_WF44_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF44_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF47TO44_WF45_SHIFT (8) /* Bits 8-15: Waveform control field 45 segment bits */
#define LCD_WF47TO44_WF45_MASK (0xff << LCD_WF47TO44_WF45_SHIFT)
# define LCD_WF47TO44_WF45_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF45_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF47TO44_WF46_SHIFT (16) /* Bits 16-23: Waveform control field 46 segment bits */
#define LCD_WF47TO44_WF46_MASK (0xff << LCD_WF47TO44_WF46_SHIFT)
# define LCD_WF47TO44_WF46_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF46_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF47TO44_WF47_SHIFT (24) /* Bits 24-31: Waveform control field 47 segment bits */
#define LCD_WF47TO44_WF47_MASK (0xff << LCD_WF47TO44_WF47_SHIFT)
# define LCD_WF47TO44_WF47_SEGMENT(n) ((1 << (n)) << LCD_WF47TO44_WF47_SHIFT) /* Segment n, n=0..7 */
@@ -341,12 +385,15 @@
#define LCD_WF51TO48_WF48_SHIFT (0) /* Bits 0-7: Waveform control field 48 segment bits */
#define LCD_WF51TO48_WF48_MASK (0xff << LCD_WF51TO48_WF48_SHIFT)
# define LCD_WF51TO48_WF48_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF48_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF51TO48_WF49_SHIFT (8) /* Bits 8-15: Waveform control field 49 segment bits */
#define LCD_WF51TO48_WF49_MASK (0xff << LCD_WF51TO48_WF49_SHIFT)
# define LCD_WF51TO48_WF49_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF49_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF51TO48_WF50_SHIFT (16) /* Bits 16-23: Waveform control field 50 segment bits */
#define LCD_WF51TO48_WF50_MASK (0xff << LCD_WF51TO48_WF50_SHIFT)
# define LCD_WF51TO48_WF50_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF50_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF51TO48_WF51_SHIFT (24) /* Bits 24-31: Waveform control field 51 segment bits */
#define LCD_WF51TO48_WF51_MASK (0xff << LCD_WF51TO48_WF51_SHIFT)
# define LCD_WF51TO48_WF51_SEGMENT(n) ((1 << (n)) << LCD_WF51TO48_WF51_SHIFT) /* Segment n, n=0..7 */
@@ -354,12 +401,15 @@
#define LCD_WF55TO52_WF52_SHIFT (0) /* Bits 0-7: Waveform control field 52 segment bits */
#define LCD_WF55TO52_WF52_MASK (0xff << LCD_WF55TO52_WF52_SHIFT)
# define LCD_WF55TO52_WF52_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF52_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF55TO52_WF53_SHIFT (8) /* Bits 8-15: Waveform control field 53 segment bits */
#define LCD_WF55TO52_WF53_MASK (0xff << LCD_WF55TO52_WF53_SHIFT)
# define LCD_WF55TO52_WF53_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF53_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF55TO52_WF54_SHIFT (16) /* Bits 16-23: Waveform control field 54 segment bits */
#define LCD_WF55TO52_WF54_MASK (0xff << LCD_WF55TO52_WF54_SHIFT)
# define LCD_WF55TO52_WF54_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF54_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF55TO52_WF55_SHIFT (24) /* Bits 24-31: Waveform control field 55 segment bits */
#define LCD_WF55TO52_WF55_MASK (0xff << LCD_WF55TO52_WF55_SHIFT)
# define LCD_WF55TO52_WF55_SEGMENT(n) ((1 << (n)) << LCD_WF55TO52_WF55_SHIFT) /* Segment n, n=0..7 */
@@ -367,12 +417,15 @@
#define LCD_WF59TO56_WF56_SHIFT (0) /* Bits 0-7: Waveform control field 56 segment bits */
#define LCD_WF59TO56_WF56_MASK (0xff << LCD_WF59TO56_WF56_SHIFT)
# define LCD_WF59TO56_WF56_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF56_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF59TO56_WF57_SHIFT (8) /* Bits 8-15: Waveform control field 57 segment bits */
#define LCD_WF59TO56_WF57_MASK (0xff << LCD_WF59TO56_WF57_SHIFT)
# define LCD_WF59TO56_WF57_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF57_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF59TO56_WF58_SHIFT (16) /* Bits 16-23: Waveform control field 58 segment bits */
#define LCD_WF59TO56_WF58_MASK (0xff << LCD_WF59TO56_WF58_SHIFT)
# define LCD_WF59TO56_WF58_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF58_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF59TO56_WF59_SHIFT (24) /* Bits 24-31: Waveform control field 59 segment bits */
#define LCD_WF59TO56_WF59_MASK (0xff << LCD_WF59TO56_WF59_SHIFT)
# define LCD_WF59TO56_WF59_SEGMENT(n) ((1 << (n)) << LCD_WF59TO56_WF59_SHIFT) /* Segment n, n=0..7 */
@@ -380,26 +433,29 @@
#define LCD_WF63TO60_WF60_SHIFT (0) /* Bits 0-7: Waveform control field 60 segment bits */
#define LCD_WF63TO60_WF60_MASK (0xff << LCD_WF63TO60_WF60_SHIFT)
# define LCD_WF63TO60_WF60_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF60_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF63TO60_WF61_SHIFT (8) /* Bits 8-15: Waveform control field 61 segment bits */
#define LCD_WF63TO60_WF61_MASK (0xff << LCD_WF63TO60_WF61_SHIFT)
# define LCD_WF63TO60_WF61_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF61_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF63TO60_WF62_SHIFT (16) /* Bits 16-23: Waveform control field 62 segment bits */
#define LCD_WF63TO60_WF62_MASK (0xff << LCD_WF63TO60_WF62_SHIFT)
# define LCD_WF63TO60_WF62_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF62_SHIFT) /* Segment n, n=0..7 */
#define LCD_WF63TO60_WF63_SHIFT (24) /* Bits 24-31: Waveform control field 63 segment bits */
#define LCD_WF63TO60_WF63_MASK (0xff << LCD_WF63TO60_WF63_SHIFT)
# define LCD_WF63TO60_WF63_SEGMENT(n) ((1 << (n)) << LCD_WF63TO60_WF63_SHIFT) /* Segment n, n=0..7 */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H */
arch/arm/src/kinetis/hardware/kinetis_smc.h
+19 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_smc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,38 +16,38 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_SMC_SRSH_OFFSET 0x0000 /* System Reset Status Register High */
#define KINETIS_SMC_SRSL_OFFSET 0x0001 /* System Reset Status Register Low */
#define KINETIS_SMC_PMPROT_OFFSET 0x0002 /* Power Mode Protection Register */
#define KINETIS_SMC_PMCTRL_OFFSET 0x0003 /* Power Mode Control Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_SMC_SRSH (KINETIS_SMC_BASE+KINETIS_SMC_SRSH_OFFSET)
#define KINETIS_SMC_SRSL (KINETIS_SMC_BASE+KINETIS_SMC_SRSL_OFFSET)
#define KINETIS_SMC_PMPROT (KINETIS_SMC_BASE+KINETIS_SMC_PMPROT_OFFSET)
#define KINETIS_SMC_PMCTRL (KINETIS_SMC_BASE+KINETIS_SMC_PMCTRL_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* System Reset Status Register High */
@@ -75,6 +75,7 @@
#define SMC_PMPROT_ALLS (1 << 4) /* Bit 4: Allow low leakage stop mode */
#define SMC_PMPROT_AVLP (1 << 5) /* Bit 5: Allow very low power modes */
/* Bits 6-7: Reserved */
/* Power Mode Control Register */
#define SMC_PMCTRL_LPLLSM_SHIFT (0) /* Bits 0-2: Low Power, Low Leakage Stop Mode */
@@ -85,23 +86,25 @@
# define SMC_PMCTRL_LPLLSM_VLLS3 (5 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 3 */
# define SMC_PMCTRL_LPLLSM_VLLS2 (6 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 2 */
# define SMC_PMCTRL_LPLLSM_VLLS1 (7 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 1 */
/* Bits 3-4: Reserved */
#define SMC_PMCTRL_RUNM_SHIFT (5) /* Bits 5-6: Run Mode Enable */
#define SMC_PMCTRL_RUNM_MASK (3 << SMC_PMCTRL_RUNM_SHIFT)
# define SMC_PMCTRL_RUNM_NORMAL (0 << SMC_PMCTRL_RUNM_SHIFT) /* Normal run mode */
# define SMC_PMCTRL_RUNM_VLP (2 << SMC_PMCTRL_RUNM_SHIFT) /* Very low power run mode */
#define SMC_PMCTRL_LPWUI (1 << 7) /* Bit 7: Low Power Wake Up on Interrupt */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H */
arch/arm/src/kinetis/hardware/kinetis_tsi.h
+36 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_tsi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_TSI_GENCS_OFFSET 0x0000 /* General Control and Status Register */
#define KINETIS_TSI_SCANC_OFFSET 0x0004 /* SCAN control register */
@@ -41,6 +41,7 @@
#define KINETIS_TSI_STATUS_OFFSET 0x000c /* Status Register */
#define KINETIS_TSI_CNTR_OFFSET(n) (0x0100+(((n)-1)<<1) /* Counter Register n */
#define KINETIS_TSI_CNTR1_OFFSET 0x0100 /* Counter Register 1 */
#define KINETIS_TSI_CNTR3_OFFSET 0x0104 /* Counter Register 3 */
#define KINETIS_TSI_CNTR5_OFFSET 0x0108 /* Counter Register 5 */
@@ -51,6 +52,7 @@
#define KINETIS_TSI_CNTR15_OFFSET 0x011c /* Counter Register 15 */
#define KINETIS_TSI_THRESHLD_OFFSET(n) (0x0120+((n)<<2)) /* Channel n threshold register */
#define KINETIS_TSI_THRESHLD0_OFFSET 0x0120 /* Channel 0 threshold register */
#define KINETIS_TSI_THRESHLD1_OFFSET 0x0124 /* Channel 1 threshold register */
#define KINETIS_TSI_THRESHLD2_OFFSET 0x0128 /* Channel 2 threshold register */
@@ -68,7 +70,7 @@
#define KINETIS_TSI_THRESHLD14_OFFSET 0x0158 /* Channel 14 threshold register */
#define KINETIS_TSI_THRESHLD15_OFFSET 0x015c /* Channel 15 threshold register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_TSI0_GENCS (KINETIS_TSI0_BASE+KINETIS_TSI_GENCS_OFFSET)
#define KINETIS_TSI0_SCANC (KINETIS_TSI0_BASE+KINETIS_TSI_SCANC_OFFSET)
@@ -103,7 +105,7 @@
#define KINETIS_TSI0_THRESHLD14 (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD14_OFFSET)
#define KINETIS_TSI0_THRESHLD15 (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD15_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* General Control and Status Register */
@@ -117,7 +119,7 @@
#define TSI_GENCS_SWTS (1 << 8) /* Bit 8: Software trigger start */
#define TSI_GENCS_SCNIP (1 << 9) /* Bit 9: Scan-in-progress status */
/* Bits 10-11: Reserved */
#define TSI_GENCS_OVRF (1 << 12) /* Bit 12: Overrun error flag
#define TSI_GENCS_OVRF (1 << 12) /* Bit 12: Overrun error flag */
#define TSI_GENCS_EXTERF (1 << 13) /* Bit 13: External electrode error occurred */
#define TSI_GENCS_OUTRGF (1 << 14) /* Bit 14: Out of Range Flag */
#define TSI_GENCS_EOSF (1 << 15) /* Bit 15: End of scan flag */
@@ -131,9 +133,11 @@
# define TSI_GENCS_PS_DIV32 (5 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 32 */
# define TSI_GENCS_PS_DIV64 (6 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 64 */
# define TSI_GENCS_PS_DIV128 (7 << TSI_GENCS_PS_SHIFT) /* Electrode oscillator / 128 */
#define TSI_GENCS_NSCN_SHIFT (19) /* Bits 19-23: Number of Consecutive Scans per Electrode */
#define TSI_GENCS_NSCN_MASK (31 << TSI_GENCS_NSCN_SHIFT)
# define TSI_GENCS_NSCN_TIMES(n) (((n)-1) << TSI_GENCS_NSCN_SHIFT) /* n times per electrode, n=1..32 */
#define TSI_GENCS_LPSCNITV_SHIFT (24) /* Bits 24-27: TSI Low Power Mode Scan Interval */
#define TSI_GENCS_LPSCNITV_MASK (15 << TSI_GENCS_LPSCNITV_SHIFT)
# define TSI_GENCS_LPSCNITV_1MS (0 << TSI_GENCS_LPSCNITV_SHIFT) /* 1 ms scan interval */
@@ -152,8 +156,10 @@
# define TSI_GENCS_LPSCNITV_300MS (13 << TSI_GENCS_LPSCNITV_SHIFT) /* 300 ms scan interval */
# define TSI_GENCS_LPSCNITV_400MS (14 << TSI_GENCS_LPSCNITV_SHIFT) /* 400 ms scan interval */
# define TSI_GENCS_LPSCNITV_500MS (15 << TSI_GENCS_LPSCNITV_SHIFT) /* 500 ms scan interval */
#define TSI_GENCS_LPCLKS (1 << 28) /* Bit 28: Low Power Mode Clock Source Selection */
/* Bits 29-31: Reserved */
/* SCAN control register */
#define TSI_SCANC_AMPSC_SHIFT (0) /* Bits 0-2: Active mode prescaler */
@@ -166,17 +172,20 @@
# define TSI_SCANC_AMPSC_DIV32 (5 << TSI_SCANC_AMPSC_SHIFT) /* Input clock source / 32 */
# define TSI_SCANC_AMPSC_DIV64 (6 << TSI_SCANC_AMPSC_SHIFT) /* Input clock source / 64 */
# define TSI_SCANC_AMPSC_DIV128 (7 << TSI_SCANC_AMPSC_SHIFT) /* Input clock source / 128 */
#define TSI_SCANC_AMCLKS_SHIFT (3) /* Bits 3-4: Active mode clock source */
#define TSI_SCANC_AMCLKS_MASK (3 << TSI_SCANC_AMCLKS_SHIFT)
# define TSI_SCANC_AMCLKS_BUSCLK (0 << TSI_SCANC_AMCLKS_SHIFT) /* Bus Clock */
# define TSI_SCANC_AMCLKS_MCGIRCLK (1 << TSI_SCANC_AMCLKS_SHIFT) /* MCGIRCLK */
# define TSI_SCANC_AMCLKS_OSCERCLK (2 << TSI_SCANC_AMCLKS_SHIFT) /* OSCERCLK */
#define TSI_SCANC_AMCLKDIV (1 << 5) /* Bit 5: Active mode clock divider */
/* Bits 6-7: Reserved */
#define TSI_SCANC_SMOD_SHIFT (8) /* Bits 8-15: Scan modulo */
#define TSI_SCANC_SMOD_MASK (0xff << TSI_SCANC_SMOD_SHIFT)
# define TSI_SCANC_SMOD_CONTINUOUS (0 << TSI_SCANC_SMOD_SHIFT)
# define TSI_SCANC_SMOD(n) ((n) << TSI_SCANC_SMOD_SHIFT)
#define TSI_SCANC_DELVOL_SHIFT (16) /* Bits 16-18: Delta voltage select applied to analog oscillators */
#define TSI_SCANC_DELVOL_MASK (7 << TSI_SCANC_DELVOL_SHIFT)
# define TSI_SCANC_DELVOL_100MV (0 << TSI_SCANC_DELVOL_SHIFT) /* 100 mV delta voltage */
@@ -187,9 +196,11 @@
# define TSI_SCANC_DELVOL_400MV (5 << TSI_SCANC_DELVOL_SHIFT) /* 400 mV delta voltage */
# define TSI_SCANC_DELVOL_500MV (6 << TSI_SCANC_DELVOL_SHIFT) /* 500 mV delta voltage */
# define TSI_SCANC_DELVOL_600MV (7 << TSI_SCANC_DELVOL_SHIFT) /* 600 mV delta voltage */
#define TSI_SCANC_EXTCHRG_SHIFT (19) /* Bits 19-23: External oscillator charge current select */
#define TSI_SCANC_EXTCHRG_MASK (31 << TSI_SCANC_EXTCHRG_SHIFT)
# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */
#define TSI_SCANC_CAPTRM_SHIFT (24) /* Bits 24-26: Internal capacitance trim value */
#define TSI_SCANC_CAPTRM_MASK (7 << TSI_SCANC_CAPTRM_SHIFT)
#define TSI_SCANC_CAPTRM_0p5PF (0 << TSI_SCANC_CAPTRM_SHIFT) /* 0.5 pF internal reference capacitance */
@@ -200,6 +211,7 @@
#define TSI_SCANC_CAPTRM_1p0PF (5 << TSI_SCANC_CAPTRM_SHIFT) /* 1.0 pF internal reference capacitance */
#define TSI_SCANC_CAPTRM_1p1PF (6 << TSI_SCANC_CAPTRM_SHIFT) /* 1.1 pF internal reference capacitance */
#define TSI_SCANC_CAPTRM_1p2PF (7 << TSI_SCANC_CAPTRM_SHIFT) /* 1.2 pF internal reference capacitance */
#define TSI_SCANC_REFCHRG_SHIFT (27) /* Bits 27-31: Reference oscillator charge current select */
#define TSI_SCANC_REFCHRG_MASK (31 << TSI_SCANC_REFCHRG_SHIFT)
# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */
@@ -222,11 +234,15 @@
#define TSI_PEN13 (1 << 13) /* Bit 13: TSI pin 13 enable */
#define TSI_PEN14 (1 << 14) /* Bit 14: TSI pin 14 enable */
#define TSI_PEN15 (1 << 15) /* Bit 15: TSI pin 15 enable */
#define TSI_PEN(n) (1 << (n)) /* Bit n: TSI pin n enable, n=0..15 */
#define TSI_PEN_LPSP_SHIFT (16) /* Bits 16-19: Low-power scan pin */
#define TSI_PEN_LPSP_MASK (15 << TSI_PEN_LPSP_SHIFT)
# define TSI_PEN_LPSP(n) ((n) << TSI_PEN_LPSP_SHIFT) /* TSI_IN[n] active in low power mode */
/* Bits 20-31: Reserved */
/* Status Register */
#define TSI_STATUS_ORNGF0 (1 << 0) /* Bit 0: Touch Sensing Electrode Out-of-Range Flag 0 */
@@ -245,8 +261,11 @@
#define TSI_STATUS_ORNGF13 (1 << 13) /* Bit 13: Touch Sensing Electrode Out-of-Range Flag 13 */
#define TSI_STATUS_ORNGF14 (1 << 14) /* Bit 14: Touch Sensing Electrode Out-of-Range Flag 14 */
#define TSI_STATUS_ORNGF15 (1 << 15) /* Bit 15: Touch Sensing Electrode Out-of-Range Flag 15 */
#define TSI_STATUS_ORNGF(n) (1 << (n)) /* Bits 0-15: Touch Sensing Electrode Out-of-Range Flag n, n=0..15 */
#define TSI_STATUS_ERROF(n) (1 << ((n)+16)) /* Bits 16-31: TouchSensing Error Flag n, n=0..15 */
#define TSI_STATUS_ERROF0 (1 << 16) /* Bit 16: TouchSensing Error Flag 0 */
#define TSI_STATUS_ERROF1 (1 << 17) /* Bit 17: TouchSensing Error Flag 1 */
#define TSI_STATUS_ERROF2 (1 << 18) /* Bit 18: TouchSensing Error Flag 2 */
@@ -281,16 +300,16 @@
#define TSI_THRESHLD_LTHH_SHIFT (16) /* Bits 16-31: Low threshold value */
#define TSI_THRESHLD_LTHH_MASK (0xffff << TSI_THRESHLD_LTHH_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H */
arch/arm/src/kinetis/hardware/kinetis_usbdcd.h
+25 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_usbdcd.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */
#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */
@@ -47,7 +47,7 @@
# define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */
#endif
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_USBDCD_CONTROL (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CONTROL_OFFSET)
#define KINETIS_USBDCD_CLOCK (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CLOCK_OFFSET)
@@ -61,7 +61,7 @@
# define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Control Register */
#define USBDCD_CONTROL_IACK (1 << 0) /* Bit 0: Interrupt Acknowledge */
@@ -73,13 +73,16 @@
#define USBDCD_CONTROL_START (1 << 24) /* Bit 24: Start Change Detection Sequence */
#define USBDCD_CONTROL_SR (1 << 25) /* Bit 25: Software Reset */
/* Bits 26-31: Reserved */
/* Clock Register */
#define USBDCD_CLOCK_UNIT (1 << 0) /* Bit 0: Unit of measurement encoding for Clock Speed */
/* Bit 1: Reserved */
#define USBDCD_CLOCK_SPEED_SHIFT (2) /* Bits 2-11: Value of Clock Speed */
#define USBDCD_CLOCK_SPEED_MASK (0x3ff << USBDCD_CLOCK_SPEED_SHIFT)
/* Bits 12-31: Reserved */
/* Status Register */
/* Bits 0-15: Reserved */
#define USBDCD_STATUS_SEQ_RES_SHIFT (16) /* Bits 16-17: Charger Detection Sequence Results */
#define USBDCD_STATUS_SEQ_RES_MASK (3 << USBDCD_STATUS_SEQ_RES_SHIFT)
@@ -87,16 +90,19 @@
# define USBDCD_STATUS_SEQ_RES_STD (1 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Standard host */
# define USBDCD_STATUS_SEQ_RES_CHGPORT (2 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Charging port */
# define USBDCD_STATUS_SEQ_RES_DEDCTD (3 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Dedicated charge */
#define USBDCD_STATUS_SEQ_STAT_SHIFT (18) /* Bits 18-19: Charger Detection Sequence Stat */
#define USBDCD_STATUS_SEQ_STAT_MASK (3 << USBDCD_STATUS_SEQ_STAT_SHIFT)
# define USBDCD_STATUS_SEQ_STAT_DISAB (0 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Not enabled or data pins not detected */
# define USBDCD_STATUS_SEQ_STAT_DATPIN (1 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Data pin contact detection complete */
# define USBDCD_STATUS_SEQ_STAT_CHGDET (2 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger detection is complete */
# define USBDCD_STATUS_SEQ_STAT_CHGTYPE (3 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger type detection complete */
#define USBDCD_STATUS_ERR (1 << 20) /* Bit 20: Error Flag */
#define USBDCD_STATUS_TO (1 << 21) /* Bit 21: Timeout Flag */
#define USBDCD_STATUS_ACTIVE (1 << 22) /* Bit 22: Active Status Indicator */
/* Bits 23-31: Reserved */
/* TIMER0 Register */
#define USBDCD_TIMER0_TUNITCON_SHIFT (0) /* Bits 0-11: Unit Connection Timer Elapse (in ms) */
@@ -105,6 +111,7 @@
#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16) /* Bits 16-25: Sequence Initiation Time */
#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3ff << USBDCD_TIMER0_TSEQ_INIT_SHIFT)
/* Bits 26-31: Reserved */
/* TIMER1 Register */
#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0) /* Bits 0-9: Time Period Comparator Enabled */
@@ -113,7 +120,9 @@
#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16) /* Bits 16-25: Time Period to Debounce D+ Signal */
#define USBDCD_TIMER1_TDCD_DBNC__MASK (0x3ff << USBDCD_TIMER1_TDCD_DBNC_SHIFT)
/* Bits 26-31: Reserved */
/* TIMER2 Register */
/* Bits 26-31: Reserved */
#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16) /* Bits 16-25: Time Period Before Enabling D+ Pullup */
#define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3ff << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)
@@ -121,16 +130,16 @@
#define USBDCD_TIMER2_CHECK_DM_SHIFT (0) /* Bits 0-3: Time Before Check of D- Line */
#define USBDCD_TIMER2_CHECK_DM_MASK (15 << USBDCD_TIMER2_CHECK_DM_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H */
arch/arm/src/kinetis/hardware/kinetis_usbhs.h
+458 -456
View File
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