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Name change: Change Cortex-M3 naming to ARMv7-M naming so support Cortex-M4

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3846 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-08-05 21:57:49 +00:00
parent 6002821387
commit f93b962f28
38 changed files with 316 additions and 328 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/README.txt
+2 -2
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@@ -144,8 +144,8 @@ arch/arm - ARM-based micro-controllers
arch/arm/src/arm and arch/arm/include/arm
Common ARM-specific logic
arch/arm/src/cortexm3 and arch/arm/include/cortexm3
Common Cortex-M3 logic
arch/arm/src/armv7-m and arch/arm/include/armv7-m
Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
arch/arm/include/c5471 and arch/arm/src/c5471
TI TMS320C5471 (also called TMS320DM180 or just C5471).
arch/arm/include/cortexm3/irq.h → arch/arm/include/armv7-m/irq.h
+4 -4
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/cortexm3/irq.h
* arch/arm/include/armv7-m/irq.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,8 +37,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
#define __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
/****************************************************************************
* Included Files
@@ -312,5 +312,5 @@ extern "C" {
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H */
arch/arm/include/cortexm3/syscall.h → arch/arm/include/armv7-m/syscall.h
+4 -4
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/cortexm3/syscall.h
* arch/arm/include/armv7-m/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,8 +37,8 @@
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H
#define __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
/****************************************************************************
* Included Files
@@ -239,5 +239,5 @@ extern "C" {
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H */
arch/arm/include/irq.h
+3 -3
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@@ -53,11 +53,11 @@
#include <arch/chip/irq.h>
/* Include ARM architecture-specific IRQ definitions (including register
* save structure and irqsave()/irqrestore() macros
* save structure and irqsave()/irqrestore() macros)
*/
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/irq.h>
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# include <arch/armv7-m/irq.h>
#else
# include <arch/arm/irq.h>
#endif
arch/arm/include/syscall.h
+2 -2
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@@ -46,8 +46,8 @@
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/syscall.h>
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# include <arch/armv7-m/syscall.h>
#else
# include <arch/arm/syscall.h>
#endif
arch/arm/src/Makefile
+6 -2
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@@ -37,11 +37,15 @@
-include chip/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(CONFIG_ARCH_CORTEXM3),y)
ARCH_SUBDIR = cortexm3
ifeq ($(CONFIG_ARCH_CORTEXM3),y) /* Cortex-M3 is ARMv7-M */
ARCH_SUBDIR = armv7-m
else
ifeq ($(CONFIG_ARCH_CORTEXM4),y) /* Cortex-M4 is ARMv7E-M */
ARCH_SUBDIR = armv7-m
else
ARCH_SUBDIR = arm
endif
endif
ifeq ($(WINTOOL),y)
NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx}"
arch/arm/src/cortexm3/exc_return.h → arch/arm/src/armv7-m/exc_return.h
+1 -1
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@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/exc_return.h
* arch/arm/src/armv7-m/exc_return.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/mpu.h → arch/arm/src/armv7-m/mpu.h
+1 -1
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@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/mpu.h
* arch/arm/src/armv7-m/mpu.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/nvic.h → arch/arm/src/armv7-m/nvic.h
+220 -220
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File diff suppressed because it is too large Load Diff
arch/arm/src/cortexm3/psr.h → arch/arm/src/armv7-m/psr.h
+29 -29
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@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/cortexm3/psr.h
* arch/arm/src/armv7-m/psr.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
#define __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H
#define __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H
/************************************************************************************
* Included Files
@@ -46,42 +46,42 @@
/* Application Program Status Register (APSR) */
#define CORTEXM3_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
#define CORTEXM3_APSR_V (1 << 28) /* Bit 28: Overflow flag */
#define CORTEXM3_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
#define CORTEXM3_APSR_Z (1 << 30) /* Bit 30: Zero flag */
#define CORTEXM3_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
#define ARMV7M_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
#define ARMV7M_APSR_V (1 << 28) /* Bit 28: Overflow flag */
#define ARMV7M_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
#define ARMV7M_APSR_Z (1 << 30) /* Bit 30: Zero flag */
#define ARMV7M_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
/* Interrupt Program Status Register (IPSR) */
#define CORTEXM3_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
#define CORTEXM3_IPSR_ISR_MASK (0x1ff << CORTEXM3_IPSR_ISR_SHIFT)
#define ARMV7M_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
#define ARMV7M_IPSR_ISR_MASK (0x1ff << ARMV7M_IPSR_ISR_SHIFT)
/* Execution PSR Register (EPSR) */
#define CORTEXM3_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
#define CORTEXM3_EPSR_ICIIT1_MASK (3 << CORTEXM3_EPSR_ICIIT1_SHIFT)
#define CORTEXM3_EPSR_T (1 << 24) /* Bit 24: T-bit */
#define CORTEXM3_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
#define CORTEXM3_EPSR_ICIIT2_MASK (3 << CORTEXM3_EPSR_ICIIT2_SHIFT)
#define ARMV7M_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
#define ARMV7M_EPSR_ICIIT1_MASK (3 << ARMV7M_EPSR_ICIIT1_SHIFT)
#define ARMV7M_EPSR_T (1 << 24) /* Bit 24: T-bit */
#define ARMV7M_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
#define ARMV7M_EPSR_ICIIT2_MASK (3 << ARMV7M_EPSR_ICIIT2_SHIFT)
/* Save xPSR bits */
#define CORTEXM3_XPSR_ISR_SHIFT CORTEXM3_IPSR_ISR_SHIFT
#define CORTEXM3_XPSR_ISR_MASK CORTEXM3_IPSR_ISR_MASK
#define CORTEXM3_XPSR_ICIIT1_SHIFT CORTEXM3_EPSR_ICIIT1_SHIFT/
#define CORTEXM3_XPSR_ICIIT1_MASK CORTEXM3_EPSR_ICIIT1_MASK
#define CORTEXM3_XPSR_T CORTEXM3_EPSR_T
#define CORTEXM3_XPSR_ICIIT2_SHIFT CORTEXM3_EPSR_ICIIT2_SHIFT
#define CORTEXM3_XPSR_ICIIT2_MASK CORTEXM3_EPSR_ICIIT2_MASK
#define CORTEXM3_XPSR_Q CORTEXM3_APSR_Q
#define CORTEXM3_XPSR_V CORTEXM3_APSR_V
#define CORTEXM3_XPSR_C CORTEXM3_APSR_C
#define CORTEXM3_XPSR_Z CORTEXM3_APSR_Z
#define CORTEXM3_XPSR_N CORTEXM3_APSR_N
#define ARMV7M_XPSR_ISR_SHIFT ARMV7M_IPSR_ISR_SHIFT
#define ARMV7M_XPSR_ISR_MASK ARMV7M_IPSR_ISR_MASK
#define ARMV7M_XPSR_ICIIT1_SHIFT ARMV7M_EPSR_ICIIT1_SHIFT/
#define ARMV7M_XPSR_ICIIT1_MASK ARMV7M_EPSR_ICIIT1_MASK
#define ARMV7M_XPSR_T ARMV7M_EPSR_T
#define ARMV7M_XPSR_ICIIT2_SHIFT ARMV7M_EPSR_ICIIT2_SHIFT
#define ARMV7M_XPSR_ICIIT2_MASK ARMV7M_EPSR_ICIIT2_MASK
#define ARMV7M_XPSR_Q ARMV7M_APSR_Q
#define ARMV7M_XPSR_V ARMV7M_APSR_V
#define ARMV7M_XPSR_C ARMV7M_APSR_C
#define ARMV7M_XPSR_Z ARMV7M_APSR_Z
#define ARMV7M_XPSR_N ARMV7M_APSR_N
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H */
#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H */
arch/arm/src/cortexm3/svcall.h → arch/arm/src/armv7-m/svcall.h
+1 -1
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@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/svcall.h
* arch/arm/src/armv7-m/svcall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_assert.c → arch/arm/src/armv7-m/up_assert.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_assert.c
* arch/arm/src/armv7-m/up_assert.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_blocktask.c → arch/arm/src/armv7-m/up_blocktask.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_blocktask.c
* arch/arm/src/armv7-m/up_blocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_copystate.c → arch/arm/src/armv7-m/up_copystate.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_copystate.c
* arch/arm/src/armv7-m/up_copystate.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_doirq.c → arch/arm/src/armv7-m/up_doirq.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_doirq.c
* arch/arm/src/armv7-m/up_doirq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_fullcontextrestore.S → arch/arm/src/armv7-m/up_fullcontextrestore.S
+1 -1
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@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/up_fullcontextrestore.S
* arch/arm/src/armv7-m/up_fullcontextrestore.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_hardfault.c → arch/arm/src/armv7-m/up_hardfault.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_hardfault.c
* arch/arm/src/armv7-m/up_hardfault.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_initialstate.c → arch/arm/src/armv7-m/up_initialstate.c
+3 -3
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@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_initialstate.c
* arch/arm/src/armv7-m/up_initialstate.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -99,7 +99,7 @@ void up_initial_state(_TCB *tcb)
/* Specify thumb mode */
xcp->regs[REG_XPSR] = CORTEXM3_XPSR_T;
xcp->regs[REG_XPSR] = ARMV7M_XPSR_T;
/* If this task is running PIC, then set the PIC base register to the
* address of the allocated D-Space region.
arch/arm/src/cortexm3/up_memfault.c → arch/arm/src/armv7-m/up_memfault.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_memfault.c
* arch/arm/src/armv7-m/up_memfault.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_mpu.c → arch/arm/src/armv7-m/up_mpu.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_mpu.c
* arch/arm/src/armv7-m/up_mpu.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_releasepending.c → arch/arm/src/armv7-m/up_releasepending.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_releasepending.c
* arch/arm/src/armv7-m/up_releasepending.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_reprioritizertr.c → arch/arm/src/armv7-m/up_reprioritizertr.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_reprioritizertr.c
* arch/arm/src/armv7-m/up_reprioritizertr.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_saveusercontext.S → arch/arm/src/armv7-m/up_saveusercontext.S
+1 -1
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@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/up_saveusercontext.S
* arch/arm/src/armv7-m/up_saveusercontext.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_schedulesigaction.c → arch/arm/src/armv7-m/up_schedulesigaction.c
+4 -4
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@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_schedulesigaction.c
* arch/arm/src/armv7-m/up_schedulesigaction.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -164,7 +164,7 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
current_regs[REG_PC] = (uint32_t)up_sigdeliver;
current_regs[REG_PRIMASK] = 1;
current_regs[REG_XPSR] = CORTEXM3_XPSR_T;
current_regs[REG_XPSR] = ARMV7M_XPSR_T;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
@@ -198,7 +198,7 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PRIMASK] = 1;
tcb->xcp.regs[REG_XPSR] = CORTEXM3_XPSR_T;
tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
}
irqrestore(flags);
arch/arm/src/cortexm3/up_sigdeliver.c → arch/arm/src/armv7-m/up_sigdeliver.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_sigdeliver.c
* arch/arm/src/armv7-m/up_sigdeliver.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_svcall.c → arch/arm/src/armv7-m/up_svcall.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_svcall.c
* arch/arm/src/armv7-m/up_svcall.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_switchcontext.S → arch/arm/src/armv7-m/up_switchcontext.S
+1 -1
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@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/up_switchcontext.S
* arch/arm/src/armv7-m/up_switchcontext.S
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/cortexm3/up_unblocktask.c → arch/arm/src/armv7-m/up_unblocktask.c
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_unblocktask.c
* arch/arm/src/armv7-m/up_unblocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
arch/arm/src/common/up_internal.h
+5 -5
View File
@@ -82,7 +82,7 @@
* a referenced is passed to get the state from the TCB.
*/
#ifdef CONFIG_ARCH_CORTEXM3
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# define up_savestate(regs) up_copystate(regs, (uint32_t*)current_regs)
# define up_restorestate(regs) (current_regs = regs)
#else
@@ -121,7 +121,7 @@ extern uint32_t g_heapbase;
/* Address of the saved user stack pointer */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
# ifdef CONFIG_ARCH_CORTEXM3
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern void g_intstackbase;
# else
extern uint32_t g_userstack;
@@ -180,14 +180,14 @@ extern void up_sigdeliver(void);
extern void up_irqinitialize(void);
extern void up_maskack_irq(int irq);
#ifdef CONFIG_ARCH_CORTEXM3
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern uint32_t *up_doirq(int irq, uint32_t *regs);
extern int up_svcall(int irq, FAR void *context);
extern int up_hardfault(int irq, FAR void *context);
extern int up_memfault(int irq, FAR void *context);
#else /* CONFIG_ARCH_CORTEXM3 */
#else /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_doirq(int irq, uint32_t *regs);
#ifdef CONFIG_PAGING
@@ -202,7 +202,7 @@ extern void up_prefetchabort(uint32_t *regs);
extern void up_syscall(uint32_t *regs);
extern void up_undefinedinsn(uint32_t *regs);
#endif /* CONFIG_ARCH_CORTEXM3 */
#endif /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_vectorundefinsn(void);
extern void up_vectorswi(void);
arch/arm/src/kinetis/kinetis_memorymap.h
+2 -2
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@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_memorymap.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -61,7 +61,7 @@
# define KINETIS_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define KINETIS_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define KINETIS_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
#define KINETIS_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
#define KINETIS_CORTEXM4_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define KINETIS_SCS_BASE 0xe000e000
#define KINETIS_DEBUGMCU_BASE 0xe0042000
arch/arm/src/lm3s/lm3s_irq.c
+2 -2
View File
@@ -320,7 +320,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM3S_IRQ_MEMFAULT);
#endif
@@ -329,7 +329,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);
arch/arm/src/lpc17xx/lpc17_irq.c
+2 -2
View File
@@ -308,7 +308,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LPC17_IRQ_MEMFAULT);
#endif
@@ -317,7 +317,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(LPC17_IRQ_NMI, lpc17_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault);
arch/arm/src/lpc17xx/lpc17_memorymap.h
+1 -1
View File
@@ -61,7 +61,7 @@
# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define LPC17_SCS_BASE 0xe000e000
#define LPC17_DEBUGMCU_BASE 0xe0042000
arch/arm/src/sam3u/sam3u_irq.c
+2 -2
View File
@@ -301,7 +301,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM3U_IRQ_MEMFAULT);
#endif
@@ -310,7 +310,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);
arch/arm/src/stm32/chip/stm32_memorymap.h
+1 -1
View File
@@ -125,7 +125,7 @@
#define STM32_FSMC_BASE 0xa0000000
/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
* address range
*/
arch/arm/src/stm32/stm32_irq.c
+2 -2
View File
@@ -335,7 +335,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
up_enable_irq(STM32_IRQ_MEMFAULT);
#endif
@@ -344,7 +344,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(STM32_IRQ_NMI, stm32_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);
arch/hc/include/syscall.h
+4 -12
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/syscall.h
* arch/hc/include/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,21 +37,13 @@
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef _ARCH_ARM_INCLUDE_SYSCALL_H
#define _ARCH_ARM_INCLUDE_SYSCALL_H
#ifndef _ARCH_HC_INCLUDE_SYSCALL_H
#define _ARCH_HC_INCLUDE_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/irq.h>
#else
# include <arch/arm/irq.h>
#endif
/****************************************************************************
* Definitions
****************************************************************************/
@@ -86,5 +78,5 @@ extern "C" {
#endif
#endif
#endif /* _ARCH_ARM_INCLUDE_SYSCALL_H */
#endif /* _ARCH_HC_INCLUDE_SYSCALL_H */
arch/z80/include/syscall.h
-8
View File
@@ -44,14 +44,6 @@
* Included Files
****************************************************************************/
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/syscall.h>
#else
# include <arch/arm/syscall.h>
#endif
/****************************************************************************
* Definitions
****************************************************************************/