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SAMA5 GMAC and GMII support is code complete and ready for test

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This commit is contained in:
Gregory Nutt
2013-09-27 13:12:04 -06:00
parent e1f9d22482
commit f7e4f25760
8 changed files with 381 additions and 392 deletions
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TODO
+6 -1
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@@ -1,4 +1,4 @@
NuttX TODO List (Last updated August 2, 2013)
NuttX TODO List (Last updated September 27, 2013)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -749,6 +749,11 @@ o Network (net/, drivers/net)
connection (lipaddr) and verifying that it is in the subnet
served by the driver.
Another issue: When sending packets to another subnet, the
current logic falls back and uses ETH0 if it cannot find the
device for the subnet. That lookup would need to be smarter...
perhaps it needs a routing table.
Status: Open. Nothing will probably be done until I have a platform
with two network interfaces that I need to support.
Priority: Medium, The feature is not important, but it is important
arch/arm/src/sama5/Kconfig
+24 -97
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@@ -314,121 +314,48 @@ config SAMA5_GMAC_PHYINIT
provide sam_phyinitialize(); The SAMA5 GMAC driver will call this function
one time before it first uses the PHY.
config SAMA5_GMAC_GMII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface (vs RMII).
config SAMA5_GMAC_RGMII
bool
default y if !SAMA5_GMAC_GMII
default n if SAMA5_GMAC_GMII
config SAMA5_GMAC_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
if !SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_ETHFD
bool "Full duplex"
default n
depends on !SAMA5_GMAC_AUTONEG
---help---
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to
select full duplex mode. Default: half-duplex
choice
prompt "GMAC Speed"
default SAMA5_GMAC_ETH100MBPS
---help---
If autonegation is not used, then you must select the fixed speed
of the PHY
config SAMA5_GMAC_ETH10MBPS
bool "10 Mbps"
---help---
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 10 MBps
speed. Default: 100 Mbps
config SAMA5_GMAC_ETH100MBPS
bool "100 Mbps"
default n
depends on !SAMA5_GMAC_AUTONEG
---help---
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
speed. Default: 100 Mbps
config SAMA5_GMAC_PHYSR
int "PHY Status Register Address (decimal)"
depends on SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_ETH1000MBPS
bool "1000 Mbps"
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 1000 MBps
speed. Default: 100 Mbps
config SAMA5_GMAC_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on SAMA5_GMAC_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config SAMA5_GMAC_PHYSR_SPEED
hex "PHY Speed Mask"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_GMAC_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_GMAC_PHYSR_MODE
hex "PHY Mode Mask"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_GMAC_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config SAMA5_GMAC_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config SAMA5_GMAC_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config SAMA5_GMAC_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config SAMA5_GMAC_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config SAMA5_GMAC_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
endchoice # GMAC speed
endif # !SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_REGDEBUG
bool "Register-Level Debug"
arch/arm/src/sama5/chip/sam_emac.h
+1
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@@ -237,6 +237,7 @@
#define EMAC_INT_WOL (1 << 14) /* Bit 14: Wake On LAN */
#define EMAC_INT_ALL (0x00007cff)
#define EMAC_INT_UNUSED (0xffff8300)
/* Phy Maintenance Register */
arch/arm/src/sama5/chip/sam_gmac.h
+1
View File
@@ -583,6 +583,7 @@
#define GMAC_INT_WOL (1 << 28) /* Bit 28: Wake On LAN (not in IMR) */
#define GMAC_INT_ALL (0x17fcfcff)
#define GMAC_INT_UNUSED (0xe8030300)
/* PHY Maintenance Register */
arch/arm/src/sama5/sam_emac.c
+12 -4
View File
@@ -1307,7 +1307,7 @@ static int sam_emac_interrupt(int irq, void *context)
tsr = sam_getreg(priv, SAM_EMAC_TSR);
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | 0xffc300);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllvdbg("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
@@ -2159,10 +2159,12 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI) >> 10) == MII_OUI_LSB)
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
nllvdbg(" Vendor Model Number: %04x\n", ((phyid2 >> 4) & 0x3f));
nllvdbg(" Model Revision Number: %04x\n", (phyid2 & 7));
nllvdbg(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllvdbg(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
@@ -2570,6 +2572,12 @@ static void sam_txreset(struct sam_emac_s *priv)
txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS - 1].status =
EMACTXD_STA_USED | EMACTXD_STA_WRAP;
/* Flush the entire TX descriptor table to RAM */
cp15_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s));
/* Set the Transmit Buffer Queue Pointer Register */
physaddr = sam_physramaddr((uintptr_t)txdesc);
arch/arm/src/sama5/sam_gmac.c
+281 -271
View File
File diff suppressed because it is too large Load Diff
include/nuttx/net/gmii.h
+47 -16
View File
@@ -64,16 +64,16 @@
#define GMII_EXPANSION MII_EXPANSION /* Auto-negotiation expansion */
#define GMII_NEXTPAGE MII_NEXTPAGE /* Auto-negotiation next page */
#define GMII_LPANEXTPAGE MII_LPANEXTPAGE /* Auto-negotiation link partner received next page */
#define GMII_CTRL1000 9 /* 1000BASE-T control */
#define GMII_STAT1000 10 /* 1000BASE-T status */
#define GMII_PSECR 11 /* PSE Control register */
#define GMII_1000BTCR 9 /* 1000BASE-T control */
#define GMII_1000BTSR 10 /* 1000BASE-T status */
#define GMII_ERCR 11 /* Extend Register - Control */
#define GMII_ERDWR 12 /* Extend Register - Data Write Register */
#define GMII_ERDRR 13 /* Extend Register - Data Read Register */
#define GMII_ESTATUS MII_ESTATUS /* Extended MII status register */
/* Extended Registers: Registers 16-31 may be used for vendor specific abilities */
/* Micrel KSZ9021/31 Vendor Specific Registers */
/* Micrel KSZ9021/31 Vendor Specific Register Addresses */
#define GMII_KSZ90x1_RLPBK 17 /* Remote loopback, LED mode */
#define GMII_KSZ90x1_LINKMD 18 /* LinkMD(c) cable diagnostic */
@@ -83,7 +83,7 @@
#define GMII_KSZ90x1_DBGCTRL1 28 /* Digital debug control 1 */
#define GMII_KSZ90x1_PHYCTRL 31 /* PHY control */
/* Micrel KSZ9021/31 Extended registers */
/* Micrel KSZ9021/31 Extended Register Addresses */
#define GMII_KSZ90x1_CCR 256 /* Common control */
#define GMII_KSZ90x1_SSR 257 /* Strap status */
@@ -130,9 +130,15 @@
/* MII ID2 register bits */
#define GMII_PHYID2_OUI MII_PHYID2_OUI
#define GMII_PHYID2_MODEL MII_PHYID2_MODEL
#define GMII_PHYID2_REV MII_PHYID2_REV
#define GMII_PHYID2_REV_SHIFT MII_PHYID2_REV_SHIFT
#define GMII_PHYID2_REV_MASK MII_PHYID2_REV_MASK
#define GMII_PHYID2_REV(n) MII_PHYID2_REV(n)
#define GMII_PHYID2_MODEL_SHIFT MII_PHYID2_MODEL_SHIFT
#define GMII_PHYID2_MODEL_MASK MII_PHYID2_MODEL
# define GMII_PHYID2_MODEL(n) MII_PHYID2_MODEL(n)
#define GMII_PHYID2_OUI_SHIFT MII_PHYID2_OUI_SHIFT
#define GMII_PHYID2_OUI_MASK MII_PHYID2_OUI_MASK
# define GMII_PHYID2_OUI(n) MII_PHYID2_OUI(n)
/* Advertisement control register bit definitions */
@@ -219,23 +225,48 @@
# define GMII_MMDCONTROL_FUNC_RWINCR MII_MMDCONTROL_FUNC_RWINCR
# define GMII_MMDCONTROL_FUNC_WINCR MII_MMDCONTROL_FUNC_WINCR
/* Extended status register */
/* Extended Status Register */
#define GMII_ESTATUS_1000BASETHALF MII_ESTATUS_1000BASETHALF
#define GMII_ESTATUS_1000BASETFULL MII_ESTATUS_1000BASETFULL
#define GMII_ESTATUS_1000BASEXHALF MII_ESTATUS_1000BASEXHALF
#define GMII_ESTATUS_1000BASEXFULL MII_ESTATUS_1000BASEXFULL
/* Extend Register - Data Write Register */
/* 1000BASE-T Control Register */
/* Bits 0-7: Reserved */
#define GMII_1000BTCR_1000BASETHALF (1 << 8) /* Bit 8: 1000Base-T half duplex able */
#define GMII_1000BTCR_1000BASETFULL (1 << 9) /* Bit 9: 1000Base-T full duplex able */
#define GMII_1000BTCR_MULTIPLE (1 << 10) /* Bit 10: Port type: Prefer multiport device */
#define GMII_1000BTCR_MMASTER (1 << 11) /* Bit 11: Configure PHY as master (manual) */
#define GMII_1000BTCR_MSMC (1 << 12) /* Bit 12: Master/slave manual configuration */
#define GMII_1000BTCR_TESTMODE_SHIFT (13) /* Bits 13-15: Test Mode */
#define GMII_1000BTCR_TESTMODE_MASK (7 << GMII_1000BTCR_TESTMODE_SHIFT)
# define GMII_1000BTCR_MODE_NORMAL (0 << GMII_1000BTCR_TESTMODE_SHIFT)
# define GMII_1000BTCR_TESTMODE(n) ((n) << GMII_1000BTCR_TESTMODE_SHIFT) /* n=1-4 */
#define GMII_ERDWR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */
#define GMII_ERDWR_ADDR_MASK (0xff << GMII_ERDWR_ADDR_SHIFT)
# define GMII_ERDWR_ADDR(n) ((n) << GMII_ERDWR_ADDR_SHIFT)
#define GMII_ERDWR_PAGE (1 << 8) /* Bit 8: Select page for extended register */
/* 1000BASE-T Status Register */
#define GMII_1000BTSR_IDLERR_SHIFT (0) /* Bits 0-7: Idle error count */
#define GMII_1000BTSR_IDLERR_MASK (0xff << GMII_1000BTSR_IDLERR_SHIFT)
/* Bits 8-9: Reserved */
#define GMII_1000BTSR_LP1000BASETHALF (1 << 10) /* Bit 10: Link partner 1000Base-T half duplex able */
#define GMII_1000BTSR_LP1000BASETFULL (1 << 11) /* Bit 11: Link partner 1000Base-T full duplex able */
#define GMII_1000BTSR_RROK (1 << 12) /* Bit 12: Remote receiver OK */
#define GMII_1000BTSR_LROK (1 << 13) /* Bit 13: Local receiver OK */
#define GMII_1000BTSR_MASTER (1 << 14) /* Bit 14: Configuration resolved to master */
#define GMII_1000BTSR_MSFAULT (1 << 15) /* Bit 15: Master/slave fault detected */
/* Extend Register - Control Register */
#define GMII_ERCR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */
#define GMII_ERCR_ADDR_MASK (0xff << GMII_ERCR_ADDR_SHIFT)
# define GMII_ERCR_ADDR(n) ((n) << GMII_ERCR_ADDR_SHIFT)
#define GMII_ERCR_PAGE (1 << 8) /* Bit 8: Select page for extended register */
/* Bits 9-14: Reserved */
#define GMII_ERDWR_READ (0) /* Bit 15: 0=Read extended register */
#define GMII_ERDWR_WRITE (1 << 15) /* Bit 15: 1=Write extended register */
#define GMII_ERCR_READ (0) /* Bit 15: 0=Read extended register */
#define GMII_ERCR_WRITE (1 << 15) /* Bit 15: 1=Write extended register */
/* Extend Register - Data Write Register (16-bit data value) */
/* Extend Register - Data Read Register (16-bit data value) */
/*********************************************************************************************
include/nuttx/net/mii.h
+9 -3
View File
@@ -202,9 +202,15 @@
/* MII ID1 register bits: Bits 3-18 of the Organizationally Unique identifier (OUI) */
/* MII ID2 register bits */
#define MII_PHYID2_OUI 0xfc00 /* Bits 10-15: OUI mask [24:19] */
#define MII_PHYID2_MODEL 0x03f0 /* Bits 4-9: Model number mask */
#define MII_PHYID2_REV 0x000f /* Bits 0-3: Revision number mask */
#define MII_PHYID2_REV_SHIFT (0) /* Bits 0-3: Revision number mask */
#define MII_PHYID2_REV_MASK (15 << MII_PHYID2_REV_SHIFT)
# define MII_PHYID2_REV(n) ((n) << MII_PHYID2_REV_SHIFT)
#define MII_PHYID2_MODEL_SHIFT (4) /* Bits 4-9: Model number mask */
#define MII_PHYID2_MODEL_MASK (0x3f << MII_PHYID2_MODEL_SHIFT)
# define MII_PHYID2_MODEL(n) ((n) << MII_PHYID2_MODEL_SHIFT)
#define MII_PHYID2_OUI_SHIFT (10) /* Bits 10-15: OUI mask [24:19] */
#define MII_PHYID2_OUI_MASK (0x3f << MII_PHYID2_OUI_SHIFT)
# define MII_PHYID2_OUI(n) ((n) << MII_PHYID2_OUI_SHIFT)
/* Advertisement control register bit definitions */