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arch: arm: stm32, stm32f0l0g0, stm32h7, stm32l4, stm32l5: Fix typos.
arch/arm/src/stm32/stm32_foc.c,
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h,
arch/arm/src/stm32h7/stm32_allocateheap.c,
arch/arm/src/stm32h7/stm32_fmc.c,
arch/arm/src/stm32h7/stm32_pmstandby.c,
arch/arm/src/stm32h7/stm32_spi.h,
arch/arm/src/stm32h7/stm32_spi_slave.c,
arch/arm/src/stm32h7/stm32_wwdg.c,
arch/arm/src/stm32l4/stm32l4_adc.h,
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h,
arch/arm/src/stm32l5/stm32l5_gpio.c,
arch/arm/src/stm32l5/stm32l5_gpio.h,
arch/arm/src/stm32l5/stm32l5_irq.c,
arch/arm/src/stm32l5/stm32l5_rcc.c,
arch/arm/src/stm32l5/stm32l5_rcc.h,
arch/arm/src/stm32l5/stm32l5_serial.c, and
arch/arm/src/stm32l5/stm32l5_spi.c:
* Fix typos in comments. No functional changes.
This commit is contained in:
Nathan Hartman
committed by
Gustavo Henrique Nihei
Gustavo Henrique Nihei
parent
3346ba304b
commit
f617c27a8c
@@ -1653,7 +1653,7 @@ static int stm32_foc_adc_handler(int irq, FAR void *context, FAR void *arg)
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STM32_ADC_INT_ACK(adc, pending);
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/* Call interrupt handler if registerd */
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/* Call interrupt handler if registered */
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if (foc_dev->adc_isr != NULL)
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{
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@@ -61,7 +61,7 @@
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# undef HAVE_ADC_VLCD
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#endif
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/* Supprot for Low frequency mode */
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/* Support for Low frequency mode */
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#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
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# define HAVE_ADC_LFM
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@@ -91,7 +91,7 @@
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* - BOARD_SDRAM2_SIZE, if defined, declares the size of SDRAM
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* at address STM32_FMC_BANK6. +1 to CONFIG_MM_REGIONS.
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*
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* - Additionaly, you may use the following options to add one more region
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* - Additionally, you may use the following options to add one more region
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* of memory to system heap:
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*
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* - CONFIG_ARCH_HAVE_HEAP2=y
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@@ -91,7 +91,7 @@
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* BOARD_FMC_SDCR[1..2] - Initial value for SDRAM control registers for SDRAM
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* bank 1-2. Note that some bits in SDCR1 influence both SDRAM banks and
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* are unused in SDCR2!
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* BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registeres for SDRAM
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* BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registers for SDRAM
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* bank 1-2. Note that some bits in SDTR1 influence both SDRAM banks and
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* are unused in SDTR2!
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* BOARD_FMC_SDRAM_REFR_PERIOD - The SDRAM refresh rate period in FMC clocks,
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@@ -69,7 +69,7 @@ void stm32_pmstandby(void)
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{
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uint32_t regval;
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/* Clear the wake-up flags before reseting. */
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/* Clear the wake-up flags before resetting. */
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modifyreg32(STM32_PWR_CPUCR, 0, STM32_PWR_CPUCR_CSSF);
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modifyreg32(STM32_PWR_WKUPCR, 0, STM32_PWR_WKUPC1 | STM32_PWR_WKUPC2 |
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@@ -75,7 +75,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
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* bus number
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*
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* Returned Value:
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* Valid SPI device structure reference on succcess; a NULL on failure
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* Valid SPI device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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@@ -1620,7 +1620,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv)
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* Mode 0: CFG2.CPHA=0 and CFG2.CPOL=0
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* Master: CFG2.MSTR=1
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* 8-bit: CFG1.DSIZE=7
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* MSB tranmitted first: CFG2.LSBFRST=0
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* MSB transmitted first: CFG2.LSBFRST=0
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* Replace NSS with SSI & SSI=1: CR1.SSI=1 CFG2.SSM=1 (prevent MODF err)
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* Two lines full duplex: CFG2.COMM=0
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*/
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@@ -1673,7 +1673,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv)
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nxsem_init(&priv->exclsem, 0, 1);
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#ifdef CONFIG_STM32H7_SPI_DMA
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/* DMA will be started in the interrupt handler, syncronized to the master
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/* DMA will be started in the interrupt handler, synchronized to the master
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* nss
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*/
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@@ -1722,10 +1722,10 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv)
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* Initialize the selected SPI port(bus) to operate as spi slave
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*
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* Input Parameters:
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* Port number (for hardware that has mutiple SPI interfaces)
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* Port number (for hardware that has multiple SPI interfaces)
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*
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* Returned Value:
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* Valid SPI device structure reference on succcess; a NULL on failure
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* Valid SPI device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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@@ -108,7 +108,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr);
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static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv,
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uint8_t window);
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/* Interrupt hanlding *******************************************************/
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/* Interrupt handling *******************************************************/
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static int stm32_interrupt(int irq, FAR void *context, FAR void *arg);
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@@ -530,7 +530,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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* reload = timeout * Fwwdg / 1000 - 1
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*
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* Where
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* timeout is the desired timout in milliseconds
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* timeout is the desired timeout in milliseconds
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* reload is the contents of T{5:0]
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* Fwwdg is the frequency of the WWDG clock
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*/
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@@ -543,7 +543,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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*/
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#if 0
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wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
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wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n",
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wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg);
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#endif
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if (reload <= WWDG_CR_T_MAX || wdgtb == 3)
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@@ -576,7 +576,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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priv->fwwdg = fwwdg;
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priv->reload = reload;
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wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n",
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wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n",
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wdgtb, fwwdg, reload, priv->timeout);
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/* Set WDGTB[1:0] bits according to calculated value */
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@@ -1132,7 +1132,7 @@
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#ifdef CONFIG_STM32L4_ADC_LL_OPS
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/* This structure provides the publicly visable representation of the
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/* This structure provides the publicly visible representation of the
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* "lower-half" ADC driver structure.
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*/
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@@ -291,7 +291,7 @@
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/* PLLSAI1 Configuration register */
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#define RCC_PLLSAI1CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI1 entry clock soure */
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#define RCC_PLLSAI1CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI1 entry clock source */
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#define RCC_PLLSAI1CFG_PLLSRC_MASK (3 << RCC_PLLSAI1CFG_PLLSRC_SHIFT)
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# define RCC_PLLSAI1CFG_PLLSRC_NONE (0 << RCC_PLLSAI1CFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
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# define RCC_PLLSAI1CFG_PLLSRC_MSI (1 << RCC_PLLSAI1CFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
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@@ -339,7 +339,7 @@
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/* PLLSAI2 Configuration register */
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#define RCC_PLLSAI2CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI2 entry clock soure */
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#define RCC_PLLSAI2CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI2 entry clock source */
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#define RCC_PLLSAI2CFG_PLLSRC_MASK (3 << RCC_PLLSAI2CFG_PLLSRC_SHIFT)
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# define RCC_PLLSAI2CFG_PLLSRC_NONE (0 << RCC_PLLSAI2CFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
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# define RCC_PLLSAI2CFG_PLLSRC_MSI (1 << RCC_PLLSAI2CFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
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@@ -93,7 +93,7 @@ const uint32_t g_gpiobase[STM32L5_NPORTS] =
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*
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* Assumptions:
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* This function is called early in the initialization sequence so that
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* no mutual exlusion is necessary.
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* no mutual exclusion is necessary.
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*
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****************************************************************************/
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@@ -112,7 +112,7 @@ void stm32l5_gpioinit(void)
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*
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* Returned Value:
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* OK on success
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* A negated errono valu on invalid port, or when pin is locked as ALT
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* A negated errno value on invalid port, or when pin is locked as ALT
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* function.
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*
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* To-Do: Auto Power Enable
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@@ -155,7 +155,7 @@
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/* If the pin is a GPIO digital output, then this identifies the initial
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* output value. If the pin is an input, this bit is overloaded to provide
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* the qualifier to distinquish input pull-up and -down:
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* the qualifier to distinguish input pull-up and -down:
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*
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* 1111 1111 1100 0000 0000
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* 9876 5432 1098 7654 3210
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@@ -133,8 +133,8 @@ static void stm32l5_dumpnvic(const char *msg, int irq)
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* stm32l5_dbgmonitor, stm32l5_pendsv, stm32l5_reserved
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*
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* Description:
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* Handlers for various execptions. None are handled and all are fatal
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* error conditions. The only advantage these provided over the default
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* Handlers for various exceptions. None are handled and all are fatal
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* error conditions. The only advantage these provide over the default
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* unexpected interrupt handler is that they provide a diagnostic output.
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*
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****************************************************************************/
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@@ -198,9 +198,9 @@ void stm32l5_clockconfig(void)
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* operation
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* re-enable/re-start the PLL
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*
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* This functional performs a subset of the operations performed by
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* This function performs a subset of the operations performed by
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* stm32l5_clockconfig()
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* reset the currenlty enabled peripheral clocks.
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* reset the currently enabled peripheral clocks.
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*
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* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
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* clocking will be enabled by an externally provided, board-specific
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@@ -131,7 +131,7 @@ void stm32l5_clockconfig(void);
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*
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* Description:
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* Any STM32L5 board may replace the "standard" board clock configuration
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* logic with its own, custom clock cofiguration logic.
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* logic with its own, custom clock configuration logic.
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*
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****************************************************************************/
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@@ -163,9 +163,9 @@ void stm32l5_stdclockconfig(void);
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* operation: When re-awakening from deep-sleep modes, it is necessary to
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* re-enable/re-start the PLL
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*
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* This functional performs a subset of the operations performed by
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* This function performs a subset of the operations performed by
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* stm32l5_clockconfig(): It does not reset any devices, and it does not
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* reset the currenlty enabled peripheral clocks.
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* reset the currently enabled peripheral clocks.
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*
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* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
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* clocking will be enabled by an externally provided, board-specific
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@@ -1795,9 +1795,9 @@ static int stm32l5serial_interrupt(int irq, FAR void *context, FAR void *arg)
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* " " USART_ISR_ORE Overrun Error Detected
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* USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used)
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*
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* NOTE: Some of these status bits must be cleared by explicity writing
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* one to the ICR register: USART_ICR_CTSCF, USART_ICR_LBDCF. Note of
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* those are currently being used.
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* NOTE: Some of these status bits must be cleared by explicitly
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* writing one to the ICR register: USART_ICR_CTSCF, USART_ICR_LBDCF.
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* Note of those are currently being used.
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*/
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#ifdef HAVE_RS485
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@@ -1727,7 +1727,7 @@ static void spi_bus_initialize(FAR struct stm32l5_spidev_s *priv)
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* Mode 0: CR1.CPHA=0 and CR1.CPOL=0
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* Master: CR1.MSTR=1
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* 8-bit: CR2.DS=7
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* MSB tranmitted first: CR1.LSBFIRST=0
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* MSB transmitted first: CR1.LSBFIRST=0
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* Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1
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* (prevents MODF error)
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* Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care)
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