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Documentation/arm: Add STM32N6 and Nucleo-N657X0-Q
Add documentation for the STMicro STM32N6 chip family and the
Nucleo-N657X0-Q development board introduced in the previous two
commits.
- platforms/arm/stm32n6/index.rst
Chip overview: core, peripherals supported in the initial
port, and a pointer to the board page.
- platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst
Board page, structured per Documentation/contributing/
doc_templates/board.rst: hardware summary, user LED and
button pin map, the two shipped configs (nsh, ostest),
and the DEV-mode flash recipe used to load NuttX into
AXISRAM via ST-LINK.
- platforms/arm/stm32n6/boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg
Photograph of the board, referenced from the board page.
The pages are picked up by the existing glob-based toctree in
Documentation/platforms/arm/index.rst, no parent index changes are
required.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
This commit is contained in:
ImBonkers
Alan C. Assis
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==================
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ST Nucleo-N657X0-Q
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==================
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.. tags:: chip:stm32, chip:stm32n6, chip:stm32n657
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.. figure:: nucleo-n657x0-q.jpg
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:width: 50 %
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:align: center
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:alt: STMicro Nucleo-N657X0-Q development board
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Nucleo-N657X0-Q
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The STM Nucleo-N657X0-Q is a development
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board for the STM32N657X0H3Q, an Arm Cortex-M55 with 4 MiB of on-chip
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AXISRAM, an on-chip Neural-ART NPU, and no internal flash. In
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production, code is fetched from external XSPI NOR flash and in
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development, the image is loaded directly into AXISRAM by the on-board
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ST-LINK-V3EC. Refer to the
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https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html website
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for the full product page.
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Features
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========
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* STM32N657X0H3Q MCU (Arm Cortex-M55, up to 800 MHz)
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* On-chip Neural-ART NPU accelerator
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* 4 MiB on-chip AXISRAM (no internal flash)
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* External XSPI NOR flash interface
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* On-board ST-LINK-V3EC
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* 3 user LEDs (LD5 red, LD6 green, LD7 blue), plus status LEDs
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(LD1 5V_PWR, LD4 PWR, LD9 COM)
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* User pushbutton (B1) and reset pushbutton
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* 32.768 kHz crystal oscillator
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* USB Type-C connectors (ST-LINK and user)
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* ST Zio connector
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* ST morpho headers
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.. warning::
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This is the initial NuttX port for the STM32N6 family. The supported
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peripheral set is intentionally minimal: USART1 (the ST-LINK VCOM
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console), GPIO, RCC, PWR, and the SysTick-based timer. Other on-chip
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peripherals and on-board features (XSPI flash boot, networking,
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user LEDs/buttons, USB, MIPI, NPU, etc) are not yet wired up. The CPU is
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currently clocked at 200 MHz from PLL1. Raising it to the standard
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600 / 800 MHz operating points is deferred to a follow-up change.
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Buttons and LEDs
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================
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The board exposes three user LEDs and a user pushbutton, but the
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initial NuttX port does not yet ship ``userleds`` or ``buttons``
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drivers. The hardware wiring is summarised here so a follow-up
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driver can be written against an authoritative pin map:
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===== ======= ======== ======================================
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ID Color GPIO Notes
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===== ======= ======== ======================================
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LD5 Red PG10 Active low
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LD6 Green PG0 Active low
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LD7 Blue PG8 Active low
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B1 Blue PC13 Active high, external pull-down
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===== ======= ======== ======================================
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Pin Mapping
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===========
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The shipped configurations map only the pins required for the serial
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console. All other GPIOs retain their reset state and are free for
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application use.
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===== ============= ======= =================================
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Pin Signal AF Notes
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===== ============= ======= =================================
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PE5 USART1_TX AF7 Routed to ST-LINK VCOM (host RX)
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PE6 USART1_RX AF7 Routed to ST-LINK VCOM (host TX)
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===== ============= ======= =================================
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Power Supply
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============
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The board is powered over either USB Type-C connector (ST-LINK or
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user) at 5 V. On-board regulators derive the MCU and I/O rails. See
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the ST user manual for the full power tree and jumper selection.
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Installation
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============
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Two host tools are required:
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* A bare-metal Arm toolchain, e.g. the GNU Arm Embedded toolchain
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(``arm-none-eabi-gcc``) packaged by most Linux distributions or
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available from Arm.
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* `STM32CubeProgrammer
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<https://www.st.com/en/development-tools/stm32cubeprog.html>`_ for
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loading images into AXISRAM over the on-board ST-LINK.
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Building NuttX
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==============
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From the top of the NuttX source tree:
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.. code:: console
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$ ./tools/configure.sh nucleo-n657x0-q:<config>
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$ make
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At the end of the build, ``nuttx.bin`` is the raw image that the
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flashing step below loads into AXISRAM.
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The toolchain selection can be changed via ``make menuconfig``.
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Flashing
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========
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The board boots in development mode: the on-board ST-LINK loads the
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image directly into AXISRAM at ``0x34000400`` (the first 1 KiB is
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reserved for the boot ROM header) and starts execution there. Signed
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XSPI flash boot via a first-stage bootloader is not yet supported.
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Use STM32CubeProgrammer's CLI to load and run ``nuttx.bin``:
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.. code:: console
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$ STM32_Programmer_CLI -c port=SWD mode=UR -halt \
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-d nuttx.bin 0x34000400 \
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-w32 0xE000ED08 0x34000400 \
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-g 0x34000400
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The ``-w32`` write retargets VTOR to the SRAM image before the ``-g``
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jump, so the Cortex-M55 starts from the NuttX vector table rather
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than the boot ROM's.
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Configurations
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==============
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Each configuration is selected with::
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$ ./tools/configure.sh nucleo-n657x0-q:<config>
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Unless otherwise noted, console output is accessed via ST-LINK
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(USART1) at 115200 8N1.
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nsh
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---
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Minimal NuttShell configuration. Boots into the NSH prompt via
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ST-LINK and exposes the built-in commands plus
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:doc:`getprime </applications/testing/getprime/index>`-style apps
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selectable via ``make menuconfig``.
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ostest
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------
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Builds the NSH configuration with :doc:`apps/testing/ostest
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</applications/testing/ostest/index>` added. Run ``ostest`` from the
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NSH prompt to exercise the core RTOS primitives (tasks, mutexes,
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semaphores, signals, message queues, POSIX timers, condition
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variables, scheduling). Used as the smoke test.
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License Exceptions
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==================
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None.
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References
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==========
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* [RM0486] STM32N647/657xx Arm\ :sup:`®`-based 32-bit MCUs reference manual
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* [UM3417] STM32N6 Nucleo-144 board (MB1940) user manual
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* [ES0620] STM32N657 errata sheet
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Binary file not shown.
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==========
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ST STM32N6
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==========
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This is a port of NuttX to the STM32N6 family.
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The STM32N6 is a chip based on the Arm Cortex-M55.
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Development is performed on the Nucleo-N657X0-Q. At this time only the
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STM32N657X0 is supported. Kconfig will need updates to support other
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MCUs in the family.
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Supported MCUs
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==============
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=========== ======= ================
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MCU Support Note
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=========== ======= ================
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STM32N645 No
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STM32N647 No
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STM32N655 No
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STM32N657 Yes STM32N657X0 only
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=========== ======= ================
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Peripheral Support
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==================
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The following list indicates peripherals supported in NuttX:
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========== ======= ===============================================
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Peripheral Support Notes
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========== ======= ===============================================
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GPIO Yes
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PWR Yes Partial.
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RCC Yes PLL1 clock tree.
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USART Yes USART1 only.
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ADC No
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DCACHE No
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DCMIPP No
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DMA No
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ETH No
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I2C No
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ICACHE No
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IWDG No
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LPTIM No
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LTDC No
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MPU No
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NPU No
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RNG No
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RTC No
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SAI No
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SDMMC No
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SPI No
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TIM No
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USB No
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XSPI No
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========== ======= ===============================================
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References
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==========
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[RM0486] STMicroelectronics, STM32N647/657xx Arm®-based 32-bit MCUs
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Supported Boards
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================
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.. toctree::
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:glob:
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:maxdepth: 1
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boards/*/*
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