mirror of
https://github.com/apache/nuttx.git
synced 2026-06-05 15:58:59 +08:00
- ADC driver has been re-organized; configuration is now handled in code
instead of Kconfig to help reduce bloat and confusion. - Timer changed to remove ADC coupling in Kconfig to code and moved configuration up from arch/arm/src/tiva to configs/tm4c123g-launchpad/src. - GPIO driver needed small fixes in the configuration routines and discovered false-positive bugs in interrupt testing: interrupts are now verified to actually be working reliably. - Attempt to apply some consistency in the tiva arch/ level's interface to the config/board/ level driver configuration. From Calvin Maguranis
This commit is contained in:
Gregory Nutt
+4
-896
File diff suppressed because it is too large
Load Diff
@@ -104,7 +104,8 @@ endif
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endif
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ifeq ($(CONFIG_TIVA_ADC),y)
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CHIP_CSRCS += tiva_adc.c
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CHIP_CSRCS += tiva_adclow.c
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CHIP_CSRCS += tiva_adclib.c
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endif
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ifeq ($(CONFIG_NET),y)
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+139
-136
@@ -48,53 +48,53 @@
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/* ADC register offsets *************************************************************/
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#define TIVA_ADC_ACTSS_OFFSET 0x00000000 /* ADC Active Sample Sequencer */
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#define TIVA_ADC_RIS_OFFSET 0x00000004 /* ADC Raw Interrupt Status */
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#define TIVA_ADC_IM_OFFSET 0x00000008 /* ADC Interrupt Mask */
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#define TIVA_ADC_ISC_OFFSET 0x0000000C /* ADC Interrupt Status and Clear */
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#define TIVA_ADC_OSTAT_OFFSET 0x00000010 /* ADC Overflow Status */
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#define TIVA_ADC_EMUX_OFFSET 0x00000014 /* ADC Event Multiplexer Select */
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#define TIVA_ADC_USTAT_OFFSET 0x00000018 /* ADC Underflow Status */
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#define TIVA_ADC_TSSEL_OFFSET 0x0000001C /* ADC Trigger Source Select */
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#define TIVA_ADC_SSPRI_OFFSET 0x00000020 /* ADC Sample Sequencer Priority */
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#define TIVA_ADC_SPC_OFFSET 0x00000024 /* ADC Sample Phase Control */
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#define TIVA_ADC_PSSI_OFFSET 0x00000028 /* ADC Processor Sample Sequence Initiate */
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#define TIVA_ADC_SAC_OFFSET 0x00000030 /* ADC Sample Averaging Control */
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#define TIVA_ADC_DCISC_OFFSET 0x00000034 /* ADC Digital Comparator Interrupt Status and Clear */
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#define TIVA_ADC_CTL_OFFSET 0x00000038 /* ADC Control */
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#define TIVA_ADC_ACTSS_OFFSET 0x000 /* ADC Active Sample Sequencer */
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#define TIVA_ADC_RIS_OFFSET 0x004 /* ADC Raw Interrupt Status */
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#define TIVA_ADC_IM_OFFSET 0x008 /* ADC Interrupt Mask */
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#define TIVA_ADC_ISC_OFFSET 0x00c /* ADC Interrupt Status and Clear */
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#define TIVA_ADC_OSTAT_OFFSET 0x010 /* ADC Overflow Status */
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#define TIVA_ADC_EMUX_OFFSET 0x014 /* ADC Event Multiplexer Select */
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#define TIVA_ADC_USTAT_OFFSET 0x018 /* ADC Underflow Status */
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#define TIVA_ADC_TSSEL_OFFSET 0x01c /* ADC Trigger Source Select */
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#define TIVA_ADC_SSPRI_OFFSET 0x020 /* ADC Sample Sequencer Priority */
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#define TIVA_ADC_SPC_OFFSET 0x024 /* ADC Sample Phase Control */
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#define TIVA_ADC_PSSI_OFFSET 0x028 /* ADC Processor Sample Sequence Initiate */
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#define TIVA_ADC_SAC_OFFSET 0x030 /* ADC Sample Averaging Control */
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#define TIVA_ADC_DCISC_OFFSET 0x034 /* ADC Digital Comparator Interrupt Status and Clear */
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#define TIVA_ADC_CTL_OFFSET 0x038 /* ADC Control */
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#define TIVA_ADC_SS_BASE 0x00000040 /* ADC Sample Sequence base address */
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#define TIVA_ADC_SSMUX_OFFSET 0x00000020 /* ADC Sample Sequence Input Multiplexer Select */
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#define TIVA_ADC_SSCTL_OFFSET 0x00000004 /* ADC Sample Sequence Control */
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#define TIVA_ADC_SSFIFO_OFFSET 0x00000008 /* ADC Sample Sequence Result FIFO */
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#define TIVA_ADC_SSFSTAT_OFFSET 0x0000000C /* ADC Sample Sequence FIFO Status */
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#define TIVA_ADC_SSOP_OFFSET 0x00000010 /* ADC Sample Sequence Operation */
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#define TIVA_ADC_SSDC_OFFSET 0x00000014 /* ADC Sample Sequence Digital Comparator Select */
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#define TIVA_ADC_SSEMUX_OFFSET 0x00000018 /* ADC Sample Sequence Extended Input Multiplexer Select */
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#define TIVA_ADC_SSTSH_OFFSET 0x0000001C /* ADC Sample Sequence Sample and Hold Time */
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#define TIVA_ADC_SS_BASE 0x040 /* ADC Sample Sequence base address */
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#define TIVA_ADC_SSMUX_OFFSET 0x020 /* ADC Sample Sequence Input Multiplexer Select */
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#define TIVA_ADC_SSCTL_OFFSET 0x004 /* ADC Sample Sequence Control */
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#define TIVA_ADC_SSFIFO_OFFSET 0x008 /* ADC Sample Sequence Result FIFO */
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#define TIVA_ADC_SSFSTAT_OFFSET 0x00c /* ADC Sample Sequence FIFO Status */
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#define TIVA_ADC_SSOP_OFFSET 0x010 /* ADC Sample Sequence Operation */
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#define TIVA_ADC_SSDC_OFFSET 0x014 /* ADC Sample Sequence Digital Comparator Select */
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#define TIVA_ADC_SSEMUX_OFFSET 0x018 /* ADC Sample Sequence Extended Input Multiplexer Select */
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#define TIVA_ADC_SSTSH_OFFSET 0x01c /* ADC Sample Sequence Sample and Hold Time */
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#define TIVA_ADC_DCRIC_OFFSET 0x00000D00 /* ADC Digital Comparator Reset Initial Conditions */
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#define TIVA_ADC_DCCTL0_OFFSET 0x00000E00 /* ADC Digital Comparator Control 0 */
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#define TIVA_ADC_DCCTL1_OFFSET 0x00000E04 /* ADC Digital Comparator Control 1 */
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#define TIVA_ADC_DCCTL2_OFFSET 0x00000E08 /* ADC Digital Comparator Control 2 */
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#define TIVA_ADC_DCCTL3_OFFSET 0x00000E0C /* ADC Digital Comparator Control 3 */
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#define TIVA_ADC_DCCTL4_OFFSET 0x00000E10 /* ADC Digital Comparator Control 4 */
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#define TIVA_ADC_DCCTL5_OFFSET 0x00000E14 /* ADC Digital Comparator Control 5 */
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#define TIVA_ADC_DCCTL6_OFFSET 0x00000E18 /* ADC Digital Comparator Control 6 */
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#define TIVA_ADC_DCCTL7_OFFSET 0x00000E1C /* ADC Digital Comparator Control 7 */
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#define TIVA_ADC_DCRIC_OFFSET 0xd00 /* ADC Digital Comparator Reset Initial Conditions */
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#define TIVA_ADC_DCCTL0_OFFSET 0xe00 /* ADC Digital Comparator Control 0 */
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#define TIVA_ADC_DCCTL1_OFFSET 0xe04 /* ADC Digital Comparator Control 1 */
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#define TIVA_ADC_DCCTL2_OFFSET 0xe08 /* ADC Digital Comparator Control 2 */
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#define TIVA_ADC_DCCTL3_OFFSET 0xe0c /* ADC Digital Comparator Control 3 */
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#define TIVA_ADC_DCCTL4_OFFSET 0xe10 /* ADC Digital Comparator Control 4 */
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#define TIVA_ADC_DCCTL5_OFFSET 0xe14 /* ADC Digital Comparator Control 5 */
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#define TIVA_ADC_DCCTL6_OFFSET 0xe18 /* ADC Digital Comparator Control 6 */
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#define TIVA_ADC_DCCTL7_OFFSET 0xe1c /* ADC Digital Comparator Control 7 */
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#define TIVA_ADC_DCCMP0_OFFSET 0x00000E40 /* ADC Digital Comparator Range 0 */
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#define TIVA_ADC_DCCMP1_OFFSET 0x00000E44 /* ADC Digital Comparator Range 1 */
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#define TIVA_ADC_DCCMP2_OFFSET 0x00000E48 /* ADC Digital Comparator Range 2 */
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#define TIVA_ADC_DCCMP3_OFFSET 0x00000E4C /* ADC Digital Comparator Range 3 */
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#define TIVA_ADC_DCCMP4_OFFSET 0x00000E50 /* ADC Digital Comparator Range 4 */
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#define TIVA_ADC_DCCMP5_OFFSET 0x00000E54 /* ADC Digital Comparator Range 5 */
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#define TIVA_ADC_DCCMP6_OFFSET 0x00000E58 /* ADC Digital Comparator Range 6 */
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#define TIVA_ADC_DCCMP7_OFFSET 0x00000E5C /* ADC Digital Comparator Range 7 */
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#define TIVA_ADC_DCCMP0_OFFSET 0xe40 /* ADC Digital Comparator Range 0 */
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#define TIVA_ADC_DCCMP1_OFFSET 0xe44 /* ADC Digital Comparator Range 1 */
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#define TIVA_ADC_DCCMP2_OFFSET 0xe48 /* ADC Digital Comparator Range 2 */
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#define TIVA_ADC_DCCMP3_OFFSET 0xe4c /* ADC Digital Comparator Range 3 */
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#define TIVA_ADC_DCCMP4_OFFSET 0xe50 /* ADC Digital Comparator Range 4 */
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#define TIVA_ADC_DCCMP5_OFFSET 0xe54 /* ADC Digital Comparator Range 5 */
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#define TIVA_ADC_DCCMP6_OFFSET 0xe58 /* ADC Digital Comparator Range 6 */
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#define TIVA_ADC_DCCMP7_OFFSET 0xe5c /* ADC Digital Comparator Range 7 */
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#define TIVA_ADC_PP_OFFSET 0x00000FC0 /* ADC Peripheral Properties */
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#define TIVA_ADC_PC_OFFSET 0x00000FC4 /* ADC Peripheral Configuration */
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#define TIVA_ADC_CC_OFFSET 0x00000FC8 /* ADC Clock Configuration */
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#define TIVA_ADC_PP_OFFSET 0xfc0 /* ADC Peripheral Properties */
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#define TIVA_ADC_PC_OFFSET 0xfc4 /* ADC Peripheral Configuration */
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#define TIVA_ADC_CC_OFFSET 0xfc8 /* ADC Clock Configuration */
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/* ADC register addresses ***********************************************************/
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@@ -329,22 +329,22 @@
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/* Bit fields in the TIVA_ADC_ISC register. */
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#define ADC_ISC_SSE(n) (1 << ((n)*4))
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#define ADC_ISC_DCIN_SHIFT 20
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# define ADC_ISC_DCINSS3 (0x8) /* Digital Comparator Interrupt Status on SS3 */
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# define ADC_ISC_DCINSS2 (0x4) /* Digital Comparator Interrupt Status on SS2 */
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# define ADC_ISC_DCINSS1 (0x2) /* Digital Comparator Interrupt Status on SS1 */
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# define ADC_ISC_DCINSS0 (0x1) /* Digital Comparator Interrupt Status on SS0 */
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#define ADC_ISC_DMAIN_SHIFT 8
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# define ADC_ISC_DMAIN3 (0x8) /* SS3 DMA Interrupt Status and Clear */
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# define ADC_ISC_DMAIN2 (0x4) /* SS2 DMA Interrupt Status and Clear */
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# define ADC_ISC_DMAIN1 (0x2) /* SS1 DMA Interrupt Status and Clear */
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# define ADC_ISC_DMAIN0 (0x1) /* SS0 DMA Interrupt Status and Clear */
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#define ADC_ISC_IN_SHIFT 0
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# define ADC_ISC_IN3 (0x8) /* SS3 Interrupt Status and Clear */
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# define ADC_ISC_IN2 (0x4) /* SS2 Interrupt Status and Clear */
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# define ADC_ISC_IN1 (0x2) /* SS1 Interrupt Status and Clear */
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# define ADC_ISC_IN0 (0x1) /* SS0 Interrupt Status and Clear */
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#define ADC_ISC_SSE(n) (1 << ((n)*4))
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#define ADC_ISC_DCIN_SHIFT 20
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# define ADC_ISC_DCINSS3 (0x8) /* Digital Comparator Interrupt Status on SS3 */
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# define ADC_ISC_DCINSS2 (0x4) /* Digital Comparator Interrupt Status on SS2 */
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# define ADC_ISC_DCINSS1 (0x2) /* Digital Comparator Interrupt Status on SS1 */
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# define ADC_ISC_DCINSS0 (0x1) /* Digital Comparator Interrupt Status on SS0 */
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#define ADC_ISC_DMAIN_SHIFT 8
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# define ADC_ISC_DMAIN3 (0x8) /* SS3 DMA Interrupt Status and Clear */
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# define ADC_ISC_DMAIN2 (0x4) /* SS2 DMA Interrupt Status and Clear */
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# define ADC_ISC_DMAIN1 (0x2) /* SS1 DMA Interrupt Status and Clear */
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# define ADC_ISC_DMAIN0 (0x1) /* SS0 DMA Interrupt Status and Clear */
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#define ADC_ISC_IN_SHIFT 0
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# define ADC_ISC_IN3 (0x8) /* SS3 Interrupt Status and Clear */
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# define ADC_ISC_IN2 (0x4) /* SS2 Interrupt Status and Clear */
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# define ADC_ISC_IN1 (0x2) /* SS1 Interrupt Status and Clear */
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# define ADC_ISC_IN0 (0x1) /* SS0 Interrupt Status and Clear */
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/* Bit fields in the TIVA_ADC_OSTAT register. */
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@@ -355,20 +355,20 @@
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/* Bit fields in the TIVA_ADC_EMUX register. */
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#define ADC_EMUX_SHIFT(n) (4 * (n)) /* SS EMUX Shift */
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#define ADC_EMUX_MASK(n) (0xF << ADC_EMUX_SHIFT(n)) /* SS EMUX Mask */
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# define ADC_EMUX_PROC (0x0) /* Processor (default) */
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# define ADC_EMUX_COMP0 (0x1) /* Analog Comparator 0 */
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# define ADC_EMUX_COMP1 (0x2) /* Analog Comparator 1 */
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# define ADC_EMUX_COMP2 (0x3) /* Analog Comparator 2 */
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# define ADC_EMUX_EXTERNAL (0x4) /* External (GPIO Pins) */
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# define ADC_EMUX_TIMER (0x5) /* Timer */
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# define ADC_EMUX_PWM0 (0x6) /* PWM generator 0 */
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# define ADC_EMUX_PWM1 (0x7) /* PWM generator 1 */
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# define ADC_EMUX_PWM2 (0x8) /* PWM generator 2 */
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# define ADC_EMUX_PWM3 (0x9) /* PWM generator 3 */
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# define ADC_EMUX_NEVER (0xE) /* Never Trigger */
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# define ADC_EMUX_ALWAYS (0xF) /* Always (continuously sample) */
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#define ADC_EMUX_SHIFT(n) (4 * (n)) /* SS EMUX Shift */
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#define ADC_EMUX_MASK(n) (0xF << ADC_EMUX_SHIFT(n)) /* SS EMUX Mask */
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# define ADC_EMUX_PROC (0x0) /* Processor (default) */
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# define ADC_EMUX_COMP0 (0x1) /* Analog Comparator 0 */
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# define ADC_EMUX_COMP1 (0x2) /* Analog Comparator 1 */
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# define ADC_EMUX_COMP2 (0x3) /* Analog Comparator 2 */
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# define ADC_EMUX_EXTERNAL (0x4) /* External (GPIO Pins) */
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# define ADC_EMUX_TIMER (0x5) /* Timer */
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# define ADC_EMUX_PWM0 (0x6) /* PWM generator 0 */
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# define ADC_EMUX_PWM1 (0x7) /* PWM generator 1 */
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# define ADC_EMUX_PWM2 (0x8) /* PWM generator 2 */
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# define ADC_EMUX_PWM3 (0x9) /* PWM generator 3 */
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# define ADC_EMUX_NEVER (0xe) /* Never Trigger */
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# define ADC_EMUX_ALWAYS (0xf) /* Always (continuously sample) */
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/* Bit fields in the TIVA_ADC_USTAT register. */
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@@ -380,18 +380,19 @@
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/* Bit fields in the TIVA_ADC_TSSEL register. */
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#define ADC_TSSEL_PS_SHIFT(n) (((n)+((n)+1))*4)
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# define ADC_TSSEL_PS_M (0x3) /* PWM module trigger select */
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# define ADC_TSSEL_PS_0 (0x0) /* Use PWM module 0 */
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# define ADC_TSSEL_PS_1 (0x1) /* Use PWM module 1 */
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#define ADC_TSSEL_PS_MASK(n) (0x3 << ADC_TSSEL_PS_SHIFT((n)))
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# define ADC_TSSEL_PS_M (0x3) /* PWM module trigger select */
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# define ADC_TSSEL_PS_0 (0x0) /* Use PWM module 0 */
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# define ADC_TSSEL_PS_1 (0x1) /* Use PWM module 1 */
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/* Bit fields in the TIVA_ADC_SSPRI register. */
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#define ADC_SSPRI_SHIFT(n) ((n) * 4) /* SSE priority mask */
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#define ADC_SSPRI_MASK(n) (0x3 << ADC_SSPRI_SHIFT(n)) /* SSE priority mask */
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# define ADC_SSPRI_0 (0x0) /* SSE priority value 0 (highest) */
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# define ADC_SSPRI_1 (0x1) /* SSE priority value 1 (high) */
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# define ADC_SSPRI_2 (0x2) /* SSE priority value 2 (low) */
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# define ADC_SSPRI_3 (0x3) /* SSE priority value 3 (lowest) */
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# define ADC_SSPRI_0 (0x0) /* SSE priority value 0 (highest) */
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# define ADC_SSPRI_1 (0x1) /* SSE priority value 1 (high) */
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# define ADC_SSPRI_2 (0x2) /* SSE priority value 2 (low) */
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# define ADC_SSPRI_3 (0x3) /* SSE priority value 3 (lowest) */
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/* Bit fields in the TIVA_ADC_SPC register. */
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@@ -417,10 +418,12 @@
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#define ADC_PSSI_GSYNC 0x80000000 /* Global Synchronize */
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#define ADC_PSSI_SYNCWAIT 0x08000000 /* Synchronize Wait */
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#define ADC_PSSI_SS3 0x00000008 /* SS3 Initiate */
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#define ADC_PSSI_SS2 0x00000004 /* SS2 Initiate */
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#define ADC_PSSI_SS1 0x00000002 /* SS1 Initiate */
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#define ADC_PSSI_SS0 0x00000001 /* SS0 Initiate */
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#define ADC_PSSI_TRIG_MASK 0xf /* Enable triggering mask */
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# define ADC_PSSI_SS3 0x8 /* SS3 Initiate */
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# define ADC_PSSI_SS2 0x4 /* SS2 Initiate */
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# define ADC_PSSI_SS1 0x2 /* SS1 Initiate */
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# define ADC_PSSI_SS0 0x1 /* SS0 Initiate */
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/* Bit fields in the TIVA_ADC_SAC register. */
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@@ -456,28 +459,28 @@
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#define ADC_SSMUX_MUX_SHIFT(n) ((n)*4) /* nth Sample Input Select */
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#define ADC_SSMUX_MUX_MASK(n) (0xF << ADC_SSMUX_MUX_SHIFT(n))
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/* Bit fields in the TIVA_ADC_SSCTL register. */
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#define ADC_SSCTL_SHIFT(n) ((n)*4)
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#define ADC_SSCTL_TS (0x8) /* Sample Temp Sensor Select */
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#define ADC_SSCTL_IE (0x4) /* Sample Interrupt Enable */
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#define ADC_SSCTL_END (0x2) /* Sample is End of Sequence */
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#define ADC_SSCTL_D (0x1) /* Sample Differential Input Select */
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#define ADC_SSCTL_MASK(n) (0xF << ADC_SSCTL_SHIFT((n)))
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# define ADC_SSCTL_TS (0x8) /* Sample Temp Sensor Select */
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# define ADC_SSCTL_IE (0x4) /* Sample Interrupt Enable */
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# define ADC_SSCTL_END (0x2) /* Sample is End of Sequence */
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# define ADC_SSCTL_D (0x1) /* Sample Differential Input Select */
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/* Bit fields in the TIVA_ADC_SSFIFO0 register. */
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#define ADC_SSFIFO0_DATA_MASK 0x00000FFF /* Conversion Result Data */
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# define ADC_SSFIFO0_DATA_SHIFT 0
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# define ADC_SSFIFO0_DATA_SHIFT 0
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/* Bit fields in the TIVA_ADC_SSFSTAT0 register. */
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#define ADC_SSFSTAT0_HPTR_MASK 0x000000F0 /* FIFO Head Pointer */
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#define ADC_SSFSTAT_TPTR_MASK 0x0000000F /* FIFO Tail Pointer */
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# define ADC_SSFSTAT_HPTR_SHIFT 4
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# define ADC_SSFSTAT_TPTR_SHIFT 0
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#define ADC_SSFSTAT_FULL 0x00001000 /* FIFO Full */
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#define ADC_SSFSTAT_EMPTY 0x00000100 /* FIFO Empty */
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#define ADC_SSFSTAT_TPTR_MASK 0x0000000F /* FIFO Tail Pointer */
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# define ADC_SSFSTAT_HPTR_SHIFT 4
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# define ADC_SSFSTAT_TPTR_SHIFT 0
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#define ADC_SSFSTAT_FULL 0x00001000 /* FIFO Full */
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#define ADC_SSFSTAT_EMPTY 0x00000100 /* FIFO Empty */
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/* Bit fields in the TIVA_ADC_SSOP0 register. */
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@@ -517,21 +520,21 @@
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/* Bit fields in the TIVA_ADC_SSTSH register. */
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#define ADC_SSTSH_SHIFT(n) ((n) * 4)
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#define ADC_SSTSH_MASK(n) (0xF << (ADC_SSTSH_SHIFT(n))) /* nth Sample and Hold Period Select */
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# define ADC_SSTH_SHOLD_4 (0x0) /* Sample and hold 4 ADC clocks */
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# define ADC_SSTH_SHOLD_8 (0x2) /* Sample and hold 8 ADC clocks */
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# define ADC_SSTH_SHOLD_16 (0x4) /* Sample and hold 16 ADC clocks */
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# define ADC_SSTH_SHOLD_32 (0x6) /* Sample and hold 32 ADC clocks */
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# define ADC_SSTH_SHOLD_64 (0x8) /* Sample and hold 64 ADC clocks */
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# define ADC_SSTH_SHOLD_128 (0xA) /* Sample and hold 128 ADC clocks */
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# define ADC_SSTH_SHOLD_256 (0xC) /* Sample and hold 256 ADC clocks */
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# define SSTSH_TSH_TS ADC_SSTH_SHOLD_4 /* Same and hold time for the temp sensor should be at least 16 ADC ticks */
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#define ADC_SSTSH_SHIFT(n) ((n) * 4)
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#define ADC_SSTSH_MASK(n) (0xf << (ADC_SSTSH_SHIFT(n))) /* nth Sample and Hold Period Select */
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# define ADC_SSTH_SHOLD_4 (0x0) /* Sample and hold 4 ADC clocks */
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# define ADC_SSTH_SHOLD_8 (0x2) /* Sample and hold 8 ADC clocks */
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# define ADC_SSTH_SHOLD_16 (0x4) /* Sample and hold 16 ADC clocks */
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# define ADC_SSTH_SHOLD_32 (0x6) /* Sample and hold 32 ADC clocks */
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# define ADC_SSTH_SHOLD_64 (0x8) /* Sample and hold 64 ADC clocks */
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# define ADC_SSTH_SHOLD_128 (0xa) /* Sample and hold 128 ADC clocks */
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# define ADC_SSTH_SHOLD_256 (0xc) /* Sample and hold 256 ADC clocks */
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# define SSTSH_TSH_TS ADC_SSTH_SHOLD_4 /* Same and hold time for the temp sensor should be at least 16 ADC ticks */
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/* Bit fields in the TIVA_ADC_SSFIFO1 register. */
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#define ADC_SSFIFO1_DATA_MASK 0x00000FFF /* Conversion Result Data */
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||||
# define ADC_SSFIFO1_DATA_SHIFT 0
|
||||
# define ADC_SSFIFO1_DATA_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_SSFSTAT1 register. */
|
||||
|
||||
@@ -607,15 +610,15 @@
|
||||
#define ADC_SSTSH2_TSH2_MASK 0x00000F00 /* 3rd Sample and Hold Period Select */
|
||||
#define ADC_SSTSH2_TSH1_MASK 0x000000F0 /* 2nd Sample and Hold Period Select */
|
||||
#define ADC_SSTSH2_TSH0_MASK 0x0000000F /* 1st Sample and Hold Period Select */
|
||||
# define ADC_SSTSH2_TSH3_SHIFT 12
|
||||
# define ADC_SSTSH2_TSH2_SHIFT 8
|
||||
# define ADC_SSTSH2_TSH1_SHIFT 4
|
||||
# define ADC_SSTSH2_TSH0_SHIFT 0
|
||||
# define ADC_SSTSH2_TSH3_SHIFT 12
|
||||
# define ADC_SSTSH2_TSH2_SHIFT 8
|
||||
# define ADC_SSTSH2_TSH1_SHIFT 4
|
||||
# define ADC_SSTSH2_TSH0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_SSFIFO3 register. */
|
||||
|
||||
#define ADC_SSFIFO3_DATA_MASK 0x00000FFF /* Conversion Result Data */
|
||||
# define ADC_SSFIFO3_DATA_SHIFT 0
|
||||
# define ADC_SSFIFO3_DATA_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_SSFSTAT3 register. */
|
||||
|
||||
@@ -637,7 +640,7 @@
|
||||
/* Bit fields in the TIVA_ADC_SSTSH3 register. */
|
||||
|
||||
#define ADC_SSTSH3_TSH0_MASK 0x0000000F /* 1st Sample and Hold Period Select */
|
||||
# define ADC_SSTSH3_TSH0_SHIFT 0
|
||||
# define ADC_SSTSH3_TSH0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCRIC register. */
|
||||
|
||||
@@ -846,57 +849,57 @@
|
||||
|
||||
#define ADC_DCCMP0_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP0_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP0_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP0_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP0_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP0_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP1 register. */
|
||||
|
||||
#define ADC_DCCMP1_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP1_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP1_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP1_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP1_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP1_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP2 register. */
|
||||
|
||||
#define ADC_DCCMP2_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP2_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP2_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP2_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP2_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP2_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP3 register. */
|
||||
|
||||
#define ADC_DCCMP3_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP3_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP3_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP3_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP3_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP3_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP4 register. */
|
||||
|
||||
#define ADC_DCCMP4_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP4_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP4_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP4_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP4_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP4_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP5 register. */
|
||||
|
||||
#define ADC_DCCMP5_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP5_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP5_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP5_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP5_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP5_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP6 register. */
|
||||
|
||||
#define ADC_DCCMP6_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP6_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP6_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP6_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP6_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP6_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_DCCMP7 register. */
|
||||
|
||||
#define ADC_DCCMP7_COMP1_MASK 0x0FFF0000 /* Compare 1 */
|
||||
#define ADC_DCCMP7_COMP0_MASK 0x00000FFF /* Compare 0 */
|
||||
# define ADC_DCCMP7_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP7_COMP0_SHIFT 0
|
||||
# define ADC_DCCMP7_COMP1_SHIFT 16
|
||||
# define ADC_DCCMP7_COMP0_SHIFT 0
|
||||
|
||||
/* Bit fields in the TIVA_ADC_PP register. */
|
||||
|
||||
@@ -906,9 +909,9 @@
|
||||
#define ADC_PP_CH_MASK 0x000003F0 /* ADC Channel Count */
|
||||
#define ADC_PP_MCR_MASK 0x0000000F /* Maximum Conversion Rate */
|
||||
#define ADC_PP_MSR_MASK 0x0000000F /* Maximum ADC Sample Rate */
|
||||
# define ADC_PP_RSL_SHIFT 18
|
||||
# define ADC_PP_DC_SHIFT 10
|
||||
# define ADC_PP_CH_SHIFT 4
|
||||
# define ADC_PP_RSL_SHIFT 18
|
||||
# define ADC_PP_DC_SHIFT 10
|
||||
# define ADC_PP_CH_SHIFT 4
|
||||
#define ADC_PP_APSHT 0x01000000 /* Application-Programmable Sample-and-Hold Time */
|
||||
#define ADC_PP_TS 0x00800000 /* Temperature Sensor */
|
||||
#define ADC_PP_TYPE_SAR 0x00000000 /* SAR */
|
||||
@@ -933,11 +936,11 @@
|
||||
|
||||
/* Bit fields in the TIVA_ADC_CC register. */
|
||||
|
||||
#define ADC_CC_CLKDIV_MASK (0x3F0) /* PLL VCO Clock Divisor */
|
||||
#define ADC_CC_CS_MASK (0x00F) /* ADC Clock Source */
|
||||
#define ADC_CC_CLKDIV_MASK (0x3F0) /* PLL VCO Clock Divisor */
|
||||
#define ADC_CC_CS_MASK (0x00F) /* ADC Clock Source */
|
||||
# define ADC_CC_CLKDIV_SHIFT 4
|
||||
#define ADC_CC_CS_SYSPLL (0x000) /* PLL VCO divided by CLKDIV */
|
||||
#define ADC_CC_CS_PIOSC (0x001) /* PIOSC */
|
||||
#define ADC_CC_CS_MOSC (0x002) /* MOSC */
|
||||
#define ADC_CC_CS_SYSPLL (0x000) /* PLL VCO divided by CLKDIV */
|
||||
#define ADC_CC_CS_PIOSC (0x001) /* PIOSC */
|
||||
#define ADC_CC_CS_MOSC (0x002) /* MOSC */
|
||||
|
||||
#endif // __ARCH_ARM_SRC_TIVA_CHIP_TIVA_ADC_H
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+569
-25
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+327
-351
File diff suppressed because it is too large
Load Diff
+196
-35
@@ -1,9 +1,11 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/tiva/tiva_gpio.h
|
||||
*
|
||||
* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009-2010, 2013-2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* With modifications from Calvin Maguranis <calvin.maguranis@trd2inc.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
@@ -31,14 +33,14 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_TIVA_GPIO_H
|
||||
#define __ARCH_ARM_SRC_TIVA_TIVA_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
@@ -51,9 +53,129 @@
|
||||
#include "up_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/* Debug ********************************************************************/
|
||||
|
||||
#ifndef CONFIG_DEBUG
|
||||
# undef CONFIG_DEBUG_GPIO
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S) || defined(CONFIG_ARCH_CHIP_LM4F) || \
|
||||
defined(CONFIG_ARCH_CHIP_CC3200)
|
||||
|
||||
/* I don't believe that any of these families support interrupts on port J. Many
|
||||
* do not support interrupts on port H either.
|
||||
*/
|
||||
|
||||
# undef CONFIG_TIVA_GPIOJ_IRQS
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
|
||||
/* The TM4C123GH6PMI supports ports A-F of which any can support interrupts */
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
|
||||
# undef CONFIG_TIVA_GPIOP_IRQS /* P-Q */
|
||||
# undef CONFIG_TIVA_GPIOQ_IRQS
|
||||
|
||||
/* The TM4C123GH6PGE supports interrupts only on port P */
|
||||
|
||||
# elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
|
||||
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
|
||||
# undef CONFIG_TIVA_GPIOB_IRQS
|
||||
# undef CONFIG_TIVA_GPIOC_IRQS
|
||||
# undef CONFIG_TIVA_GPIOD_IRQS
|
||||
# undef CONFIG_TIVA_GPIOE_IRQS
|
||||
# undef CONFIG_TIVA_GPIOF_IRQS
|
||||
|
||||
# undef CONFIG_TIVA_GPIOQ_IRQS /* Q */
|
||||
|
||||
/* The TM4C123GH6ZRB and the TM4C129x support interrupts only on ports P and Q. */
|
||||
|
||||
# else
|
||||
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
|
||||
# undef CONFIG_TIVA_GPIOB_IRQS
|
||||
# undef CONFIG_TIVA_GPIOC_IRQS
|
||||
# undef CONFIG_TIVA_GPIOD_IRQS
|
||||
# undef CONFIG_TIVA_GPIOE_IRQS
|
||||
# undef CONFIG_TIVA_GPIOF_IRQS
|
||||
|
||||
# endif
|
||||
|
||||
/* No supported architecture supports interrupts on ports G-N or R-T */
|
||||
|
||||
# undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
|
||||
# undef CONFIG_TIVA_GPIOH_IRQS
|
||||
# undef CONFIG_TIVA_GPIOJ_IRQS
|
||||
# undef CONFIG_TIVA_GPIOK_IRQS
|
||||
# undef CONFIG_TIVA_GPIOL_IRQS
|
||||
# undef CONFIG_TIVA_GPIOM_IRQS
|
||||
# undef CONFIG_TIVA_GPION_IRQS
|
||||
|
||||
# undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
|
||||
# undef CONFIG_TIVA_GPIOS_IRQS
|
||||
# undef CONFIG_TIVA_GPIOT_IRQS
|
||||
|
||||
#endif
|
||||
|
||||
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
|
||||
|
||||
#if TIVA_NPORTS < 1
|
||||
# undef CONFIG_TIVA_GPIOA_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 2
|
||||
# undef CONFIG_TIVA_GPIOB_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 3
|
||||
# undef CONFIG_TIVA_GPIOC_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 4
|
||||
# undef CONFIG_TIVA_GPIOD_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 5
|
||||
# undef CONFIG_TIVA_GPIOE_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 6
|
||||
# undef CONFIG_TIVA_GPIOF_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 7
|
||||
# undef CONFIG_TIVA_GPIOG_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 8
|
||||
# undef CONFIG_TIVA_GPIOH_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 9
|
||||
# undef CONFIG_TIVA_GPIOJ_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 10
|
||||
# undef CONFIG_TIVA_GPIOK_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 11
|
||||
# undef CONFIG_TIVA_GPIOL_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 12
|
||||
# undef CONFIG_TIVA_GPIOM_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 13
|
||||
# undef CONFIG_TIVA_GPION_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 14
|
||||
# undef CONFIG_TIVA_GPIOP_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 15
|
||||
# undef CONFIG_TIVA_GPIOQ_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 16
|
||||
# undef CONFIG_TIVA_GPIOQ_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 17
|
||||
# undef CONFIG_TIVA_GPIOQ_IRQS
|
||||
#endif
|
||||
#if TIVA_NPORTS < 18
|
||||
# undef CONFIG_TIVA_GPIOQ_IRQS
|
||||
#endif
|
||||
|
||||
/* Bit-encoded input to tiva_configgpio() *******************************************/
|
||||
|
||||
@@ -200,68 +322,68 @@
|
||||
# define GPIO_PIN_6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN_7 (7 << GPIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
uintptr_t tiva_gpiobaseaddress(unsigned int port);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: tiva_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
int tiva_configgpio(uint32_t cfgset);
|
||||
int tiva_configgpio(uint32_t pinset);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpiowrite(uint32_t pinset, bool value);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
bool tiva_gpioread(uint32_t pinset);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Function: tiva_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the provided base address
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
int tiva_dumpgpio(uint32_t pinset, const char *msg);
|
||||
|
||||
@@ -276,14 +398,18 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg);
|
||||
|
||||
void tiva_gpio_lockport(uint32_t pinset, bool lock);
|
||||
|
||||
# ifdef CONFIG_TIVA_GPIO_IRQS
|
||||
/************************************************************************************
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
void tiva_gpio_dumpconfig(uint32_t pinset);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TIVA_GPIO_IRQS
|
||||
/****************************************************************************
|
||||
* Name: gpio_irqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize all vectors to the unexpected interrupt handler
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
int weak_function tiva_gpioirqinitialize(void);
|
||||
|
||||
@@ -291,34 +417,69 @@ int weak_function tiva_gpioirqinitialize(void);
|
||||
* Name: tiva_gpioirqattach
|
||||
*
|
||||
* Description:
|
||||
* Attach the interrupt handler 'isr' to the GPIO IRQ 'irq'
|
||||
* Attach a GPIO interrupt to the provided 'isr'
|
||||
*
|
||||
* Returns:
|
||||
* oldhandler - the old interrupt handler assigned to this pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int tiva_gpioirqattach(int irq, xcpt_t isr);
|
||||
# define tiva_gpioirqdetach(isr) tiva_gpioirqattach(isr, NULL)
|
||||
xcpt_t tiva_gpioirqattach(uint32_t pinset, xcpt_t isr);
|
||||
# define tiva_gpioirqdetach(pinset) tiva_gpioirqattach(pinset, NULL)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioportirqattach
|
||||
*
|
||||
* Description:
|
||||
* Attach 'isr' to the GPIO port. Only use this if you want to handle
|
||||
* the entire ports interrupts explicitly.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioportirqattach(uint8_t port, xcpt_t isr);
|
||||
# define tiva_gpioportirqdetach(port) tiva_gpioportirqattach(port, NULL)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the GPIO IRQ specified by 'irq'
|
||||
* Enable the GPIO port IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqenable(int irq);
|
||||
void tiva_gpioirqenable(uint8_t port, uint8_t pin);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the GPIO IRQ specified by 'irq'
|
||||
* Disable the GPIO port IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqdisable(int irq);
|
||||
# endif
|
||||
void tiva_gpioirqdisable(uint8_t port, uint8_t pin);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqstatus
|
||||
*
|
||||
* Description:
|
||||
* Returns raw or masked interrupt status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t tiva_gpioirqstatus(uint8_t port, bool masked);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqclear
|
||||
*
|
||||
* Description:
|
||||
* Clears the interrupt status of the input base
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqclear(uint8_t port, uint32_t pinmask);
|
||||
|
||||
#endif /* CONFIG_TIVA_GPIO_IRQS */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
+463
-124
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/tiva/tiva_timer.h
|
||||
*
|
||||
* Copyright (C) 201r Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -831,7 +831,7 @@ static inline void tiva_gptm0_synchronize(uint32_t sync)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer_register
|
||||
* Name: tiva_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* Bind the configuration timer to a timer lower half instance and
|
||||
@@ -847,8 +847,7 @@ static inline void tiva_gptm0_synchronize(uint32_t sync)
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the timer device. This should be of the
|
||||
* form /dev/timer0
|
||||
* gptm - General purpose timer number
|
||||
* altlck - True: Use alternate clock source.
|
||||
* config - 32-bit timer configuration values.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned
|
||||
@@ -857,7 +856,8 @@ static inline void tiva_gptm0_synchronize(uint32_t sync)
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TIMER
|
||||
int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk);
|
||||
int tiva_timer_initialize(FAR const char *devpath,
|
||||
struct tiva_gptm32config_s *config);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_TIMER_H */
|
||||
|
||||
@@ -1644,7 +1644,6 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config)
|
||||
case 0:
|
||||
/* Enable GPTM0 clocking and power */
|
||||
|
||||
|
||||
attr = &g_gptm0_attr;
|
||||
priv = &g_gptm0_state;
|
||||
break;
|
||||
@@ -2321,9 +2320,12 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval)
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
bool toints;
|
||||
|
||||
DEBUGASSERT(priv && priv->attr && priv->config &&
|
||||
priv->config->mode != TIMER16_MODE);
|
||||
DEBUGASSERT(priv);
|
||||
DEBUGASSERT(priv->attr);
|
||||
DEBUGASSERT(priv->config);
|
||||
config = (const struct tiva_gptm32config_s *)priv->config;
|
||||
|
||||
DEBUGASSERT(config->cmn.mode != TIMER16_MODE);
|
||||
timer = &config->config;
|
||||
|
||||
/* Do we need to enable timeout interrupts? Interrupts are only enabled
|
||||
|
||||
@@ -42,6 +42,7 @@
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
@@ -91,7 +92,7 @@ static void tiva_timeout(struct tiva_lowerhalf_s *priv, uint32_t timeout);
|
||||
|
||||
/* Interrupt handling *******************************************************/
|
||||
|
||||
static void tiva_handler(TIMER_HANDLE handle, void *arg, uint32_t status);
|
||||
static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status);
|
||||
|
||||
/* "Lower half" driver methods **********************************************/
|
||||
|
||||
@@ -218,7 +219,7 @@ static void tiva_timeout(struct tiva_lowerhalf_s *priv, uint32_t timeout)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_handler
|
||||
* Name: tiva_timer_handler
|
||||
*
|
||||
* Description:
|
||||
* 32-bit timer interrupt handler
|
||||
@@ -231,7 +232,7 @@ static void tiva_timeout(struct tiva_lowerhalf_s *priv, uint32_t timeout)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void tiva_handler(TIMER_HANDLE handle, void *arg, uint32_t status)
|
||||
static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status)
|
||||
{
|
||||
struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)arg;
|
||||
|
||||
@@ -511,7 +512,6 @@ static tccb_t tiva_sethandler(struct timer_lowerhalf_s *lower,
|
||||
static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)lower;
|
||||
int ret = -ENOTTY;
|
||||
|
||||
DEBUGASSERT(priv);
|
||||
@@ -525,7 +525,7 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd,
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_timer_register
|
||||
* Name: tiva_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* Bind the configuration timer to a timer lower half instance and
|
||||
@@ -541,8 +541,7 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd,
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the timer device. This should be of the
|
||||
* form /dev/timer0
|
||||
* gptm - General purpose timer number
|
||||
* altlck - True: Use alternate clock source.
|
||||
* config - 32-bit timer configuration values.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned
|
||||
@@ -550,15 +549,15 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk)
|
||||
int tiva_timer_initialize(FAR const char *devpath,
|
||||
struct tiva_gptm32config_s *config)
|
||||
{
|
||||
struct tiva_lowerhalf_s *priv;
|
||||
struct tiva_gptm32config_s *config;
|
||||
void *drvr;
|
||||
int ret;
|
||||
|
||||
timvdbg("\n");
|
||||
DEBUGASSERT(devpath);
|
||||
timvdbg("Entry: devpath=%s\n", devpath);
|
||||
|
||||
/* Allocate an instance of the lower half state structure */
|
||||
|
||||
@@ -573,9 +572,9 @@ int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk)
|
||||
|
||||
priv->ops = &g_timer_ops;
|
||||
#ifdef CONFIG_ARCH_CHIP_TM4C129
|
||||
priv->clkin = altclk ? ALTCLK_FREQUENCY : SYSCLK_FREQUENCY;
|
||||
priv->clkin = config->cmn.alternate ? ALTCLK_FREQUENCY : SYSCLK_FREQUENCY;
|
||||
#else
|
||||
if (altclk)
|
||||
if (config->cmn.alternate)
|
||||
{
|
||||
timdbg("ERROR: Alternate clock unsupported on TM4C123 architecture\n");
|
||||
return -ENOMEM;
|
||||
@@ -586,16 +585,9 @@ int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk)
|
||||
}
|
||||
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
||||
|
||||
config = &priv->config;
|
||||
config->cmn.gptm = gptm;
|
||||
config->cmn.mode = TIMER32_MODE_PERIODIC;
|
||||
config->cmn.alternate = altclk;
|
||||
config->config.flags = TIMER_FLAG_COUNTUP;
|
||||
#ifdef CONFIG_TIVA_TIMER32_ADCEVENT
|
||||
config->config.flags |= TIMER_FLAG_ADCTIMEOUT;
|
||||
#endif
|
||||
config->config.handler = tiva_handler;
|
||||
config->config.handler = tiva_timer_handler;
|
||||
config->config.arg = priv;
|
||||
memcpy(&(priv->config), config, sizeof(struct tiva_gptm32config_s));
|
||||
|
||||
/* Set the initial timer interval */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user