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stm32l5: Architecture Support for STM32L5
Architecture support for STMicroelectronics STM32L552xx and STM32L562xx MCUs. This is based on corresponding code for STM32L4, but has been considerably adjusted. Tested with Nucleo-L552ZE-Q and STM32L562E-DK boards with simple NSH configurations. Signed-off-by: Michael Jung <mijung@gmx.net>
This commit is contained in:
Michael Jung
Xiang Xiao
@@ -396,6 +396,20 @@ config ARCH_CHIP_STM32L4
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---help---
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STMicro STM32 architectures (ARM Cortex-M4).
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config ARCH_CHIP_STM32L5
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bool "STMicro STM32 L5"
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select ARCH_CORTEXM33
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_PROGMEM
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select ARCH_HAVE_SPI_BITORDER
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select ARCH_HAVE_TICKLESS
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select ARM_HAVE_MPU_UNIFIED
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select ARMV8M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M33).
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config ARCH_CHIP_STR71X
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bool "STMicro STR71x"
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select ARCH_ARM7TDMI
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@@ -769,6 +783,7 @@ config ARCH_CHIP
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default "stm32f7" if ARCH_CHIP_STM32F7
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default "stm32h7" if ARCH_CHIP_STM32H7
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default "stm32l4" if ARCH_CHIP_STM32L4
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default "stm32l5" if ARCH_CHIP_STM32L5
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default "str71x" if ARCH_CHIP_STR71X
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default "tms570" if ARCH_CHIP_TMS570
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default "xmc4" if ARCH_CHIP_XMC4
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@@ -1027,6 +1042,9 @@ endif
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if ARCH_CHIP_STM32L4
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source arch/arm/src/stm32l4/Kconfig
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endif
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if ARCH_CHIP_STM32L5
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source arch/arm/src/stm32l5/Kconfig
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endif
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if ARCH_CHIP_STR71X
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source arch/arm/src/str71x/Kconfig
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endif
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@@ -0,0 +1,81 @@
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/*****************************************************************************
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* arch/arm/include/stm32l5/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32L5_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32L5_CHIP_H
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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/*****************************************************************************
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* Pre-processor Definitions
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*****************************************************************************/
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#if defined(CONFIG_STM32L5_STM32L562XX)
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# define STM32L5_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32L5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L5 chip"
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#endif
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#if defined(CONFIG_STM32L5_STM32L562XX)
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# define STM32L5_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L5_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L5_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L5_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L5_NRNG 1 /* Random number generator (RNG) */
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# define STM32L5_NUART 2 /* UART 4-5 */
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# define STM32L5_NUSART 3 /* USART 1-3 */
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# define STM32L5_NLPUART 1 /* LPUART 1 */
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# define STM32L5_QSPI 0 /* No QuadSPI1 */
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# define STM32L5_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32L5_NSPI 3 /* SPI1-3 */
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# define STM32L5_NI2C 4 /* I2C1-4 */
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# define STM32L5_NSWPMI 0 /* No SWPMI1 */
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# define STM32L5_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L5_NUSBFS 0 /* No USB FS */
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# define STM32L5_NCAN 1 /* CAN1 */
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# define STM32L5_NSAI 2 /* SAI1-2 */
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# define STM32L5_NSDMMC 1 /* SDMMC interface */
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# define STM32L5_NDMA 2 /* DMA1-2 */
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# define STM32L5_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L5_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32L5_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L5_NCRC 1 /* CRC */
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# define STM32L5_NCOMP 2 /* Comparators */
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# define STM32L5_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L5_STM32L562XX */
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/* NVIC priority levels ******************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32L5_CHIP_H */
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@@ -0,0 +1,40 @@
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/*****************************************************************************
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* arch/arm/include/stm32l5/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*****************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32L5_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32L5_IRQ_H
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_STM32L5_STM32L562XX)
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# include <arch/stm32l5/stm32l562xx_irq.h>
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#else
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# error "Unsupported STM32 L5 chip"
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32L5_IRQ_H */
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@@ -0,0 +1,171 @@
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/*****************************************************************************
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* arch/arm/include/stm32l5/stm32l562xx_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/stm32l5/stm32l5_irq.h>
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/*****************************************************************************
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* Pre-processor Definitions
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*****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in the file nuttx/arch/arm/include/stm32l5/stm32l5_irq.h, which is included
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* above.
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*
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* External interrupts (vectors >= 16)
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*
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* These interrupts vectors was implemented based on RM0438 Table 88
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* (STM32L552xx and STM32L562xx vector table) and should work for
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* STM32L552xx and STL32L562xx.
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*
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*/
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#define STM32L5_IRQ_WWDG (STM32L5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
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#define STM32L5_IRQ_PVD_PVM (STM32L5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */
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#define STM32L5_IRQ_RTC (STM32L5_IRQ_FIRST + 2) /* 2: RTC global interrupts */
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#define STM32L5_IRQ_RTC_S (STM32L5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */
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#define STM32L5_IRQ_TAMP (STM32L5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */
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#define STM32L5_IRQ_TAMP_S (STM32L5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */
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#define STM32L5_IRQ_FLASH (STM32L5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */
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#define STM32L5_IRQ_FLASH_S (STM32L5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */
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#define STM32L5_IRQ_GTZC (STM32L5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */
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#define STM32L5_IRQ_RCC (STM32L5_IRQ_FIRST + 9) /* 9: RCC global interrupt */
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#define STM32L5_IRQ_RCC_S (STM32L5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */
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#define STM32L5_IRQ_EXTI0 (STM32L5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */
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#define STM32L5_IRQ_EXTI1 (STM32L5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */
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#define STM32L5_IRQ_EXTI2 (STM32L5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */
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#define STM32L5_IRQ_EXTI3 (STM32L5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */
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#define STM32L5_IRQ_EXTI4 (STM32L5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */
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#define STM32L5_IRQ_EXTI5 (STM32L5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */
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#define STM32L5_IRQ_EXTI6 (STM32L5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */
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#define STM32L5_IRQ_EXTI7 (STM32L5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */
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#define STM32L5_IRQ_EXTI8 (STM32L5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */
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#define STM32L5_IRQ_EXTI9 (STM32L5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */
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#define STM32L5_IRQ_EXTI10 (STM32L5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */
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#define STM32L5_IRQ_EXTI11 (STM32L5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */
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#define STM32L5_IRQ_EXTI12 (STM32L5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */
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#define STM32L5_IRQ_EXTI13 (STM32L5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */
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#define STM32L5_IRQ_EXTI14 (STM32L5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */
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#define STM32L5_IRQ_EXTI15 (STM32L5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */
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#define STM32L5_IRQ_DMAMUX1_OVR (STM32L5_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */
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#define STM32L5_IRQ_DMAMUX1_OVR_S (STM32L5_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */
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#define STM32L5_IRQ_DMA1CH1 (STM32L5_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */
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#define STM32L5_IRQ_DMA1CH2 (STM32L5_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */
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#define STM32L5_IRQ_DMA1CH3 (STM32L5_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */
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#define STM32L5_IRQ_DMA1CH4 (STM32L5_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */
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#define STM32L5_IRQ_DMA1CH5 (STM32L5_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */
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#define STM32L5_IRQ_DMA1CH6 (STM32L5_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */
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#define STM32L5_IRQ_DMA1CH7 (STM32L5_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */
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#define STM32L5_IRQ_DMA1CH8 (STM32L5_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */
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#define STM32L5_IRQ_ADC1_2 (STM32L5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */
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#define STM32L5_IRQ_DAC (STM32L5_IRQ_FIRST + 38) /* 38: DAC global interrupt */
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#define STM32L5_IRQ_FDCAN1_IT0 (STM32L5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */
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#define STM32L5_IRQ_FDCAN1_IT1 (STM32L5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */
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#define STM32L5_IRQ_TIM1_BRK (STM32L5_IRQ_FIRST + 41) /* 41: TIM1 break */
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#define STM32L5_IRQ_TIM1_UP (STM32L5_IRQ_FIRST + 42) /* 42: TIM1 update */
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#define STM32L5_IRQ_TIM1_TRG_COM (STM32L5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
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#define STM32L5_IRQ_TIM1_CC (STM32L5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
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#define STM32L5_IRQ_TIM2 (STM32L5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
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#define STM32L5_IRQ_TIM3 (STM32L5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
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#define STM32L5_IRQ_TIM4 (STM32L5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
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#define STM32L5_IRQ_TIM5 (STM32L5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */
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#define STM32L5_IRQ_TIM6 (STM32L5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */
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#define STM32L5_IRQ_TIM7 (STM32L5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */
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#define STM32L5_IRQ_TIM8_BRK (STM32L5_IRQ_FIRST + 51) /* 51: TIM8 break */
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#define STM32L5_IRQ_TIM8_UP (STM32L5_IRQ_FIRST + 52) /* 52: TIM8 update */
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#define STM32L5_IRQ_TIM8_TRG_COM (STM32L5_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
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#define STM32L5_IRQ_TIM8_CC (STM32L5_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
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#define STM32L5_IRQ_I2C1_EV (STM32L5_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */
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#define STM32L5_IRQ_I2C1_ER (STM32L5_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */
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#define STM32L5_IRQ_I2C2_EV (STM32L5_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */
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#define STM32L5_IRQ_I2C2_ER (STM32L5_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */
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#define STM32L5_IRQ_SPI1 (STM32L5_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */
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#define STM32L5_IRQ_SPI2 (STM32L5_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */
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#define STM32L5_IRQ_USART1 (STM32L5_IRQ_FIRST + 61) /* 61: USART1 global interrupt */
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#define STM32L5_IRQ_USART2 (STM32L5_IRQ_FIRST + 62) /* 62: USART2 global interrupt */
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#define STM32L5_IRQ_USART3 (STM32L5_IRQ_FIRST + 63) /* 63: USART3 global interrupt */
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#define STM32L5_IRQ_UART4 (STM32L5_IRQ_FIRST + 64) /* 64: UART4 global interrupt */
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#define STM32L5_IRQ_UART5 (STM32L5_IRQ_FIRST + 65) /* 65: UART5 global interrupt */
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#define STM32L5_IRQ_LPUART1 (STM32L5_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */
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#define STM32L5_IRQ_LPTIM1 (STM32L5_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */
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#define STM32L5_IRQ_LPTIM2 (STM32L5_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */
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#define STM32L5_IRQ_TIM15 (STM32L5_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */
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#define STM32L5_IRQ_TIM16 (STM32L5_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */
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#define STM32L5_IRQ_TIM17 (STM32L5_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */
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#define STM32L5_IRQ_COMP (STM32L5_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */
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#define STM32L5_IRQ_USB_FS (STM32L5_IRQ_FIRST + 73) /* 73: USB global interrupt */
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#define STM32L5_IRQ_CRS (STM32L5_IRQ_FIRST + 74) /* 74: CRS global interrupt */
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#define STM32L5_IRQ_FMC (STM32L5_IRQ_FIRST + 75) /* 75: FMC global interrupt */
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#define STM32L5_IRQ_OCTOSPI1 (STM32L5_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */
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/* 77: Reserved */
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#define STM32L5_IRQ_SDMMC1 (STM32L5_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */
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/* 79: Reserved */
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#define STM32L5_IRQ_DMA2CH1 (STM32L5_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */
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#define STM32L5_IRQ_DMA2CH2 (STM32L5_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */
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#define STM32L5_IRQ_DMA2CH3 (STM32L5_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */
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#define STM32L5_IRQ_DMA2CH4 (STM32L5_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */
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#define STM32L5_IRQ_DMA2CH5 (STM32L5_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */
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#define STM32L5_IRQ_DMA2CH6 (STM32L5_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */
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#define STM32L5_IRQ_DMA2CH7 (STM32L5_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */
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#define STM32L5_IRQ_DMA2CH8 (STM32L5_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */
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#define STM32L5_IRQ_I2C3_EV (STM32L5_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */
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#define STM32L5_IRQ_I2C3_ER (STM32L5_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */
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#define STM32L5_IRQ_SAI1 (STM32L5_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */
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#define STM32L5_IRQ_SAI2 (STM32L5_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */
|
||||
#define STM32L5_IRQ_TSC (STM32L5_IRQ_FIRST + 92) /* 92: TSC global interrupt */
|
||||
#define STM32L5_IRQ_AES (STM32L5_IRQ_FIRST + 93) /* 93: AES global interrupt */
|
||||
#define STM32L5_IRQ_RNG (STM32L5_IRQ_FIRST + 94) /* 94: RNG global interrupt */
|
||||
#define STM32L5_IRQ_FPU (STM32L5_IRQ_FIRST + 95) /* 95: FPU global interrupt */
|
||||
#define STM32L5_IRQ_HASH (STM32L5_IRQ_FIRST + 96) /* 96: HASH global interrupt */
|
||||
#define STM32L5_IRQ_PKA (STM32L5_IRQ_FIRST + 97) /* 97: PKA global interrupt */
|
||||
#define STM32L5_IRQ_LPTIM3 (STM32L5_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */
|
||||
#define STM32L5_IRQ_SPI3 (STM32L5_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */
|
||||
#define STM32L5_IRQ_I2C4_EV (STM32L5_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */
|
||||
#define STM32L5_IRQ_I2C4_ER (STM32L5_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */
|
||||
#define STM32L5_IRQ_DFSDM1_FLT0 (STM32L5_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */
|
||||
#define STM32L5_IRQ_DFSDM1_FLT1 (STM32L5_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */
|
||||
#define STM32L5_IRQ_DFSDM1_FLT2 (STM32L5_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */
|
||||
#define STM32L5_IRQ_DFSDM1_FLT3 (STM32L5_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */
|
||||
#define STM32L5_IRQ_UCPD1 (STM32L5_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */
|
||||
#define STM32L5_IRQ_ICACHE (STM32L5_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */
|
||||
#define STM32L5_IRQ_OTFDEC1 (STM32L5_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32L5_STM32L562XX)
|
||||
# define STM32L5_IRQ_NEXTINTS 109
|
||||
#else
|
||||
# error "Unsupported STM32L5 chip"
|
||||
#endif
|
||||
|
||||
/* (EXTI interrupts do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L5_IRQ_FIRST + STM32L5_IRQ_NEXTINTS)
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H */
|
||||
@@ -0,0 +1,91 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/include/stm32l5/stm32l5_irq.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly by
|
||||
* the chip type specific header files (e.g. stm32l562xx_irq.h)
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map
|
||||
* directly to bits in the NVIC. This does, however, waste several words of
|
||||
* memory in the IRQ to handle mapping tables.
|
||||
*/
|
||||
|
||||
/* Processor Exceptions (vectors 0-15) */
|
||||
|
||||
#define STM32L5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32L5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32L5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define STM32L5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define STM32L5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define STM32L5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
/* Vectors 7-10: Reserved */
|
||||
#define STM32L5_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define STM32L5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define STM32L5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32L5_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
|
||||
/* External interrupts (vectors >= 16). These definitions are chip-specific */
|
||||
|
||||
#define STM32L5_IRQ_FIRST (16) /* Vector number of the first external interrupt */
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Types
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Data
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
##############################################################################
|
||||
# arch/arm/src/stm32l5/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
##############################################################################
|
||||
|
||||
# The start-up, "head", file. Only common vectors are support so there
|
||||
# isn't one.
|
||||
|
||||
HEAD_ASRC =
|
||||
|
||||
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
|
||||
|
||||
CMN_UASRCS =
|
||||
CMN_UCSRCS =
|
||||
|
||||
CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S arm_switchcontext.S
|
||||
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SETJMP_H),y)
|
||||
ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
|
||||
CMN_ASRCS += arm_setjmp.S
|
||||
endif
|
||||
endif
|
||||
|
||||
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_createstack.c
|
||||
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
|
||||
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
|
||||
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
|
||||
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
|
||||
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
|
||||
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_udelay.c
|
||||
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c
|
||||
|
||||
# Configuration-dependent common files
|
||||
|
||||
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
|
||||
CMN_CSRCS += arm_stackcheck.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARMV8M_LAZYFPU),y)
|
||||
CMN_ASRCS += arm_lazyexception.S
|
||||
else
|
||||
CMN_ASRCS += arm_exception.S
|
||||
endif
|
||||
CMN_CSRCS += arm_vectors.c
|
||||
|
||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||
CMN_ASRCS += arm_fpu.S
|
||||
CMN_CSRCS += arm_copyarmstate.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
|
||||
CMN_CSRCS += arm_signal_dispatch.c
|
||||
CMN_UASRCS += arm_signal_handler.S
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STACK_COLORATION),y)
|
||||
CMN_CSRCS += arm_checkstack.c
|
||||
endif
|
||||
|
||||
# Required STM32L5 files
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c
|
||||
CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c
|
||||
CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c stm32l5_waste.c stm32l5_uid.c
|
||||
CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c
|
||||
CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c
|
||||
|
||||
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
||||
CHIP_CSRCS += stm32l5_idle.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_TIMER),y)
|
||||
CHIP_CSRCS += stm32l5_tim_lowerhalf.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CHIP_CSRCS += stm32l5_userspace.c stm32l5_mpuinit.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_FEATURES),y)
|
||||
CHIP_CSRCS += stm32l5_dumpgpio.c
|
||||
endif
|
||||
|
||||
# Required chip type specific files
|
||||
|
||||
ifeq ($(CONFIG_STM32L5_STM32L562XX),y)
|
||||
CHIP_CSRCS += stm32l562xx_rcc.c
|
||||
endif
|
||||
@@ -0,0 +1,18 @@
|
||||
This is a port of NuttX to the STM32L5 Family
|
||||
|
||||
Used development boards are the Nucleo L552ZE-Q, and STM32L562E-DK.
|
||||
|
||||
Most code is copied and adapted from the STM32L4 port.
|
||||
|
||||
The only supported STM32L5 family currently is:
|
||||
|
||||
-----------------------------------------------------------------
|
||||
| NuttX config | Manual | Chips
|
||||
| STM32L5 | RM0438 | STM32L552xx and STM32L562xx
|
||||
------------------------------------------------------------------
|
||||
|
||||
TODO list
|
||||
---------
|
||||
|
||||
Extensive testing. Only initial sniff tests have been done.
|
||||
A prober TODO list should be generated.
|
||||
@@ -0,0 +1,56 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/chip.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_CHIP_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_CHIP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the memory map and the chip definitions file. Other chip hardware
|
||||
* files should then include this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include <arch/stm32l5/chip.h>
|
||||
#include "hardware/stm32l5_pinmap.h"
|
||||
#include "hardware/stm32l5_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* If the common ARMv8-M vector handling logic is used, then it expects the
|
||||
* following definition in this file that provides the number of supported
|
||||
* external interrupts which, for this architecture, is provided in the
|
||||
* arch/stm32l5/chip.h header file.
|
||||
*/
|
||||
|
||||
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS
|
||||
|
||||
/* Cache line sizes (in bytes) for the STM32L5 */
|
||||
|
||||
#define ARMV8M_DCACHE_LINESIZE 0 /* no cache */
|
||||
#define ARMV8M_ICACHE_LINESIZE 0 /* no cache */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */
|
||||
@@ -0,0 +1,118 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l562xx_dbgmcu.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Michael Jung <mijung@gmx.net>
|
||||
*
|
||||
* Based on arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_DBGMCU_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_DBGMCU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32_DBGMCU_IDCODE 0xe0044000 /* MCU identifier */
|
||||
#define STM32_DBGMCU_CR 0xe0044004 /* MCU debug */
|
||||
#define STM32_DBGMCU_APB1_FZ 0xe0044008 /* Debug MCU APB1 freeze register */
|
||||
#define STM32_DBGMCU_APB1_FZ2 0xe004400c /* Debug MCU APB1 freeze register 2 */
|
||||
#define STM32_DBGMCU_APB2_FZ 0xe0044010 /* Debug MCU APB2 freeze register */
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* MCU identifier */
|
||||
|
||||
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
|
||||
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
|
||||
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
|
||||
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
|
||||
|
||||
/* MCU debug */
|
||||
|
||||
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Allows debug in Stop mode */
|
||||
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Allows debug in Standby mode */
|
||||
#define DBGMCU_CR_TRACEIOEN (1 << 4) /* Bit 4: Trace pin enable */
|
||||
#define DBGMCU_CR_TRACEEN (1 << 5) /* Bit 5: Trace port and clock enable */
|
||||
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
|
||||
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
|
||||
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
|
||||
#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
|
||||
#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
|
||||
#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
|
||||
|
||||
/* Debug MCU APB1 freeze register */
|
||||
|
||||
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
|
||||
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
|
||||
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */
|
||||
|
||||
/* Debug MCU APB1 freeze register 2 */
|
||||
|
||||
#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopped when core is halted */
|
||||
#define DBGMCU_APB1_FZ2_LPTIM3STOP (1 << 6) /* Bit 6: LPTIM3 stopped when core is halted */
|
||||
#define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 stopped when core is halted */
|
||||
|
||||
/* Debug MCU APB2 freeze register */
|
||||
|
||||
#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 13: TIM8 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XXDBGMCU_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,135 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L5_STM32L562XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */
|
||||
#define STM32L5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32L5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */
|
||||
#define STM32L5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */
|
||||
#define STM32L5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */
|
||||
#define STM32L5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */
|
||||
#define STM32L5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */
|
||||
#define STM32L5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */
|
||||
#define STM32L5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SECCFGR_OFFSET)
|
||||
#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_FPUIMR_OFFSET)
|
||||
#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CNSLCKR_OFFSET)
|
||||
#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CSLCKR_OFFSET)
|
||||
#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SWPR2_OFFSET)
|
||||
#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_RSSCMDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* SYSCFG secure configuration register */
|
||||
|
||||
#define SYSCFG_SECCFGR_SYSCFGSEC (1 << 0) /* SYSCFG clock control security */
|
||||
#define SYSCFG_SECCFGR_CLASSBSEC (1 << 1) /* ClassB security */
|
||||
#define SYSCFG_SECCFGR_SRAM2SEC (1 << 2) /* SRAM2 security */
|
||||
#define SYSCFG_SECCFGR_FPUSEC (1 << 3) /* FPU security */
|
||||
|
||||
/* SYSCFG configuration register 1 */
|
||||
|
||||
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
|
||||
#define SYSCFG_CFGR1_ANASWVDD (1 << 9) /* Bit 9: GPIO analog switch control voltage selection */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
|
||||
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
|
||||
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
|
||||
|
||||
/* SYSCFG FPU interrupt mask register */
|
||||
|
||||
#define SYSCFG_FPUIMR_IE0 (1 << 0) /* Bit 0: FPU Invalid operation interrupt enable */
|
||||
#define SYSCFG_FPUIMR_IE1 (1 << 1) /* Bit 1: FPU Divide-by-zero interrupt enable */
|
||||
#define SYSCFG_FPUIMR_IE2 (1 << 2) /* Bit 2: FPU Underflow interrupt enable */
|
||||
#define SYSCFG_FPUIMR_IE3 (1 << 3) /* Bit 3: FPU Overflow interrupt enable */
|
||||
#define SYSCFG_FPUIMR_IE4 (1 << 4) /* Bit 4: FPU Input abnormal interrupt enable */
|
||||
#define SYSCFG_FPUIMR_IE5 (1 << 5) /* Bit 5: FPU Inexact interrupt enable */
|
||||
|
||||
/* SYSCFG CPU non-secure lock register */
|
||||
|
||||
#define SYSCFG_CNSLCKR_LOCKNSVTOR (1 << 0) /* Bit 0: VTOR_NS register lock */
|
||||
#define SYSCFG_CNSLCKR_LOCKNSMPU (1 << 1) /* Bit 1: Non-seucre MPU registers lock */
|
||||
|
||||
/* SYSCFG CPU secure lock register */
|
||||
|
||||
#define SYSCFG_CSLCKR_LOCKSVTAIRCR (1 << 0) /* Bit 0: VTOR_S register and AIRCR register bits lock */
|
||||
#define SYSCFG_CSLCKR_LOCKSMPU (1 << 1) /* Bit 1: Secure MPU registers lock */
|
||||
#define SYSCFG_CSLCKR_LOCKSAU (1 << 2) /* Bit 2: SAU registers lock */
|
||||
|
||||
/* SYSCFG configuration register 2 */
|
||||
|
||||
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M33 LOCKUP (hardfault) output enable */
|
||||
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock */
|
||||
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable */
|
||||
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock */
|
||||
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
|
||||
|
||||
/* SYSCFG SRAM2 control and status register */
|
||||
|
||||
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
|
||||
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
|
||||
|
||||
/* SYSCFG SRAM2 key register */
|
||||
|
||||
#define SYSCFG_SKR_SHIFT 0
|
||||
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
|
||||
|
||||
/* SYSCFG SRAM2 write protection register 1 and 2: There is one bit per SRAM2
|
||||
* page (0 to 31 and 32 to 63, respectively).
|
||||
*/
|
||||
|
||||
/* SYSCFG RSS command register */
|
||||
|
||||
#define SYSCFG_RSSCMDR_SHIFT 0
|
||||
#define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32L5_STM32L562XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H */
|
||||
@@ -0,0 +1,119 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l5_exti.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */
|
||||
#define STM32L5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */
|
||||
#define STM32L5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */
|
||||
#define STM32L5_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */
|
||||
#define STM32L5_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */
|
||||
#define STM32L5_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */
|
||||
#define STM32L5_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */
|
||||
#define STM32L5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */
|
||||
#define STM32L5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */
|
||||
#define STM32L5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */
|
||||
#define STM32L5_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */
|
||||
#define STM32L5_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */
|
||||
#define STM32L5_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */
|
||||
#define STM32L5_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */
|
||||
#define STM32L5_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */
|
||||
#define STM32L5_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */
|
||||
#define STM32L5_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */
|
||||
#define STM32L5_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */
|
||||
#define STM32L5_EXTI_LOCKR_OFFSET 0x0070 /* Lock */
|
||||
#define STM32L5_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */
|
||||
#define STM32L5_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */
|
||||
#define STM32L5_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */
|
||||
#define STM32L5_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_RTSR1_OFFSET)
|
||||
#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_FTSR1_OFFSET)
|
||||
#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE+STM32L5_EXTI_SWIER1_OFFSET)
|
||||
#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_RPR1_OFFSET)
|
||||
#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_FPR1_OFFSET)
|
||||
#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_SECCFGR1_OFFSET)
|
||||
#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_PRIVCFGR1_OFFSET)
|
||||
#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_RTSR2_OFFSET)
|
||||
#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_FTSR2_OFFSET)
|
||||
#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE+STM32L5_EXTI_SWIER2_OFFSET)
|
||||
#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_RPR2_OFFSET)
|
||||
#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_FPR2_OFFSET)
|
||||
#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_SECCFGR2_OFFSET)
|
||||
#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_PRIVCFGR2_OFFSET)
|
||||
#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR1_OFFSET)
|
||||
#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR2_OFFSET)
|
||||
#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR3_OFFSET)
|
||||
#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR4_OFFSET)
|
||||
#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE+STM32L5_EXTI_LOCKR_OFFSET)
|
||||
#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_IMR1_OFFSET)
|
||||
#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_EMR1_OFFSET)
|
||||
#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_IMR2_OFFSET)
|
||||
#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_EMR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* EXTI lines > 15 are associated with internal devices: */
|
||||
|
||||
#define EXTI1_PVD (1 << 16) /* EXTI line 16: PVD output */
|
||||
#define EXTI1_RTC (1 << 17) /* EXTI line 17: RTC */
|
||||
#define EXTI1_RTC_SECURE (1 << 18) /* EXTI line 18: RTC secure */
|
||||
#define EXTI1_TAMP (1 << 19) /* EXTI line 19: TAMP */
|
||||
#define EXTI1_TAMP_SECURE (1 << 20) /* EXTI line 20: TAMP secure */
|
||||
#define EXTI1_COMP1 (1 << 21) /* EXTI line 21: COMP1 output */
|
||||
#define EXTI1_COMP2 (1 << 22) /* EXTI line 22: COMP2 output */
|
||||
#define EXTI1_I2C1 (1 << 23) /* EXTI line 23: I2C1 wakeup */
|
||||
#define EXTI1_I2C2 (1 << 24) /* EXTI line 24: I2C2 wakeup */
|
||||
#define EXTI1_I2C3 (1 << 25) /* EXTI line 25: I2C3 wakeup */
|
||||
#define EXTI1_USART1 (1 << 26) /* EXTI line 26: USART1 wakeup */
|
||||
#define EXTI1_USART2 (1 << 27) /* EXTI line 27: USART2 wakeup */
|
||||
#define EXTI1_USART3 (1 << 28) /* EXTI line 28: USART3 wakeup */
|
||||
#define EXTI1_USART4 (1 << 29) /* EXTI line 29: USART4 wakeup */
|
||||
#define EXTI1_USART5 (1 << 30) /* EXTI line 30: USART5 wakeup */
|
||||
#define EXTI1_LPUART1 (1 << 31) /* EXTI line 31: LPUART1 wakeup */
|
||||
#define EXTI2_LPTIM1 (1 << 0) /* EXTI line 32: LPTIM1 */
|
||||
#define EXTI2_LPTIM2 (1 << 1) /* EXTI line 33: LPTIM2 */
|
||||
#define EXTI2_USBFS (1 << 2) /* EXTI line 34: USB FS wakeup */
|
||||
#define EXTI2_PVM1 (1 << 3) /* EXTI line 35: PVM1 wakeup */
|
||||
#define EXTI2_PVM2 (1 << 4) /* EXTI line 36: PVM2 wakeup */
|
||||
#define EXTI2_PVM3 (1 << 5) /* EXTI line 37: PVM3 wakeup */
|
||||
#define EXTI2_PVM4 (1 << 6) /* EXTI line 38: PVM4 wakeup */
|
||||
#define EXTI2_RSVD (1 << 7) /* EXTI line 39: reserved */
|
||||
#define EXTI2_I2C4 (1 << 8) /* EXTI line 40: I2C4 wakeup */
|
||||
#define EXTI2_UCPD1 (1 << 9) /* EXTI line 41: UCPD1 wakeup */
|
||||
#define EXTI2_LPTIM3 (1 << 10) /* EXTI line 42: LPTIM3 wakeup */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,153 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_MEMORYMAP_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/* STM32L5XXX Address Blocks *************************************************/
|
||||
|
||||
#define STM32L5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32L5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32L5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32L5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32L5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
#define STM32L5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
|
||||
# define STM32L5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32L5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32L5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
|
||||
#define STM32L5_REGION_MASK 0xF0000000
|
||||
#define STM32L5_IS_SRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_SRAM_BASE)
|
||||
#define STM32L5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_FMC_BANK1)
|
||||
|
||||
/* Code Base Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
#define STM32L5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */
|
||||
#define STM32L5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
|
||||
#define STM32L5_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
|
||||
|
||||
/* System Memory Addresses ***************************************************/
|
||||
|
||||
#define STM32L5_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */
|
||||
#define STM32L5_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */
|
||||
#define STM32L5_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */
|
||||
|
||||
/* Peripheral Base Addresses *************************************************/
|
||||
|
||||
#define STM32L5_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */
|
||||
#define STM32L5_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */
|
||||
#define STM32L5_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */
|
||||
#define STM32L5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */
|
||||
#define STM32L5_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */
|
||||
|
||||
/* APB1 Base Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_UCPD1_BASE 0x4000DC00
|
||||
#define STM32L5_USB_SRAM_BASE 0x4000D800
|
||||
#define STM32L5_USB_FS_BASE 0x4000D400
|
||||
#define STM32L5_FDCAN_RAM_BASE 0x4000AC00
|
||||
#define STM32L5_FDCAN1_BASE 0x4000A400
|
||||
#define STM32L5_LPTIM3_BASE 0x40009800
|
||||
#define STM32L5_LPTIM2_BASE 0x40009400
|
||||
#define STM32L5_I2C4_BASE 0x40008400
|
||||
#define STM32L5_LPUART1_BASE 0x40008000
|
||||
#define STM32L5_LPTIM1_BASE 0x40007C00
|
||||
#define STM32L5_OPAMP_BASE 0x40007800
|
||||
#define STM32L5_DAC_BASE 0x40007400
|
||||
#define STM32L5_PWR_BASE 0x40007000
|
||||
#define STM32L5_CRS_BASE 0x40006000
|
||||
#define STM32L5_I2C3_BASE 0x40005C00
|
||||
#define STM32L5_I2C2_BASE 0x40005800
|
||||
#define STM32L5_I2C1_BASE 0x40005400
|
||||
#define STM32L5_UART5_BASE 0x40005000
|
||||
#define STM32L5_UART4_BASE 0x40004C00
|
||||
#define STM32L5_USART3_BASE 0x40004800
|
||||
#define STM32L5_USART2_BASE 0x40004400
|
||||
#define STM32L5_SPI3_BASE 0x40003C00
|
||||
#define STM32L5_SPI2_BASE 0x40003800
|
||||
#define STM32L5_TAMP_BASE 0x40003400
|
||||
#define STM32L5_IWDG_BASE 0x40003000
|
||||
#define STM32L5_WWDG_BASE 0x40002C00
|
||||
#define STM32L5_RTC_BASE 0x40002800
|
||||
#define STM32L5_TIM7_BASE 0x40001400
|
||||
#define STM32L5_TIM6_BASE 0x40001000
|
||||
#define STM32L5_TIM5_BASE 0x40000C00
|
||||
#define STM32L5_TIM4_BASE 0x40000800
|
||||
#define STM32L5_TIM3_BASE 0x40000400
|
||||
#define STM32L5_TIM2_BASE 0x40000000
|
||||
|
||||
/* APB2 Base Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_DFSDM1_BASE 0x40016000
|
||||
#define STM32L5_SAI2_BASE 0x40015800
|
||||
#define STM32L5_SAI1_BASE 0x40015400
|
||||
#define STM32L5_TIM17_BASE 0x40014800
|
||||
#define STM32L5_TIM16_BASE 0x40014400
|
||||
#define STM32L5_TIM15_BASE 0x40014000
|
||||
#define STM32L5_USART1_BASE 0x40013800
|
||||
#define STM32L5_TIM8_BASE 0x40013400
|
||||
#define STM32L5_SPI1_BASE 0x40013000
|
||||
#define STM32L5_TIM1_BASE 0x40012C00
|
||||
#define STM32L5_COMP_BASE 0x40010200
|
||||
#define STM32L5_VREFBUF_BASE 0x40010100
|
||||
#define STM32L5_SYSCFG_BASE 0x40010000
|
||||
|
||||
/* AHB1 Base Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_GTZC_BASE 0x40032400
|
||||
#define STM32L5_ICACHE_BASE 0x40030400
|
||||
#define STM32L5_EXTI_BASE 0x4002F400
|
||||
#define STM32L5_TSC_BASE 0x40024000
|
||||
#define STM32L5_CRC_BASE 0x40023000
|
||||
#define STM32L5_FLASHIF_BASE 0x40022000
|
||||
#define STM32L5_RCC_BASE 0x40021000
|
||||
#define STM32L5_DMAMUX1_BASE 0x40020800
|
||||
#define STM32L5_DMA2_BASE 0x40020400
|
||||
#define STM32L5_DMA1_BASE 0x40020000
|
||||
|
||||
/* AHB2 Base Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_SDMMC1_BASE 0x420C8000
|
||||
#define STM32L5_OTFDEC1_BASE 0x420C5000
|
||||
#define STM32L5_PKA_BASE 0x420C2000
|
||||
#define STM32L5_RNG_BASE 0x420C0800
|
||||
#define STM32L5_HASH_BASE 0x420C0400
|
||||
#define STM32L5_AES_BASE 0x420C0000
|
||||
#define STM32L5_ADC_BASE 0x42028000
|
||||
#define STM32L5_GPIOH_BASE 0x42021C00
|
||||
#define STM32L5_GPIOG_BASE 0x42021800
|
||||
#define STM32L5_GPIOF_BASE 0x42021400
|
||||
#define STM32L5_GPIOE_BASE 0x42021000
|
||||
#define STM32L5_GPIOD_BASE 0x42020c00
|
||||
#define STM32L5_GPIOC_BASE 0x42020800
|
||||
#define STM32L5_GPIOB_BASE 0x42020400
|
||||
#define STM32L5_GPIOA_BASE 0x42020000
|
||||
|
||||
/* AHB2 Base Addresses *******************************************************/
|
||||
|
||||
#define STM32L5_OCTOSPI1_BASE 0x44021000
|
||||
#define STM32L5_FMC_BASE 0x44020000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MEMORYMAP_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L5_STM32L562XX)
|
||||
# include "hardware/stm32l562xx_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 L5 pin map"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,165 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l5_spi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
#if defined(CONFIG_STM32L5_STM32L562XX)
|
||||
# define STM32L5_SPI_CLK_MAX 55000000UL
|
||||
#else
|
||||
# error "Unsupported STM32 L5 chip"
|
||||
#endif
|
||||
|
||||
/* Register Offsets **********************************************************/
|
||||
|
||||
#define STM32L5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32L5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32L5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32L5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32L5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32L5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32L5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
/* Register Addresses ********************************************************/
|
||||
|
||||
#if STM32L5_NSPI > 0
|
||||
# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE+STM32L5_SPI_CR1_OFFSET)
|
||||
# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE+STM32L5_SPI_CR2_OFFSET)
|
||||
# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE+STM32L5_SPI_SR_OFFSET)
|
||||
# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE+STM32L5_SPI_DR_OFFSET)
|
||||
# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE+STM32L5_SPI_CRCPR_OFFSET)
|
||||
# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE+STM32L5_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE+STM32L5_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L5_NSPI > 1
|
||||
# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE+STM32L5_SPI_CR1_OFFSET)
|
||||
# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE+STM32L5_SPI_CR2_OFFSET)
|
||||
# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE+STM32L5_SPI_SR_OFFSET)
|
||||
# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE+STM32L5_SPI_DR_OFFSET)
|
||||
# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE+STM32L5_SPI_CRCPR_OFFSET)
|
||||
# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE+STM32L5_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE+STM32L5_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L5_NSPI > 2
|
||||
# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE+STM32L5_SPI_CR1_OFFSET)
|
||||
# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE+STM32L5_SPI_CR2_OFFSET)
|
||||
# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE+STM32L5_SPI_SR_OFFSET)
|
||||
# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE+STM32L5_SPI_DR_OFFSET)
|
||||
# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE+STM32L5_SPI_CRCPR_OFFSET)
|
||||
# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE+STM32L5_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE+STM32L5_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions *********************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
|
||||
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
|
||||
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
|
||||
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
|
||||
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
|
||||
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
|
||||
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
|
||||
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
|
||||
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
|
||||
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
|
||||
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
|
||||
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
|
||||
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
|
||||
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
|
||||
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
|
||||
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
|
||||
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
|
||||
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
|
||||
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
|
||||
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
|
||||
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
|
||||
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
|
||||
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
|
||||
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
|
||||
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
|
||||
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
|
||||
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
|
||||
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
|
||||
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
|
||||
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
|
||||
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
|
||||
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_VAL(bits) ( ((bits)-1) << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
|
||||
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
|
||||
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
|
||||
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
|
||||
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
|
||||
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
|
||||
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
|
||||
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
|
||||
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
|
||||
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
|
||||
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
|
||||
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
|
||||
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
|
||||
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
|
||||
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
|
||||
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
|
||||
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
|
||||
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
|
||||
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
|
||||
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
|
||||
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
|
||||
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
|
||||
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
|
||||
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L5_STM32L562XX)
|
||||
# include "hardware/stm32l562xx_syscfg.h"
|
||||
#else
|
||||
# error "Unsupported STM32 L5 chip"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,48 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
|
||||
/* Peripherals ***************************************************************/
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32l5_dbgmcu.h"
|
||||
#include "stm32l5_flash.h"
|
||||
#include "stm32l5_gpio.h"
|
||||
#include "stm32l5_pwr.h"
|
||||
#include "stm32l5_rcc.h"
|
||||
#include "stm32l5_spi.h"
|
||||
#include "stm32l5_tim.h"
|
||||
#include "stm32l5_uart.h"
|
||||
#include "stm32l5_lowputc.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_dbgmcu.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L5_STM32L562XX)
|
||||
# include "hardware/stm32l562xx_dbgmcu.h"
|
||||
#else
|
||||
# error "Unsupported STM32L5 chip"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H */
|
||||
@@ -0,0 +1,139 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_dumpgpio.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Output debug info even if debug output is not selected. */
|
||||
|
||||
#undef CONFIG_DEBUG_INFO
|
||||
#define CONFIG_DEBUG_INFO 1
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
#include "chip.h"
|
||||
#include "stm32l5_gpio.h"
|
||||
#include "stm32l5_rcc.h"
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Port letters for prettier debug output */
|
||||
|
||||
static const char g_portchar[STM32L5_NPORTS] =
|
||||
{
|
||||
#if STM32L5_NPORTS > 11
|
||||
# error "Additional support required for this number of GPIOs"
|
||||
#elif STM32L5_NPORTS > 10
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
|
||||
#elif STM32L5_NPORTS > 9
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
|
||||
#elif STM32L5_NPORTS > 8
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
|
||||
#elif STM32L5_NPORTS > 7
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
|
||||
#elif STM32L5_NPORTS > 6
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G'
|
||||
#elif STM32L5_NPORTS > 5
|
||||
'A', 'B', 'C', 'D', 'E', 'F'
|
||||
#elif STM32L5_NPORTS > 4
|
||||
'A', 'B', 'C', 'D', 'E'
|
||||
#elif STM32L5_NPORTS > 3
|
||||
'A', 'B', 'C', 'D'
|
||||
#elif STM32L5_NPORTS > 2
|
||||
'A', 'B', 'C'
|
||||
#elif STM32L5_NPORTS > 1
|
||||
'A', 'B'
|
||||
#elif STM32L5_NPORTS > 0
|
||||
'A'
|
||||
#else
|
||||
# error "Bad number of GPIOs"
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32l5_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the provided base address
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32l5_dumpgpio(uint32_t pinset, const char *msg)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t base;
|
||||
unsigned int port;
|
||||
|
||||
/* Get the base address associated with the GPIO port */
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
base = g_gpiobase[port];
|
||||
|
||||
/* The following requires exclusive access to the GPIO registers */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
DEBUGASSERT(port < STM32L5_NPORTS);
|
||||
|
||||
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
|
||||
g_portchar[port], pinset, base, msg);
|
||||
|
||||
if ((getreg32(STM32L5_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
|
||||
{
|
||||
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
|
||||
getreg32(base + STM32L5_GPIO_MODER_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_OTYPER_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_OSPEED_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_PUPDR_OFFSET));
|
||||
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
|
||||
getreg32(base + STM32L5_GPIO_IDR_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_ODR_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_BSRR_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_LCKR_OFFSET));
|
||||
_info(" AFRH: %08x AFRL: %08x\n",
|
||||
getreg32(base + STM32L5_GPIO_AFRH_OFFSET),
|
||||
getreg32(base + STM32L5_GPIO_AFRL_OFFSET));
|
||||
}
|
||||
else
|
||||
{
|
||||
_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
|
||||
g_portchar[port], getreg32(STM32L5_RCC_AHB2ENR));
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DEBUG_FEATURES */
|
||||
@@ -0,0 +1,153 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_exti.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32l5_exti.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_gpiosetevent
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
*
|
||||
* Input Parameters:
|
||||
* pinset - GPIO pin configuration
|
||||
* risingedge - Enables interrupt on rising edges
|
||||
* fallingedge - Enables interrupt on falling edges
|
||||
* event - Generate event when set
|
||||
* func - When non-NULL, generate interrupt
|
||||
* arg - Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success, otherwise a negated errno value is
|
||||
* returned to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
bool event, xcpt_t func, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_exti_alarm
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears EXTI alarm interrupt.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - rising/falling edge: enables interrupt on rising/falling edges
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure indicating the
|
||||
* nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event,
|
||||
xcpt_t func, void *arg);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_exti_wakeup
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears EXTI wakeup interrupt.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - rising/falling edge: enables interrupt on rising/falling edges
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure indicating the
|
||||
* nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_PERIODIC
|
||||
int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event,
|
||||
xcpt_t func, void *arg);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_exti_comp
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears comparator based events and interrupt triggers.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - cmp: comparator
|
||||
* - rising/falling edge: enables interrupt on rising/falling edges
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
* - arg: Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) returned on success; a negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L5_COMP
|
||||
int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge,
|
||||
bool event, xcpt_t func, void *arg);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H */
|
||||
@@ -0,0 +1,172 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_exti_gpio.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
#include "chip.h"
|
||||
#include "stm32l5_gpio.h"
|
||||
#include "stm32l5_exti.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
struct gpio_callback_s
|
||||
{
|
||||
xcpt_t callback; /* Callback entry point */
|
||||
void *arg; /* The argument that accompanies the callback */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Interrupt handlers attached to each EXTI */
|
||||
|
||||
static struct gpio_callback_s g_gpio_handlers[16];
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Interrupt Service Routine - Dispatcher
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32l5_exti0_15_isr(int irq, void *context, FAR void *arg)
|
||||
{
|
||||
int ret = OK;
|
||||
int exti;
|
||||
|
||||
exti = irq - STM32L5_IRQ_EXTI0;
|
||||
DEBUGASSERT((exti >= 0) && (exti <= 15));
|
||||
|
||||
/* Clear the pending interrupt for both rising and falling edges. */
|
||||
|
||||
putreg32(0x0001 << exti, STM32L5_EXTI_RPR1);
|
||||
putreg32(0x0001 << exti, STM32L5_EXTI_FPR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
if (g_gpio_handlers[exti].callback != NULL)
|
||||
{
|
||||
xcpt_t callback = g_gpio_handlers[exti].callback;
|
||||
void *cbarg = g_gpio_handlers[exti].arg;
|
||||
|
||||
ret = callback(irq, context, cbarg);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_gpiosetevent
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears GPIO based event and interrupt triggers.
|
||||
*
|
||||
* Input Parameters:
|
||||
* pinset - GPIO pin configuration
|
||||
* risingedge - Enables interrupt on rising edges
|
||||
* fallingedge - Enables interrupt on falling edges
|
||||
* event - Generate event when set
|
||||
* func - When non-NULL, generate interrupt
|
||||
* arg - Argument passed to the interrupt callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success, otherwise a negated errno value is
|
||||
* returned to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
bool event, xcpt_t func, void *arg)
|
||||
{
|
||||
uint32_t pin = pinset & GPIO_PIN_MASK;
|
||||
uint32_t exti = 1 << pin;
|
||||
int irq = STM32L5_IRQ_EXTI0 + pin;
|
||||
|
||||
g_gpio_handlers[pin].callback = func;
|
||||
g_gpio_handlers[pin].arg = arg;
|
||||
|
||||
/* Install external interrupt handlers */
|
||||
|
||||
if (func)
|
||||
{
|
||||
irq_attach(irq, stm32l5_exti0_15_isr, NULL);
|
||||
up_enable_irq(irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(irq);
|
||||
}
|
||||
|
||||
/* Configure GPIO, enable EXTI line enabled if event or interrupt is
|
||||
* enabled.
|
||||
*/
|
||||
|
||||
if (event || func)
|
||||
{
|
||||
pinset |= GPIO_EXTI;
|
||||
}
|
||||
|
||||
stm32l5_configgpio(pinset);
|
||||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32L5_EXTI_RTSR1,
|
||||
risingedge ? 0 : exti,
|
||||
risingedge ? exti : 0);
|
||||
modifyreg32(STM32L5_EXTI_FTSR1,
|
||||
fallingedge ? 0 : exti,
|
||||
fallingedge ? exti : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32L5_EXTI_EMR1,
|
||||
event ? 0 : exti,
|
||||
event ? exti : 0);
|
||||
modifyreg32(STM32L5_EXTI_IMR1,
|
||||
func ? 0 : exti,
|
||||
func ? exti : 0);
|
||||
|
||||
return OK;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,79 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_flash.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Michael Jung <mijung@gmx.net>
|
||||
*
|
||||
* Based on arch/arm/src/stm32l4/stm32l4_flash.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/stm32l5_flash.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_flash_lock(void);
|
||||
void stm32l5_flash_unlock(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_flash_user_optbytes
|
||||
*
|
||||
* Description:
|
||||
* Modify the contents of the user option bytes (USR OPT) on the flash.
|
||||
* This does not set OBL_LAUNCH so new options take effect only after
|
||||
* next power reset.
|
||||
*
|
||||
* Input Parameters:
|
||||
* clrbits - Bits in the option bytes to be cleared
|
||||
* setbits - Bits in the option bytes to be set
|
||||
*
|
||||
* Returned Value:
|
||||
* Option bytes after operation is completed
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,100 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_idle.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/power/pm.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32l5_rcc.h"
|
||||
#include "arm_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
|
||||
# define END_IDLE() board_autoled_off(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
#define up_idlepm()
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when their is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
nxsched_process_timer();
|
||||
#else
|
||||
|
||||
/* Perform IDLE mode power management */
|
||||
|
||||
up_idlepm();
|
||||
|
||||
/* Sleep until an interrupt occurs to save power. */
|
||||
|
||||
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,64 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_lowputc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level
|
||||
* initialization of serial console.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_lowsetup(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H */
|
||||
@@ -0,0 +1,166 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_lse.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Michael Jung <mijung@gmx.net>
|
||||
*
|
||||
* Based on arch/arm/src/stm32l4/stm32l4_lse.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: dev@ziggurat29.com
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "stm32l5_pwr.h"
|
||||
#include "stm32l5_rcc.h"
|
||||
#include "stm32l5_waste.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY
|
||||
# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
|
||||
CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
|
||||
# error "Invalid LSE drive capability setting"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY
|
||||
# if CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
|
||||
CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
|
||||
# error "Invalid LSE drive capability setting"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External Low-Speed (LSE) oscillator and the LSE system clock.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_rcc_enablelse(void)
|
||||
{
|
||||
bool writable;
|
||||
uint32_t regval;
|
||||
|
||||
/* Check if both the External Low-Speed (LSE) oscillator and the LSE system
|
||||
* clock are already running.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L5_RCC_BDCR);
|
||||
|
||||
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
|
||||
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) !=
|
||||
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
|
||||
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN))
|
||||
{
|
||||
/* The LSE is in the RTC domain and write access is denied to this
|
||||
* domain after reset, you have to enable write access using DBP bit in
|
||||
* the PWR CR register before to configuring the LSE.
|
||||
*/
|
||||
|
||||
writable = stm32l5_pwr_enablebkp(true);
|
||||
|
||||
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON
|
||||
* bit the RCC BDCR register.
|
||||
*/
|
||||
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
|
||||
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY
|
||||
/* Set start-up drive capability for LSE oscillator. */
|
||||
|
||||
regval &= ~RCC_BDCR_LSEDRV_MASK;
|
||||
regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
|
||||
RCC_BDCR_LSEDRV_SHIFT;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L5_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE clock to be ready */
|
||||
|
||||
while (((regval = getreg32(STM32L5_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0)
|
||||
{
|
||||
up_waste();
|
||||
}
|
||||
|
||||
/* Enable LSE system clock. The LSE system clock has been introduced
|
||||
* first by the STM32L5 family of MCUs. It seems to provide a means
|
||||
* to gate the LSE clock distribution to peripherals. It must be
|
||||
* enabled for MSI PLL mode (syncing the MSI to the LSE).
|
||||
*/
|
||||
|
||||
regval |= RCC_BDCR_LSESYSEN;
|
||||
|
||||
putreg32(regval, STM32L5_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE system clock to be ready */
|
||||
|
||||
while (!((regval = getreg32(STM32L5_RCC_BDCR)) & RCC_BDCR_LSESYSRDY))
|
||||
{
|
||||
up_waste();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \
|
||||
CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY != \
|
||||
CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY
|
||||
|
||||
# if CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0
|
||||
# error "STM32L5 only allows lowering LSE drive capability to zero"
|
||||
# endif
|
||||
|
||||
/* Set running drive capability for LSE oscillator. */
|
||||
|
||||
regval &= ~RCC_BDCR_LSEDRV_MASK;
|
||||
regval |= CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
|
||||
RCC_BDCR_LSEDRV_SHIFT;
|
||||
putreg32(regval, STM32L5_RCC_BDCR);
|
||||
#endif
|
||||
|
||||
/* Disable backup domain access if it was disabled on entry */
|
||||
|
||||
(void)stm32l5_pwr_enablebkp(writable);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,92 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_lsi.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Michael Jung <mijung@gmx.net>
|
||||
*
|
||||
* Based on arch/arm/src/stm32l4/stm32l4_lsi.c
|
||||
*
|
||||
* Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "arm_arch.h"
|
||||
#include "stm32l5_rcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_rcc_enablelsi
|
||||
*
|
||||
* Description:
|
||||
* Enable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_rcc_enablelsi(void)
|
||||
{
|
||||
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
|
||||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32L5_RCC_CSR, 0, RCC_CSR_LSION);
|
||||
|
||||
/* Wait for the internal LSI oscillator to be stable. */
|
||||
|
||||
while ((getreg32(STM32L5_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_rcc_disablelsi
|
||||
*
|
||||
* Description:
|
||||
* Disable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_rcc_disablelsi(void)
|
||||
{
|
||||
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
|
||||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32L5_RCC_CSR, RCC_CSR_LSION, 0);
|
||||
|
||||
/* LSIRDY should go low after 3 LSI clock cycles */
|
||||
}
|
||||
@@ -0,0 +1,100 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_mpuinit.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/userspace.h>
|
||||
|
||||
#include "mpu.h"
|
||||
#include "stm32l5_mpuinit.h"
|
||||
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef MAX
|
||||
# define MAX(a,b) a > b ? a : b
|
||||
#endif
|
||||
|
||||
#ifndef MIN
|
||||
# define MIN(a,b) a < b ? a : b
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_mpuinitialize
|
||||
*
|
||||
* Description:
|
||||
* Configure the MPU to permit user-space access to only restricted SAM3U
|
||||
* resources.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_mpuinitialize(void)
|
||||
{
|
||||
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
|
||||
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
|
||||
dataend >= datastart);
|
||||
|
||||
/* Show MPU information */
|
||||
|
||||
mpu_showtype();
|
||||
|
||||
/* Configure user flash and SRAM space */
|
||||
|
||||
mpu_user_flash(USERSPACE->us_textstart,
|
||||
USERSPACE->us_textend - USERSPACE->us_textstart);
|
||||
|
||||
mpu_user_intsram(datastart, dataend - datastart);
|
||||
|
||||
/* Then enable the MPU */
|
||||
|
||||
mpu_control(true, false, true);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_mpu_uheap
|
||||
*
|
||||
* Description:
|
||||
* Map the user-heap region.
|
||||
*
|
||||
* This logic may need an extension to handle external SDRAM).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32l5_mpu_uheap(uintptr_t start, size_t size)
|
||||
{
|
||||
mpu_user_intsram(start, size);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */
|
||||
@@ -0,0 +1,63 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_mpuinit.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_mpuinitialize
|
||||
*
|
||||
* Description:
|
||||
* Configure the MPU to permit user-space access to only unrestricted MCU
|
||||
* resources.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
void stm32l5_mpuinitialize(void);
|
||||
#else
|
||||
# define stm32l5_mpuinitialize()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_mpu_uheap
|
||||
*
|
||||
* Description:
|
||||
* Map the user heap region.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
void stm32l5_mpu_uheap(uintptr_t start, size_t size);
|
||||
#else
|
||||
# define stm32l5_mpu_uheap(start,size)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,131 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_pwr.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32l5_pwr.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: enableclk
|
||||
*
|
||||
* Description:
|
||||
* Enable/disable the clock to the power control peripheral. Enabling must
|
||||
* be done after the APB1 clock is validly configured, and prior to using
|
||||
* any functionality controlled by the PWR block (i.e. much of anything
|
||||
* else provided by this module).
|
||||
*
|
||||
* Input Parameters:
|
||||
* enable - True: enable the clock to the Power control (PWR) block.
|
||||
*
|
||||
* Returned Value:
|
||||
* True: the PWR block was previously enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32l5_pwr_enableclk(bool enable);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables access to the backup domain (RTC registers, RTC backup data
|
||||
* registers and backup SRAM).
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* True: The backup domain was previously writable.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32l5_pwr_enablebkp(bool writable);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_pwr_enableusv
|
||||
*
|
||||
* Description:
|
||||
* Enables or disables the USB Supply Valid monitoring. Setting this bit
|
||||
* is mandatory to use the USB OTG FS peripheral.
|
||||
*
|
||||
* Input Parameters:
|
||||
* set - True: Vddusb is valid; False: Vddusb is not present. Logical and
|
||||
* electrical isolation is applied to ignore this supply.
|
||||
*
|
||||
* Returned Value:
|
||||
* True: The bit was previously set.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32l5_pwr_enableusv(bool set);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l5_pwr_vddio2_valid
|
||||
*
|
||||
* Description:
|
||||
* Report that the Vddio2 independent I/Os supply voltage is valid or not.
|
||||
* Setting this bit is mandatory to use the PG2 - PG15 I/Os.
|
||||
*
|
||||
* Input Parameters:
|
||||
* set - True: Vddio2 is value; False: Vddio2 is not present. Logical and
|
||||
* electrical isolation is applied to ignore this supply.
|
||||
*
|
||||
* Returned Value:
|
||||
* True: The bit was previously set.
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32l5_pwr_vddio2_valid(bool set);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,192 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_spi.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Michael Jung <mijung@gmx.net>
|
||||
*
|
||||
* Based on arch/arm/src/stm32l4/stm32l4_spi.h
|
||||
*
|
||||
* Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32l5_spi.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Data
|
||||
*****************************************************************************/
|
||||
|
||||
struct spi_dev_s;
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32l5_spibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI bus
|
||||
*
|
||||
* Input Parameters:
|
||||
* bus number (for hardware that has multiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *stm32l5_spibus_initialize(int bus);
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32l5_spi1/2/...select and stm32l5_spi1/2/...status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32l5_spi1/2/...select,
|
||||
* stm32l5_spi1/2/...status, and stm32l5_spi1/2/...cmddata must be provided
|
||||
* by board-specific logic. These are implementations of the select,
|
||||
* status, and cmddata methods of the SPI interface defined by struct
|
||||
* spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including
|
||||
* stm32l5_spibus_initialize()) are provided by common STM32 logic. To use
|
||||
* this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in stm32l5_board_initialize() to configure SPI chip
|
||||
* select pins.
|
||||
* 2. Provide stm32l5_spi1/2/...select() and stm32l5_spi1/2/...status()
|
||||
* functions in your board-specific logic. These functions will perform
|
||||
* chip selection and status operations using GPIOs in the way your board
|
||||
* is configured.
|
||||
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
|
||||
* then provide stm32l5_spi1/2/...cmddata() functions in your
|
||||
* board-specific logic. These functions will perform cmd/data selection
|
||||
* operations using GPIOs in the way your board is configured.
|
||||
* 4. Add a calls to stm32l5_spibus_initialize() in your low level
|
||||
* application initialization logic
|
||||
* 5. The handle returned by stm32l5_spibus_initialize() may then be used to
|
||||
* bind the SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L5_SPI1
|
||||
void stm32l5_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32l5_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32l5_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L5_SPI2
|
||||
void stm32l5_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32l5_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32l5_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L5_SPI3
|
||||
void stm32l5_spi3select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t stm32l5_spi3status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
int stm32l5_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32l5_spi1/2/...register
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based
|
||||
* MMC/SD driver when an SD card is inserted or removed, then
|
||||
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
|
||||
* be implemented. These functions implements the registercallback method
|
||||
* of the SPI interface (see include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The function to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_STM32L5_SPI1
|
||||
int stm32l5_spi1register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L5_SPI2
|
||||
int stm32l5_spi2register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L5_SPI3
|
||||
int stm32l5_spi3register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,44 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_start.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_START_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_START_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32l5_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32L5 architectures must provide the following entry point. This
|
||||
* entry point is called early in the initialization -- after all memory has
|
||||
* been configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
void stm32l5_board_initialize(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_START_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,149 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_timerisr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock/clock.h"
|
||||
#include "arm_internal.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32l5.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
|
||||
* divided by 8. The SysTick can work either with this clock or with the
|
||||
* Cortex clock (HCLK), configurable in the SysTick Control and Status
|
||||
* register.
|
||||
*/
|
||||
|
||||
/* Power up default is HCLK, not HCLK/8. And I don't know now to re-configure
|
||||
* it yet
|
||||
*/
|
||||
|
||||
#undef CONFIG_STM32L5_SYSTICK_HCLKd8
|
||||
|
||||
#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8
|
||||
# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
|
||||
#else
|
||||
# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / CLK_TCK) - 1)
|
||||
#endif
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Private Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: stm32l5_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static int stm32l5_timerisr(int irq, uint32_t *regs, void *arg)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
nxsched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
|
||||
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
|
||||
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
|
||||
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
|
||||
|
||||
/* Make sure that the SYSTICK clock source is set correctly */
|
||||
|
||||
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
|
||||
regval = getreg32(NVIC_SYSTICK_CTRL);
|
||||
#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8
|
||||
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
|
||||
#else
|
||||
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
|
||||
#endif
|
||||
putreg32(regval, NVIC_SYSTICK_CTRL);
|
||||
#endif
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL);
|
||||
|
||||
/* Enable SysTick interrupts */
|
||||
|
||||
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
|
||||
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(STM32L5_IRQ_SYSTICK);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,46 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_uid.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hardware/stm32l5_memorymap.h"
|
||||
#include "stm32l5_uid.h"
|
||||
|
||||
#ifdef STM32L5_SYSMEM_UID
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
void stm32l5_get_uniqueid(uint8_t uniqueid[12])
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 12; i++)
|
||||
{
|
||||
uniqueid[i] = *((uint8_t *)(STM32L5_SYSMEM_UID) + i);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* STM32L5_SYSMEM_UID */
|
||||
@@ -0,0 +1,36 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_uid.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
void stm32l5_get_uniqueid(uint8_t uniqueid[12]);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H */
|
||||
@@ -0,0 +1,91 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_userspace.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/userspace.h>
|
||||
|
||||
#include "stm32l5_mpuinit.h"
|
||||
#include "stm32l5_userspace.h"
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32l5_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
void stm32l5_userspace(void)
|
||||
{
|
||||
uint8_t *src;
|
||||
uint8_t *dest;
|
||||
uint8_t *end;
|
||||
|
||||
/* Clear all of user-space .bss */
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
|
||||
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
|
||||
|
||||
dest = (uint8_t *)USERSPACE->us_bssstart;
|
||||
end = (uint8_t *)USERSPACE->us_bssend;
|
||||
|
||||
while (dest != end)
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
/* Initialize all of user-space .data */
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
|
||||
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
|
||||
USERSPACE->us_datastart <= USERSPACE->us_dataend);
|
||||
|
||||
src = (uint8_t *)USERSPACE->us_datasource;
|
||||
dest = (uint8_t *)USERSPACE->us_datastart;
|
||||
end = (uint8_t *)USERSPACE->us_dataend;
|
||||
|
||||
while (dest != end)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Configure the MPU to permit user-space access to its FLASH and RAM */
|
||||
|
||||
stm32l5_mpuinitialize();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BUILD_PROTECTED */
|
||||
@@ -0,0 +1,49 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_userspace.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32l5_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
void stm32l5_userspace(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H */
|
||||
@@ -0,0 +1,42 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_waste.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include "stm32l5_waste.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private Data
|
||||
*****************************************************************************/
|
||||
|
||||
uint32_t idle_wastecounter = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
void up_waste(void)
|
||||
{
|
||||
idle_wastecounter++;
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/stm32l5/stm32l5_waste.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H
|
||||
#define __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H
|
||||
|
||||
/* Waste CPU Time */
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
/* Waste CPU Time
|
||||
*
|
||||
* up_waste() is the logic that will be executed when portions of kernel
|
||||
* or user-app is polling some register or similar, waiting for desired
|
||||
* status. This time is wasted away. This function offers a measure of
|
||||
* badly written piece of software or some undesired behavior.
|
||||
*
|
||||
* At the same time this function adds to some IDLE time which portion
|
||||
* cannot be used for other purposes (yet).
|
||||
*/
|
||||
|
||||
void up_waste(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H */
|
||||
Reference in New Issue
Block a user