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stm32l5: Architecture Support for STM32L5

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Architecture support for STMicroelectronics STM32L552xx and STM32L562xx
MCUs.  This is based on corresponding code for STM32L4, but has been
considerably adjusted.  Tested with Nucleo-L552ZE-Q and STM32L562E-DK
boards with simple NSH configurations.

Signed-off-by: Michael Jung <mijung@gmx.net>
This commit is contained in:
Michael Jung
2021-03-03 18:19:51 +01:00
committed by Xiang Xiao
parent c9db653c8d
commit f3a5675cc4
62 changed files with 23432 additions and 0 deletions
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arch/arm/Kconfig
+18
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@@ -396,6 +396,20 @@ config ARCH_CHIP_STM32L4
---help---
STMicro STM32 architectures (ARM Cortex-M4).
config ARCH_CHIP_STM32L5
bool "STMicro STM32 L5"
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS
select ARM_HAVE_MPU_UNIFIED
select ARMV8M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M33).
config ARCH_CHIP_STR71X
bool "STMicro STR71x"
select ARCH_ARM7TDMI
@@ -769,6 +783,7 @@ config ARCH_CHIP
default "stm32f7" if ARCH_CHIP_STM32F7
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
default "stm32l5" if ARCH_CHIP_STM32L5
default "str71x" if ARCH_CHIP_STR71X
default "tms570" if ARCH_CHIP_TMS570
default "xmc4" if ARCH_CHIP_XMC4
@@ -1027,6 +1042,9 @@ endif
if ARCH_CHIP_STM32L4
source arch/arm/src/stm32l4/Kconfig
endif
if ARCH_CHIP_STM32L5
source arch/arm/src/stm32l5/Kconfig
endif
if ARCH_CHIP_STR71X
source arch/arm/src/str71x/Kconfig
endif
arch/arm/include/stm32l5/chip.h
+81
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@@ -0,0 +1,81 @@
/*****************************************************************************
* arch/arm/include/stm32l5/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32L5_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32L5_CHIP_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
#if defined(CONFIG_STM32L5_STM32L562XX)
# define STM32L5_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32L5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
#else
# error "Unsupported STM32L5 chip"
#endif
#if defined(CONFIG_STM32L5_STM32L562XX)
# define STM32L5_NFSMC 1 /* Have FSMC memory controller */
# define STM32L5_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32L5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32L5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32L5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
# define STM32L5_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32L5_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
# define STM32L5_NRNG 1 /* Random number generator (RNG) */
# define STM32L5_NUART 2 /* UART 4-5 */
# define STM32L5_NUSART 3 /* USART 1-3 */
# define STM32L5_NLPUART 1 /* LPUART 1 */
# define STM32L5_QSPI 0 /* No QuadSPI1 */
# define STM32L5_OCTOSPI 2 /* OCTOSPI1-2 */
# define STM32L5_NSPI 3 /* SPI1-3 */
# define STM32L5_NI2C 4 /* I2C1-4 */
# define STM32L5_NSWPMI 0 /* No SWPMI1 */
# define STM32L5_NUSBOTGFS 1 /* USB OTG FS */
# define STM32L5_NUSBFS 0 /* No USB FS */
# define STM32L5_NCAN 1 /* CAN1 */
# define STM32L5_NSAI 2 /* SAI1-2 */
# define STM32L5_NSDMMC 1 /* SDMMC interface */
# define STM32L5_NDMA 2 /* DMA1-2 */
# define STM32L5_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
# define STM32L5_NADC 1 /* 12-bit ADC1, up to 20 channels */
# define STM32L5_NDAC 2 /* 12-bit DAC1-2 */
# define STM32L5_NCRC 1 /* CRC */
# define STM32L5_NCOMP 2 /* Comparators */
# define STM32L5_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32L5_STM32L562XX */
/* NVIC priority levels ******************************************************/
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_STM32L5_CHIP_H */
arch/arm/include/stm32l5/irq.h
+40
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@@ -0,0 +1,40 @@
/*****************************************************************************
* arch/arm/include/stm32l5/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32L5_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32L5_IRQ_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_STM32L5_STM32L562XX)
# include <arch/stm32l5/stm32l562xx_irq.h>
#else
# error "Unsupported STM32 L5 chip"
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32L5_IRQ_H */
arch/arm/include/stm32l5/stm32l562xx_irq.h
+171
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@@ -0,0 +1,171 @@
/*****************************************************************************
* arch/arm/include/stm32l5/stm32l562xx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32l5/stm32l5_irq.h>
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in the file nuttx/arch/arm/include/stm32l5/stm32l5_irq.h, which is included
* above.
*
* External interrupts (vectors >= 16)
*
* These interrupts vectors was implemented based on RM0438 Table 88
* (STM32L552xx and STM32L562xx vector table) and should work for
* STM32L552xx and STL32L562xx.
*
*/
#define STM32L5_IRQ_WWDG (STM32L5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32L5_IRQ_PVD_PVM (STM32L5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */
#define STM32L5_IRQ_RTC (STM32L5_IRQ_FIRST + 2) /* 2: RTC global interrupts */
#define STM32L5_IRQ_RTC_S (STM32L5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */
#define STM32L5_IRQ_TAMP (STM32L5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */
#define STM32L5_IRQ_TAMP_S (STM32L5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */
#define STM32L5_IRQ_FLASH (STM32L5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */
#define STM32L5_IRQ_FLASH_S (STM32L5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */
#define STM32L5_IRQ_GTZC (STM32L5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */
#define STM32L5_IRQ_RCC (STM32L5_IRQ_FIRST + 9) /* 9: RCC global interrupt */
#define STM32L5_IRQ_RCC_S (STM32L5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */
#define STM32L5_IRQ_EXTI0 (STM32L5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */
#define STM32L5_IRQ_EXTI1 (STM32L5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */
#define STM32L5_IRQ_EXTI2 (STM32L5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */
#define STM32L5_IRQ_EXTI3 (STM32L5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */
#define STM32L5_IRQ_EXTI4 (STM32L5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */
#define STM32L5_IRQ_EXTI5 (STM32L5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */
#define STM32L5_IRQ_EXTI6 (STM32L5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */
#define STM32L5_IRQ_EXTI7 (STM32L5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */
#define STM32L5_IRQ_EXTI8 (STM32L5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */
#define STM32L5_IRQ_EXTI9 (STM32L5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */
#define STM32L5_IRQ_EXTI10 (STM32L5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */
#define STM32L5_IRQ_EXTI11 (STM32L5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */
#define STM32L5_IRQ_EXTI12 (STM32L5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */
#define STM32L5_IRQ_EXTI13 (STM32L5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */
#define STM32L5_IRQ_EXTI14 (STM32L5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */
#define STM32L5_IRQ_EXTI15 (STM32L5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */
#define STM32L5_IRQ_DMAMUX1_OVR (STM32L5_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */
#define STM32L5_IRQ_DMAMUX1_OVR_S (STM32L5_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */
#define STM32L5_IRQ_DMA1CH1 (STM32L5_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */
#define STM32L5_IRQ_DMA1CH2 (STM32L5_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */
#define STM32L5_IRQ_DMA1CH3 (STM32L5_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */
#define STM32L5_IRQ_DMA1CH4 (STM32L5_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */
#define STM32L5_IRQ_DMA1CH5 (STM32L5_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */
#define STM32L5_IRQ_DMA1CH6 (STM32L5_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */
#define STM32L5_IRQ_DMA1CH7 (STM32L5_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */
#define STM32L5_IRQ_DMA1CH8 (STM32L5_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */
#define STM32L5_IRQ_ADC1_2 (STM32L5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */
#define STM32L5_IRQ_DAC (STM32L5_IRQ_FIRST + 38) /* 38: DAC global interrupt */
#define STM32L5_IRQ_FDCAN1_IT0 (STM32L5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */
#define STM32L5_IRQ_FDCAN1_IT1 (STM32L5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */
#define STM32L5_IRQ_TIM1_BRK (STM32L5_IRQ_FIRST + 41) /* 41: TIM1 break */
#define STM32L5_IRQ_TIM1_UP (STM32L5_IRQ_FIRST + 42) /* 42: TIM1 update */
#define STM32L5_IRQ_TIM1_TRG_COM (STM32L5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
#define STM32L5_IRQ_TIM1_CC (STM32L5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
#define STM32L5_IRQ_TIM2 (STM32L5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
#define STM32L5_IRQ_TIM3 (STM32L5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
#define STM32L5_IRQ_TIM4 (STM32L5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
#define STM32L5_IRQ_TIM5 (STM32L5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */
#define STM32L5_IRQ_TIM6 (STM32L5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */
#define STM32L5_IRQ_TIM7 (STM32L5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */
#define STM32L5_IRQ_TIM8_BRK (STM32L5_IRQ_FIRST + 51) /* 51: TIM8 break */
#define STM32L5_IRQ_TIM8_UP (STM32L5_IRQ_FIRST + 52) /* 52: TIM8 update */
#define STM32L5_IRQ_TIM8_TRG_COM (STM32L5_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
#define STM32L5_IRQ_TIM8_CC (STM32L5_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
#define STM32L5_IRQ_I2C1_EV (STM32L5_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */
#define STM32L5_IRQ_I2C1_ER (STM32L5_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */
#define STM32L5_IRQ_I2C2_EV (STM32L5_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */
#define STM32L5_IRQ_I2C2_ER (STM32L5_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */
#define STM32L5_IRQ_SPI1 (STM32L5_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */
#define STM32L5_IRQ_SPI2 (STM32L5_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */
#define STM32L5_IRQ_USART1 (STM32L5_IRQ_FIRST + 61) /* 61: USART1 global interrupt */
#define STM32L5_IRQ_USART2 (STM32L5_IRQ_FIRST + 62) /* 62: USART2 global interrupt */
#define STM32L5_IRQ_USART3 (STM32L5_IRQ_FIRST + 63) /* 63: USART3 global interrupt */
#define STM32L5_IRQ_UART4 (STM32L5_IRQ_FIRST + 64) /* 64: UART4 global interrupt */
#define STM32L5_IRQ_UART5 (STM32L5_IRQ_FIRST + 65) /* 65: UART5 global interrupt */
#define STM32L5_IRQ_LPUART1 (STM32L5_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */
#define STM32L5_IRQ_LPTIM1 (STM32L5_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */
#define STM32L5_IRQ_LPTIM2 (STM32L5_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */
#define STM32L5_IRQ_TIM15 (STM32L5_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */
#define STM32L5_IRQ_TIM16 (STM32L5_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */
#define STM32L5_IRQ_TIM17 (STM32L5_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */
#define STM32L5_IRQ_COMP (STM32L5_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */
#define STM32L5_IRQ_USB_FS (STM32L5_IRQ_FIRST + 73) /* 73: USB global interrupt */
#define STM32L5_IRQ_CRS (STM32L5_IRQ_FIRST + 74) /* 74: CRS global interrupt */
#define STM32L5_IRQ_FMC (STM32L5_IRQ_FIRST + 75) /* 75: FMC global interrupt */
#define STM32L5_IRQ_OCTOSPI1 (STM32L5_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */
/* 77: Reserved */
#define STM32L5_IRQ_SDMMC1 (STM32L5_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */
/* 79: Reserved */
#define STM32L5_IRQ_DMA2CH1 (STM32L5_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */
#define STM32L5_IRQ_DMA2CH2 (STM32L5_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */
#define STM32L5_IRQ_DMA2CH3 (STM32L5_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */
#define STM32L5_IRQ_DMA2CH4 (STM32L5_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */
#define STM32L5_IRQ_DMA2CH5 (STM32L5_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */
#define STM32L5_IRQ_DMA2CH6 (STM32L5_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */
#define STM32L5_IRQ_DMA2CH7 (STM32L5_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */
#define STM32L5_IRQ_DMA2CH8 (STM32L5_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */
#define STM32L5_IRQ_I2C3_EV (STM32L5_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */
#define STM32L5_IRQ_I2C3_ER (STM32L5_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */
#define STM32L5_IRQ_SAI1 (STM32L5_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */
#define STM32L5_IRQ_SAI2 (STM32L5_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */
#define STM32L5_IRQ_TSC (STM32L5_IRQ_FIRST + 92) /* 92: TSC global interrupt */
#define STM32L5_IRQ_AES (STM32L5_IRQ_FIRST + 93) /* 93: AES global interrupt */
#define STM32L5_IRQ_RNG (STM32L5_IRQ_FIRST + 94) /* 94: RNG global interrupt */
#define STM32L5_IRQ_FPU (STM32L5_IRQ_FIRST + 95) /* 95: FPU global interrupt */
#define STM32L5_IRQ_HASH (STM32L5_IRQ_FIRST + 96) /* 96: HASH global interrupt */
#define STM32L5_IRQ_PKA (STM32L5_IRQ_FIRST + 97) /* 97: PKA global interrupt */
#define STM32L5_IRQ_LPTIM3 (STM32L5_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */
#define STM32L5_IRQ_SPI3 (STM32L5_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */
#define STM32L5_IRQ_I2C4_EV (STM32L5_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */
#define STM32L5_IRQ_I2C4_ER (STM32L5_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */
#define STM32L5_IRQ_DFSDM1_FLT0 (STM32L5_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */
#define STM32L5_IRQ_DFSDM1_FLT1 (STM32L5_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */
#define STM32L5_IRQ_DFSDM1_FLT2 (STM32L5_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */
#define STM32L5_IRQ_DFSDM1_FLT3 (STM32L5_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */
#define STM32L5_IRQ_UCPD1 (STM32L5_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */
#define STM32L5_IRQ_ICACHE (STM32L5_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */
#define STM32L5_IRQ_OTFDEC1 (STM32L5_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */
#if defined(CONFIG_STM32L5_STM32L562XX)
# define STM32L5_IRQ_NEXTINTS 109
#else
# error "Unsupported STM32L5 chip"
#endif
/* (EXTI interrupts do not use IRQ numbers) */
#define NR_IRQS (STM32L5_IRQ_FIRST + STM32L5_IRQ_NEXTINTS)
#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H */
arch/arm/include/stm32l5/stm32l5_irq.h
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@@ -0,0 +1,91 @@
/*****************************************************************************
* arch/arm/include/stm32l5/stm32l5_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
/* This file should never be included directed but, rather, only indirectly by
* the chip type specific header files (e.g. stm32l562xx_irq.h)
*/
#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define STM32L5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32L5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32L5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32L5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32L5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32L5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define STM32L5_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32L5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32L5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32L5_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define STM32L5_IRQ_FIRST (16) /* Vector number of the first external interrupt */
/*****************************************************************************
* Public Types
*****************************************************************************/
/*****************************************************************************
* Public Data
*****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Function Prototypes
*****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H */
arch/arm/src/stm32l5/Kconfig
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arch/arm/src/stm32l5/Make.defs
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##############################################################################
# arch/arm/src/stm32l5/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
##############################################################################
# The start-up, "head", file. Only common vectors are support so there
# isn't one.
HEAD_ASRC =
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S arm_switchcontext.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
ifeq ($(CONFIG_ARCH_SETJMP_H),y)
ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
CMN_ASRCS += arm_setjmp.S
endif
endif
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_createstack.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_udelay.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARMV8M_LAZYFPU),y)
CMN_ASRCS += arm_lazyexception.S
else
CMN_ASRCS += arm_exception.S
endif
CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_copyarmstate.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required STM32L5 files
CHIP_ASRCS =
CHIP_CSRCS = stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c
CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c
CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c stm32l5_waste.c stm32l5_uid.c
CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c
CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32l5_idle.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32l5_tim_lowerhalf.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32l5_userspace.c stm32l5_mpuinit.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += stm32l5_dumpgpio.c
endif
# Required chip type specific files
ifeq ($(CONFIG_STM32L5_STM32L562XX),y)
CHIP_CSRCS += stm32l562xx_rcc.c
endif
arch/arm/src/stm32l5/README.txt
+18
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@@ -0,0 +1,18 @@
This is a port of NuttX to the STM32L5 Family
Used development boards are the Nucleo L552ZE-Q, and STM32L562E-DK.
Most code is copied and adapted from the STM32L4 port.
The only supported STM32L5 family currently is:
-----------------------------------------------------------------
| NuttX config | Manual | Chips
| STM32L5 | RM0438 | STM32L552xx and STM32L562xx
------------------------------------------------------------------
TODO list
---------
Extensive testing. Only initial sniff tests have been done.
A prober TODO list should be generated.
arch/arm/src/stm32l5/chip.h
+56
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@@ -0,0 +1,56 @@
/****************************************************************************
* arch/arm/src/stm32l5/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_CHIP_H
#define __ARCH_ARM_SRC_STM32L5_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware
* files should then include this file for the proper setup.
*/
#include <arch/irq.h>
#include <arch/stm32l5/chip.h>
#include "hardware/stm32l5_pinmap.h"
#include "hardware/stm32l5_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If the common ARMv8-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/stm32l5/chip.h header file.
*/
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS
/* Cache line sizes (in bytes) for the STM32L5 */
#define ARMV8M_DCACHE_LINESIZE 0 /* no cache */
#define ARMV8M_ICACHE_LINESIZE 0 /* no cache */
#endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */
arch/arm/src/stm32l5/hardware/stm32l562xx_dbgmcu.h
+118
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@@ -0,0 +1,118 @@
/****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l562xx_dbgmcu.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_DBGMCU_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Addresses *******************************************************/
#define STM32_DBGMCU_IDCODE 0xe0044000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0044004 /* MCU debug */
#define STM32_DBGMCU_APB1_FZ 0xe0044008 /* Debug MCU APB1 freeze register */
#define STM32_DBGMCU_APB1_FZ2 0xe004400c /* Debug MCU APB1 freeze register 2 */
#define STM32_DBGMCU_APB2_FZ 0xe0044010 /* Debug MCU APB2 freeze register */
/* Register Bitfield Definitions ********************************************/
/* MCU identifier */
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
/* MCU debug */
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Allows debug in Stop mode */
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Allows debug in Standby mode */
#define DBGMCU_CR_TRACEIOEN (1 << 4) /* Bit 4: Trace pin enable */
#define DBGMCU_CR_TRACEEN (1 << 5) /* Bit 5: Trace port and clock enable */
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
/* Debug MCU APB1 freeze register */
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */
/* Debug MCU APB1 freeze register 2 */
#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopped when core is halted */
#define DBGMCU_APB1_FZ2_LPTIM3STOP (1 << 6) /* Bit 6: LPTIM3 stopped when core is halted */
#define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 stopped when core is halted */
/* Debug MCU APB2 freeze register */
#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
#define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 13: TIM8 stopped when core is halted */
#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XXDBGMCU_H */
arch/arm/src/stm32l5/hardware/stm32l562xx_pinmap.h
+745
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h
+867
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h
+135
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@@ -0,0 +1,135 @@
/****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32L5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */
#define STM32L5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
#define STM32L5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */
#define STM32L5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */
#define STM32L5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */
#define STM32L5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */
#define STM32L5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
#define STM32L5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */
#define STM32L5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
#define STM32L5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */
#define STM32L5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */
/* Register Addresses *******************************************************/
#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SECCFGR_OFFSET)
#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CFGR1_OFFSET)
#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_FPUIMR_OFFSET)
#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CNSLCKR_OFFSET)
#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CSLCKR_OFFSET)
#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_CFGR2_OFFSET)
#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SCSR_OFFSET)
#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SKR_OFFSET)
#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SWPR_OFFSET)
#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_SWPR2_OFFSET)
#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE+STM32L5_SYSCFG_RSSCMDR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* SYSCFG secure configuration register */
#define SYSCFG_SECCFGR_SYSCFGSEC (1 << 0) /* SYSCFG clock control security */
#define SYSCFG_SECCFGR_CLASSBSEC (1 << 1) /* ClassB security */
#define SYSCFG_SECCFGR_SRAM2SEC (1 << 2) /* SRAM2 security */
#define SYSCFG_SECCFGR_FPUSEC (1 << 3) /* FPU security */
/* SYSCFG configuration register 1 */
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
#define SYSCFG_CFGR1_ANASWVDD (1 << 9) /* Bit 9: GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
/* SYSCFG FPU interrupt mask register */
#define SYSCFG_FPUIMR_IE0 (1 << 0) /* Bit 0: FPU Invalid operation interrupt enable */
#define SYSCFG_FPUIMR_IE1 (1 << 1) /* Bit 1: FPU Divide-by-zero interrupt enable */
#define SYSCFG_FPUIMR_IE2 (1 << 2) /* Bit 2: FPU Underflow interrupt enable */
#define SYSCFG_FPUIMR_IE3 (1 << 3) /* Bit 3: FPU Overflow interrupt enable */
#define SYSCFG_FPUIMR_IE4 (1 << 4) /* Bit 4: FPU Input abnormal interrupt enable */
#define SYSCFG_FPUIMR_IE5 (1 << 5) /* Bit 5: FPU Inexact interrupt enable */
/* SYSCFG CPU non-secure lock register */
#define SYSCFG_CNSLCKR_LOCKNSVTOR (1 << 0) /* Bit 0: VTOR_NS register lock */
#define SYSCFG_CNSLCKR_LOCKNSMPU (1 << 1) /* Bit 1: Non-seucre MPU registers lock */
/* SYSCFG CPU secure lock register */
#define SYSCFG_CSLCKR_LOCKSVTAIRCR (1 << 0) /* Bit 0: VTOR_S register and AIRCR register bits lock */
#define SYSCFG_CSLCKR_LOCKSMPU (1 << 1) /* Bit 1: Secure MPU registers lock */
#define SYSCFG_CSLCKR_LOCKSAU (1 << 2) /* Bit 2: SAU registers lock */
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M33 LOCKUP (hardfault) output enable */
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock */
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable */
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock */
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
/* SYSCFG SRAM2 control and status register */
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
/* SYSCFG SRAM2 key register */
#define SYSCFG_SKR_SHIFT 0
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
/* SYSCFG SRAM2 write protection register 1 and 2: There is one bit per SRAM2
* page (0 to 31 and 32 to 63, respectively).
*/
/* SYSCFG RSS command register */
#define SYSCFG_RSSCMDR_SHIFT 0
#define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT)
#endif /* CONFIG_STM32L5_STM32L562XX */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H */
arch/arm/src/stm32l5/hardware/stm32l5_exti.h
+119
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@@ -0,0 +1,119 @@
/****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32L5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */
#define STM32L5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */
#define STM32L5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */
#define STM32L5_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */
#define STM32L5_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */
#define STM32L5_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */
#define STM32L5_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */
#define STM32L5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */
#define STM32L5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */
#define STM32L5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */
#define STM32L5_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */
#define STM32L5_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */
#define STM32L5_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */
#define STM32L5_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */
#define STM32L5_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */
#define STM32L5_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */
#define STM32L5_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */
#define STM32L5_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */
#define STM32L5_EXTI_LOCKR_OFFSET 0x0070 /* Lock */
#define STM32L5_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */
#define STM32L5_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */
#define STM32L5_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */
#define STM32L5_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */
/* Register Addresses *******************************************************/
#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_RTSR1_OFFSET)
#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_FTSR1_OFFSET)
#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE+STM32L5_EXTI_SWIER1_OFFSET)
#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_RPR1_OFFSET)
#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_FPR1_OFFSET)
#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_SECCFGR1_OFFSET)
#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_PRIVCFGR1_OFFSET)
#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_RTSR2_OFFSET)
#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_FTSR2_OFFSET)
#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE+STM32L5_EXTI_SWIER2_OFFSET)
#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_RPR2_OFFSET)
#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_FPR2_OFFSET)
#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_SECCFGR2_OFFSET)
#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_PRIVCFGR2_OFFSET)
#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR1_OFFSET)
#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR2_OFFSET)
#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR3_OFFSET)
#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE+STM32L5_EXTI_EXTICR4_OFFSET)
#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE+STM32L5_EXTI_LOCKR_OFFSET)
#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_IMR1_OFFSET)
#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE+STM32L5_EXTI_EMR1_OFFSET)
#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_IMR2_OFFSET)
#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE+STM32L5_EXTI_EMR2_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* EXTI lines > 15 are associated with internal devices: */
#define EXTI1_PVD (1 << 16) /* EXTI line 16: PVD output */
#define EXTI1_RTC (1 << 17) /* EXTI line 17: RTC */
#define EXTI1_RTC_SECURE (1 << 18) /* EXTI line 18: RTC secure */
#define EXTI1_TAMP (1 << 19) /* EXTI line 19: TAMP */
#define EXTI1_TAMP_SECURE (1 << 20) /* EXTI line 20: TAMP secure */
#define EXTI1_COMP1 (1 << 21) /* EXTI line 21: COMP1 output */
#define EXTI1_COMP2 (1 << 22) /* EXTI line 22: COMP2 output */
#define EXTI1_I2C1 (1 << 23) /* EXTI line 23: I2C1 wakeup */
#define EXTI1_I2C2 (1 << 24) /* EXTI line 24: I2C2 wakeup */
#define EXTI1_I2C3 (1 << 25) /* EXTI line 25: I2C3 wakeup */
#define EXTI1_USART1 (1 << 26) /* EXTI line 26: USART1 wakeup */
#define EXTI1_USART2 (1 << 27) /* EXTI line 27: USART2 wakeup */
#define EXTI1_USART3 (1 << 28) /* EXTI line 28: USART3 wakeup */
#define EXTI1_USART4 (1 << 29) /* EXTI line 29: USART4 wakeup */
#define EXTI1_USART5 (1 << 30) /* EXTI line 30: USART5 wakeup */
#define EXTI1_LPUART1 (1 << 31) /* EXTI line 31: LPUART1 wakeup */
#define EXTI2_LPTIM1 (1 << 0) /* EXTI line 32: LPTIM1 */
#define EXTI2_LPTIM2 (1 << 1) /* EXTI line 33: LPTIM2 */
#define EXTI2_USBFS (1 << 2) /* EXTI line 34: USB FS wakeup */
#define EXTI2_PVM1 (1 << 3) /* EXTI line 35: PVM1 wakeup */
#define EXTI2_PVM2 (1 << 4) /* EXTI line 36: PVM2 wakeup */
#define EXTI2_PVM3 (1 << 5) /* EXTI line 37: PVM3 wakeup */
#define EXTI2_PVM4 (1 << 6) /* EXTI line 38: PVM4 wakeup */
#define EXTI2_RSVD (1 << 7) /* EXTI line 39: reserved */
#define EXTI2_I2C4 (1 << 8) /* EXTI line 40: I2C4 wakeup */
#define EXTI2_UCPD1 (1 << 9) /* EXTI line 41: UCPD1 wakeup */
#define EXTI2_LPTIM3 (1 << 10) /* EXTI line 42: LPTIM3 wakeup */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H */
arch/arm/src/stm32l5/hardware/stm32l5_flash.h
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/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_flash.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/hardware/stm32l4_flash.h
*
* Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32L5_FLASH_CONFIG_x selects the default FLASH size based on the
* chip part number. This value can be overridden with
* CONFIG_STM32L5_FLASH_OVERRIDE_x
*
* Parts STM32L552xC and STM32L562xC have 256Kb of FLASH
* Parts STM32L552xE and STM32L562xE have 512Kb of FLASH
*
* N.B. Only Single bank mode is supported
*/
#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32L5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32L5_FLASH_CONFIG_E)
# define CONFIG_STM32L5_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32L5_FLASH_CONFIG_C
# undef CONFIG_STM32L5_FLASH_CONFIG_E
# if defined(CONFIG_STM32L5_FLASH_OVERRIDE_C)
# define CONFIG_STM32L5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32L5_FLASH_OVERRIDE_E)
# define CONFIG_STM32L5_FLASH_CONFIG_E
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */
# define STM32L5_FLASH_NPAGES 64
# define STM32L5_FLASH_PAGESIZE 4096
#elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */
# define STM32L5_FLASH_NPAGES 128
# define STM32L5_FLASH_PAGESIZE 4096
#else
# error "unknown flash configuration!"
#endif
#ifdef STM32L5_FLASH_PAGESIZE
# define STM32L5_FLASH_SIZE (STM32L5_FLASH_NPAGES * STM32L5_FLASH_PAGESIZE)
#endif
/* Register Offsets **********************************************************/
#define STM32L5_FLASH_ACR_OFFSET 0x0000
#define STM32L5_FLASH_PDKEYR_OFFSET 0x0004
#define STM32L5_FLASH_NSKEYR_OFFSET 0x0008
#define STM32L5_FLASH_SECKEYR_OFFSET 0x000c
#define STM32L5_FLASH_OPTKEYR_OFFSET 0x0010
#define STM32L5_FLASH_LVEKEYR_OFFSET 0x0014
#define STM32L5_FLASH_NSSR_OFFSET 0x0020
#define STM32L5_FLASH_SECSR_OFFSET 0x0024
#define STM32L5_FLASH_NSCR_OFFSET 0x0028
#define STM32L5_FLASH_SECCR_OFFSET 0x002c
#define STM32L5_FLASH_ECCR_OFFSET 0x0030
#define STM32L5_FLASH_OPTR_OFFSET 0x0040
#define STM32L5_FLASH_NSBOOTADDR0R_OFFSET 0x0044
#define STM32L5_FLASH_NSBOOTADDR1R_OFFSET 0x0048
#define STM32L5_FLASH_SECBOOTADDR0R_OFFSET 0x004c
#define STM32L5_FLASH_SECWM1R1_OFFSET 0x0050
#define STM32L5_FLASH_SECWM1R2_OFFSET 0x0054
#define STM32L5_FLASH_WRP1AR_OFFSET 0x0058
#define STM32L5_FLASH_WRP1BR_OFFSET 0x005c
#define STM32L5_FLASH_SECWM2R1_OFFSET 0x0060
#define STM32L5_FLASH_SECWM2R2_OFFSET 0x0064
#define STM32L5_FLASH_WRP2AR_OFFSET 0x0068
#define STM32L5_FLASH_WRP2BR_OFFSET 0x006c
#define STM32L5_FLASH_SECBB1R1_OFFSET 0x0080
#define STM32L5_FLASH_SECBB1R2_OFFSET 0x0084
#define STM32L5_FLASH_SECBB1R3_OFFSET 0x0088
#define STM32L5_FLASH_SECBB1R4_OFFSET 0x008c
#define STM32L5_FLASH_SECBB2R1_OFFSET 0x00a0
#define STM32L5_FLASH_SECBB2R2_OFFSET 0x00a4
#define STM32L5_FLASH_SECBB2R3_OFFSET 0x00a8
#define STM32L5_FLASH_SECBB2R4_OFFSET 0x00ac
#define STM32L5_FLASH_SECHDPCR_OFFSET 0x00c0
#define STM32L5_FLASH_PRIVCFGR_OFFSET 0x00c4
/* Register Addresses ********************************************************/
#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_ACR_OFFSET)
#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_PDKEYR_OFFSET)
#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSKEYR_OFFSET)
#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECKEYR_OFFSET)
#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_OPTKEYR_OFFSET)
#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_LVEKEYR_OFFSET)
#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSSR_OFFSET)
#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECSR_OFFSET)
#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSCR_OFFSET)
#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECCR_OFFSET)
#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_ECCR_OFFSET)
#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_OPTR_OFFSET)
#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSBOOTADDR0R_OFFSET)
#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE+STM32L5_FLASH_NSBOOTADDR1R_OFFSET)
#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBOOTADDR0R_OFFSET)
#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM1R1_OFFSET)
#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM1R2_OFFSET)
#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP1AR_OFFSET)
#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP1BR_OFFSET)
#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM2R1_OFFSET)
#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECWM2R2_OFFSET)
#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP2AR_OFFSET)
#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_WRP2BR_OFFSET)
#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R1_OFFSET)
#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R2_OFFSET)
#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R3_OFFSET)
#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB1R4_OFFSET)
#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R1_OFFSET)
#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R2_OFFSET)
#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R3_OFFSET)
#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECBB2R4_OFFSET)
#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_SECHDPCR_OFFSET)
#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE+STM32L5_FLASH_PRIVCFGR_OFFSET)
/* Register Bitfield Definitions *********************************************/
/* Flash Access Control Register (ACR) */
#define FLASH_ACR_LATENCY_SHIFT (0)
#define FLASH_ACR_LATENCY_MASK (0xF << FLASH_ACR_LATENCY_SHIFT)
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */
# define FLASH_ACR_LATENCY_0 ( 0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
# define FLASH_ACR_LATENCY_1 ( 1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
# define FLASH_ACR_LATENCY_2 ( 2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
# define FLASH_ACR_LATENCY_3 ( 3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
# define FLASH_ACR_LATENCY_4 ( 4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
# define FLASH_ACR_LATENCY_5 ( 5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
# define FLASH_ACR_LATENCY_6 ( 6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
# define FLASH_ACR_LATENCY_7 ( 7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait state */
# define FLASH_ACR_LATENCY_8 ( 8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
# define FLASH_ACR_LATENCY_9 ( 9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */
# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait state */
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen states */
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
#define FLASH_ACR_RUN_PD (1 << 13) /* Bit 13: Flash mode during Run */
#define FLASH_ACR_SLEEP_PD (1 << 14) /* Bit 14: Flash mode during Sleep */
#define FLASH_ACR_LVE (1 << 15) /* Bit 15: Flash low-voltage enable */
/* Flash Status Register (SR) */
#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
#define FLASH_SR_OPTWERR (1 << 13) /* Bit 13: Option write error */
#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
/* Flash Control Register (CR) */
#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */
#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */
#define FLASH_CR_MER1 (1 << 2) /* Bit 2 : Mass Erase Bank 1 */
#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */
#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT)
#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+128 (if BKER=1), n=0..127 */
#define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */
#define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */
#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */
#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */
#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */
#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */
#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
/* Flash ECC Register (ECCR) */
#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-18: ECC fail address */
#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
#define FLASH_ECCR_BK_ECC (1 << 21) /* Bit 21: ECC fail bank */
#define FLASH_ECCR_SYSF_ECC (1 << 22) /* Bit 22: System Flash ECC fail */
#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
#define FLASH_ECCR_ECCC2 (1 << 28) /* Bit 28: ECC2 correction */
#define FLASH_ECCR_ECCD2 (1 << 29) /* Bit 29: ECC2 detection */
#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
/* Flash Option Register (OPTR) */
#define FLASH_OPTR_NRST_STOP (1 << 12) /* Bit 12: Generate reset when entering the Stop mode */
#define FLASH_OPTR_NRST_STDBY (1 << 13) /* Bit 13: Generate reset when entering the Standby mode */
#define FLASH_OPTR_NRST_SHDW (1 << 14) /* Bit 14: Generate reset when entering the Shutdown mode */
#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
#define FLASH_OPTR_SWAP_BANK (1 << 20) /* Bit 20: Swap banks */
#define FLASH_OPTR_DB256K (1 << 21) /* Bit 21: Dual bank on 256K flash memory devices */
#define FLASH_OPTR_DBANK (1 << 22) /* Bit 22: Dual bank enable */
#define FLASH_OPTR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
#define FLASH_OPTR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
#define FLASH_OPTR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
#define FLASH_OPTR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
#define FLASH_OPTR_PA15_PUPEN (1 << 28) /* Bit 28: PA15 pull-up enable */
#define FLASH_OPTR_TZEN (1 << 31) /* Bit 31: Global TrustZone security enable */
#define FLASH_OPTR_BORLEV_SHIFT (8) /* Bits 8-10: BOR reset Level */
#define FLASH_OPTR_BORLEV_MASK (7 << FLASH_OPTR_BORLEV_SHIFT)
#define FLASH_OPTR_VBOR0 (0 << FLASH_OPTR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */
#define FLASH_OPTR_VBOR1 (1 << FLASH_OPTR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */
#define FLASH_OPTR_VBOR2 (2 << FLASH_OPTR_BORLEV_SHIFT) /* 010: BOR Level 2 (2.2 V) */
#define FLASH_OPTR_VBOR3 (3 << FLASH_OPTR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */
#define FLASH_OPTR_VBOR4 (4 << FLASH_OPTR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */
#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */
#define FLASH_OPTR_RDP_MASK (0xFF << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_NONE (0xAA << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_NSDBG (0x55 << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_CHIP (0xCC << FLASH_OPTR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H */
arch/arm/src/stm32l5/hardware/stm32l5_gpio.h
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/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32l5/chip.h>
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Register Offsets **********************************************************/
#define STM32L5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
#define STM32L5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
#define STM32L5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
#define STM32L5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
#define STM32L5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
#define STM32L5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
#define STM32L5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
#define STM32L5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
#define STM32L5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
#define STM32L5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
#define STM32L5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
#define STM32L5_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */
/* Register Addresses ********************************************************/
#if STM32L5_NPORTS > 0
# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 1
# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 2
# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 3
# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 4
# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 5
# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 6
# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 7
# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
#if STM32L5_NPORTS > 8
# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE+STM32L5_GPIO_MODER_OFFSET)
# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE+STM32L5_GPIO_OTYPER_OFFSET)
# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE+STM32L5_GPIO_OSPEED_OFFSET)
# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE+STM32L5_GPIO_PUPDR_OFFSET)
# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE+STM32L5_GPIO_IDR_OFFSET)
# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE+STM32L5_GPIO_ODR_OFFSET)
# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE+STM32L5_GPIO_BSRR_OFFSET)
# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE+STM32L5_GPIO_LCKR_OFFSET)
# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE+STM32L5_GPIO_AFRL_OFFSET)
# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE+STM32L5_GPIO_AFRH_OFFSET)
# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE+STM32L5_GPIO_BRR_OFFSET)
# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE+STM32L5_GPIO_SECCFGR_OFFSET)
#endif
/* Register Bitfield Definitions *********************************************/
/* GPIO port mode register */
#define GPIO_MODER_INPUT (0) /* Input */
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
#define GPIO_MODER_ALT (2) /* Alternate mode */
#define GPIO_MODER_ANALOG (3) /* Analog mode */
#define GPIO_MODER_SHIFT(n) ((n) << 1)
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
#define GPIO_MODER0_SHIFT (0)
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
#define GPIO_MODER1_SHIFT (2)
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
#define GPIO_MODER2_SHIFT (4)
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
#define GPIO_MODER3_SHIFT (6)
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
#define GPIO_MODER4_SHIFT (8)
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
#define GPIO_MODER5_SHIFT (10)
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
#define GPIO_MODER6_SHIFT (12)
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
#define GPIO_MODER7_SHIFT (14)
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
#define GPIO_MODER8_SHIFT (16)
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
#define GPIO_MODER9_SHIFT (18)
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
#define GPIO_MODER10_SHIFT (20)
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
#define GPIO_MODER11_SHIFT (22)
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
#define GPIO_MODER12_SHIFT (24)
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
#define GPIO_MODER13_SHIFT (26)
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
#define GPIO_MODER14_SHIFT (28)
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
#define GPIO_MODER15_SHIFT (30)
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
/* GPIO port output type register */
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */
/* GPIO port output speed register */
#define GPIO_OSPEED_2MHZ (0) /* 2 MHz Low speed */
#define GPIO_OSPEED_25MHZ (1) /* 25 MHz Medium speed */
#define GPIO_OSPEED_50MHZ (2) /* 50 MHz High speed */
#define GPIO_OSPEED_100MHZ (3) /* 100 MHz Very High speed on 30 pF (80 MHz Output max speed on 15 pF) */
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
#define GPIO_OSPEED0_SHIFT (0)
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
#define GPIO_OSPEED1_SHIFT (2)
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
#define GPIO_OSPEED2_SHIFT (4)
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
#define GPIO_OSPEED3_SHIFT (6)
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
#define GPIO_OSPEED4_SHIFT (8)
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
#define GPIO_OSPEED5_SHIFT (10)
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
#define GPIO_OSPEED6_SHIFT (12)
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
#define GPIO_OSPEED7_SHIFT (14)
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
#define GPIO_OSPEED8_SHIFT (16)
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
#define GPIO_OSPEED9_SHIFT (18)
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
#define GPIO_OSPEED10_SHIFT (20)
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
#define GPIO_OSPEED11_SHIFT (22)
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
#define GPIO_OSPEED12_SHIFT (24)
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
#define GPIO_OSPEED13_SHIFT (26)
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
#define GPIO_OSPEED14_SHIFT (28)
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
#define GPIO_OSPEED15_SHIFT (30)
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
/* GPIO port pull-up/pull-down register */
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
#define GPIO_PUPDR0_SHIFT (0)
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
#define GPIO_PUPDR1_SHIFT (2)
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
#define GPIO_PUPDR2_SHIFT (4)
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
#define GPIO_PUPDR3_SHIFT (6)
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
#define GPIO_PUPDR4_SHIFT (8)
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
#define GPIO_PUPDR5_SHIFT (10)
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
#define GPIO_PUPDR6_SHIFT (12)
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
#define GPIO_PUPDR7_SHIFT (14)
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
#define GPIO_PUPDR8_SHIFT (16)
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
#define GPIO_PUPDR9_SHIFT (18)
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
#define GPIO_PUPDR10_SHIFT (20)
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
#define GPIO_PUPDR11_SHIFT (22)
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
#define GPIO_PUPDR12_SHIFT (24)
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
#define GPIO_PUPDR13_SHIFT (26)
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
#define GPIO_PUPDR14_SHIFT (28)
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
#define GPIO_PUPDR15_SHIFT (30)
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
/* GPIO port input data register */
#define GPIO_IDR(n) (1 << (n))
/* GPIO port output data register */
#define GPIO_ODR(n) (1 << (n))
/* GPIO port bit set/reset register */
#define GPIO_BSRR_SET(n) (1 << (n))
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
/* GPIO port configuration lock register */
#define GPIO_LCKR(n) (1 << (n))
#define GPIO_LCKK (1 << 16) /* Lock key */
/* GPIO alternate function low/high register */
#define GPIO_AFR_SHIFT(n) ((n) << 2)
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
#define GPIO_AFRL0_SHIFT (0)
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
#define GPIO_AFRL1_SHIFT (4)
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
#define GPIO_AFRL2_SHIFT (8)
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
#define GPIO_AFRL3_SHIFT (12)
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
#define GPIO_AFRL4_SHIFT (16)
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
#define GPIO_AFRL5_SHIFT (20)
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
#define GPIO_AFRL6_SHIFT (24)
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
#define GPIO_AFRL7_SHIFT (28)
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
#define GPIO_AFRH8_SHIFT (0)
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
#define GPIO_AFRH9_SHIFT (4)
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
#define GPIO_AFRH10_SHIFT (8)
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
#define GPIO_AFRH11_SHIFT (12)
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
#define GPIO_AFRH12_SHIFT (16)
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
#define GPIO_AFRH13_SHIFT (20)
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
#define GPIO_AFRH14_SHIFT (24)
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
/* GPIO port bit reset register */
#define GPIO_BRR_SET(n) (1 << (n))
/* GPIO port secure configuration register */
#define GPIO_SECCFGR_SET(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H */
arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h
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/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_MEMORYMAP_H
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* STM32L5XXX Address Blocks *************************************************/
#define STM32L5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32L5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
#define STM32L5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32L5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
# define STM32L5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
#define STM32L5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
# define STM32L5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32L5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
#define STM32L5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32L5_REGION_MASK 0xF0000000
#define STM32L5_IS_SRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_SRAM_BASE)
#define STM32L5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_FMC_BANK1)
/* Code Base Addresses *******************************************************/
#define STM32L5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
#define STM32L5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */
#define STM32L5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
#define STM32L5_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
/* System Memory Addresses ***************************************************/
#define STM32L5_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */
#define STM32L5_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */
#define STM32L5_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */
/* Peripheral Base Addresses *************************************************/
#define STM32L5_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */
#define STM32L5_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */
#define STM32L5_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */
#define STM32L5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */
#define STM32L5_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */
/* APB1 Base Addresses *******************************************************/
#define STM32L5_UCPD1_BASE 0x4000DC00
#define STM32L5_USB_SRAM_BASE 0x4000D800
#define STM32L5_USB_FS_BASE 0x4000D400
#define STM32L5_FDCAN_RAM_BASE 0x4000AC00
#define STM32L5_FDCAN1_BASE 0x4000A400
#define STM32L5_LPTIM3_BASE 0x40009800
#define STM32L5_LPTIM2_BASE 0x40009400
#define STM32L5_I2C4_BASE 0x40008400
#define STM32L5_LPUART1_BASE 0x40008000
#define STM32L5_LPTIM1_BASE 0x40007C00
#define STM32L5_OPAMP_BASE 0x40007800
#define STM32L5_DAC_BASE 0x40007400
#define STM32L5_PWR_BASE 0x40007000
#define STM32L5_CRS_BASE 0x40006000
#define STM32L5_I2C3_BASE 0x40005C00
#define STM32L5_I2C2_BASE 0x40005800
#define STM32L5_I2C1_BASE 0x40005400
#define STM32L5_UART5_BASE 0x40005000
#define STM32L5_UART4_BASE 0x40004C00
#define STM32L5_USART3_BASE 0x40004800
#define STM32L5_USART2_BASE 0x40004400
#define STM32L5_SPI3_BASE 0x40003C00
#define STM32L5_SPI2_BASE 0x40003800
#define STM32L5_TAMP_BASE 0x40003400
#define STM32L5_IWDG_BASE 0x40003000
#define STM32L5_WWDG_BASE 0x40002C00
#define STM32L5_RTC_BASE 0x40002800
#define STM32L5_TIM7_BASE 0x40001400
#define STM32L5_TIM6_BASE 0x40001000
#define STM32L5_TIM5_BASE 0x40000C00
#define STM32L5_TIM4_BASE 0x40000800
#define STM32L5_TIM3_BASE 0x40000400
#define STM32L5_TIM2_BASE 0x40000000
/* APB2 Base Addresses *******************************************************/
#define STM32L5_DFSDM1_BASE 0x40016000
#define STM32L5_SAI2_BASE 0x40015800
#define STM32L5_SAI1_BASE 0x40015400
#define STM32L5_TIM17_BASE 0x40014800
#define STM32L5_TIM16_BASE 0x40014400
#define STM32L5_TIM15_BASE 0x40014000
#define STM32L5_USART1_BASE 0x40013800
#define STM32L5_TIM8_BASE 0x40013400
#define STM32L5_SPI1_BASE 0x40013000
#define STM32L5_TIM1_BASE 0x40012C00
#define STM32L5_COMP_BASE 0x40010200
#define STM32L5_VREFBUF_BASE 0x40010100
#define STM32L5_SYSCFG_BASE 0x40010000
/* AHB1 Base Addresses *******************************************************/
#define STM32L5_GTZC_BASE 0x40032400
#define STM32L5_ICACHE_BASE 0x40030400
#define STM32L5_EXTI_BASE 0x4002F400
#define STM32L5_TSC_BASE 0x40024000
#define STM32L5_CRC_BASE 0x40023000
#define STM32L5_FLASHIF_BASE 0x40022000
#define STM32L5_RCC_BASE 0x40021000
#define STM32L5_DMAMUX1_BASE 0x40020800
#define STM32L5_DMA2_BASE 0x40020400
#define STM32L5_DMA1_BASE 0x40020000
/* AHB2 Base Addresses *******************************************************/
#define STM32L5_SDMMC1_BASE 0x420C8000
#define STM32L5_OTFDEC1_BASE 0x420C5000
#define STM32L5_PKA_BASE 0x420C2000
#define STM32L5_RNG_BASE 0x420C0800
#define STM32L5_HASH_BASE 0x420C0400
#define STM32L5_AES_BASE 0x420C0000
#define STM32L5_ADC_BASE 0x42028000
#define STM32L5_GPIOH_BASE 0x42021C00
#define STM32L5_GPIOG_BASE 0x42021800
#define STM32L5_GPIOF_BASE 0x42021400
#define STM32L5_GPIOE_BASE 0x42021000
#define STM32L5_GPIOD_BASE 0x42020c00
#define STM32L5_GPIOC_BASE 0x42020800
#define STM32L5_GPIOB_BASE 0x42020400
#define STM32L5_GPIOA_BASE 0x42020000
/* AHB2 Base Addresses *******************************************************/
#define STM32L5_OCTOSPI1_BASE 0x44021000
#define STM32L5_FMC_BASE 0x44020000
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MEMORYMAP_H */
arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h
+37
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@@ -0,0 +1,37 @@
/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
# include "hardware/stm32l562xx_pinmap.h"
#else
# error "Unsupported STM32 L5 pin map"
#endif
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H */
arch/arm/src/stm32l5/hardware/stm32l5_pwr.h
+215
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@@ -0,0 +1,215 @@
/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Register Offsets **********************************************************/
#define STM32L5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
#define STM32L5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
#define STM32L5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
#define STM32L5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
#define STM32L5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
#define STM32L5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
#define STM32L5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
#define STM32L5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
#define STM32L5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
#define STM32L5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
#define STM32L5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
#define STM32L5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
#define STM32L5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
#define STM32L5_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
#define STM32L5_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
#define STM32L5_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */
#define STM32L5_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */
#define STM32L5_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */
#define STM32L5_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */
#define STM32L5_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */
#define STM32L5_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */
#define STM32L5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
#define STM32L5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
#define STM32L5_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */
#define STM32L5_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */
/* Register Addresses ********************************************************/
#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE+STM32L5_PWR_CR1_OFFSET)
#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE+STM32L5_PWR_CR2_OFFSET)
#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE+STM32L5_PWR_CR3_OFFSET)
#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE+STM32L5_PWR_CR4_OFFSET)
#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE+STM32L5_PWR_SR1_OFFSET)
#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE+STM32L5_PWR_SR2_OFFSET)
#define STM32L5_PWR_SCR (STM32L5_PWR_BASE+STM32L5_PWR_SCR_OFFSET)
#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE+STM32L5_PWR_PUCRA_OFFSET)
#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE+STM32L5_PWR_PDCRA_OFFSET)
#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE+STM32L5_PWR_PUCRB_OFFSET)
#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE+STM32L5_PWR_PDCRB_OFFSET)
#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE+STM32L5_PWR_PUCRC_OFFSET)
#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE+STM32L5_PWR_PDCRC_OFFSET)
#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE+STM32L5_PWR_PUCRD_OFFSET)
#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE+STM32L5_PWR_PDCRD_OFFSET)
#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE+STM32L5_PWR_PUCRE_OFFSET)
#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE+STM32L5_PWR_PDCRE_OFFSET)
#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE+STM32L5_PWR_PUCRF_OFFSET)
#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE+STM32L5_PWR_PDCRF_OFFSET)
#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE+STM32L5_PWR_PUCRG_OFFSET)
#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE+STM32L5_PWR_PDCRG_OFFSET)
#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE+STM32L5_PWR_PUCRH_OFFSET)
#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE+STM32L5_PWR_PDCRH_OFFSET)
#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE+STM32L5_PWR_SECCFGR_OFFSET)
#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE+STM32L5_PWR_PRIVCFGR_OFFSET)
/* Register Bitfield Definitions *********************************************/
/* Power control register 1 */
#define PWR_CR1_LPMS_SHIFT 0
#define PWR_CR1_LPMS_MASK (7 << PWR_CR1_LPMS_SHIFT) /* Bits 0-2: Low-power mode selection */
# define PWR_CR1_LPMS_STOP0 (0 << PWR_CR1_LPMS_SHIFT) /* 000: Stop 0 mode */
# define PWR_CR1_LPMS_STOP1 (1 << PWR_CR1_LPMS_SHIFT) /* 001:Stop 1 mode */
# define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
# define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
# define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */
#define PWR_CR1_VOS_SHIFT 9
#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) /* Bits 9-10: Voltage scaling range selection */
#define PWR_CR1_VOS_RANGE0 (0 << PWR_CR1_VOS_SHIFT) /* 00: Range 0 */
#define PWR_CR1_VOS_RANGE1 (1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 */
#define PWR_CR1_VOS_RANGE2 (2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 */
#define PWR_CR1_LPR (1 << 14) /* Bit 14: Low-power run */
/* Power control register 2 */
#define PWR_CR2_PVDE (1 << 0) /* Bit 0: Power voltage detector enable */
#define PWR_CR2_PLS_SHIFT 1
#define PWR_CR2_PLS_MASK (7 << PWR_CR2_PLS_SHIFT) /* Bits 1-3: Power voltage detector level selection */
# define PWR_CR2_PLS_2000mv (0 << PWR_CR2_PLS_SHIFT) /* 000: VPVD0 around 2.0V */
# define PWR_CR2_PLS_2200mv (1 << PWR_CR2_PLS_SHIFT) /* 001: VPVD1 around 2.2V */
# define PWR_CR2_PLS_2400mv (2 << PWR_CR2_PLS_SHIFT) /* 010: VPVD2 around 2.4V */
# define PWR_CR2_PLS_2500mv (3 << PWR_CR2_PLS_SHIFT) /* 011: VPVD3 around 2.5V */
# define PWR_CR2_PLS_2600mv (4 << PWR_CR2_PLS_SHIFT) /* 100: VPVD4 around 2.6V */
# define PWR_CR2_PLS_2800mv (5 << PWR_CR2_PLS_SHIFT) /* 101: VPVD5 around 2.8V */
# define PWR_CR2_PLS_2900mv (6 << PWR_CR2_PLS_SHIFT) /* 110: VPVD6 around 2.9V */
# define PWR_CR2_PLS_EXT (7 << PWR_CR2_PLS_SHIFT) /* 111: External input analog voltage PVD_IN */
#define PWR_CR2_PVME1 (1 << 4) /* Bit 4: Peripheral voltage monitoring 1 enable (VDDUSB vs 1.2V) */
#define PWR_CR2_PVME2 (1 << 5) /* Bit 5: Peripheral voltage monitoring 2 enable (VDDIO2 vs 0.9V) */
#define PWR_CR2_PVME3 (1 << 6) /* Bit 6: Peripheral voltage monitoring 3 enable (VDDA vs 1.62V) */
#define PWR_CR2_PVME4 (1 << 7) /* Bit 7: Peripheral voltage monitoring 4 enable (VDDA vs 2.2V) */
#define PWR_CR2_IOSV (1 << 9) /* Bit 9: VDDIO2 Independent I/Os supply valid */
#define PWR_CR2_USV (1 << 10) /* Bit 10: VDDUSB USB supply valid */
/* Power control register 3 */
#define PWR_CR3_EWUP1 (1 << 0) /* Bit 0: Enable Wakeup pin WKUP1 */
#define PWR_CR3_EWUP2 (1 << 1) /* Bit 1: Enable Wakeup pin WKUP2 */
#define PWR_CR3_EWUP3 (1 << 2) /* Bit 2: Enable Wakeup pin WKUP3 */
#define PWR_CR3_EWUP4 (1 << 3) /* Bit 3: Enable Wakeup pin WKUP4 */
#define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */
#define PWR_CR3_RRS_SHIFT 8
#define PWR_CR3_RRS_MASK (3 << PWR_CR3_RRS_SHIFT) /* Bits 8-9: SRAM2 retention in Standby-mode */
# define PWR_CR3_RRS_OFF (0 << PWR_CR3_RRS_SHIFT) /* 00: SRAM2 is powered off in Standby-mode */
# define PWR_CR3_RRS_ON (1 << PWR_CR3_RRS_SHIFT) /* 01: SRAM2 is powered on in Standby-mode */
# define PWR_CR3_RRS_4K_ON (2 << PWE_CR3_RRS_SHIFT) /* 10: Upper 4KB of SRAM2 powered on in Standby-mode */
#define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
#define PWR_CR3_ULPMEN (1 << 11) /* Bit 11: Ultra-low-power mode enable */
#define PWR_CR3_UCPD_STBY (1 << 13) /* Bit 13: USB Type-C power delivery Standby-mode */
#define PWR_CR3_UCPD_DBDIS (1 << 14) /* Bit 14: USB Type-C power delivery dead battery disable */
/* Power control register 4 */
#define PWR_CR4_WP1 (1 << 0) /* Bit 0: Wakeup pin WKUP1 polarity */
#define PWR_CR4_WP2 (1 << 1) /* Bit 1: Wakeup pin WKUP2 polarity */
#define PWR_CR4_WP3 (1 << 2) /* Bit 2: Wakeup pin WKUP3 polarity */
#define PWR_CR4_WP4 (1 << 3) /* Bit 3: Wakeup pin WKUP4 polarity */
#define PWR_CR4_WP5 (1 << 4) /* Bit 4: Wakeup pin WKUP5 polarity */
#define PWR_CR4_VBE (1 << 8) /* Bit 8: Vbat battery charging enable */
#define PWR_CR4_VBRS (1 << 9) /* Bit 9: Vbat battery charging resistor selection */
# define PWR_CR4_VBRS_5k 0 /* 0: 5k resistor */
# define PWR_CR4_VBRS_1k5 PWR_CR4_VBRS /* 1: 1k5 resistor */
#define PWR_CR4_SMPSBYP (1 << 12) /* Bit 12: SMPS Bypass mode */
#define PWR_CR4_EXTSMPSEN (1 << 13) /* Bit 13: Enable external SMPS mode */
#define PWR_CR4_SMPSFSTEN (1 << 14) /* Bit 14: Enable SMPS fast soft start */
#define PWR_CR4_SMPSLPEN (1 << 15) /* Bit 15: Enable SMPS low-power mode */
/* Power status register 1 */
#define PWR_SR1_WUF1 (1 << 0) /* Bit 0: Wakeup flag 1 */
#define PWR_SR1_WUF2 (1 << 1) /* Bit 1: Wakeup flag 2 */
#define PWR_SR1_WUF3 (1 << 2) /* Bit 2: Wakeup flag 3 */
#define PWR_SR1_WUF4 (1 << 3) /* Bit 3: Wakeup flag 4 */
#define PWR_SR1_WUF5 (1 << 4) /* Bit 4: Wakeup flag 5 */
#define PWR_SR1_SBF (1 << 8) /* Bit 8: Standby flag */
#define PWR_SR1_SMPSBYPRDY (1 << 12) /* Bit 12: SMPS BYPASS ready */
#define PWR_SR1_EXTSMPSRDY (1 << 13) /* Bit 13: External SMPS mode ready */
#define PWR_SR1_SMPSHPRDY (1 << 15) /* Bit 15: SMPS high-power mode ready */
/* Power status register 2 */
#define PWR_SR2_REGLPS (1 << 8) /* Bit 8: Low power regulator started */
#define PWR_SR2_REGLPF (1 << 9) /* Bit 9: Low power regulator flag */
#define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */
#define PWR_SR2_PVDO (1 << 11) /* Bit 11: Power voltage detector output */
#define PWR_SR2_PVMO1 (1 << 12) /* Bit 12: Peripheral voltage monitoring output 1 (VDDUSB vs 1.2V) */
#define PWR_SR2_PVMO2 (1 << 13) /* Bit 13: Peripheral voltage monitoring output 2 (VDDIO2 vs 0.9V) */
#define PWR_SR2_PVMO3 (1 << 14) /* Bit 14: Peripheral voltage monitoring output 3 (VDDA vs 1.62V) */
#define PWR_SR2_PVMO4 (1 << 15) /* Bit 15: Peripheral voltage monitoring output 4 (VDDA vs 2.2V) */
/* Power status clear register */
#define PWR_SCR_CWUF1 (1 << 0) /* Bit 0: Clear wakeup flag 1 */
#define PWR_SCR_CWUF2 (1 << 1) /* Bit 1: Clear wakeup flag 2 */
#define PWR_SCR_CWUF3 (1 << 2) /* Bit 2: Clear wakeup flag 3 */
#define PWR_SCR_CWUF4 (1 << 3) /* Bit 3: Clear wakeup flag 4 */
#define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */
#define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */
/* Port X pull-up/down registers have one bit per port line, with a few
* exceptions.
*/
/* Power secure configuration register */
#define PWR_SECCFGR_WUP1SEC (1 << 0) /* Bit 0: WKUP1 pin security */
#define PWR_SECCFGR_WUP2SEC (1 << 1) /* Bit 1: WKUP2 pin security */
#define PWR_SECCFGR_WUP3SEC (1 << 2) /* Bit 2: WKUP3 pin security */
#define PWR_SECCFGR_WUP4SEC (1 << 3) /* Bit 3: WKUP4 pin security */
#define PWR_SECCFGR_WUP5SEC (1 << 4) /* Bit 4: WKUP5 pin security */
#define PWR_SECCFGR_LPMSEC (1 << 8) /* Bit 8: Low-power mode security */
#define PWR_SECCFGR_VDMSEC (1 << 9) /* Bit 9: Voltage detection and monitoring security */
#define PWR_SECCFGR_VBSEC (1 << 10) /* Bit 10: Voltage battery security */
#define PWR_SECCFGR_APCSEC (1 << 11) /* Bit 11: APC security */
/* Power privilege configuration register */
#define PWR_PRIVCFGR_PRIV (1 << 0) /* Bit 0: Privilege protection */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H */
arch/arm/src/stm32l5/hardware/stm32l5_spi.h
+165
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/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Maximum allowed speed as per specifications for all SPIs */
#if defined(CONFIG_STM32L5_STM32L562XX)
# define STM32L5_SPI_CLK_MAX 55000000UL
#else
# error "Unsupported STM32 L5 chip"
#endif
/* Register Offsets **********************************************************/
#define STM32L5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32L5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32L5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32L5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32L5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32L5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32L5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
/* Register Addresses ********************************************************/
#if STM32L5_NSPI > 0
# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE+STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE+STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE+STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE+STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE+STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE+STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE+STM32L5_SPI_TXCRCR_OFFSET)
#endif
#if STM32L5_NSPI > 1
# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE+STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE+STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE+STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE+STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE+STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE+STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE+STM32L5_SPI_TXCRCR_OFFSET)
#endif
#if STM32L5_NSPI > 2
# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE+STM32L5_SPI_CR1_OFFSET)
# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE+STM32L5_SPI_CR2_OFFSET)
# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE+STM32L5_SPI_SR_OFFSET)
# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE+STM32L5_SPI_DR_OFFSET)
# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE+STM32L5_SPI_CRCPR_OFFSET)
# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE+STM32L5_SPI_RXCRCR_OFFSET)
# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE+STM32L5_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions *********************************************/
/* SPI Control Register 1 */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
/* SPI Control Register 2 */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_VAL(bits) ( ((bits)-1) << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
/* SPI status register */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H */
arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h
+37
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/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
# include "hardware/stm32l562xx_syscfg.h"
#else
# error "Unsupported STM32 L5 chip"
#endif
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H */
arch/arm/src/stm32l5/hardware/stm32l5_tim.h
+1077
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arch/arm/src/stm32l5/hardware/stm32l5_uart.h
+307
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/*****************************************************************************
* arch/arm/src/stm32l5/hardware/stm32l5_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H
#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Register Offsets **********************************************************/
#define STM32L5_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32L5_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32L5_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32L5_USART_BRR_OFFSET 0x000c /* Baud Rate register */
#define STM32L5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32L5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32L5_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32L5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
#define STM32L5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32L5_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32L5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
#define STM32L5_USART_PRESC_OFFSET 0x002c /* Prescaler register */
/* Register Addresses ********************************************************/
#if STM32L5_NUSART > 0
# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART1_BRR (STM32L5_USART1_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART1_RQR (STM32L5_USART1_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART1_ISR (STM32L5_USART1_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART1_ICR (STM32L5_USART1_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART1_RDR (STM32L5_USART1_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART1_TDR (STM32L5_USART1_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE+STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 1
# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART2_BRR (STM32L5_USART2_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART2_RQR (STM32L5_USART2_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART2_ISR (STM32L5_USART2_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART2_ICR (STM32L5_USART2_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART2_RDR (STM32L5_USART2_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART2_TDR (STM32L5_USART2_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE+STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 2
# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_USART3_BRR (STM32L5_USART3_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_USART3_RQR (STM32L5_USART3_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_USART3_ISR (STM32L5_USART3_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_USART3_ICR (STM32L5_USART3_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_USART3_RDR (STM32L5_USART3_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_USART3_TDR (STM32L5_USART3_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE+STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 3
# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_UART4_BRR (STM32L5_UART4_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_UART4_RQR (STM32L5_UART4_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_UART4_ISR (STM32L5_UART4_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_UART4_ICR (STM32L5_UART4_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_UART4_RDR (STM32L5_UART4_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_UART4_TDR (STM32L5_UART4_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE+STM32L5_USART_PRESC_OFFSET)
#endif
#if STM32L5_NUSART > 4
# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE+STM32L5_USART_CR1_OFFSET)
# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE+STM32L5_USART_CR2_OFFSET)
# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE+STM32L5_USART_CR3_OFFSET)
# define STM32L5_UART5_BRR (STM32L5_UART5_BASE+STM32L5_USART_BRR_OFFSET)
# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE+STM32L5_USART_GTPR_OFFSET)
# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE+STM32L5_USART_RTOR_OFFSET)
# define STM32L5_UART5_RQR (STM32L5_UART5_BASE+STM32L5_USART_RQR_OFFSET)
# define STM32L5_UART5_ISR (STM32L5_UART5_BASE+STM32L5_USART_ISR_OFFSET)
# define STM32L5_UART5_ICR (STM32L5_UART5_BASE+STM32L5_USART_ICR_OFFSET)
# define STM32L5_UART5_RDR (STM32L5_UART5_BASE+STM32L5_USART_RDR_OFFSET)
# define STM32L5_UART5_TDR (STM32L5_UART5_BASE+STM32L5_USART_TDR_OFFSET)
# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE+STM32L5_USART_PRESC_OFFSET)
#endif
/* Register Bitfield Definitions *********************************************/
/* Control register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
USART_CR1_TCIE|USART_CR1_TXEIE| \
USART_CR1_PEIE|USART_CR1_CMIE| \
USART_CR1_RTOIE|USART_CR1_EOBIE)
/* Control register 2 */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Receiver timeout register */
/* Request Register */
#define USART_CR1_SBRKQ (1 << 1) /* Bit 1: Send Break */
/* Interrupt and Status register */
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt Flag */
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS Flag */
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout Flag */
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block Flag */
#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate Error */
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate Flag */
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy Flag */
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match Flag */
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break Flag */
#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode Flag */
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge Flag */
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge Flag */
/* ICR */
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
/* Receive Data register */
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
/* Transmit Data register */
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
/*****************************************************************************
* Public Types
*****************************************************************************/
/*****************************************************************************
* Public Data
*****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H */
arch/arm/src/stm32l5/stm32l5.h
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/*****************************************************************************
* arch/arm/src/stm32l5/stm32l5.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals ***************************************************************/
#include "chip.h"
#include "stm32l5_dbgmcu.h"
#include "stm32l5_flash.h"
#include "stm32l5_gpio.h"
#include "stm32l5_pwr.h"
#include "stm32l5_rcc.h"
#include "stm32l5_spi.h"
#include "stm32l5_tim.h"
#include "stm32l5_uart.h"
#include "stm32l5_lowputc.h"
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_H */
arch/arm/src/stm32l5/stm32l562xx_rcc.c
+979
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arch/arm/src/stm32l5/stm32l5_allocateheap.c
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_allocateheap.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "arm_arch.h"
#include "arm_internal.h"
#include "stm32l5_mpuinit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Internal SRAM is available in all members of the STM32L5 family. The
* following definitions must be provided to specify the size and
* location of internal (system) SRAM1 and SRAM2:
*
* SRAM1_START 0x20000000
* SRAM1_END
* SRAM2_START 0x10000000
* SRAM2_END
*
* In addition to internal SRAM, memory may also be available through the
* FSMC. In order to use FSMC SRAM, the following additional things need to
* be present in the NuttX configuration file:
*
* CONFIG_STM32L5_FSMC=y : Enables the FSMC
* CONFIG_STM32L5_FSMC_SRAM=y : Indicates that SRAM is available via the
* FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
* address space
* CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
* address space
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the additional regions.
*/
#ifndef CONFIG_STM32L5_FSMC
# undef CONFIG_STM32L5_FSMC_SRAM
#endif
/* STM32L5[7,8]6xx have 128 Kib in two banks, both accessible to DMA:
*
* 1) 96 KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000
* 2) 32 KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000
*
* STM32L596xx have 320 Kib in two banks, both accessible to DMA:
*
* 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
*
* STM32L5Rxxx have 640 Kib in three banks:
*
* 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
* 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000
*
* In addition, external FSMC SRAM may be available.
*/
/* Set the range of system SRAM */
#define SRAM1_START STM32L5_SRAM_BASE
#define SRAM1_END (SRAM1_START + STM32L5_SRAM1_SIZE)
/* Set the range of SRAM2 as well, requires a second memory region */
#define SRAM2_START STM32L5_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE)
/* Set the range of SRAM3, requiring a third memory region */
#ifdef STM32L5_SRAM3_SIZE
# define SRAM3_START STM32L5_SRAM3_BASE
# define SRAM3_END (SRAM3_START + STM32L5_SRAM3_SIZE)
#endif
/* Some sanity checking. If multiple memory regions are defined, verify
* that CONFIG_MM_REGIONS is set to match the number of memory regions
* that we have been asked to add to the heap.
*/
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L5_SRAM2_HEAP) + \
defined(CONFIG_STM32L5_SRAM3_HEAP) + \
defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1
# error "You need more memory manager regions to support selected heap components"
#endif
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L5_SRAM2_HEAP) + \
defined(CONFIG_STM32L5_SRAM3_HEAP) + \
defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1
# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
#endif
/* If FSMC SRAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_STM32L5_FSMC_SRAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_STM32L5_FSMC_SRAM
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_heap_color
*
* Description:
* Set heap memory to a known, non-zero state to checking heap usage.
*
****************************************************************************/
#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(FAR void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
}
#else
# define up_heap_color(start,size)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. Size given by CONFIG_IDLETHREAD_STACKSIZE.
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((FAR void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
stm32l5_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;
/* Colorize the heap for debug */
up_heap_color(*heap_start, *heap_size);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifdef CONFIG_STM32L5_SRAM2_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM2 heap */
stm32l5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
/* Add the SRAM2 user heap region. */
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
#endif /* SRAM2 */
#ifdef CONFIG_STM32L5_SRAM3_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM3 heap */
stm32l5_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM3_START, SRAM3_END - SRAM3_START);
/* Add the SRAM3 user heap region. */
kumm_addregion((FAR void *)SRAM3_START, SRAM3_END - SRAM3_START);
#endif /* SRAM3 */
#ifdef CONFIG_STM32L5_FSMC_SRAM_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
stm32l5_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif
arch/arm/src/stm32l5/stm32l5_dbgmcu.h
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
# include "hardware/stm32l562xx_dbgmcu.h"
#else
# error "Unsupported STM32L5 chip"
#endif
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H */
arch/arm/src/stm32l5/stm32l5_dumpgpio.c
+139
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_dumpgpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Output debug info even if debug output is not selected. */
#undef CONFIG_DEBUG_INFO
#define CONFIG_DEBUG_INFO 1
#include <sys/types.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_arch.h"
#include "chip.h"
#include "stm32l5_gpio.h"
#include "stm32l5_rcc.h"
#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
static const char g_portchar[STM32L5_NPORTS] =
{
#if STM32L5_NPORTS > 11
# error "Additional support required for this number of GPIOs"
#elif STM32L5_NPORTS > 10
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
#elif STM32L5_NPORTS > 9
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
#elif STM32L5_NPORTS > 8
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
#elif STM32L5_NPORTS > 7
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
#elif STM32L5_NPORTS > 6
'A', 'B', 'C', 'D', 'E', 'F', 'G'
#elif STM32L5_NPORTS > 5
'A', 'B', 'C', 'D', 'E', 'F'
#elif STM32L5_NPORTS > 4
'A', 'B', 'C', 'D', 'E'
#elif STM32L5_NPORTS > 3
'A', 'B', 'C', 'D'
#elif STM32L5_NPORTS > 2
'A', 'B', 'C'
#elif STM32L5_NPORTS > 1
'A', 'B'
#elif STM32L5_NPORTS > 0
'A'
#else
# error "Bad number of GPIOs"
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32l5_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
int stm32l5_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
unsigned int port;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
base = g_gpiobase[port];
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
DEBUGASSERT(port < STM32L5_NPORTS);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32L5_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
{
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32L5_GPIO_MODER_OFFSET),
getreg32(base + STM32L5_GPIO_OTYPER_OFFSET),
getreg32(base + STM32L5_GPIO_OSPEED_OFFSET),
getreg32(base + STM32L5_GPIO_PUPDR_OFFSET));
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32L5_GPIO_IDR_OFFSET),
getreg32(base + STM32L5_GPIO_ODR_OFFSET),
getreg32(base + STM32L5_GPIO_BSRR_OFFSET),
getreg32(base + STM32L5_GPIO_LCKR_OFFSET));
_info(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32L5_GPIO_AFRH_OFFSET),
getreg32(base + STM32L5_GPIO_AFRL_OFFSET));
}
else
{
_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
g_portchar[port], getreg32(STM32L5_RCC_AHB2ENR));
}
leave_critical_section(flags);
return OK;
}
#endif /* CONFIG_DEBUG_FEATURES */
arch/arm/src/stm32l5/stm32l5_exti.h
+153
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "hardware/stm32l5_exti.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32l5_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* pinset - GPIO pin configuration
* risingedge - Enables interrupt on rising edges
* fallingedge - Enables interrupt on falling edges
* event - Generate event when set
* func - When non-NULL, generate interrupt
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) is returned on success, otherwise a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Name: stm32l5_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: stm32l5_exti_wakeup
*
* Description:
* Sets/clears EXTI wakeup interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: stm32l5_exti_comp
*
* Description:
* Sets/clears comparator based events and interrupt triggers.
*
* Input Parameters:
* - cmp: comparator
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#ifdef CONFIG_STM32L5_COMP
int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H */
arch/arm/src/stm32l5/stm32l5_exti_gpio.c
+172
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_exti_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "arm_arch.h"
#include "chip.h"
#include "stm32l5_gpio.h"
#include "stm32l5_exti.h"
/****************************************************************************
* Private Types
****************************************************************************/
struct gpio_callback_s
{
xcpt_t callback; /* Callback entry point */
void *arg; /* The argument that accompanies the callback */
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to each EXTI */
static struct gpio_callback_s g_gpio_handlers[16];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Interrupt Service Routine - Dispatcher
****************************************************************************/
static int stm32l5_exti0_15_isr(int irq, void *context, FAR void *arg)
{
int ret = OK;
int exti;
exti = irq - STM32L5_IRQ_EXTI0;
DEBUGASSERT((exti >= 0) && (exti <= 15));
/* Clear the pending interrupt for both rising and falling edges. */
putreg32(0x0001 << exti, STM32L5_EXTI_RPR1);
putreg32(0x0001 << exti, STM32L5_EXTI_FPR1);
/* And dispatch the interrupt to the handler */
if (g_gpio_handlers[exti].callback != NULL)
{
xcpt_t callback = g_gpio_handlers[exti].callback;
void *cbarg = g_gpio_handlers[exti].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l5_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* pinset - GPIO pin configuration
* risingedge - Enables interrupt on rising edges
* fallingedge - Enables interrupt on falling edges
* event - Generate event when set
* func - When non-NULL, generate interrupt
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) is returned on success, otherwise a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg)
{
uint32_t pin = pinset & GPIO_PIN_MASK;
uint32_t exti = 1 << pin;
int irq = STM32L5_IRQ_EXTI0 + pin;
g_gpio_handlers[pin].callback = func;
g_gpio_handlers[pin].arg = arg;
/* Install external interrupt handlers */
if (func)
{
irq_attach(irq, stm32l5_exti0_15_isr, NULL);
up_enable_irq(irq);
}
else
{
up_disable_irq(irq);
}
/* Configure GPIO, enable EXTI line enabled if event or interrupt is
* enabled.
*/
if (event || func)
{
pinset |= GPIO_EXTI;
}
stm32l5_configgpio(pinset);
/* Configure rising/falling edges */
modifyreg32(STM32L5_EXTI_RTSR1,
risingedge ? 0 : exti,
risingedge ? exti : 0);
modifyreg32(STM32L5_EXTI_FTSR1,
fallingedge ? 0 : exti,
fallingedge ? exti : 0);
/* Enable Events and Interrupts */
modifyreg32(STM32L5_EXTI_EMR1,
event ? 0 : exti,
event ? exti : 0);
modifyreg32(STM32L5_EXTI_IMR1,
func ? 0 : exti,
func ? exti : 0);
return OK;
}
arch/arm/src/stm32l5/stm32l5_flash.c
+528
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l5/stm32l5_flash.h
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_flash.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_flash.h
*
* Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/stm32l5_flash.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void stm32l5_flash_lock(void);
void stm32l5_flash_unlock(void);
/****************************************************************************
* Name: stm32l5_flash_user_optbytes
*
* Description:
* Modify the contents of the user option bytes (USR OPT) on the flash.
* This does not set OBL_LAUNCH so new options take effect only after
* next power reset.
*
* Input Parameters:
* clrbits - Bits in the option bytes to be cleared
* setbits - Bits in the option bytes to be set
*
* Returned Value:
* Option bytes after operation is completed
*
****************************************************************************/
uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits);
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */
arch/arm/src/stm32l5/stm32l5_gpio.c
+422
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_gpio.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_gpio.c
*
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include <arch/stm32l5/chip.h>
#include "arm_arch.h"
#include "chip.h"
#include "stm32l5_gpio.h"
#include "hardware/stm32l5_syscfg.h"
/****************************************************************************
* Public Data
****************************************************************************/
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[STM32L5_NPORTS] =
{
#if STM32L5_NPORTS > 0
STM32L5_GPIOA_BASE,
#endif
#if STM32L5_NPORTS > 1
STM32L5_GPIOB_BASE,
#endif
#if STM32L5_NPORTS > 2
STM32L5_GPIOC_BASE,
#endif
#if STM32L5_NPORTS > 3
STM32L5_GPIOD_BASE,
#endif
#if STM32L5_NPORTS > 4
STM32L5_GPIOE_BASE,
#endif
#if STM32L5_NPORTS > 5
STM32L5_GPIOF_BASE,
#endif
#if STM32L5_NPORTS > 6
STM32L5_GPIOG_BASE,
#endif
#if STM32L5_NPORTS > 7
STM32L5_GPIOH_BASE,
#endif
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32l5_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32l5_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exlusion is necessary.
*
****************************************************************************/
void stm32l5_gpioinit(void)
{
}
/****************************************************************************
* Name: stm32l5_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32l5_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* A negated errono valu on invalid port, or when pin is locked as ALT
* function.
*
* To-Do: Auto Power Enable
****************************************************************************/
int stm32l5_configgpio(uint32_t cfgset)
{
uintptr_t base;
uint32_t regval;
uint32_t setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
unsigned int pos;
unsigned int pinmode;
irqstate_t flags;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32L5_NPORTS)
{
return -EINVAL;
}
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and select the port configuration register for that
* pin
*/
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set up the mode register (and remember whether the pin mode) */
switch (cfgset & GPIO_MODE_MASK)
{
default:
case GPIO_INPUT: /* Input mode */
pinmode = GPIO_MODER_INPUT;
break;
case GPIO_OUTPUT: /* General purpose output mode */
/* Set the initial output value */
stm32l5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
pinmode = GPIO_MODER_OUTPUT;
break;
case GPIO_ALT: /* Alternate function mode */
pinmode = GPIO_MODER_ALT;
break;
case GPIO_ANALOG: /* Analog mode */
pinmode = GPIO_MODER_ANALOG;
break;
}
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = enter_critical_section();
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32L5_GPIO_MODER_OFFSET);
regval &= ~GPIO_MODER_MASK(pin);
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
putreg32(regval, base + STM32L5_GPIO_MODER_OFFSET);
/* Set up the pull-up/pull-down configuration (all but analog pins) */
setting = GPIO_PUPDR_NONE;
if (pinmode != GPIO_MODER_ANALOG)
{
switch (cfgset & GPIO_PUPD_MASK)
{
default:
case GPIO_FLOAT: /* No pull-up, pull-down */
break;
case GPIO_PULLUP: /* Pull-up */
setting = GPIO_PUPDR_PULLUP;
break;
case GPIO_PULLDOWN: /* Pull-down */
setting = GPIO_PUPDR_PULLDOWN;
break;
}
}
regval = getreg32(base + STM32L5_GPIO_PUPDR_OFFSET);
regval &= ~GPIO_PUPDR_MASK(pin);
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32L5_GPIO_PUPDR_OFFSET);
/* Set the alternate function (Only alternate function pins) */
if (pinmode == GPIO_MODER_ALT)
{
setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
}
else
{
setting = 0;
}
if (pin < 8)
{
regoffset = STM32L5_GPIO_AFRL_OFFSET;
pos = pin;
}
else
{
regoffset = STM32L5_GPIO_AFRH_OFFSET;
pos = pin - 8;
}
regval = getreg32(base + regoffset);
regval &= ~GPIO_AFR_MASK(pos);
regval |= (setting << GPIO_AFR_SHIFT(pos));
putreg32(regval, base + regoffset);
/* Set speed (Only outputs and alternate function pins) */
if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT)
{
switch (cfgset & GPIO_SPEED_MASK)
{
default:
case GPIO_SPEED_2MHZ: /* 2 MHz Low speed output */
setting = GPIO_OSPEED_2MHZ;
break;
case GPIO_SPEED_25MHZ: /* 25 MHz Medium speed output */
setting = GPIO_OSPEED_25MHZ;
break;
case GPIO_SPEED_50MHZ: /* 50 MHz High speed output */
setting = GPIO_OSPEED_50MHZ;
break;
case GPIO_SPEED_100MHZ: /* 100 MHz Very High speed output */
setting = GPIO_OSPEED_100MHZ;
break;
}
}
else
{
setting = 0;
}
regval = getreg32(base + STM32L5_GPIO_OSPEED_OFFSET);
regval &= ~GPIO_OSPEED_MASK(pin);
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
putreg32(regval, base + STM32L5_GPIO_OSPEED_OFFSET);
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
regval = getreg32(base + STM32L5_GPIO_OTYPER_OFFSET);
setting = GPIO_OTYPER_OD(pin);
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
(cfgset & GPIO_OPENDRAIN) != 0)
{
regval |= setting;
}
else
{
regval &= ~setting;
}
putreg32(regval, base + STM32L5_GPIO_OTYPER_OFFSET);
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: stm32l5_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previsouly selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from schocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port
*
* To-Do: Auto Power Disable
****************************************************************************/
int stm32l5_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
cfgset |= GPIO_INPUT | GPIO_FLOAT;
/* To-Do: Mark its unuse for automatic power saving options */
return stm32l5_configgpio(cfgset);
}
/****************************************************************************
* Name: stm32l5_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32l5_gpiowrite(uint32_t pinset, bool value)
{
uint32_t base;
uint32_t bit;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32L5_NPORTS)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set or clear the output on the pin */
if (value)
{
bit = GPIO_BSRR_SET(pin);
}
else
{
bit = GPIO_BSRR_RESET(pin);
}
putreg32(bit, base + STM32L5_GPIO_BSRR_OFFSET);
}
}
/****************************************************************************
* Name: stm32l5_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32l5_gpioread(uint32_t pinset)
{
uint32_t base;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32L5_NPORTS)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and return the input state of that pin */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
return ((getreg32(base + STM32L5_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
}
return 0;
}
arch/arm/src/stm32l5/stm32l5_gpio.h
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_gpio.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_gpio.h
*
* Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include <arch/stm32l5/chip.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
# include "hardware/stm32l5_gpio.h"
#else
# error "Unsupported STM32L5 chip"
#endif
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
/* Bit-encoded input to stm32l5_configgpio() */
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually
* configured by software in several modes:
*
* - Input floating
* - Input pull-up
* - Input-pull-down
* - Output open-drain with pull-up or pull-down capability
* - Output push-pull with pull-up or pull-down capability
* - Alternate function push-pull with pull-up or pull-down capability
* - Alternate function open-drain with pull-up or pull-down capability
* - Analog
*
* 20-bit Encoding: 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* Inputs: MMUU .... ...X PPPP BBBB
* Outputs: MMUU .... FFOV PPPP BBBB
* Alternate Functions: MMUU AAAA FFO. PPPP BBBB
* Analog: MM.. .... .... PPPP BBBB
*/
/* Mode:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* MM.. .... .... .... ....
*/
#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
/* Input/output pull-ups/downs (not used with analog):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* ..UU .... .... .... ....
*/
#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */
#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */
/* Alternate Functions:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... AAAA .... .... ....
*/
#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT)
# define GPIO_AF0 (0 << GPIO_AF_SHIFT)
# define GPIO_AF1 (1 << GPIO_AF_SHIFT)
# define GPIO_AF2 (2 << GPIO_AF_SHIFT)
# define GPIO_AF3 (3 << GPIO_AF_SHIFT)
# define GPIO_AF4 (4 << GPIO_AF_SHIFT)
# define GPIO_AF5 (5 << GPIO_AF_SHIFT)
# define GPIO_AF6 (6 << GPIO_AF_SHIFT)
# define GPIO_AF7 (7 << GPIO_AF_SHIFT)
# define GPIO_AF8 (8 << GPIO_AF_SHIFT)
# define GPIO_AF9 (9 << GPIO_AF_SHIFT)
# define GPIO_AF10 (10 << GPIO_AF_SHIFT)
# define GPIO_AF11 (11 << GPIO_AF_SHIFT)
# define GPIO_AF12 (12 << GPIO_AF_SHIFT)
# define GPIO_AF13 (13 << GPIO_AF_SHIFT)
# define GPIO_AF14 (14 << GPIO_AF_SHIFT)
# define GPIO_AF15 (15 << GPIO_AF_SHIFT)
/* Output/Alt function frequency selection:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... FF.. .... ....
*/
#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
# define GPIO_SPEED_2MHZ (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
# define GPIO_SPEED_25MHZ (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
# define GPIO_SPEED_50MHZ (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */
# define GPIO_SPEED_100MHZ (3 << GPIO_SPEED_SHIFT) /* 100 MHz Very High speed output */
/* Output/Alt function type selection:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ..O. .... ....
*/
#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */
#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */
/* If the pin is a GPIO digital output, then this identifies the initial
* output value. If the pin is an input, this bit is overloaded to provide
* the qualifier to distinquish input pull-up and -down:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ...V .... ....
*/
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* External interrupt selection (GPIO inputs only):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ...X .... ....
*/
#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */
/* This identifies the GPIO port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... PPPP ....
*/
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
/* This identifies the bit in the port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... .... BBBB
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpiobase[STM32L5_NPORTS];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32l5_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32l5_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
****************************************************************************/
int stm32l5_configgpio(uint32_t cfgset);
/****************************************************************************
* Name: stm32l5_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previsouly selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from schocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* ERROR on invalid port
*
****************************************************************************/
int stm32l5_unconfiggpio(uint32_t cfgset);
/****************************************************************************
* Name: stm32l5_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32l5_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: stm32l5_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32l5_gpioread(uint32_t pinset);
/****************************************************************************
* Name: stm32l5_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* pinset - GPIO pin configuration
* risingedge - Enables interrupt on rising edges
* fallingedge - Enables interrupt on falling edges
* event - Generate event when set
* func - When non-NULL, generate interrupt
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) is returned on success, otherwise a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Function: stm32l5_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int stm32l5_dumpgpio(uint32_t pinset, const char *msg);
#else
# define stm32l5_dumpgpio(p,m)
#endif
/****************************************************************************
* Function: stm32l5_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32l5_start().
*
****************************************************************************/
void stm32l5_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H */
arch/arm/src/stm32l5/stm32l5_idle.c
+100
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include "chip.h"
#include "stm32l5_rcc.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
#define up_idlepm()
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
}
arch/arm/src/stm32l5/stm32l5_irq.c
+540
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arch/arm/src/stm32l5/stm32l5_lowputc.c
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "arm_arch.h"
#include "chip.h"
#include "stm32l5.h"
#include "stm32l5_rcc.h"
#include "stm32l5_gpio.h"
#include "stm32l5_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select USART parameters for the selected console */
#ifdef HAVE_CONSOLE
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define STM32L5_CONSOLE_BASE STM32L5_LPUART1_BASE
# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY
# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR2
# define STM32L5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
# define STM32L5_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define STM32L5_CONSOLE_BITS CONFIG_LPUART1_BITS
# define STM32L5_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define STM32L5_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# define STM32L5_CONSOLE_TX GPIO_LPUART1_TX
# define STM32L5_CONSOLE_RX GPIO_LPUART1_RX
# ifdef CONFIG_LPUART1_RS485
# define STM32L5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
# define STM32L5_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32L5_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32L5_CONSOLE_BASE STM32L5_USART1_BASE
# define STM32L5_APBCLOCK STM32L5_PCLK2_FREQUENCY
# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB2ENR
# define STM32L5_CONSOLE_APBEN RCC_APB2ENR_USART1EN
# define STM32L5_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32L5_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32L5_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32L5_CONSOLE_2STOP CONFIG_USART1_2STOP
# define STM32L5_CONSOLE_TX GPIO_USART1_TX
# define STM32L5_CONSOLE_RX GPIO_USART1_RX
# ifdef CONFIG_USART1_RS485
# define STM32L5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
# define STM32L5_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32L5_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32L5_CONSOLE_BASE STM32L5_USART2_BASE
# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY
# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1
# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
# define STM32L5_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32L5_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32L5_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32L5_CONSOLE_2STOP CONFIG_USART2_2STOP
# define STM32L5_CONSOLE_TX GPIO_USART2_TX
# define STM32L5_CONSOLE_RX GPIO_USART2_RX
# ifdef CONFIG_USART2_RS485
# define STM32L5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
# define STM32L5_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32L5_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32L5_CONSOLE_BASE STM32L5_USART3_BASE
# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY
# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1
# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART3EN
# define STM32L5_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32L5_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32L5_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32L5_CONSOLE_2STOP CONFIG_USART3_2STOP
# define STM32L5_CONSOLE_TX GPIO_USART3_TX
# define STM32L5_CONSOLE_RX GPIO_USART3_RX
# ifdef CONFIG_USART3_RS485
# define STM32L5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
# define STM32L5_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32L5_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define STM32L5_CONSOLE_BASE STM32L5_UART4_BASE
# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY
# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1
# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART4EN
# define STM32L5_CONSOLE_BAUD CONFIG_UART4_BAUD
# define STM32L5_CONSOLE_BITS CONFIG_UART4_BITS
# define STM32L5_CONSOLE_PARITY CONFIG_UART4_PARITY
# define STM32L5_CONSOLE_2STOP CONFIG_UART4_2STOP
# define STM32L5_CONSOLE_TX GPIO_UART4_TX
# define STM32L5_CONSOLE_RX GPIO_UART4_RX
# ifdef CONFIG_UART4_RS485
# define STM32L5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
# define STM32L5_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32L5_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define STM32L5_CONSOLE_BASE STM32L5_UART5_BASE
# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY
# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1
# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART5EN
# define STM32L5_CONSOLE_BAUD CONFIG_UART5_BAUD
# define STM32L5_CONSOLE_BITS CONFIG_UART5_BITS
# define STM32L5_CONSOLE_PARITY CONFIG_UART5_PARITY
# define STM32L5_CONSOLE_2STOP CONFIG_UART5_2STOP
# define STM32L5_CONSOLE_TX GPIO_UART5_TX
# define STM32L5_CONSOLE_RX GPIO_UART5_RX
# ifdef CONFIG_UART5_RS485
# define STM32L5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
# define STM32L5_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32L5_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */
# if STM32L5_CONSOLE_BITS == 9
# define USART_CR1_M0_VALUE USART_CR1_M0
# define USART_CR1_M1_VALUE 0
# elif STM32L5_CONSOLE_BITS == 7
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE USART_CR1_M1
# else /* 8 bits */
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE 0
# endif
# if STM32L5_CONSOLE_PARITY == 1 /* odd parity */
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
# elif STM32L5_CONSOLE_PARITY == 2 /* even parity */
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
# else /* no parity */
# define USART_CR1_PARITY_VALUE 0
# endif
# define USART_CR1_CLRBITS \
(USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
/* CR2 settings */
# if STM32L5_CONSOLE_2STOP != 0
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
# else
# define USART_CR2_STOP2_VALUE 0
# endif
# define USART_CR2_CLRBITS \
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
/* CR3 settings */
# define USART_CR3_CLRBITS \
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
# define USART_CR3_SETBITS 0
# undef USE_OVER8
/* Calculate USART BAUD rate divider */
/* Baud rate for standard USART (SPI mode included):
*
* In case of oversampling by 16, the equation is:
* baud = fCK / UARTDIV
* UARTDIV = fCK / baud
*
* In case of oversampling by 8, the equation is:
*
* baud = 2 * fCK / UARTDIV
* UARTDIV = 2 * fCK / baud
*/
# define STM32L5_USARTDIV8 \
(((STM32L5_APBCLOCK << 1) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD)
# define STM32L5_USARTDIV16 \
((STM32L5_APBCLOCK + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD)
/* Use oversamply by 8 only if the divisor is small. But what is small? */
# if STM32L5_USARTDIV8 > 2000
# define STM32L5_BRR_VALUE STM32L5_USARTDIV16
# else
# define USE_OVER8 1
# define STM32L5_BRR_VALUE \
((STM32L5_USARTDIV8 & 0xfff0) | ((STM32L5_USARTDIV8 & 0x000f) >> 1))
# endif
#endif /* HAVE_CONSOLE */
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Variables
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) &
USART_ISR_TXE) == 0);
#ifdef STM32L5_CONSOLE_RS485_DIR
stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR,
STM32L5_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
putreg32((uint32_t)ch, STM32L5_CONSOLE_BASE + STM32L5_USART_TDR_OFFSET);
#ifdef STM32L5_CONSOLE_RS485_DIR
while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) &
USART_ISR_TC) == 0);
stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR,
!STM32L5_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: stm32l5_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void stm32l5_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
modifyreg32(STM32L5_CONSOLE_APBREG, 0, STM32L5_CONSOLE_APBEN);
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in
* stm32l5_rcc.c
*/
#ifdef STM32L5_CONSOLE_TX
stm32l5_configgpio(STM32L5_CONSOLE_TX);
#endif
#ifdef STM32L5_CONSOLE_RX
stm32l5_configgpio(STM32L5_CONSOLE_RX);
#endif
#ifdef STM32L5_CONSOLE_RS485_DIR
stm32l5_configgpio(STM32L5_CONSOLE_RS485_DIR);
stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR,
!STM32L5_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Enable and configure the selected console device */
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Configure CR2 */
cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET);
/* Configure CR1 */
cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET);
/* Configure CR3 */
cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET);
/* Configure the USART Baud Rate */
putreg32(STM32L5_BRR_VALUE,
STM32L5_CONSOLE_BASE + STM32L5_USART_BRR_OFFSET);
/* Select oversampling by 8 */
cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET);
#ifdef USE_OVER8
cr |= USART_CR1_OVER8;
putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET);
#endif
/* Enable Rx, Tx, and the USART */
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
}
arch/arm/src/stm32l5/stm32l5_lowputc.h
+64
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32l5_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization of serial console.
*
****************************************************************************/
void stm32l5_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H */
arch/arm/src/stm32l5/stm32l5_lse.c
+166
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_lse.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_lse.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include "stm32l5_pwr.h"
#include "stm32l5_rcc.h"
#include "stm32l5_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
#endif
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l5_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) oscillator and the LSE system clock.
*
****************************************************************************/
void stm32l5_rcc_enablelse(void)
{
bool writable;
uint32_t regval;
/* Check if both the External Low-Speed (LSE) oscillator and the LSE system
* clock are already running.
*/
regval = getreg32(STM32L5_RCC_BDCR);
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) !=
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN))
{
/* The LSE is in the RTC domain and write access is denied to this
* domain after reset, you have to enable write access using DBP bit in
* the PWR CR register before to configuring the LSE.
*/
writable = stm32l5_pwr_enablebkp(true);
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON
* bit the RCC BDCR register.
*/
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. */
regval &= ~RCC_BDCR_LSEDRV_MASK;
regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
#endif
putreg32(regval, STM32L5_RCC_BDCR);
/* Wait for the LSE clock to be ready */
while (((regval = getreg32(STM32L5_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0)
{
up_waste();
}
/* Enable LSE system clock. The LSE system clock has been introduced
* first by the STM32L5 family of MCUs. It seems to provide a means
* to gate the LSE clock distribution to peripherals. It must be
* enabled for MSI PLL mode (syncing the MSI to the LSE).
*/
regval |= RCC_BDCR_LSESYSEN;
putreg32(regval, STM32L5_RCC_BDCR);
/* Wait for the LSE system clock to be ready */
while (!((regval = getreg32(STM32L5_RCC_BDCR)) & RCC_BDCR_LSESYSRDY))
{
up_waste();
}
#if defined(CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \
CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY != \
CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0
# error "STM32L5 only allows lowering LSE drive capability to zero"
# endif
/* Set running drive capability for LSE oscillator. */
regval &= ~RCC_BDCR_LSEDRV_MASK;
regval |= CONFIG_STM32L5_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32L5_RCC_BDCR);
#endif
/* Disable backup domain access if it was disabled on entry */
(void)stm32l5_pwr_enablebkp(writable);
}
}
arch/arm/src/stm32l5/stm32l5_lsi.c
+92
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@@ -0,0 +1,92 @@
/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_lsi.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_lsi.c
*
* Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include "stm32l5_rcc.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l5_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32l5_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32L5_RCC_CSR, 0, RCC_CSR_LSION);
/* Wait for the internal LSI oscillator to be stable. */
while ((getreg32(STM32L5_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
}
/****************************************************************************
* Name: stm32l5_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32l5_rcc_disablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32L5_RCC_CSR, RCC_CSR_LSION, 0);
/* LSIRDY should go low after 3 LSI clock cycles */
}
arch/arm/src/stm32l5/stm32l5_mpuinit.c
+100
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_mpuinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "stm32l5_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l5_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
*
****************************************************************************/
void stm32l5_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: stm32l5_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void stm32l5_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */
arch/arm/src/stm32l5/stm32l5_mpuinit.h
+63
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@@ -0,0 +1,63 @@
/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_mpuinit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32l5_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32l5_mpuinitialize(void);
#else
# define stm32l5_mpuinitialize()
#endif
/****************************************************************************
* Name: stm32l5_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32l5_mpu_uheap(uintptr_t start, size_t size);
#else
# define stm32l5_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H */
arch/arm/src/stm32l5/stm32l5_pwr.c
+273
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/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_pwr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include "arm_arch.h"
#include "stm32l5_pwr.h"
#include "stm32l5_rcc.h"
/****************************************************************************
* Private Functions
****************************************************************************/
static inline uint16_t stm32l5_pwr_getreg(uint8_t offset)
{
return (uint16_t)getreg32(STM32L5_PWR_BASE + (uint32_t)offset);
}
static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value)
{
putreg32((uint32_t)value, STM32L5_PWR_BASE + (uint32_t)offset);
}
static inline void stm32l5_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
uint16_t setbits)
{
modifyreg32(STM32L5_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits,
(uint32_t)setbits);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: enableclk
*
* Description:
* Enable/disable the clock to the power control peripheral. Enabling must
* be done after the APB1 clock is validly configured, and prior to using
* any functionality controlled by the PWR block (i.e. much of anything
* else provided by this module).
*
* Input Parameters:
* enable - True: enable the clock to the Power control (PWR) block.
*
* Returned Value:
* True: the PWR block was previously enabled.
*
****************************************************************************/
bool stm32l5_pwr_enableclk(bool enable)
{
uint32_t regval;
bool wasenabled;
regval = getreg32(STM32L5_RCC_APB1ENR1);
wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
/* Power interface clock enable. */
if (wasenabled && !enable)
{
/* Disable power interface clock */
regval &= ~RCC_APB1ENR1_PWREN;
putreg32(regval, STM32L5_RCC_APB1ENR1);
}
else if (!wasenabled && enable)
{
/* Enable power interface clock */
regval |= RCC_APB1ENR1_PWREN;
putreg32(regval, STM32L5_RCC_APB1ENR1);
}
return wasenabled;
}
/****************************************************************************
* Name: stm32l5_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
****************************************************************************/
bool stm32l5_pwr_enablebkp(bool writable)
{
uint16_t regval;
bool waswritable;
/* Get the current state of the STM32L5 PWR control register 1 */
regval = stm32l5_pwr_getreg(STM32L5_PWR_CR1_OFFSET);
waswritable = ((regval & PWR_CR1_DBP) != 0);
/* Enable or disable the ability to write */
if (waswritable && !writable)
{
/* Disable backup domain access */
regval &= ~PWR_CR1_DBP;
stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval);
}
else if (!waswritable && writable)
{
/* Enable backup domain access */
regval |= PWR_CR1_DBP;
stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval);
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/****************************************************************************
* Name: stm32l5_pwr_enableusv
*
* Description:
* Enables or disables the USB Supply Valid monitoring. Setting this bit
* is mandatory to use the USB OTG FS peripheral.
*
* Input Parameters:
* set - True: Vddusb is valid; False: Vddusb is not present. Logical and
* electrical isolation is applied to ignore this supply.
*
* Returned Value:
* True: The bit was previously set.
*
****************************************************************************/
bool stm32l5_pwr_enableusv(bool set)
{
uint32_t regval;
bool was_set;
bool was_clk_enabled;
regval = getreg32(STM32L5_RCC_APB1ENR1);
was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
if (!was_clk_enabled)
{
stm32l5_pwr_enableclk(true);
}
/* Get the current state of the STM32L5 PWR control register 2 */
regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET);
was_set = ((regval & PWR_CR2_USV) != 0);
/* Enable or disable the ability to write */
if (was_set && !set)
{
/* Disable the Vddusb monitoring */
regval &= ~PWR_CR2_USV;
stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval);
}
else if (!was_set && set)
{
/* Enable the Vddusb monitoring */
regval |= PWR_CR2_USV;
stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval);
}
if (!was_clk_enabled)
{
stm32l5_pwr_enableclk(false);
}
return was_set;
}
/****************************************************************************
* Name: stm32l5_pwr_vddio2_valid
*
* Description:
* Report that the Vddio2 independent I/Os supply voltage is valid or not.
* Setting this bit is mandatory to use the PG2 - PG15 I/Os.
*
* Input Parameters:
* set - True: Vddio2 is value; False: Vddio2 is not present. Logical and
* electrical isolation is applied to ignore this supply.
*
* Returned Value:
* True: The bit was previously set.
*
****************************************************************************/
bool stm32l5_pwr_vddio2_valid(bool set)
{
uint32_t regval;
bool was_set;
bool was_clk_enabled;
regval = getreg32(STM32L5_RCC_APB1ENR1);
was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
if (!was_clk_enabled)
{
stm32l5_pwr_enableclk(true);
}
/* Get the current state of the STM32L5 PWR control register 2 */
regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET);
was_set = ((regval & PWR_CR2_IOSV) != 0);
/* Enable or disable the ability to write */
if (was_set && !set)
{
/* Reset the Vddio2 invalid I/O supply valid bit. */
regval &= ~PWR_CR2_IOSV;
stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval);
}
else if (!was_set && set)
{
/* Set the Vddio2 invalid I/O supply valid bit. */
regval |= PWR_CR2_IOSV;
stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval);
}
if (!was_clk_enabled)
{
stm32l5_pwr_enableclk(false);
}
return was_set;
}
arch/arm/src/stm32l5/stm32l5_pwr.h
+131
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@@ -0,0 +1,131 @@
/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/stm32l5_pwr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: enableclk
*
* Description:
* Enable/disable the clock to the power control peripheral. Enabling must
* be done after the APB1 clock is validly configured, and prior to using
* any functionality controlled by the PWR block (i.e. much of anything
* else provided by this module).
*
* Input Parameters:
* enable - True: enable the clock to the Power control (PWR) block.
*
* Returned Value:
* True: the PWR block was previously enabled.
*
****************************************************************************/
bool stm32l5_pwr_enableclk(bool enable);
/****************************************************************************
* Name: stm32l5_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
****************************************************************************/
bool stm32l5_pwr_enablebkp(bool writable);
/****************************************************************************
* Name: stm32l5_pwr_enableusv
*
* Description:
* Enables or disables the USB Supply Valid monitoring. Setting this bit
* is mandatory to use the USB OTG FS peripheral.
*
* Input Parameters:
* set - True: Vddusb is valid; False: Vddusb is not present. Logical and
* electrical isolation is applied to ignore this supply.
*
* Returned Value:
* True: The bit was previously set.
*
****************************************************************************/
bool stm32l5_pwr_enableusv(bool set);
/****************************************************************************
* Name: stm32l5_pwr_vddio2_valid
*
* Description:
* Report that the Vddio2 independent I/Os supply voltage is valid or not.
* Setting this bit is mandatory to use the PG2 - PG15 I/Os.
*
* Input Parameters:
* set - True: Vddio2 is value; False: Vddio2 is not present. Logical and
* electrical isolation is applied to ignore this supply.
*
* Returned Value:
* True: The bit was previously set.
****************************************************************************/
bool stm32l5_pwr_vddio2_valid(bool set);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H */
arch/arm/src/stm32l5/stm32l5_rcc.c
+258
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@@ -0,0 +1,258 @@
/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_rcc.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author
*
* Based on arch/arm/src/stm32l4/stm32l4_rcc.c
*
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
* Author
* Author
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "arm_arch.h"
#include "chip.h"
#include "stm32l5_rcc.h"
#include "stm32l5_flash.h"
#include "stm32l5.h"
#include "stm32l5_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name
*
* Description
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
* the Backup Domain renders to disabling the LSE as consequence. In
* order to avoid resetting the Backup Domain when we already configured
* LSE we will reset the Backup Domain early (here).
*
* Input Parameters
* None
*
* Returned Value
* None
*
****************************************************************************/
#if defined(CONFIG_STM32L5_PWR) && defined(CONFIG_STM32L5_RTC)
static inline void rcc_resetbkp(void)
{
bool init_stat;
/* Check if the RTC is already configured */
init_stat = stm32l5_rtc_is_initialized();
if (!init_stat)
{
uint32_t bkregs[STM32L5_RTC_BKCOUNT];
int i;
/* Backup backup-registers before RTC reset. */
for (i = 0; i < STM32L5_RTC_BKCOUNT; i++)
{
bkregs[i] = getreg32(STM32L5_RTC_BKR(i));
}
/* Enable write access to the backup domain (RTC registers, RTC
* backup data registers and backup SRAM).
*/
(void)stm32l5_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
*/
modifyreg32(STM32L5_RCC_BDCR, 0, RCC_BDCR_BDRST);
modifyreg32(STM32L5_RCC_BDCR, RCC_BDCR_BDRST, 0);
/* Restore backup-registers, except RTC related. */
for (i = 0; i < STM32L5_RTC_BKCOUNT; i++)
{
if (RTC_MAGIC_REG == STM32L5_RTC_BKR(i))
{
continue;
}
putreg32(bkregs[i], STM32L5_RTC_BKR(i));
}
(void)stm32l5_pwr_enablebkp(false);
}
}
#else
# define rcc_resetbkp()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name
*
* Description
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32l5_board_clockconfig().
*
* Input Parameters
* None
*
* Returned Value
* None
*
****************************************************************************/
void stm32l5_clockconfig(void)
{
#if 0
/* Make sure that we are starting in the reset state */
rcc_reset();
/* Reset backup domain if appropriate */
rcc_resetbkp();
#endif
#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32l5_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions in
* board.h
*/
stm32l5_stdclockconfig();
#endif
/* Enable peripheral clocking */
stm32l5_rcc_enableperipherals();
}
/****************************************************************************
* Name
*
* Description
* Re-enable the clock and restore the clock settings based on settings in
* board.h. This function is only available to support low-power modes of
* operation
* re-enable/re-start the PLL
*
* This functional performs a subset of the operations performed by
* stm32l5_clockconfig()
* reset the currenlty enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32l5_board_clockconfig().
*
* Input Parameters
* None
*
* Returned Value
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32l5_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32l5_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions in
* board.h
*/
stm32l5_stdclockconfig();
#endif
}
#endif
arch/arm/src/stm32l5/stm32l5_rcc.h
+259
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@@ -0,0 +1,259 @@
/****************************************************************************
* arch/arm/src/stm32l5/stm32l5_rcc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_rcc.h
*
* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
# include "hardware/stm32l562xx_rcc.h"
#else
# error "Unsupported STM32L5 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#elseO
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This symbol references the Cortex-M33 vector table (as positioned by the
* linker script, ld.script or ld.script.dfu. The standard location for the
* vector table is at the beginning of FLASH at address 0x0800:0000. If we
* are using the STMicro DFU bootloader, then the vector table will be offset
* to a different location in FLASH and we will need to set the NVIC vector
* location to this alternative location.
*/
extern uint32_t _vectors[]; /* See stm32l5_vectors.S */
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: stm32l5_mcoconfig
*
* Description:
* Selects the clock source to output on MC pin (PA8) for stm32l562xx
* PA8 should be configured in alternate function mode.
*
* Input Parameters:
* source - One of the definitions for the RCC_CFGR_MCO definitions from
* chip/stm32l562xx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK,
* RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK,
* RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK}
*
* Returned Value:
* None
*
****************************************************************************/
static inline void stm32l5_mcoconfig(uint32_t source)
{
uint32_t regval;
/* Set MCO source */
regval = getreg32(STM32L5_RCC_CFGR);
regval &= ~(RCC_CFGR_MCOSEL_MASK);
regval |= (source & RCC_CFGR_MCOSEL_MASK);
putreg32(regval, STM32L5_RCC_CFGR);
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32l5_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32l5_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32l5_clockconfig(void);
/****************************************************************************
* Name: stm32l5_board_clockconfig
*
* Description:
* Any STM32L5 board may replace the "standard" board clock configuration
* logic with its own, custom clock cofiguration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG
void stm32l5_board_clockconfig(void);
#endif
/****************************************************************************
* Name: stm32l5_stdclockconfig
*
* Description:
* The standard logic to configure the clocks based on settings in board.h.
* Applicable if no custom clock config is provided. This function is
* chip type specific and implemented in corresponding modules such as e.g.
* stm32l562xx_rcc.c
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG
void stm32l5_stdclockconfig(void);
#endif
/****************************************************************************
* Name: stm32l5_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h. This function is only available to support low-power modes of
* operation: When re-awakening from deep-sleep modes, it is necessary to
* re-enable/re-start the PLL
*
* This functional performs a subset of the operations performed by
* stm32l5_clockconfig(): It does not reset any devices, and it does not
* reset the currenlty enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32l5_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32l5_clockenable(void);
#endif
/****************************************************************************
* Name: stm32l5_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32l5_rcc_enablelse(void);
/****************************************************************************
* Name: stm32l5_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32l5_rcc_enablelsi(void);
/****************************************************************************
* Name: stm32l5_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32l5_rcc_disablelsi(void);
/****************************************************************************
* Name: stm32l5_rcc_enableperipherals
*
* Description:
* Enable all the chip peripherals according to configuration. This is
* chip type specific and thus implemented in corresponding modules such as
* e.g. stm32l562xx_rcc.c
*
****************************************************************************/
void stm32l5_rcc_enableperipherals(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H */
arch/arm/src/stm32l5/stm32l5_serial.c
+3268
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arch/arm/src/stm32l5/stm32l5_spi.c
+1928
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arch/arm/src/stm32l5/stm32l5_spi.h
+192
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@@ -0,0 +1,192 @@
/*****************************************************************************
* arch/arm/src/stm32l5/stm32l5_spi.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net>
*
* Based on arch/arm/src/stm32l4/stm32l4_spi.h
*
* Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H
#define __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/stm32l5_spi.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Data
*****************************************************************************/
struct spi_dev_s;
/*****************************************************************************
* Public Function Prototypes
*****************************************************************************/
/*****************************************************************************
* Name: stm32l5_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameters:
* bus number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
*****************************************************************************/
FAR struct spi_dev_s *stm32l5_spibus_initialize(int bus);
/*****************************************************************************
* Name: stm32l5_spi1/2/...select and stm32l5_spi1/2/...status
*
* Description:
* The external functions, stm32l5_spi1/2/...select,
* stm32l5_spi1/2/...status, and stm32l5_spi1/2/...cmddata must be provided
* by board-specific logic. These are implementations of the select,
* status, and cmddata methods of the SPI interface defined by struct
* spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including
* stm32l5_spibus_initialize()) are provided by common STM32 logic. To use
* this common SPI logic on your board:
*
* 1. Provide logic in stm32l5_board_initialize() to configure SPI chip
* select pins.
* 2. Provide stm32l5_spi1/2/...select() and stm32l5_spi1/2/...status()
* functions in your board-specific logic. These functions will perform
* chip selection and status operations using GPIOs in the way your board
* is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
* then provide stm32l5_spi1/2/...cmddata() functions in your
* board-specific logic. These functions will perform cmd/data selection
* operations using GPIOs in the way your board is configured.
* 4. Add a calls to stm32l5_spibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by stm32l5_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
*****************************************************************************/
#ifdef CONFIG_STM32L5_SPI1
void stm32l5_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32l5_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32l5_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32L5_SPI2
void stm32l5_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32l5_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32l5_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32L5_SPI3
void stm32l5_spi3select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32l5_spi3status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32l5_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/*****************************************************************************
* Name: stm32l5_spi1/2/...register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
* be implemented. These functions implements the registercallback method
* of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
*****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32L5_SPI1
int stm32l5_spi1register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32L5_SPI2
int stm32l5_spi2register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32L5_SPI3
int stm32l5_spi3register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H */
arch/arm/src/stm32l5/stm32l5_start.c
+369
View File
@@ -0,0 +1,369 @@
/*****************************************************************************
* arch/arm/src/stm32l5/stm32l5_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "arm_internal.h"
#include "nvic.h"
#include "stm32l5.h"
#include "stm32l5_gpio.h"
#include "stm32l5_userspace.h"
#include "stm32l5_start.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* Memory Map ****************************************************************/
/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata)
* - End of .data (_edata) and start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
* start of heap. NOTE that the ARM uses a decrement before
* store stack so that the correct initial value is the end of
* the stack + 4;
* 0x2002:ffff - End of internal SRAM1
* 0x2003:0000 - Start of internal SRAM2
* 0x2003:ffff - End of internal SRAM2
*/
#define SRAM2_START STM32L5_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE)
#define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/*****************************************************************************
* Private Function prototypes
*****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32l5_fpuconfig(void);
#endif
#ifdef CONFIG_STACK_COLORATION
static void go_nx_start(void *pv, unsigned int nbytes)
__attribute__ ((naked, no_instrument_function, noreturn));
#endif
/*****************************************************************************
* Private Functions
*****************************************************************************/
/*****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
*****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/*****************************************************************************
* Public Functions
*****************************************************************************/
#ifdef CONFIG_ARMV8M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) __attribute__ ((no_instrument_function));
#endif
/*****************************************************************************
* Name: stm32l5_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
*****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV8M_LAZYFPU
static inline void stm32l5_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= (1 << 2);
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32l5_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~(1 << 2);
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32l5_fpuconfig()
#endif
/*****************************************************************************
* Name: go_nx_start
*
* Description:
* Set the IDLE stack to the coloration value and jump into nx_start()
*
*****************************************************************************/
#ifdef CONFIG_STACK_COLORATION
static void go_nx_start(void *pv, unsigned int nbytes)
{
/* Set the IDLE stack to the stack coloration value then jump to
* nx_start(). We take extreme care here because were currently
* executing on this stack.
*
* We want to avoid sneak stack access generated by the compiler.
*/
__asm__ __volatile__
(
"\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */
"\tcmp r1, #0\n" /* Check (nwords == 0) */
"\tbeq 2f\n" /* (should not happen) */
"\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */
"\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */
"\tmovt r2, #0xdead\n"
"1:\n" /* Top of the loop */
"\tsub r1, r1, #1\n" /* R1 nwords-- */
"\tcmp r1, #0\n" /* Check (nwords == 0) */
"\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */
"\tbne 1b\n" /* Bottom of the loop */
"2:\n"
"\tmov r14, #0\n" /* LR = return address (none) */
"\tb nx_start\n" /* Branch to nx_start */
);
}
#endif
/*****************************************************************************
* Public Functions
*****************************************************************************/
/*****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
*****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV8M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile
("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32L5_SRAM2_INIT
/* The SRAM2 region is parity checked, but upon power up, it will be in
* a random state and probably invalid with respect to parity, potentially
* generating faults if accessed. If elected, we will write zeros to the
* memory, forcing the parity to be set to a valid state.
* NOTE: this is optional because this may be inappropriate, especially
* if the memory is being used for it's battery backed purpose. In that
* case, the first-time initialization needs to be performed by the board
* under application-specific circumstances. On the other hand, if we're
* using this memory for, say, additional heap space, then this is handy.
*/
for (dest = (uint32_t *)SRAM2_START; dest < (uint32_t *)SRAM2_END; )
{
*dest++ = 0;
}
#endif
/* Configure the UART so that we can get debug output as soon as possible */
stm32l5_clockconfig();
stm32l5_fpuconfig();
stm32l5_lowsetup();
stm32l5_gpioinit();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; )
{
*dest++ = 0;
}
showprogress('B');
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
{
*dest++ = *src++;
}
showprogress('C');
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('D');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
stm32l5_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
stm32l5_board_initialize();
showprogress('F');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
#ifdef CONFIG_STACK_COLORATION
/* Set the IDLE stack to the coloration value and jump into nx_start() */
go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
#else
/* Call nx_start() */
nx_start();
/* Shoulnd't get here */
for (; ; );
#endif
}

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