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SAMA5: LCDC driver incorporated into the build system.

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This commit is contained in:
Gregory Nutt
2013-10-08 15:30:38 -06:00
parent 3ccbb7a07f
commit f3a4fc42d7
5 changed files with 877 additions and 272 deletions
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arch/arm/src/sama5/Kconfig
+483
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arch/arm/src/sama5/Make.defs
+4
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@@ -119,6 +119,10 @@ else
endif
endif
ifeq ($(CONFIG_SAMA5_LCDC),y)
CHIP_CSRCS += sam_lcd.c
endif
ifeq ($(CONFIG_SAMA5_UHPHS),y)
ifeq ($(CONFIG_SAMA5_OHCI),y)
CHIP_CSRCS += sam_ohci.c
arch/arm/src/sama5/chip/sam_lcdc.h
+3 -3
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@@ -540,7 +540,7 @@
# define LCDC_LCDCFG6_PWMPS_DIV8 (3 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/8 */
# define LCDC_LCDCFG6_PWMPS_DIV (4 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/16 */
# define LCDC_LCDCFG6_PWMPS_DIV32 (5 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/32 */
# define LCDC_LCDCFG6_PWMPS _DIV64 (6 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/64 */
# define LCDC_LCDCFG6_PWMPS_DIV64 (6 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/64 */
#define LCDC_LCDCFG6_PWMPOL (1 << 4) /* Bit 4: LCD Controller PWM Signal Polarity */
#define LCDC_LCDCFG6_PWMCVAL_SHIFT (8) /* Bits 8-15: LCD Controller PWM Compare Value */
#define LCDC_LCDCFG6_PWMCVAL_MASK (0xff << LCDC_LCDCFG6_PWMCVAL_SHIFT)
@@ -686,7 +686,7 @@
#define LCDC_BASECFG4_DMA (1 << 8) /* Bit 8: Use DMA Data Path */
#define LCDC_BASECFG4_REP (1 << 9) /* Bit 9: Use Replication logic to expand RGB */
#define LCDC_BASECFG4_DISCEN (1 << 11) /* Bit 11: Discard Area Enable
#define LCDC_BASECFG4_DISCEN (1 << 11) /* Bit 11: Discard Area Enable */
/* Base Configuration register 5 */
@@ -1568,7 +1568,7 @@
#define LCDC_HCRCHSR_A2Q (1 << 2) /* Bit 2: Add To Queue Pending */
/* Hardware Cursor Interrupt Enable Register, Hardware Cursor Interrupt Disable Register,
/* Hardware Cursor Interrupt Mask Register, and Hardware Cursor Interrupt Status Register
* Hardware Cursor Interrupt Mask Register, and Hardware Cursor Interrupt Status Register
*/
#define LCDC_HCRINT_DMA (1 << 2) /* Bit 2: End of DMA Transfer */
arch/arm/src/sama5/sam_lcd.c
+387 -170
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arch/arm/src/sama5/sam_lcd.h
-99
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@@ -51,105 +51,6 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration */
/* Base address of the video RAM frame buffer */
#ifndef CONFIG_SAM_LCD_VRAMBASE
# define CONFIG_SAM_LCD_VRAMBASE ((uint32_t)SAM_EXTDRAM_CS0 + 0x00010000)
#endif
/* LCD refresh rate */
#ifndef CONFIG_SAM_LCD_REFRESH_FREQ
# define CONFIG_SAM_LCD_REFRESH_FREQ (50) /* Hz */
#endif
/* Bits per pixel / color format */
#undef SAM_COLOR_FMT
#if defined(CONFIG_SAM_LCD_BPP1)
# define SAM_BPP 1
# define SAM_COLOR_FMT FB_FMT_Y1
#elif defined(CONFIG_SAM_LCD_BPP2)
# define SAM_BPP 2
# define SAM_COLOR_FMT FB_FMT_Y2
#elif defined(CONFIG_SAM_LCD_BPP4)
# define SAM_BPP 4
# define SAM_COLOR_FMT FB_FMT_Y4
#elif defined(CONFIG_SAM_LCD_BPP8)
# define SAM_BPP 8
# define SAM_COLOR_FMT FB_FMT_Y8
#elif defined(CONFIG_SAM_LCD_BPP16)
# define SAM_BPP 16
# define SAM_COLOR_FMT FB_FMT_Y16
#elif defined(CONFIG_SAM_LCD_BPP24)
# define SAM_BPP 32 /* Only 24 of 32 bits used for RGB */
# define SAM_COLOR_FMT FB_FMT_RGB24
# ifndef CONFIG_SAM_LCD_TFTPANEL
# error "24 BPP is only available for a TFT panel"
# endif
#elif defined(CONFIG_SAM_LCD_BPP16_565)
# define SAM_BPP 16
# define SAM_COLOR_FMT FB_FMT_RGB16_565
#elif defined(CONFIG_SAM_LCD_BPP12_444)
# define SAM_BPP 1 2
# define SAM_COLOR_FMT FB_FMT_RGB12_444
#else
# ifndef CONFIG_SAM_LCD_TFTPANEL
# warning "Assuming 24 BPP"
# define SAM_BPP 24
# define CONFIG_SAM_LCD_BPP24 1
# define SAM_COLOR_FMT FB_FMT_RGB24
# else
# warning "Assuming 16 BPP 5:6:5"
# define SAM_BPP 16
# define CONFIG_SAM_LCD_BPP16_565 1
# define SAM_COLOR_FMT FB_FMT_RGB16_565
# endif
#endif
/* Background color */
#ifndef CONFIG_SAM_LCD_BACKCOLOR
# define CONFIG_SAM_LCD_BACKCOLOR 0 /* Initial background color */
#endif
/* Horizontal video characteristics */
#ifndef CONFIG_SAM_LCD_HWIDTH
# define CONFIG_SAM_LCD_HWIDTH 480 /* Width in pixels */
#endif
#ifndef CONFIG_SAM_LCD_HPULSE
# define CONFIG_SAM_LCD_HPULSE 2
#endif
#ifndef CONFIG_SAM_LCD_HFRONTPORCH
# define CONFIG_SAM_LCD_HFRONTPORCH 5
#endif
#ifndef CONFIG_SAM_LCD_HBACKPORCH
# define CONFIG_SAM_LCD_HBACKPORCH 40
#endif
/* Vertical video characteristics */
#ifndef CONFIG_SAM_LCD_VHEIGHT
# define CONFIG_SAM_LCD_VHEIGHT 272 /* Height in rows */
#endif
#ifndef CONFIG_SAM_LCD_VPULSE
# define CONFIG_SAM_LCD_VPULSE 2
#endif
#ifndef CONFIG_SAM_LCD_VFRONTPORCH
# define CONFIG_SAM_LCD_VFRONTPORCH 8
#endif
#ifndef CONFIG_SAM_LCD_VBACKPORCH
# define CONFIG_SAM_LCD_VBACKPORCH 8
#endif
/************************************************************************************
* Public Types