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include/nuttx/usb/max3421e.h: Update MAX3421E header file.

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This commit is contained in:
Gregory Nutt
2018-07-01 16:03:59 -06:00
parent 83d6c9b1b9
commit f3229cc00a
1 changed files with 133 additions and 133 deletions
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include/nuttx/usb/max3421e.h
+133 -133
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@@ -59,32 +59,29 @@
* Bit 0: ACKSTAT
*/
#define MAX3421E_USBHOST_EP0FIFO (0 << 3)
#define MAX3421E_USBHOST_EP1OUTFIFO (1 << 3)
#define MAX3421E_USBHOST_EP2INFIFO (2 << 3)
#define MAX3421E_USBHOST_EP3INFIFO (3 << 3)
#define MAX3421E_USBHOST_RCVFIFO (1 << 3)
#define MAX3421E_USBHOST_SNDFIFO (2 << 3)
#define MAX3421E_USBHOST_SUDFIFO (4 << 3)
#define MAX3421E_USBHOST_EP0BC (5 << 3)
#define MAX3421E_USBHOST_EP1OUTBC (6 << 3)
#define MAX3421E_USBHOST_EP2INBC (7 << 3)
#define MAX3421E_USBHOST_EP3INBC (8 << 3)
#define MAX3421E_USBHOST_EPSTALLS (9 << 3)
#define MAX3421E_USBHOST_CLRTOGS (10 << 3)
#define MAX3421E_USBHOST_EPIRQ (11 << 3)
#define MAX3421E_USBHOST_EPIEN (12 << 3)
#define MAX3421E_USBHOST_RCVBC (6 << 3)
#define MAX3421E_USBHOST_SNDBC (7 << 3)
#define MAX3421E_USBHOST_USBIRQ (13 << 3)
#define MAX3421E_USBHOST_USBIEN (14 << 3)
#define MAX3421E_USBHOST_USBCTL (15 << 3)
#define MAX3421E_USBHOST_CPUCTL (16 << 3)
#define MAX3421E_USBHOST_PINCTL (17 << 3)
#define MAX3421E_USBHOST_REVISION (18 << 3)
#define MAX3421E_USBHOST_FNADDR (19 << 3)
#define MAX3421E_USBHOST_IOPINS1 (20 << 3)
#define MAX3421E_USBHOST_IOPINS2 (21 << 3)
#define MAX3421E_USBHOST_GPINIRQ (22 << 3)
#define MAX3421E_USBHOST_GPINIEN (23 << 3)
#define MAX3421E_USBHOST_GPINPOL (24 << 3)
#define MAX3421E_USBHOST_HIRQ (25 << 3)
#define MAX3421E_USBHOST_HIEN (26 << 3)
#define MAX3421E_USBHOST_MODE (27 << 3)
#define MAX3421E_USBHOST_PERADDR (28 << 3)
#define MAX3421E_USBHOST_HCTL (29 << 3)
#define MAX3421E_USBHOST_HXFR (30 << 3)
#define MAX3421E_USBHOST_HRSL (31 << 3)
/* Peripheral Mode Register Addresses ***************************************/
/* The command byte contains the register address, a direction bit, and an
@@ -96,90 +93,48 @@
* Bit 0: ACKSTAT
*/
#define MAX3421E_USBDEV_RCVFIFO (1 << 3)
#define MAX3421E_USBDEV_SNDFIFO (2 << 3)
#define MAX3421E_USBDEV_EP0FIFO (0 << 3)
#define MAX3421E_USBDEV_EP1OUTFIFO (1 << 3)
#define MAX3421E_USBDEV_EP2INFIFO (2 << 3)
#define MAX3421E_USBDEV_EP3INFIFO (3 << 3)
#define MAX3421E_USBDEV_SUDFIFO (4 << 3)
#define MAX3421E_USBDEV_RCVBC (6 << 3)
#define MAX3421E_USBDEV_SNDBC (7 << 3)
#define MAX3421E_USBDEV_EP0BC (5 << 3)
#define MAX3421E_USBDEV_EP1OUTBC (6 << 3)
#define MAX3421E_USBDEV_EP2INBC (7 << 3)
#define MAX3421E_USBDEV_EP3INBC (8 << 3)
#define MAX3421E_USBDEV_EPSTALLS (9 << 3)
#define MAX3421E_USBDEV_CLRTOGS (10 << 3)
#define MAX3421E_USBDEV_EPIRQ (11 << 3)
#define MAX3421E_USBDEV_EPIEN (12 << 3)
#define MAX3421E_USBDEV_USBIRQ (13 << 3)
#define MAX3421E_USBDEV_USBIEN (14 << 3)
#define MAX3421E_USBDEV_USBCTL (15 << 3)
#define MAX3421E_USBDEV_CPUCTL (16 << 3)
#define MAX3421E_USBDEV_PINCTL (17 << 3)
#define MAX3421E_USBDEV_REVISION (18 << 3)
#define MAX3421E_USBDEV_FNADDR (19 << 3)
#define MAX3421E_USBDEV_IOPINS1 (20 << 3)
#define MAX3421E_USBDEV_IOPINS2 (21 << 3)
#define MAX3421E_USBDEV_GPINIRQ (22 << 3)
#define MAX3421E_USBDEV_GPINIEN (23 << 3)
#define MAX3421E_USBDEV_GPINPOL (24 << 3)
#define MAX3421E_USBDEV_HIRQ (25 << 3)
#define MAX3421E_USBDEV_HIEN (26 << 3)
#define MAX3421E_USBDEV_MODE (27 << 3)
#define MAX3421E_USBDEV_PERADDR (28 << 3)
#define MAX3421E_USBDEV_HCTL (29 << 3)
#define MAX3421E_USBDEV_HXFR (30 << 3)
#define MAX3421E_USBDEV_HRSL (31 << 3)
/* Host Mode Register Bit-Field Definitions *********************************/
#define USBHOST_EP0BC_MASK 0x7f
#define USBHOST_EP1OUTBC_MASK 0x7f
#define USBHOST_EP2INBC_MASK 0x7f
#define USBHOST_EP3INBC_MASK 0x7f
#define USBHOST_EPSTALLS_STLEP0IN (1 << 0)
#define USBHOST_EPSTALLS_STLEP0OUT (1 << 1)
#define USBHOST_EPSTALLS_STLEP1OUT (1 << 2)
#define USBHOST_EPSTALLS_STLEP2IN (1 << 3)
#define USBHOST_EPSTALLS_STLEP3IN (1 << 4)
#define USBHOST_EPSTALLS_STLSTAT (1 << 5)
#define USBHOST_EPSTALLS_ACKSTAT (1 << 6)
#define USBHOST_CLRTOGS_CTGEP1OUT (1 << 2)
#define USBHOST_CLRTOGS_CTGEP2IN (1 << 3)
#define USBHOST_CLRTOGS_CTGEP3IN (1 << 4)
#define USBHOST_CLRTOGS_EP1DISAB (1 << 5)
#define USBHOST_CLRTOGS_EP2DISAB (1 << 6)
#define USBHOST_CLRTOGS_EP3DISAB (1 << 7)
#define USBHOST_EPIRQ_IN0BAVIRQ (1 << 0)
#define USBHOST_EPIRQ_OUT0DAVIRQ (1 << 1)
#define USBHOST_EPIRQ_OUT1DAVIRQ (1 << 2)
#define USBHOST_EPIRQ_IN2BAVIRQ (1 << 3)
#define USBHOST_EPIRQ_IN3BAVIRQ (1 << 4)
#define USBHOST_EPIRQ_SUDAVIRQ (1 << 5)
#define USBHOST_EPIEN_IN0BAVIE (1 << 0)
#define USBHOST_EPIEN_OUT0DAVIE (1 << 1)
#define USBHOST_EPIEN_OUT1DAVIE (1 << 2)
#define USBHOST_EPIEN_IN2BAVIE (1 << 3)
#define USBHOST_EPIEN_IN3BAVIE (1 << 4)
#define USBHOST_EPIEN_SUDAVIE (1 << 5)
#define USBHOST_RCVBC_MASK 0x7f
#define USBHOST_SNDBC_MASK 0x7f
#define USBHOST_USBIRQ_OSCOKIRQ (1 << 0)
#define USBHOST_USBIRQ_RWUDNIRQ (1 << 1)
#define USBHOST_USBIRQ_BUSACTIRQ (1 << 2)
#define USBHOST_USBIRQ_URESIRQ (1 << 3)
#define USBHOST_USBIRQ_SUSPIRQ (1 << 4)
#define USBHOST_USBIRQ_NOVBUSIRQ (1 << 5)
#define USBHOST_USBIRQ_VBUSIRQ (1 << 6)
#define USBHOST_USBIRQ_URESDNIRQ (1 << 7)
#define USBHOST_USBIEN_OSCOKIE (1 << 0)
#define USBHOST_USBIEN_RWUDNIE (1 << 1)
#define USBHOST_USBIEN_BUSACTIE (1 << 2)
#define USBHOST_USBIEN_URESIE (1 << 3)
#define USBHOST_USBIEN_SUSPIE (1 << 4)
#define USBHOST_USBIEN_NOVBUSIE (1 << 5)
#define USBHOST_USBIEN_VBUSIEN (1 << 6)
#define USBHOST_USBIEN_URESDNIE (1 << 7)
#define USBHOST_USBCTL_SIGRWU (1 << 2)
#define USBHOST_USBCTL_CONNECT (1 << 3)
#define USBHOST_USBCTL_PWRDOWN (1 << 4)
#define USBHOST_USBCTL_CHIPRES (1 << 5)
#define USBHOST_USBCTL_VBGATE (1 << 6)
#define USBHOST_USBCTL_HOSCSTEN (1 << 7)
#define USBHOST_CPUCTL_IE (1 << 0)
#define USBHOST_CPUCTL_PULSEWID0 (1 << 6)
@@ -195,7 +150,6 @@
#define USBHOST_PINCTL_EP3INAK (1 << 7)
#define USBHOST_REVISION 0x13
#define USBHOST_FNADDR_MASK 0x7f
#define USBHOST_IOPINS1_GPOUT(n) (1 << (n))
#define USBHOST_IOPINS1_GPIN(n) (1 << ((n) + 4))
@@ -205,24 +159,122 @@
#define USBHOST_GPINIEN(n) (1 << (n))
#define USBHOST_GPINPOL(n) (1 << (n))
#define USBHOST_MODE_SEPIRQ (1 << 4)
#define USBHOST_HIRQ_BUSEVENTIRQ (1 << 0)
#define USBHOST_HIRQ_RSMREQIRQ (1 << 1)
#define USBHOST_HIRQ_RCVDAVIRQ (1 << 2)
#define USBHOST_HIRQ_SNDBAVIRQ (1 << 3)
#define USBHOST_HIRQ_SUSDNIRQ (1 << 4)
#define USBHOST_HIRQ_CONNIRQ (1 << 5)
#define USBHOST_HIRQ_FRAMEIRQ (1 << 6)
#define USBHOST_HIRQ_HXFRDNIRQ (1 << 7)
#define USBHOST_HIEN_BUSEVENTIE (1 << 0)
#define USBHOST_HIEN_RSMREQIE (1 << 1)
#define USBHOST_HIEN_RCVDAVIE (1 << 2)
#define USBHOST_HIEN_SNDBAVIE (1 << 3)
#define USBHOST_HIEN_SUSDNIE (1 << 4)
#define USBHOST_HIEN_CONNIE (1 << 5)
#define USBHOST_HIEN_FRAMEIE (1 << 6)
#define USBHOST_HIEN_HXFRDNIE (1 << 7)
#define USBHOST_MODE_HOST (1 << 0)
#define USBHOST_MODE_SPEED (1 << 1)
#define USBHOST_MODE_HUBPRE (1 << 2)
#define USBHOST_MODE_SOFKAENAB (1 << 3)
#define USBHOST_MODE_SEPIRQ (1 << 4)
#define USBHOST_MODE_NDELAYISO (1 << 5)
#define USBHOST_MODE_DMPULLD (1 << 6)
#define USBHOST_MODE_DPPULLDN (1 << 7)
#define USBHOST_PERADDR_MASK 0x7f
#define USBHOST_HCTL_BUSRST (1 << 0)
#define USBHOST_HCTL_FRMRST (1 << 1)
#define USBHOST_HCTL_BUSSAMPLE (1 << 2)
#define USBHOST_HCTL_SIGRSM (1 << 3)
#define USBHOST_HCTL_RCVTOG0 (1 << 4)
#define USBHOST_HCTL_RCVTOG1 (1 << 5)
#define USBHOST_HCTL_SNDTOG0 (1 << 6)
#define USBHOST_HCTL_SNDTOG1 (1 << 7)
#define USBHOST_HXFR_EP0 (1 << 0)
#define USBHOST_HXFR_EP1 (1 << 1)
#define USBHOST_HXFR_EP2 (1 << 2)
#define USBHOST_HXFR_EP3 (1 << 3)
#define USBHOST_HXFR_SETUP (1 << 4)
#define USBHOST_HXFR_OUTNIN (1 << 5)
#define USBHOST_HXFR_ISO (1 << 6)
#define USBHOST_HXFR_HS (1 << 7)
#define USBHOST_HRSL_HRSLT0 (1 << 0)
#define USBHOST_HRSL_HRSLT1 (1 << 1)
#define USBHOST_HRSL_HRSLT2 (1 << 2)
#define USBHOST_HRSL_HRSLT3 (1 << 3)
#define USBHOST_HRSL_RCVTOGRD (1 << 4)
#define USBHOST_HRSL_SNDTOGRD (1 << 5)
#define USBHOST_HRSL_KSTATUS (1 << 6)
#define USBHOST_HRSL_JSTATUS (1 << 7)
/* Peripheral Mode Register Bit-Field Definitions ***************************/
#define USBDEV_RCVBC_MASK 0x7f
#define USBDEV_SNDBC_MASK 0x7f
#define USBDEV_EP0BC_MASK 0x7f
#define USBDEV_EP1OUTBC_MASK 0x7f
#define USBDEV_EP2INBC_MASK 0x7f
#define USBDEV_EP3INBC_MASK 0x7f
#define USBDEV_EPSTALLS_STLEP0IN (1 << 0)
#define USBDEV_EPSTALLS_STLEP0OUT (1 << 1)
#define USBDEV_EPSTALLS_STLEP1OUT (1 << 2)
#define USBDEV_EPSTALLS_STLEP2IN (1 << 3)
#define USBDEV_EPSTALLS_STLEP3IN (1 << 4)
#define USBDEV_EPSTALLS_STLSTAT (1 << 5)
#define USBDEV_EPSTALLS_ACKSTAT (1 << 6)
#define USBDEV_CLRTOGS_CTGEP1OUT (1 << 2)
#define USBDEV_CLRTOGS_CTGEP2IN (1 << 3)
#define USBDEV_CLRTOGS_CTGEP3IN (1 << 4)
#define USBDEV_CLRTOGS_EP1DISAB (1 << 5)
#define USBDEV_CLRTOGS_EP2DISAB (1 << 6)
#define USBDEV_CLRTOGS_EP3DISAB (1 << 7)
#define USBDEV_EPIRQ_IN0BAVIRQ (1 << 0)
#define USBDEV_EPIRQ_OUT0DAVIRQ (1 << 1)
#define USBDEV_EPIRQ_OUT1DAVIRQ (1 << 2)
#define USBDEV_EPIRQ_IN2BAVIRQ (1 << 3)
#define USBDEV_EPIRQ_IN3BAVIRQ (1 << 4)
#define USBDEV_EPIRQ_SUDAVIRQ (1 << 5)
#define USBDEV_EPIEN_IN0BAVIE (1 << 0)
#define USBDEV_EPIEN_OUT0DAVIE (1 << 1)
#define USBDEV_EPIEN_OUT1DAVIE (1 << 2)
#define USBDEV_EPIEN_IN2BAVIE (1 << 3)
#define USBDEV_EPIEN_IN3BAVIE (1 << 4)
#define USBDEV_EPIEN_SUDAVIE (1 << 5)
#define USBDEV_USBIRQ_OSCOKIRQ (1 << 0)
#define USBDEV_USBIRQ_RWUDNIRQ (1 << 1)
#define USBDEV_USBIRQ_BUSACTIRQ (1 << 2)
#define USBDEV_USBIRQ_URESIRQ (1 << 3)
#define USBDEV_USBIRQ_SUSPIRQ (1 << 4)
#define USBDEV_USBIRQ_NOVBUSIRQ (1 << 5)
#define USBDEV_USBIRQ_VBUSIRQ (1 << 6)
#define USBDEV_USBIRQ_URESDNIRQ (1 << 7)
#define USBDEV_USBIEN_OSCOKIE (1 << 0)
#define USBDEV_USBIEN_RWUDNIE (1 << 1)
#define USBDEV_USBIEN_BUSACTIE (1 << 2)
#define USBDEV_USBIEN_URESIE (1 << 3)
#define USBDEV_USBIEN_SUSPIE (1 << 4)
#define USBDEV_USBIEN_NOVBUSIE (1 << 5)
#define USBDEV_USBIEN_VBUSIEN (1 << 6)
#define USBDEV_USBIEN_URESDNIE (1 << 7)
#define USBDEV_USBCTL_SIGRWU (1 << 2)
#define USBDEV_USBCTL_CONNECT (1 << 3)
#define USBDEV_USBCTL_PWRDOWN (1 << 4)
#define USBDEV_USBCTL_CHIPRES (1 << 5)
#define USBDEV_USBCTL_VBGATE (1 << 6)
#define USBDEV_USBCTL_HOSCSTEN (1 << 7)
#define USBDEV_CPUCTL_IE (1 << 0)
#define USBDEV_CPUCTL_PULSEWID0 (1 << 6)
@@ -238,6 +290,7 @@
#define USBDEV_PINCTL_EP3INAK (1 << 7)
#define USBDEV_REVISION 0x13
#define USBDEV_FNADDR_MASK 0x7f
#define USBDEV_IOPINS1_GPOUT(n) (1 << (n))
#define USBDEV_IOPINS1_GPIN(n) (1 << ((n) + 4))
@@ -247,61 +300,8 @@
#define USBDEV_GPINIEN(n) (1 << (n))
#define USBDEV_GPINPOL(n) (1 << (n))
#define USBDEV_HIRQ_BUSEVENTIRQ (1 << 0)
#define USBDEV_HIRQ_RSMREQIRQ (1 << 1)
#define USBDEV_HIRQ_RCVDAVIRQ (1 << 2)
#define USBDEV_HIRQ_SNDBAVIRQ (1 << 3)
#define USBDEV_HIRQ_SUSDNIRQ (1 << 4)
#define USBDEV_HIRQ_CONNIRQ (1 << 5)
#define USBDEV_HIRQ_FRAMEIRQ (1 << 6)
#define USBDEV_HIRQ_HXFRDNIRQ (1 << 7)
#define USBDEV_HIEN_BUSEVENTIE (1 << 0)
#define USBDEV_HIEN_RSMREQIE (1 << 1)
#define USBDEV_HIEN_RCVDAVIE (1 << 2)
#define USBDEV_HIEN_SNDBAVIE (1 << 3)
#define USBDEV_HIEN_SUSDNIE (1 << 4)
#define USBDEV_HIEN_CONNIE (1 << 5)
#define USBDEV_HIEN_FRAMEIE (1 << 6)
#define USBDEV_HIEN_HXFRDNIE (1 << 7)
#define USBDEV_MODE_HOST (1 << 0)
#define USBDEV_MODE_SPEED (1 << 1)
#define USBDEV_MODE_HUBPRE (1 << 2)
#define USBDEV_MODE_SOFKAENAB (1 << 3)
#define USBDEV_MODE_SEPIRQ (1 << 4)
#define USBDEV_MODE_NDELAYISO (1 << 5)
#define USBDEV_MODE_DMPULLD (1 << 6)
#define USBDEV_MODE_DPPULLDN (1 << 7)
#define USBDEV_PERADDR_MASK 0x7f
#define USBDEV_HCTL_BUSRST (1 << 0)
#define USBDEV_HCTL_FRMRST (1 << 1)
#define USBDEV_HCTL_BUSSAMPLE (1 << 2)
#define USBDEV_HCTL_SIGRSM (1 << 3)
#define USBDEV_HCTL_RCVTOG0 (1 << 4)
#define USBDEV_HCTL_RCVTOG1 (1 << 5)
#define USBDEV_HCTL_SNDTOG0 (1 << 6)
#define USBDEV_HCTL_SNDTOG1 (1 << 7)
#define USBDEV_HXFR_EP0 (1 << 0)
#define USBDEV_HXFR_EP1 (1 << 1)
#define USBDEV_HXFR_EP2 (1 << 2)
#define USBDEV_HXFR_EP3 (1 << 3)
#define USBDEV_HXFR_SETUP (1 << 4)
#define USBDEV_HXFR_OUTNIN (1 << 5)
#define USBDEV_HXFR_ISO (1 << 6)
#define USBDEV_HXFR_HS (1 << 7)
#define USBDEV_HRSL_HRSLT0 (1 << 0)
#define USBDEV_HRSL_HRSLT1 (1 << 1)
#define USBDEV_HRSL_HRSLT2 (1 << 2)
#define USBDEV_HRSL_HRSLT3 (1 << 3)
#define USBDEV_HRSL_RCVTOGRD (1 << 4)
#define USBDEV_HRSL_SNDTOGRD (1 << 5)
#define USBDEV_HRSL_KSTATUS (1 << 6)
#define USBDEV_HRSL_JSTATUS (1 << 7)
#define USBDEV_MODE_HOST (1 << 0)
/* Misc. Definitions ********************************************************/
@@ -357,7 +357,7 @@
enum spi_mode_e; /* Forward reference */
struct spi_dev_s; /* Forward reference */
struct m3421e_lowerhalf_s
struct max3421e_lowerhalf_s
{
/* Device characterization */
@@ -375,11 +375,11 @@ struct m3421e_lowerhalf_s
* acknowledge - Acknowledge/clear any pending GPIO interrupt
*/
CODE int (*attach)(FAR struct m3421e_lowerhalf_s *lower, xcpt_t isr,
CODE int (*attach)(FAR struct max3421e_lowerhalf_s *lower, xcpt_t isr,
FAR void *arg);
CODE void (*enable)(FAR const struct m3421e_lowerhalf_s *lower,
CODE void (*enable)(FAR const struct max3421e_lowerhalf_s *lower,
bool enable);
CODE void (*acknowledge)(FAR const struct m3421e_lowerhalf_s *lower);
CODE void (*acknowledge)(FAR const struct max3421e_lowerhalf_s *lower);
/* Additional, driver-specific state data may follow */
};
@@ -426,7 +426,7 @@ struct usbhost_connection_s; /* Forward reference */
****************************************************************************/
FAR struct usbhost_connection_s *
max3421e_usbhost_initialize(FAR const struct m3421e_lowerhalf_s *lower);
max3421e_usbhost_initialize(FAR const struct max3421e_lowerhalf_s *lower);
#undef EXTERN
#ifdef __cplusplus