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Merge branch 'master' into stm32l4_pinouts

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This commit is contained in:
Sebastien Lorquet
2016-10-26 13:31:54 +02:00
parent 68dae715b0 b8462d3e04
commit f24701f5c7
42 changed files with 6154 additions and 375 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/stm32/chip.h
+2 -2
View File
@@ -1101,7 +1101,6 @@
* c = C (48pins) R (68 pins) V (100 pins)
* c = K (32 pins), C (48 pins), R (68 pins), V (100 pins)
* f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
* f = 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
* xxx = Package, temperature range, options (ignored here)
*/
@@ -1534,7 +1533,8 @@
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
# define STM32_NADC 1 /* (3) 12-bit ADC1 */
# define STM32_NADC 1 /* (1) 12-bit ADC1 */
# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
arch/arm/src/stm32/Kconfig
+84
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@@ -1394,6 +1394,9 @@ config STM32_STM32F37XX
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
select STM32_HAVE_SDADC1
select STM32_HAVE_SDADC2
select STM32_HAVE_SDADC3
select STM32_HAVE_CAN1
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
@@ -1777,6 +1780,30 @@ config STM32_HAVE_ADC4_DMA
bool
default n
config STM32_HAVE_SDADC1
bool
default n
config STM32_HAVE_SDADC2
bool
default n
config STM32_HAVE_SDADC3
bool
default n
config STM32_HAVE_SDADC1_DMA
bool
default n
config STM32_HAVE_SDADC2_DMA
bool
default n
config STM32_HAVE_SDADC3_DMA
bool
default n
config STM32_HAVE_CAN1
bool
default n
@@ -1844,6 +1871,7 @@ config STM32_ADC1
default n
select STM32_ADC
select STM32_HAVE_ADC1_DMA if STM32_STM32F10XX && STM32_DMA1
select STM32_HAVE_ADC1_DMA if STM32_STM32F37XX && STM32_DMA1
select STM32_HAVE_ADC1_DMA if !STM32_STM32F10XX && STM32_DMA2
config STM32_ADC2
@@ -1867,6 +1895,27 @@ config STM32_ADC4
depends on STM32_HAVE_ADC4
select STM32_HAVE_ADC4_DMA if STM32_DMA2
config STM32_SDADC1
bool "SDADC1"
default n
select STM32_SDADC
depends on STM32_HAVE_SDADC1
select STM32_HAVE_SDADC1_DMA if STM32_DMA2
config STM32_SDADC2
bool "SDADC2"
default n
select STM32_SDADC
depends on STM32_HAVE_SDADC2
select STM32_HAVE_SDADC2_DMA if STM32_DMA2
config STM32_SDADC3
bool "SDADC3"
default n
select STM32_SDADC
depends on STM32_HAVE_SDADC3
select STM32_HAVE_SDADC3_DMA if STM32_DMA2
config STM32_COMP
bool "COMP"
default n
@@ -2239,6 +2288,9 @@ endmenu
config STM32_ADC
bool
config STM32_SDADC
bool
config STM32_DAC
bool
@@ -5403,6 +5455,38 @@ config STM32_ADC4_DMA
endmenu
menu "SDADC Configuration"
depends on STM32_SDADC
config STM32_SDADC1_DMA
bool "SDADC1 DMA"
depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA
default n
---help---
If DMA is selected, then the SDADC may be configured to support
DMA transfer, which is advisable if multiple channels are read
or if very high trigger frequencies are used.
config STM32_SDADC2_DMA
bool "SDADC2 DMA"
depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA
default n
---help---
If DMA is selected, then the SDADC may be configured to support
DMA transfer, which is advisable if multiple channels are read
or if very high trigger frequencies are used.
config STM32_SDADC3_DMA
bool "SDADC3 DMA"
depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA
default n
---help---
If DMA is selected, then the SDADC may be configured to support
DMA transfer, which is advisable if multiple channels are read
or if very high trigger frequencies are used.
endmenu
menu "DAC Configuration"
depends on STM32_DAC1 || STM32_DAC2
arch/arm/src/stm32/Make.defs
+6
View File
@@ -148,6 +148,8 @@ ifeq ($(CONFIG_STM32_I2C_ALT),y)
CHIP_CSRCS += stm32_i2c_alt.c
else ifeq ($(CONFIG_STM32_STM32F30XX),y)
CHIP_CSRCS += stm32f30xxx_i2c.c
else ifeq ($(CONFIG_STM32_STM32F37XX),y)
CHIP_CSRCS += stm32f30xxx_i2c.c
else ifeq ($(CONFIG_STM32_STM32F40XX),y)
CHIP_CSRCS += stm32f40xxx_i2c.c
else
@@ -217,6 +219,10 @@ ifeq ($(CONFIG_STM32_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32_SDADC),y)
CHIP_CSRCS += stm32_sdadc.c
endif
ifeq ($(CONFIG_DAC),y)
CHIP_CSRCS += stm32_dac.c
endif
arch/arm/src/stm32/chip/stm32_dac.h
+50 -14
View File
@@ -66,20 +66,56 @@
/* Register Addresses ***************************************************************/
#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET)
#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET)
#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET)
#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET)
#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET)
#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET)
#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET)
#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET)
#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET)
#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET)
#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET)
#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET)
#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET)
#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET)
#if STM32_NDAC < 2
# define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET)
# define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET)
# define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET)
# define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET)
# define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET)
# define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET)
# define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET)
# define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET)
# define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET)
# define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET)
# define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET)
# define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET)
# define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET)
# define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET)
#else
/* DAC1 */
# define STM32_DAC1_CR (STM32_DAC1_BASE+STM32_DAC_CR_OFFSET)
# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE+STM32_DAC_SWTRIGR_OFFSET)
# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE+STM32_DAC_DHR12R1_OFFSET)
# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE+STM32_DAC_DHR12L1_OFFSET)
# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE+STM32_DAC_DHR8R1_OFFSET)
# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE+STM32_DAC_DHR12R2_OFFSET)
# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE+STM32_DAC_DHR12L2_OFFSET)
# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE+STM32_DAC_DHR8R2_OFFSET)
# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE+STM32_DAC_DHR12RD_OFFSET)
# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE+STM32_DAC_DHR12LD_OFFSET)
# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE+STM32_DAC_DHR8RD_OFFSET)
# define STM32_DAC1_DOR1 (STM32_DAC1_BASE+STM32_DAC_DOR1_OFFSET)
# define STM32_DAC1_DOR2 (STM32_DAC1_BASE+STM32_DAC_DOR2_OFFSET)
# define STM32_DAC1_SR (STM32_DAC1_BASE+STM32_DAC_SR_OFFSET)
/* DAC2 */
# define STM32_DAC2_CR (STM32_DAC2_BASE+STM32_DAC_CR_OFFSET)
# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE+STM32_DAC_SWTRIGR_OFFSET)
# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE+STM32_DAC_DHR12R1_OFFSET)
# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE+STM32_DAC_DHR12L1_OFFSET)
# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE+STM32_DAC_DHR8R1_OFFSET)
# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE+STM32_DAC_DHR12R2_OFFSET)
# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE+STM32_DAC_DHR12L2_OFFSET)
# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE+STM32_DAC_DHR8R2_OFFSET)
# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE+STM32_DAC_DHR12RD_OFFSET)
# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE+STM32_DAC_DHR12LD_OFFSET)
# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE+STM32_DAC_DHR8RD_OFFSET)
# define STM32_DAC2_DOR1 (STM32_DAC2_BASE+STM32_DAC_DOR1_OFFSET)
# define STM32_DAC2_DOR2 (STM32_DAC2_BASE+STM32_DAC_DOR2_OFFSET)
# define STM32_DAC2_SR (STM32_DAC2_BASE+STM32_DAC_SR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
arch/arm/src/stm32/chip/stm32_pwr.h
+9 -2
View File
@@ -105,6 +105,12 @@
# endif
#endif
#if defined(CONFIG_STM32_STM32F37XX)
#define PWR_CR_ENSD1 (1 << 9) /* Bit 9: Enable SDADC1 */
#define PWR_CR_ENSD2 (1 << 10) /* Bit 10: Enable SDADC2 */
#define PWR_CR_ENSD3 (1 << 11) /* Bit 11: Enable SDADC3 */
#endif
#if defined(CONFIG_STM32_STM32L15XX)
# define PWR_CR_ULP (1 << 9) /* Ultralow power mode */
# define PWR_CR_FWU (1 << 10) /* Fast wake-up */
@@ -132,7 +138,8 @@
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX)
# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */
#elif defined(CONFIG_STM32_STM32L15XX)
# define PWR_CSR_VREFINTRDYF (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
@@ -143,7 +150,7 @@
#if defined(CONFIG_STM32_STM32F30XX)
# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
#elif defined(CONFIG_STM32_STM32L15XX)
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F37XX)
# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
# define PWR_CSR_EWUP3 (1 << 10) /* Bit 8: Enable WKUP3 pin */
arch/arm/src/stm32/chip/stm32f30xxx_adc.h
+2 -2
View File
@@ -60,8 +60,8 @@
#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
#define STM32_ADC_TR2_OFFSET 0x0020 /* ADC watchdog threshold register 2 */
#define STM32_ADC_TR3_OFFSET 0x0020 /* ADC watchdog threshold register 3 */
#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */
#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */
#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */
#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */
#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */
arch/arm/src/stm32/chip/stm32f37xxx_adc.h
+321
View File
@@ -0,0 +1,321 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32f30xxx_adc.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Studelec SA. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Marc Rechté <mrechte@studelec-sa.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register */
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 */
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 */
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 */
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 */
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 */
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 */
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 */
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 */
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register */
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register */
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 */
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 */
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 */
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register */
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 */
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 2 */
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 3 */
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 4 */
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register */
/* Register Addresses *******************************************************************************/
#define STM32_ADC_SR (STM32_ADC_BASE+STM32_ADC_SR_OFFSET)
#define STM32_ADC_CR1 (STM32_ADC_BASE+STM32_ADC_CR1_OFFSET)
#define STM32_ADC_CR2 (STM32_ADC_BASE+STM32_ADC_CR2_OFFSET)
#define STM32_ADC_SMPR1 (STM32_ADC_BASE+STM32_ADC_SMPR1_OFFSET)
#define STM32_ADC_SMPR2 (STM32_ADC_BASE+STM32_ADC_SMPR2_OFFSET)
#define STM32_ADC_JOFR1 (STM32_ADC_BASE+STM32_ADC_JOFR1_OFFSET)
#define STM32_ADC_JOFR2 (STM32_ADC_BASE+STM32_ADC_JOFR2_OFFSET)
#define STM32_ADC_JOFR3 (STM32_ADC_BASE+STM32_ADC_JOFR3_OFFSET)
#define STM32_ADC_JOFR4 (STM32_ADC_BASE+STM32_ADC_JOFR4_OFFSET)
#define STM32_ADC_HTR (STM32_ADC_BASE+STM32_ADC_HTR_OFFSET)
#define STM32_ADC_LTR (STM32_ADC_BASE+STM32_ADC_LTR_OFFSET)
#define STM32_ADC_SQR1 (STM32_ADC_BASE+STM32_ADC_SQR1_OFFSET)
#define STM32_ADC_SQR2 (STM32_ADC_BASE+STM32_ADC_SQR2_OFFSET)
#define STM32_ADC_SQR3 (STM32_ADC_BASE+STM32_ADC_SQR3_OFFSET)
#define STM32_ADC_JSQR (STM32_ADC_BASE+STM32_ADC_JSQR_OFFSET)
#define STM32_ADC_JDR1 (STM32_ADC_BASE+STM32_ADC_JDR1_OFFSET)
#define STM32_ADC_JDR2 (STM32_ADC_BASE+STM32_ADC_JDR2_OFFSET)
#define STM32_ADC_JDR3 (STM32_ADC_BASE+STM32_ADC_JDR3_OFFSET)
#define STM32_ADC_JDR4 (STM32_ADC_BASE+STM32_ADC_JDR4_OFFSET)
#define STM32_ADC_DR (STM32_ADC_BASE+STM32_ADC_DR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* ADC status register (SR) */
#define ADC_SR_AWD (1 << 0) /* Bit 0: Analog wtchdog flag */
#define ADC_SR_EOC (1 << 1) /* Bit 1: End of conversion */
#define ADC_SR_JEOC (1 << 2) /* Bit 2: Injected channel end of conversion */
#define ADC_SR_JSTRT (1 << 3) /* Bit 3: Injected channel start flag */
#define ADC_SR_RSTRT (1 << 4) /* Bit 4: Regular channel start flag */
/* ADC control register 1 */
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 0-4: Analog watchdog channel select bits */
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable EOC */
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog watchdog interrupt enable */
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
#define ADC_CR1_DISNUM_SHIFT (13) /* Bit 13-15: Discontinuous mode channel count */
#define ADC_CR1_DISNUM_MASK (0x7 << ADC_CR1_DISNUM_SHIFT)
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
/* ADC control register 2 */
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D converter ON / OFF */
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous conversion */
#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset calibration */
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct memory access mode */
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data alignment */
#define ADC_CR2_JEXTSEL_SHIFT (12) /* Bit 12-14: External event select for injected group */
#define ADC_CR2_JEXTSEL_MASK (0x7 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_TIM19_CC1 (0 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_TIM19_CC2 (1 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_TIM2_TRGO (2 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_TIM2_CC1 (3 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_TIM3_CC4 (4 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_TIM4_TRGO (5 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT)
# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT)
#define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External trigger conversion mode for injected channels */
#define ADC_CR2_EXTSEL_SHIFT (17) /* Bit 17-19: External event select for regular group */
#define ADC_CR2_EXTSEL_MASK (0x7 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_TIM19_TRGO (0 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_TIM19_CC3 (1 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_TIM19_CC4 (2 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT)
# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT)
#define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External trigger conversion mode for regular channels */
#define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start conversion of injected channels */
#define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start conversion of regular channels */
#define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and V REFINT enable */
/* ADC sample time register 1 */
#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
#define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
#define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */
#define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */
#define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */
#define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */
#define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */
#define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
/* ADC sample time register 2 */
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
/* ADC injected channel data offset register 1, 2, 3, and 4 */
#define ADC_JOFR_OFFSETX_SHIFT (0) /* Bits 0-11: Data offset for injected channel x */
#define ADC_JOFR_OFFSETX_MASK (0x0fff << ADC_JOFR_OFFSETX_SHIFT)
/* ADC watchdog high threshold register */
#define ADC_HTR_HT_SHIFT (0) /* Bits 0-11: Analog watchdog high threshold */
#define ADC_HTR_HT_MASK (0xfff << ADC_HTR_HT_SHIFT)
/* ADC watchdog low threshold register */
#define ADC_LTR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog low threshold */
#define ADC_LTR_LT_MASK (0xfff << ADC_LTR_LT_SHIFT)
/* Offset between SQ bits */
#define ADC_SQ_OFFSET (5)
/* ADC regular sequence register 1 */
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 0-4: 13th conversion in regular sequence */
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 5-9: 14th conversion in regular sequence */
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 10-14: 15th conversion in regular sequence */
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 15-19: 16th conversion in regular sequence */
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
#define ADC_SQR1_L_SHIFT (20) /* Bits 20-23: Regular channel sequence length */
#define ADC_SQR1_L_MASK (0xf << ADC_SQR1_L_SHIFT)
#define ADC_SQR1_RESERVED (0xff000000)
#define ADC_SQR1_FIRST (13)
#define ADC_SQR1_LAST (16)
#define ADC_SQR1_SQ_OFFSET (0)
/* ADC regular sequence register 2 */
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 0-4: 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 5-9: 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 10-14: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 15-19: 10th conversion in regular sequence */
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
#define ADC_SQR2_SQ11_SHIFT (15) /* Bits 20-24: 11th conversion in regular sequence */
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT)
#define ADC_SQR2_SQ12_SHIFT (15) /* Bits 25-29: 12th conversion in regular sequence */
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
#define ADC_SQR2_RESERVED (0xc0000000)
#define ADC_SQR2_FIRST (7)
#define ADC_SQR2_LAST (12)
#define ADC_SQR2_SQ_OFFSET (0)
/* ADC regular sequence register 3 */
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in regular sequence */
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in regular sequence */
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in regular sequence */
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 15-19: 4th conversion in regular sequence */
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
#define ADC_SQR3_SQ5_SHIFT (15) /* Bits 20-24: 5th conversion in regular sequence */
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT)
#define ADC_SQR3_SQ6_SHIFT (15) /* Bits 25-29: 6th conversion in regular sequence */
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
#define ADC_SQR3_RESERVED (0xc0000000)
#define ADC_SQR3_FIRST (1)
#define ADC_SQR3_LAST (6)
#define ADC_SQR3_SQ_OFFSET (0)
/* ADC injected sequence register */
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in injected sequence */
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in injected sequence */
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in injected sequence */
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 15-19: 4th conversion in injected sequence */
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
#define ADC_JSQR_JL_SHIFT (20) /* Bits 20-21: Injected sequence length */
#define ADC_JSQR_JL_MASK (0x3 << ADC_JSQR_JL_SHIFT)
/* ADC injected data register 1, 2, 3, and 4 */
#define ADC_JDR_JDATA_SHIFT (0)
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
/* ADC regular data register */
#define ADC_DR_RDATA_SHIFT (0)
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Function Prototypes
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H */
arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+3 -1
View File
@@ -117,7 +117,7 @@
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
@@ -128,6 +128,8 @@
#define STM32_SDADC2_BASE 0x40016400 /* 0x40016000-0x400167ff SDADC2 */
#define STM32_SDADC3_BASE 0x40016800 /* 0x40016000-0x40016bff SDADC3 */
#define STM32_ADC1_BASE STM32_ADC_BASE
/* AHB1 Base Addresses **************************************************************/
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h
+68 -5
View File
@@ -69,6 +69,71 @@
* pins in this file.
*/
/* ADC */
#define GPIO_ADC_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ADC_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
#define GPIO_ADC_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
#define GPIO_ADC_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_ADC_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_ADC_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
#define GPIO_ADC_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ADC_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_ADC_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_ADC_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
#define GPIO_ADC_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
#define GPIO_ADC_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
#define GPIO_ADC_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ADC_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
/* SDADC */
#define GPIO_SDADC1_AIN0P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
#define GPIO_SDADC1_AIN0M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13)
#define GPIO_SDADC1_AIN1P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
#define GPIO_SDADC1_AIN2P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10)
#define GPIO_SDADC1_AIN2M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
#define GPIO_SDADC1_AIN3P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
#define GPIO_SDADC1_AIN4P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
#define GPIO_SDADC1_AIN4M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
#define GPIO_SDADC1_AIN5P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_SDADC1_AIN6P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_SDADC1_AIN6M (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_SDADC1_AIN7P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
#define GPIO_SDADC1_AIN8P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
#define GPIO_SDADC1_AIN8M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
#define GPIO_SDADC2_AIN0P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN15)
#define GPIO_SDADC2_AIN0M (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
#define GPIO_SDADC2_AIN1P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14)
#define GPIO_SDADC2_AIN2P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13)
#define GPIO_SDADC2_AIN2M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14)
#define GPIO_SDADC2_AIN3P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
#define GPIO_SDADC2_AIN4P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
#define GPIO_SDADC2_AIN4M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
#define GPIO_SDADC2_AIN5P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
#define GPIO_SDADC2_AIN6P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
#define GPIO_SDADC2_AIN6M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
#define GPIO_SDADC2_AIN7P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
#define GPIO_SDADC2_AIN8P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
#define GPIO_SDADC2_AIN8M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
#define GPIO_SDADC3_AIN0P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
#define GPIO_SDADC3_AIN0M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN15)
#define GPIO_SDADC3_AIN1P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
#define GPIO_SDADC3_AIN2P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
#define GPIO_SDADC3_AIN2M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
#define GPIO_SDADC3_AIN3P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
#define GPIO_SDADC3_AIN4P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
#define GPIO_SDADC3_AIN4M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
#define GPIO_SDADC3_AIN5P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
#define GPIO_SDADC3_AIN6P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
#define GPIO_SDADC3_AIN6M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
#define GPIO_SDADC3_AIN7P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
#define GPIO_SDADC3_AIN8P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SDADC3_AIN8M (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
/* CAN */
#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
@@ -96,9 +161,9 @@
* should first be configured to analog (AIN)".
*/
#define GPIO_DAC1_1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC2_1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC2_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
/* I2C */
@@ -233,7 +298,6 @@
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
/* Timers */
#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN0)
@@ -544,6 +608,5 @@
#define GPIO_PF9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9)
#define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H */
arch/arm/src/stm32/chip/stm32f37xxx_rcc.h
+26 -20
View File
@@ -128,6 +128,12 @@
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
#define RCC_CFGR_ADCPRE_SHIFT (13) /* Bits 14-15: ADC prescaler */
#define RCC_CFGR_ADCPRE_MASK (7 << RCC_CFGR_ADCPRE_SHIFT)
# define RCC_CFGR_ADCPRE_PCLKd2 (0 << RCC_CFGR_ADCPRE_SHIFT) /* 00: PCLK divided by 2 */
# define RCC_CFGR_ADCPRE_PCLKd4 (1 << RCC_CFGR_ADCPRE_SHIFT) /* 01: PCLK divided by 4 */
# define RCC_CFGR_ADCPRE_PCLKd6 (2 << RCC_CFGR_ADCPRE_SHIFT) /* 10: PCLK divided by 6 */
# define RCC_CFGR_ADCPRE_PCLKd8 (3 << RCC_CFGR_ADCPRE_SHIFT) /* 11: PCLK divided by 8 */
#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */
#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */
#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */
@@ -157,24 +163,24 @@
# define RCC_CFGR_MCO_HSICLK (5 << RCC_CFGR_MCO_SHIFT) /* 101: HSI clock selected */
# define RCC_CFGR_MCO_HSECLK (6 << RCC_CFGR_MCO_SHIFT) /* 101: HSE clock selected */
# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */
#define RCC_CFGR_SDADCPRE_SHIFT (24) /* Bits 27-31: SDADC Prescaler */
#define RCC_CFGR_SDADCPRE_MASK (31 << RCC_CFGR_SDADCPRE_SHIFT)
# define RCC_CFGR_SDADCPRE_DIV2 (0 << RCC_CFGR_SDADCPRE_SHIFT) /* 0xxxx: System clock divided by 2 */
# define RCC_CFGR_SDADCPRE_DIV4 (17 << RCC_CFGR_SDADCPRE_SHIFT) /* 10001: System clock divided by 4 */
# define RCC_CFGR_SDADCPRE_DIV6 (18 << RCC_CFGR_SDADCPRE_SHIFT) /* 10010: System clock divided by 6 */
# define RCC_CFGR_SDADCPRE_DIV8 (19 << RCC_CFGR_SDADCPRE_SHIFT) /* 10011: System clock divided by 8 */
# define RCC_CFGR_SDADCPRE_DIV10 (20 << RCC_CFGR_SDADCPRE_SHIFT) /* 10100: System clock divided by 10 */
# define RCC_CFGR_SDADCPRE_DIV12 (21 << RCC_CFGR_SDADCPRE_SHIFT) /* 10101: System clock divided by 12 */
# define RCC_CFGR_SDADCPRE_DIV14 (22 << RCC_CFGR_SDADCPRE_SHIFT) /* 10110: System clock divided by 14 */
# define RCC_CFGR_SDADCPRE_DIV16 (23 << RCC_CFGR_SDADCPRE_SHIFT) /* 10111: System clock divided by 16 */
# define RCC_CFGR_SDADCPRE_DIV20 (24 << RCC_CFGR_SDADCPRE_SHIFT) /* 11000: System clock divided by 20 */
# define RCC_CFGR_SDADCPRE_DIV24 (25 << RCC_CFGR_SDADCPRE_SHIFT) /* 11001: System clock divided by 24 */
# define RCC_CFGR_SDADCPRE_DIV28 (26 << RCC_CFGR_SDADCPRE_SHIFT) /* 11010: System clock divided by 28 */
# define RCC_CFGR_SDADCPRE_DIV32 (27 << RCC_CFGR_SDADCPRE_SHIFT) /* 11011: System clock divided by 32 */
# define RCC_CFGR_SDADCPRE_DIV36 (28 << RCC_CFGR_SDADCPRE_SHIFT) /* 11100: System clock divided by 36 */
# define RCC_CFGR_SDADCPRE_DIV40 (29 << RCC_CFGR_SDADCPRE_SHIFT) /* 11101: System clock divided by 40 */
# define RCC_CFGR_SDADCPRE_DIV44 (30 << RCC_CFGR_SDADCPRE_SHIFT) /* 11110: System clock divided by 44 */
# define RCC_CFGR_SDADCPRE_DIV48 (31 << RCC_CFGR_SDADCPRE_SHIFT) /* 11111: System clock divided by 48 */
#define RCC_CFGR_SDPRE_SHIFT (27) /* Bits 27-31: SDADC Prescaler */
#define RCC_CFGR_SDPRE_MASK (0x1f << RCC_CFGR_SDPRE_SHIFT)
# define RCC_CFGR_SDPRE_DIV2 (0 << RCC_CFGR_SDPRE_SHIFT) /* 0xxxx: System clock divided by 2 */
# define RCC_CFGR_SDPRE_DIV4 (17 << RCC_CFGR_SDPRE_SHIFT) /* 10001: System clock divided by 4 */
# define RCC_CFGR_SDPRE_DIV6 (18 << RCC_CFGR_SDPRE_SHIFT) /* 10010: System clock divided by 6 */
# define RCC_CFGR_SDPRE_DIV8 (19 << RCC_CFGR_SDPRE_SHIFT) /* 10011: System clock divided by 8 */
# define RCC_CFGR_SDPRE_DIV10 (20 << RCC_CFGR_SDPRE_SHIFT) /* 10100: System clock divided by 10 */
# define RCC_CFGR_SDPRE_DIV12 (21 << RCC_CFGR_SDPRE_SHIFT) /* 10101: System clock divided by 12 */
# define RCC_CFGR_SDPRE_DIV14 (22 << RCC_CFGR_SDPRE_SHIFT) /* 10110: System clock divided by 14 */
# define RCC_CFGR_SDPRE_DIV16 (23 << RCC_CFGR_SDPRE_SHIFT) /* 10111: System clock divided by 16 */
# define RCC_CFGR_SDPRE_DIV20 (24 << RCC_CFGR_SDPRE_SHIFT) /* 11000: System clock divided by 20 */
# define RCC_CFGR_SDPRE_DIV24 (25 << RCC_CFGR_SDPRE_SHIFT) /* 11001: System clock divided by 24 */
# define RCC_CFGR_SDPRE_DIV28 (26 << RCC_CFGR_SDPRE_SHIFT) /* 11010: System clock divided by 28 */
# define RCC_CFGR_SDPRE_DIV32 (27 << RCC_CFGR_SDPRE_SHIFT) /* 11011: System clock divided by 32 */
# define RCC_CFGR_SDPRE_DIV36 (28 << RCC_CFGR_SDPRE_SHIFT) /* 11100: System clock divided by 36 */
# define RCC_CFGR_SDPRE_DIV40 (29 << RCC_CFGR_SDPRE_SHIFT) /* 11101: System clock divided by 40 */
# define RCC_CFGR_SDPRE_DIV44 (30 << RCC_CFGR_SDPRE_SHIFT) /* 11110: System clock divided by 44 */
# define RCC_CFGR_SDPRE_DIV48 (31 << RCC_CFGR_SDPRE_SHIFT) /* 11111: System clock divided by 48 */
/* Clock interrupt register */
@@ -199,7 +205,7 @@
/* APB2 Peripheral reset register */
#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */
#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 reset */
#define RCC_APB2RSTR_ADCRST (1 << 9) /* Bit 9: ADC reset */
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */
@@ -232,7 +238,7 @@
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
#define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN reset */
#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC1 interface reset */
#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC2 interface reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */
#define RCC_APB1RSTR_CECRST (1 << 30) /* Bit 30: CEC reset */
arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h
+304
View File
@@ -0,0 +1,304 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Studelec SA. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Marc Rechté <mrechte@studelec-sa.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32_SDADC_CR1_OFFSET 0x0000 /* SDADC control register 1 */
#define STM32_SDADC_CR2_OFFSET 0x0004 /* SDADC control register 2 */
#define STM32_SDADC_ISR_OFFSET 0x0008 /* SDADC interrupt and status register */
#define STM32_SDADC_CLRISR_OFFSET 0x000c /* SDADC interrupt and status clear register */
#define STM32_SDADC_JCHGR_OFFSET 0x0014 /* SDADC injected channel group selection register */
#define STM32_SDADC_CONF0R_OFFSET 0x0020 /* SDADC configuration 0 register */
#define STM32_SDADC_CONF1R_OFFSET 0x0024 /* SDADC configuration 1 register */
#define STM32_SDADC_CONF2R_OFFSET 0x0028 /* SDADC configuration 2 register */
#define STM32_SDADC_CONFCHR1_OFFSET 0x0040 /* SDADC channel configuration register 1 */
#define STM32_SDADC_CONFCHR2_OFFSET 0x0044 /* SDADC channel configuration register 2 */
#define STM32_SDADC_JDATAR_OFFSET 0x0060 /* SDADC data register for injected group */
#define STM32_SDADC_RDATAR_OFFSET 0x0064 /* SDADC data register for the regular channel */
#define STM32_SDADC_JDATA12R_OFFSET 0x0070 /* SDADC1 and SDADC2 injected data register */
#define STM32_SDADC_RDATA12R_OFFSET 0x0074 /* SDADC1 and SDADC2 regular data register */
#define STM32_SDADC_JDATA13R_OFFSET 0x0078 /* SDADC1 and SDADC3 injected data register */
#define STM32_SDADC_RDATA13R_OFFSET 0x007c /* SDADC1 and SDADC3 regular data register */
/* Register Addresses *******************************************************************************/
#define STM32_SDADC1_CR1 (STM32_SDADC1_BASE+STM32_SDADC_CR1_OFFSET)
#define STM32_SDADC1_CR2 (STM32_SDADC1_BASE+STM32_SDADC_CR2_OFFSET)
#define STM32_SDADC1_ISR (STM32_SDADC1_BASE+STM32_SDADC_ISR_OFFSET)
#define STM32_SDADC1_CLRISR (STM32_SDADC1_BASE+STM32_SDADC_CLRISR_OFFSET)
#define STM32_SDADC1_JCHGR (STM32_SDADC1_BASE+STM32_SDADC_JCHGR_OFFSET)
#define STM32_SDADC1_CONF0R (STM32_SDADC1_BASE+STM32_SDADC_CONF0R_OFFSET)
#define STM32_SDADC1_CONF1R (STM32_SDADC1_BASE+STM32_SDADC_CONF1R_OFFSET)
#define STM32_SDADC1_CONF2R (STM32_SDADC1_BASE+STM32_SDADC_CONF2R_OFFSET)
#define STM32_SDADC1_CONFCHR1 (STM32_SDADC1_BASE+STM32_SDADC_CONFCHR1_OFFSET)
#define STM32_SDADC1_CONFCHR2 (STM32_SDADC1_BASE+STM32_SDADC_CONFCHR2_OFFSET)
#define STM32_SDADC1_JDATAR (STM32_SDADC1_BASE+STM32_SDADC_JDATAR_OFFSET)
#define STM32_SDADC1_RDATAR (STM32_SDADC1_BASE+STM32_SDADC_RDATAR_OFFSET)
#define STM32_SDADC1_JDATA12R (STM32_SDADC1_BASE+STM32_SDADC_JDATA12R_OFFSET)
#define STM32_SDADC1_RDATA12R (STM32_SDADC1_BASE+STM32_SDADC_RDATA12R_OFFSET)
#define STM32_SDADC1_JDATA13R (STM32_SDADC1_BASE+STM32_SDADC_JDATA13R_OFFSET)
#define STM32_SDADC1_RDATA13R (STM32_SDADC1_BASE+STM32_SDADC_RDATA13R_OFFSET)
#define STM32_SDADC2_CR1 (STM32_SDADC2_BASE+STM32_SDADC_CR1_OFFSET)
#define STM32_SDADC2_CR2 (STM32_SDADC2_BASE+STM32_SDADC_CR2_OFFSET)
#define STM32_SDADC2_ISR (STM32_SDADC2_BASE+STM32_SDADC_ISR_OFFSET)
#define STM32_SDADC2_CLRISR (STM32_SDADC2_BASE+STM32_SDADC_CLRISR_OFFSET)
#define STM32_SDADC2_JCHGR (STM32_SDADC2_BASE+STM32_SDADC_JCHGR_OFFSET)
#define STM32_SDADC2_CONF0R (STM32_SDADC2_BASE+STM32_SDADC_CONF0R_OFFSET)
#define STM32_SDADC2_CONF1R (STM32_SDADC2_BASE+STM32_SDADC_CONF1R_OFFSET)
#define STM32_SDADC2_CONF2R (STM32_SDADC2_BASE+STM32_SDADC_CONF2R_OFFSET)
#define STM32_SDADC2_CONFCHR1 (STM32_SDADC2_BASE+STM32_SDADC_CONFCHR1_OFFSET)
#define STM32_SDADC2_CONFCHR2 (STM32_SDADC2_BASE+STM32_SDADC_CONFCHR2_OFFSET)
#define STM32_SDADC2_JDATAR (STM32_SDADC2_BASE+STM32_SDADC_JDATAR_OFFSET)
#define STM32_SDADC2_RDATAR (STM32_SDADC2_BASE+STM32_SDADC_RDATAR_OFFSET)
#define STM32_SDADC3_CR1 (STM32_SDADC3_BASE+STM32_SDADC_CR1_OFFSET)
#define STM32_SDADC3_CR2 (STM32_SDADC3_BASE+STM32_SDADC_CR2_OFFSET)
#define STM32_SDADC3_ISR (STM32_SDADC3_BASE+STM32_SDADC_ISR_OFFSET)
#define STM32_SDADC3_CLRISR (STM32_SDADC3_BASE+STM32_SDADC_CLRISR_OFFSET)
#define STM32_SDADC3_JCHGR (STM32_SDADC3_BASE+STM32_SDADC_JCHGR_OFFSET)
#define STM32_SDADC3_CONF0R (STM32_SDADC3_BASE+STM32_SDADC_CONF0R_OFFSET)
#define STM32_SDADC3_CONF1R (STM32_SDADC3_BASE+STM32_SDADC_CONF1R_OFFSET)
#define STM32_SDADC3_CONF2R (STM32_SDADC3_BASE+STM32_SDADC_CONF2R_OFFSET)
#define STM32_SDADC3_CONFCHR1 (STM32_SDADC3_BASE+STM32_SDADC_CONFCHR1_OFFSET)
#define STM32_SDADC3_CONFCHR2 (STM32_SDADC3_BASE+STM32_SDADC_CONFCHR2_OFFSET)
#define STM32_SDADC3_JDATAR (STM32_SDADC3_BASE+STM32_SDADC_JDATAR_OFFSET)
#define STM32_SDADC3_RDATAR (STM32_SDADC3_BASE+STM32_SDADC_RDATAR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SDADC control register 1 */
#define SDADC_CR1_EOCALIE (1 << 0) /* Bit 0: End of calibration interrupt enable */
#define SDADC_CR1_JEOCIE (1 << 1) /* Bit 1: Injected end of conversion interrupt enable */
#define SDADC_CR1_JOVRIE (1 << 2) /* Bit 2: Injected data overrun interrupt enable */
#define SDADC_CR1_REOCIE (1 << 3) /* Bit 3: Regular end of conversion interrupt enable */
#define SDADC_CR1_ROVRIE (1 << 4) /* Bit 4: Regular data overrun interrupt enable */
#define SDADC_CR1_REFV_SHIFT (8) /* Bits 8-9: Reference voltage selection */
#define SDADC_CR1_REFV_MASK (0x3 << SDADC_CR1_REFV_SHIFT)
# define SDADC_CR1_REFV_EXT (0 << SDADC_CR1_REFV_SHIFT)
# define SDADC_CR1_REFV_INT1p2 (1 << SDADC_CR1_REFV_SHIFT)
# define SDADC_CR1_REFV_INT1p8 (2 << SDADC_CR1_REFV_SHIFT)
# define SDADC_CR1_REFV_INT (3 << SDADC_CR1_REFV_SHIFT)
#define SDADC_CR1_SLOWCK (1 << 10) /* Bit 10: Slow clock mode enable */
#define SDADC_CR1_SBI (1 << 11) /* Bit 11: Enter Standby mode when idle */
#define SDADC_CR1_PDI (1 << 12) /* Bit 12: Enter power down mode when idle */
#define SDADC_CR1_JSYNC (1 << 14) /* Bit 14: Launch a injected conversion synchronously with SDADC1 */
#define SDADC_CR1_RSYNC (1 << 15) /* Bit 15: Launch regular conversion synchronously with SDADC1 */
#define SDADC_CR1_JDMAEN (1 << 16) /* Bit 16: DMA channel enabled to read data for the injected channel group */
#define SDADC_CR1_RDMAEN (1 << 17) /* Bit 17: DMA channel enabled to read data for the regular channel */
#define SDADC_CR1_INIT (1 << 31) /* Bit 31: Initialization mode request */
/* SDADC control register 2 */
#define SDADC_CR2_ADON (1 << 0) /* Bit 0: SDADC enable */
#define SDADC_CR2_CALIBCNT_SHIFT (1) /* Bit 1-2: Number of calibration sequences to be performed (number of valid configurations) */
#define SDADC_CR2_CALIBCNT_MASK (0x3 << SDADC_CR2_CALIBCNT_SHIFT)
#define SDADC_CR2_STARTCALIB (1 << 4) /* Bit 4: Start calibration */
#define SDADC_CR2_JCONT (1 << 5) /* Bit 5: Continuous mode selection for injected conversions */
#define SDADC_CR2_JDS (1 << 6) /* Bit 6: Delay start of injected conversions */
#define SDADC_CR2_JEXTSEL_SHIFT (8) /* Bit 8-10: Trigger signal selection for launching injected conversions */
#define SDADC_CR2_JEXTSEL_MASK (0x7 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_TIM13_CH1 (0 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_TIM14_CH1 (1 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_TIM15_CH2 (2 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_TIM3_CH1 (3 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_TIM4_CH1 (4 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_TIM19_CH2 (5 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_EXTI15 (6 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC1_CR2_JEXTSEL_EXTI11 (7 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_TIM17_CH1 (0 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_TIM12_CH1 (1 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_TIM2_CH3 (2 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_TIM3_CH2 (3 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_TIM4_CH2 (4 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_TIM19_CH3 (5 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_EXTI15 (6 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC2_CR2_JEXTSEL_EXTI11 (7 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_TIM16_CH1 (0 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_TIM12_CH1 (1 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_TIM2_CH4 (2 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_TIM3_CH3 (3 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_TIM4_CH3 (4 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_TIM19_CH4 (5 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_EXTI15 (6 << SDADC_CR2_JEXTSEL_SHIFT)
# define SDADC3_CR2_JEXTSEL_EXTI11 (7 << SDADC_CR2_JEXTSEL_SHIFT)
#define SDADC_CR2_JEXTEN_SHIFT (13) /* Bit 13-14: Trigger enable and trigger edge selection for injected conversions */
#define SDADC_CR2_JEXTEN_MASK (0x3 << SDADC_CR2_JEXTEN_SHIFT)
# define SDADC_CR2_JEXTEN_NONE (0 << SDADC_CR2_JEXTEN_SHIFT)
# define SDADC_CR2_JEXTEN_RISING (1 << SDADC_CR2_JEXTEN_SHIFT)
# define SDADC_CR2_JEXTEN_FALLING (2 << SDADC_CR2_JEXTEN_SHIFT)
# define SDADC_CR2_JEXTEN_BOTH (3 << SDADC_CR2_JEXTEN_SHIFT)
#define SDADC_CR2_JSWSTART (1 << 15) /* Bit 15: Start a conversion of the injected group of channels */
#define SDADC_CR2_RCH_SHIFT (16) /* Bit 16-19: Regular channel selection */
#define SDADC_CR2_RCH_MASK (0xf << SDADC_CR2_RCH_SHIFT)
#define SDADC_CR2_RCONT (1 << 22) /* Bit 22: Continuous mode selection for regular conversions */
#define SDADC_CR2_RSWSTART (1 << 23) /* Bit 23: Software start of a conversion on the regular channel */
#define SDADC_CR2_FAST (1 << 24) /* Bit 24: Fast conversion mode selection */
/* SDADC interrupt and status register */
#define SDADC_ISR_EOCALF (1 << 0) /* Bit 0: End of calibration flag */
#define SDADC_ISR_JEOCF (1 << 1) /* Bit 1: End of injected conversion flag */
#define SDADC_ISR_JOVRF (1 << 2) /* Bit 2: Injected conversion overrun flag */
#define SDADC_ISR_REOCF (1 << 3) /* Bit 3: End of regular conversion flag */
#define SDADC_ISR_ROVRF (1 << 4) /* Bit 4: Regular conversion overrun flag */
#define SDADC_ISR_CALIBIP (1 << 12) /* Bit 12: Calibration in progress status */
#define SDADC_ISR_JCIP (1 << 13) /* Bit 13: Injected conversion in progress status */
#define SDADC_ISR_RCIP (1 << 14) /* Bit 14: Regular conversion in progress status */
#define SDADC_ISR_STABIP (1 << 15) /* Bit 15: Stabilization in progress status */
#define SDADC_ISR_INITRDY (1 << 31) /* Bit 31: Initialization mode is ready */
/* SDADC interrupt and status clear register */
#define SDADC_CLRISR_CLREOCALF (1 << 0) /* Bit 0: Clear the end of calibration flag */
#define SDADC_CLRISR_CLRJOVRF (1 << 2) /* Bit 2: Clear the injected conversion overrun flag */
#define SDADC_CLRISR_CLRROVRF (1 << 4) /* Bit 4: Clear the regular conversion overrun flag */
/* SDADC injected channel group selection register */
#define SDADC_JCHGR_JCHG_SHIFT (0) /* Bit 0-8: Injected channel group selection */
#define SDADC_JCHGR_JCHG_MASK (0x1ff << SDADC_JCHGR_JCHG_SHIFT)
#define SDADC_JCHGR_JCHG_CH(n) (1 << (n + SDADC_JCHGR_JCHG_SHIFT))
/* SDADC configuration 0-2 register */
#define SDADC_CONF0R 0
#define SDADC_CONF1R 1
#define SDADC_CONF2R 2
#define SDADC_CONFR_OFFSET_SHIFT (0) /* Bit 0-11: Twelve-bit calibration offset for configuration 0-2 */
#define SDADC_CONFR_OFFSET_MASK (0xfff << SDADC_CONFR_OFFSET_SHIFT)
#define SDADC_CONFR_GAIN_SHIFT (20) /* Bit 20-22: Gain setting for configuration 0-2 */
#define SDADC_CONFR_GAIN_MASK (0x7 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_1X (0 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_2X (1 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_4X (2 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_8X (3 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_16X (4 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_32X (5 << SDADC_CONFR_GAIN_SHIFT)
# define SDADC_CONFR_GAIN_0p5X (7 << SDADC_CONFR_GAIN_SHIFT)
#define SDADC_CONFR_SE_SHIFT (26) /* Bit 27-26: Single-ended mode for configuration 0-2 */
#define SDADC_CONFR_SE_MASK (0x3 << SDADC_CONFR_SE_SHIFT)
# define SDADC_CONFR_SE_DIF (0 << SDADC_CONFR_SE_SHIFT)
# define SDADC_CONFR_SE_SE_OFFSET (1 << SDADC_CONFR_SE_SHIFT)
# define SDADC_CONFR_SE_SE_ZERO (3 << SDADC_CONFR_SE_SHIFT)
#define SDADC_CONFR_COMMON_SHIFT (30) /* Bit 30-31: Common mode for configuration 0-2 */
#define SDADC_CONFR_COMMON_MASK (0x3 << SDADC_CONFR_COMMON_SHIFT)
# define SDADC_CONFR_COMMON_GND (0 << SDADC_CONFR_COMMON_SHIFT)
# define SDADC_CONFR_COMMON_VCM (1 << SDADC_CONFR_COMMON_SHIFT)
# define SDADC_CONFR_COMMON_VDD (2 << SDADC_CONFR_COMMON_SHIFT)
/* SDADC channel configuration register 1 */
#define SDADC_CONFCHR1_CH_SHIFT(i) (2*i) /* Bit 0-1: Channel i configuration 0-7 */
#define SDADC_CONFCHR1_CH_MASK(i) (0x3 << SDADC_CONFCHR1_CH_SHIFT(i))
/* SDADC channel configuration register 2 */
#define SDADC_CONFCHR2_CH8_SHIFT (0) /* Bit 0-1: Channel 8 configuration */
#define SDADC_CONFCHR2_CH8_MASK (0x3 << SDADC_CONFCHR2_CH8_SHIFT)
/* SDADC data register for injected group */
#define SDADC_JDATAR_JDATA_SHIFT (0) /* Bit 0-15: Injected group conversion data */
#define SDADC_JDATAR_JDATA_MASK (0xffff << SDADC_JDATAR_JDATA_SHIFT)
#define SDADC_JDATAR_JDATACH_SHIFT (24) /* Bit 24-27: Injected channel most recently converted */
#define SDADC_JDATAR_JDATACH_MASK (0xf << SDADC_JDATAR_JDATACH_SHIFT)
/* SDADC data register for the regular channel */
#define SDADC_RDATAR_RDATA_SHIFT (0) /* Bit 0-15: Regular channel conversion data */
#define SDADC_RDATAR_RDATA_MASK (0xffff << SDADC_RDATAR_RDATA_SHIFT)
/* SDADC1 and SDADC2 injected data register */
#define SDADC_JDATA12R_JDATA1_SHIFT (0) /* Bit 0-15: Injected group conversion data for SDADC1 */
#define SDADC_JDATA12R_JDATA1_MASK (0xffff << SDADC_JDATA12R_JDATA1_SHIFT)
#define SDADC_JDATA12R_JDATA2_SHIFT (16) /* Bit 16-31: Injected group conversion data for SDADC2 */
#define SDADC_JDATA12R_JDATA2_MASK (0xffff << SDADC_JDATA12R_JDATA2_SHIFT)
/* SDADC1 and SDADC2 regular data register */
#define SDADC_RDATA12R_RDATA1_SHIFT (0) /* Bit 0-15: Regular conversion data for SDADC1 */
#define SDADC_RDATA12R_RDATA1_MASK (0xffff << SDADC_RDATA12R_RDATA1_SHIFT)
#define SDADC_RDATA12R_RDATA2_SHIFT (16) /* Bit 16-31: Regular conversion data for SDADC2 */
#define SDADC_RDATA12R_RDATA2_MASK (0xffff << SDADC_RDATA12R_RDATA2_SHIFT)
/* SDADC1 and SDADC3 injected data register */
#define SDADC_JDATA13R_JDATA1_SHIFT (0) /* Bit 0-15: Injected group conversion data for SDADC1 */
#define SDADC_JDATA13R_JDATA1_MASK (0xffff << SDADC_JDATA13R_JDATA1_SHIFT)
#define SDADC_JDATA13R_JDATA3_SHIFT (16) /* Bit 16-31: Injected group conversion data for SDADC3 */
#define SDADC_JDATA13R_JDATA3_MASK (0xffff << SDADC_JDATA13R_JDATA3_SHIFT)
/* SDADC1 and SDADC3 regular data register */
#define SDADC_RDATA13R_RDATA1_SHIFT (0) /* Bit 0-15: Regular conversion data for SDADC1 */
#define SDADC_RDATA13R_RDATA1_MASK (0xffff << SDADC_RDATA13R_RDATA1_SHIFT)
#define SDADC_RDATA13R_RDATA3_SHIFT (16) /* Bit 16-31: Regular conversion data for SDADC3 */
#define SDADC_RDATA13R_RDATA3_MASK (0xffff << SDADC_RDATA13R_RDATA3_SHIFT)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Function Prototypes
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H */
arch/arm/src/stm32/stm32.h
+1
View File
@@ -61,6 +61,7 @@
#include "stm32_can.h"
#include "stm32_dbgmcu.h"
#include "stm32_dma.h"
#include "stm32_dac.h"
#include "stm32_exti.h"
#include "stm32_flash.h"
#include "stm32_fsmc.h"
arch/arm/src/stm32/stm32_adc.c
+56 -19
View File
@@ -79,8 +79,8 @@
/* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
/* At the moment there is no proper implementation for timers external
* trigger in STM32L15XX May be added latter
@@ -107,6 +107,9 @@
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
# define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST
# define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST
#elif defined(CONFIG_STM32_STM32F37XX)
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
@@ -148,7 +151,7 @@
# define ADC_IER_AWD ADC_CR1_AWDIE
# define ADC_ISR_JEOC ADC_SR_JEOC
# define ADC_IER_JEOC ADC_CR1_JEOCIE
# ifdef CONFIG_STM32_STM32F10XX
# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F37XX)
# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG
# define ADC_EXTREG_EXTEN_NONE 0
# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG
@@ -180,7 +183,11 @@
#ifdef ADC_HAVE_DMA
# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA
#else
# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA
# if defined(CONFIG_STM32_STM32F30XX)
# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA /* Works without DMA should sampling frequency be reduced */
# else
# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA
# endif
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
@@ -219,7 +226,12 @@
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
#elif defined(CONFIG_STM32_STM32F30XX)
# define ADC_SMPR_DEFAULT ADC_SMPR_61p5
# ifdef ADC_HAVE_DMA || (ADC_MAX_SAMPLES == 1)
# define ADC_SMPR_DEFAULT ADC_SMPR_61p5
# else /* Slow down sampling frequency */
# define ADC_SMPR_DEFAULT ADC_SMPR_601p5
# endif
# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \
@@ -238,8 +250,13 @@
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT))
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_SMPR_DEFAULT ADC_SMPR_112
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F37XX)
# define ADC_SMPR_DEFAULT ADC_SMPR_239p5 /* TODO choose 1p5? */
# else
# define ADC_SMPR_DEFAULT ADC_SMPR_112
# endif
# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \
@@ -320,7 +337,8 @@ struct stm32_dev_s
/* ADC Register access */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits);
#endif
@@ -587,7 +605,8 @@ static struct adc_dev_s g_adcdev4 =
****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits)
{
@@ -1626,7 +1645,7 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev)
#endif
/****************************************************************************
* Name: adc_dmacovcallback
* Name: adc_dmaconvcallback
*
* Description:
* Callback for DMA. Called from the DMA transfer complete interrupt after
@@ -1850,7 +1869,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
#else
#else /* ifdef CONFIG_STM32_STM32F30XX */
/* Enable the analog watchdog */
@@ -1864,7 +1883,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
clrbits |= ADC_CR1_DUALMOD_MASK;
setbits |= ADC_CR1_IND;
#else
#elif (! defined(CONFIG_STM32_STM32F37XX))
/* Set the resolution of the conversion */
@@ -1880,10 +1899,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
}
#endif
/* Enable interrupt flags, but disable overrun interrupt */
/* Enable interrupt flags, but disable overrun interrupt: TODO this is
* done later by upper half when opening device by adc_rxint().
*/
#ifndef CONFIG_STM32_STM32F37XX
clrbits |= ADC_IER_OVR;
setbits |= ADC_IER_ALLINTS & ~ADC_IER_OVR;
#else
/* TODO NON DMA mode */
#endif
/* Set CR1 configuration */
@@ -1916,6 +1941,13 @@ static void adc_reset(FAR struct adc_dev_s *dev)
clrbits |= ADC_EXTREG_EXTEN_MASK;
setbits |= ADC_EXTREG_EXTEN_NONE;
/* Enable software trigger for regular channels */
#ifdef CONFIG_STM32_STM32F37XX
clrbits |= ADC_CR2_EXTSEL_MASK;
setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */
#endif
#ifdef ADC_HAVE_DMA
if (priv->hasdma)
{
@@ -2176,9 +2208,12 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
if (enable)
{
/* Enable the end-of-conversion ADC and analog watchdog interrupts */
/* Enable the analog watchdog / overrun interrupts, and if no DMA,
* end-of-conversion ADC.
*/
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_ALLINTS);
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0,
priv->hasdma ? ADC_IER_AWD | ADC_ISR_OVR : ADC_IER_ALLINTS);
}
else
{
@@ -2766,8 +2801,10 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
}
}
regval &= ~pending;
adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval);
/* by MR regval &= ~pending; */
/* by MR adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval);
adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); */
return OK;
}
@@ -3039,8 +3076,8 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
}
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX ||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F40XX ||
* CONFIG_STM32_STM32L15XX
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX ||
* CONFIG_STM32_STM32F40XX || CONFIG_STM32_STM32L15XX
*/
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
* CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4
arch/arm/src/stm32/stm32_adc.h
+2
View File
@@ -48,6 +48,8 @@
#if defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_adc.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_adc.h"
#else
# include "chip/stm32_adc.h"
#endif
arch/arm/src/stm32/stm32_dac.c
+73 -20
View File
@@ -348,7 +348,9 @@ struct stm32_chan_s
uint8_t timer; /* Timer number 2-8 */
#endif
uint8_t intf; /* DAC zero-based interface number (0 or 1) */
uint32_t pin; /* Pin configuration */
uint32_t dro; /* Data output register */
uint32_t cr; /* Control register */
uint32_t tsel; /* CR trigger select value */
#ifdef HAVE_DMA
uint16_t dmachan; /* DMA channel needed by this DAC */
@@ -408,10 +410,20 @@ static const struct dac_ops_s g_dacops =
};
#ifdef CONFIG_STM32_DAC1
/* Channel 1 */
static struct stm32_chan_s g_dac1priv =
{
.intf = 0,
#if STM32_NDAC < 2
.pin = GPIO_DAC1_OUT,
.dro = STM32_DAC_DHR12R1,
.cr = STM32_DAC_CR,
#else
.pin = GPIO_DAC1_OUT1,
.dro = STM32_DAC1_DHR12R1,
.cr = STM32_DAC1_CR,
#endif
#ifdef CONFIG_STM32_DAC1_DMA
.hasdma = 1,
.dmachan = DAC1_DMA_CHAN,
@@ -427,13 +439,21 @@ static struct dac_dev_s g_dac1dev =
.ad_ops = &g_dacops,
.ad_priv = &g_dac1priv,
};
#endif
#ifdef CONFIG_STM32_DAC2
/* Channel 2 */
static struct stm32_chan_s g_dac2priv =
{
.intf = 1,
#if STM32_NDAC < 2
.pin = GPIO_DAC2_OUT,
.dro = STM32_DAC_DHR12R2,
.cr = STM32_DAC_CR,
#else
.pin = GPIO_DAC1_OUT2,
.dro = STM32_DAC1_DHR12R2,
.cr = STM32_DAC1_CR,
#endif
#ifdef CONFIG_STM32_DAC2_DMA
.hasdma = 1,
.dmachan = DAC2_DMA_CHAN,
@@ -451,6 +471,24 @@ static struct dac_dev_s g_dac2dev =
};
#endif
#ifdef CONFIG_STM32_DAC2
/* Channel 1 */
static struct stm32_chan_s g_dac3priv =
{
.intf = 2,
.pin = GPIO_DAC2_OUT1,
.dro = STM32_DAC2_DHR12R1,
.cr = STM32_DAC2_CR,
};
static struct dac_dev_s g_dac3dev =
{
.ad_ops = &g_dacops,
.ad_priv = &g_dac3priv,
};
#endif
static struct stm32_dac_s g_dacblock;
/****************************************************************************
@@ -479,7 +517,7 @@ static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan,
uint32_t shift;
shift = chan->intf * 16;
modifyreg32(STM32_DAC_CR, clearbits << shift, setbits << shift);
modifyreg32(chan->cr, clearbits << shift, setbits << shift);
}
/****************************************************************************
@@ -738,16 +776,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
/* Non-DMA transfer */
putreg16(msg->am_data, chan->dro);
#ifdef CONFIG_STM32_DAC2
if (chan->intf)
{
dac_txdone(&g_dac2dev);
}
else
#endif
{
dac_txdone(&g_dac1dev);
}
dac_txdone(dev);
}
/* Reset counters (generate an update) */
@@ -978,7 +1007,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
* should first be configured to analog (AIN)".
*/
stm32_configgpio(chan->intf ? GPIO_DAC2_OUT : GPIO_DAC1_OUT);
stm32_configgpio(chan->pin);
/* DAC channel configuration:
*
@@ -1041,7 +1070,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
* Name: dac_blockinit
*
* Description:
* All ioctl calls will be routed through this method.
* Initialize the DAC block.
*
* Input Parameters:
*
@@ -1055,7 +1084,7 @@ static int dac_blockinit(void)
irqstate_t flags;
uint32_t regval;
/* Has the DMA block already been initialized? */
/* Has the DAC block already been initialized? */
if (g_dacblock.init)
{
@@ -1068,12 +1097,30 @@ static int dac_blockinit(void)
flags = enter_critical_section();
regval = getreg32(STM32_RCC_APB1RSTR);
#if STM32_NDAC < 2
regval |= RCC_APB1RSTR_DACRST;
#else
#ifdef CONFIG_STM32_DAC1
regval |= RCC_APB1RSTR_DAC1RST;
#endif
#ifdef CONFIG_STM32_DAC2
regval |= RCC_APB1RSTR_DAC2RST;
#endif
#endif
putreg32(regval, STM32_RCC_APB1RSTR);
/* Take the DAC out of reset state */
#if STM32_NDAC < 2
regval &= ~RCC_APB1RSTR_DACRST;
#else
#ifdef CONFIG_STM32_DAC1
regval &= ~RCC_APB1RSTR_DAC1RST;
#endif
#ifdef CONFIG_STM32_DAC2
regval &= ~RCC_APB1RSTR_DAC2RST;
#endif
#endif
putreg32(regval, STM32_RCC_APB1RSTR);
leave_critical_section(flags);
@@ -1114,16 +1161,22 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
#ifdef CONFIG_STM32_DAC1
if (intf == 1)
{
ainfo("DAC1 Selected\n");
ainfo("DAC1-1 Selected\n");
dev = &g_dac1dev;
}
else
if (intf == 2)
{
ainfo("DAC1-2 Selected\n");
dev = &g_dac2dev;
}
else
#endif
#ifdef CONFIG_STM32_DAC2
if (intf == 2)
if (intf == 3)
{
ainfo("DAC2 Selected\n");
dev = &g_dac2dev;
ainfo("DAC2-1 Selected\n");
dev = &g_dac3dev;
}
else
#endif
arch/arm/src/stm32/stm32_i2c.h
+1 -1
View File
@@ -44,7 +44,7 @@
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
#if defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f30xxx_i2c.h"
#else
# include "chip/stm32_i2c.h"
arch/arm/src/stm32/stm32_pwr.c
+40
View File
@@ -76,6 +76,46 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_pwr_enablesdadc
*
* Description:
* Enables SDADC power
*
* Input Parameters:
* sdadc - SDADC number 1-3
*
* Returned Value:
* None
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F37XX)
void stm32_pwr_enablesdadc(uint8_t sdadc)
{
uint32_t setbits = 0;
switch (sdadc)
{
case 1:
setbits = PWR_CR_ENSD1;
break;
case 2:
setbits = PWR_CR_ENSD2;
break;
case 3:
setbits = PWR_CR_ENSD3;
break;
}
stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, setbits);
}
#endif
/************************************************************************************
* Name: stm32_pwr_enablebkp
*
arch/arm/src/stm32/stm32_pwr.h
+18
View File
@@ -66,6 +66,24 @@ extern "C"
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_pwr_enablesdadc
*
* Description:
* Enables SDADC power
*
* Input Parameters:
* sdadc - SDADC number 1-3
*
* Returned Value:
* None
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F37XX)
void stm32_pwr_enablesdadc(uint8_t sdadc);
#endif
/************************************************************************************
* Name: stm32_pwr_enablebkp
*
arch/arm/src/stm32/stm32_sdadc.c
+1456
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32_sdadc.h
+426
View File
@@ -0,0 +1,426 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_sdadc.h
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Studelec. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Marc Rechté <mrechte@studelec-sa.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_SDADC_H
#define __ARCH_ARM_SRC_STM32_STM32_SDADC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_sdadc.h"
#else
/* No generic chip/stm32_sdadc.h yet */
# error "This chip is not yet supported"
#endif
#include <nuttx/analog/adc.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* Timer devices may be used for different purposes. One special purpose is to
* control periodic SDADC sampling. If CONFIG_STM32_TIMn is defined then
* CONFIG_STM32_TIMn_SDADC must also be defined to indicate that timer "n" is intended
* to be used for that purpose.
*/
/* For the STM32 F37XX line, timers 2-4, 12-17 an 19 may be used. */
/* TODO cf. stm32_adc.h */
/* Up to 3 SDADC interfaces are supported */
#if STM32_NSDADC < 3
# undef CONFIG_STM32_SDADC3
#endif
#if STM32_NSDADC < 2
# undef CONFIG_STM32_SDADC2
#endif
#if STM32_NSDADC < 1
# undef CONFIG_STM32_SDADC1
#endif
#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \
defined(CONFIG_STM32_SDADC3)
/* DMA support */
#if defined(CONFIG_STM32_SDADC1_DMA) || defined(CONFIG_STM32_SDADC2_DMA) || \
defined(CONFIG_STM32_SDADC3_DMA)
# define SDADC_HAVE_DMA 1
#endif
#ifdef CONFIG_STM32_SDADC1_DMA
# define SDADC1_HAVE_DMA 1
#else
# undef SDADC1_HAVE_DMA
#endif
#ifdef CONFIG_STM32_SDADC2_DMA
# define SDADC2_HAVE_DMA 1
#else
# undef SDADC2_HAVE_DMA
#endif
#ifdef CONFIG_STM32_SDADC3_DMA
# define SDADC3_HAVE_DMA 1
#else
# undef SDADC3_HAVE_DMA
#endif
/* SDADC Channels/DMA ******************************************************
* The maximum number of channels that can be sampled at each scan.
* If DMA support is not enabled, then only a single channel
* ought to be sampled.
* Otherwise, unless sampling frequency is reduced,
* data overruns would occur.
*/
#define SDADC_MAX_CHANNELS_DMA 9
#define SDADC_MAX_CHANNELS_NODMA 1
#ifndef SDADC_MAX_SAMPLES
#ifdef SDADC_HAVE_DMA
# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_DMA
#else
# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_NODMA
#endif
#endif
/* Timer configuration: If a timer trigger is specified, then get
* information about the timer.
*/
#if defined(CONFIG_STM32_TIM3_SDADC1)
# define SDADC1_HAVE_TIMER 1
# define SDADC1_TIMER_BASE STM32_TIM3_BASE
# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32_TIM4_SDADC1)
# define SDADC1_HAVE_TIMER 1
# define SDADC1_TIMER_BASE STM32_TIM4_BASE
# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32_TIM13_SDADC1)
# define SDADC1_HAVE_TIMER 1
# define SDADC1_TIMER_BASE STM32_TIM13_BASE
# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM13_CLKIN
#elif defined(CONFIG_STM32_TIM14_SDADC1)
# define SDADC1_HAVE_TIMER 1
# define SDADC1_TIMER_BASE STM32_TIM14_BASE
# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM14_CLKIN
#elif defined(CONFIG_STM32_TIM15_SDADC1)
# define SDADC1_HAVE_TIMER 1
# define SDADC1_TIMER_BASE STM32_TIM15_BASE
# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
#elif defined(CONFIG_STM32_TIM19_SDADC1)
# define SDADC1_HAVE_TIMER 1
# define SDADC1_TIMER_BASE STM32_TIM19_BASE
# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN
#else
# undef SDADC1_HAVE_TIMER
#endif
#ifdef SDADC1_HAVE_TIMER
# ifndef CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32_SDADC1_TIMTRIG
# error "CONFIG_STM32_SDADC1_TIMTRIG not defined"
# warning "Values 0:TIM13_CH1 1:TIM14_CH1 2:TIM15_CH2 3:TIM3_CH1 4:TIM4_CH1 5:TIM19_CH2"
# endif
#endif
#if defined(CONFIG_STM32_TIM2_SDADC2)
# define SDADC2_HAVE_TIMER 1
# define SDADC2_TIMER_BASE STM32_TIM2_BASE
# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32_TIM3_SDADC2)
# define SDADC2_HAVE_TIMER 1
# define SDADC2_TIMER_BASE STM32_TIM3_BASE
# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32_TIM4_SDADC2)
# define SDADC2_HAVE_TIMER 1
# define SDADC2_TIMER_BASE STM32_TIM4_BASE
# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32_TIM12_SDADC2)
# define SDADC2_HAVE_TIMER 1
# define SDADC2_TIMER_BASE STM32_TIM12_BASE
# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN
#elif defined(CONFIG_STM32_TIM17_SDADC2)
# define SDADC2_HAVE_TIMER 1
# define SDADC2_TIMER_BASE STM32_TIM17_BASE
# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM17_CLKIN
#elif defined(CONFIG_STM32_TIM19_SDADC2)
# define SDADC2_HAVE_TIMER 1
# define SDADC2_TIMER_BASE STM32_TIM19_BASE
# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN
#else
# undef SDADC2_HAVE_TIMER
#endif
#ifdef SDADC2_HAVE_TIMER
# ifndef CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY
# error "CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32_SDADC2_TIMTRIG
# error "CONFIG_STM32_SDADC2_TIMTRIG not defined"
# warning "Values 0:TIM17_CH1 1:TIM12_CH1 2:TIM2_CH3 3:TIM3_CH2 4:TIM4_CH2 5:TIM19_CH3"
# endif
#endif
#if defined(CONFIG_STM32_TIM2_SDADC3)
# define SDADC3_HAVE_TIMER 1
# define SDADC3_TIMER_BASE STM32_TIM2_BASE
# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32_TIM3_SDADC3)
# define SDADC3_HAVE_TIMER 1
# define SDADC3_TIMER_BASE STM32_TIM3_BASE
# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32_TIM4_SDADC3)
# define SDADC3_HAVE_TIMER 1
# define SDADC3_TIMER_BASE STM32_TIM4_BASE
# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32_TIM12_SDADC3)
# define SDADC3_HAVE_TIMER 1
# define SDADC3_TIMER_BASE STM32_TIM12_BASE
# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN
#elif defined(CONFIG_STM32_TIM16_SDADC3)
# define SDADC3_HAVE_TIMER 1
# define SDADC3_TIMER_BASE STM32_TIM16_BASE
# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN
#elif defined(CONFIG_STM32_TIM19_SDADC3)
# define SDADC3_HAVE_TIMER 1
# define SDADC3_TIMER_BASE STM32_TIM19_BASE
# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN
#else
# undef SDADC3_HAVE_TIMER
#endif
#ifdef SDADC3_HAVE_TIMER
# ifndef CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY
# error "CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32_SDADC3_TIMTRIG
# error "CONFIG_STM32_SDADC3_TIMTRIG not defined"
# warning "Values 0:TIM16_CH1 1:TIM12_CH2 2:TIM2_CH4 3:TIM3_CH3 4:TIM4_CH3 5:TIM19_CH4"
# endif
#endif
#if defined(SDADC1_HAVE_TIMER) || defined(SDADC2_HAVE_TIMER) || \
defined(SDADC3_HAVE_TIMER)
# define SDADC_HAVE_TIMER 1
# if defined(CONFIG_STM32_STM32F37XX) && !defined(CONFIG_STM32_FORCEPOWER)
# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)"
# endif
#else
# undef SDADC_HAVE_TIMER
#endif
/* NOTE: The following assumes that all possible combinations of timers and
* values are support JEXTSEL. That is not so and it varies from one STM32
* to another. But this (wrong) assumptions keeps the logic as simple as
* possible. If unsupported combination is used, an error will show up
* later during compilation although it may be difficult to track it back
* to this simplification.
*
* STM32L37XX-family has 3 SDADC onboard
*/
#ifdef CONFIG_STM32_STM32F37XX
# define SDADC1_JEXTSEL_TIM13_CH1 SDADC1_CR2_JEXTSEL_TIM13_CH1
# define SDADC1_JEXTSEL_TIM14_CH1 SDADC1_CR2_JEXTSEL_TIM14_CH1
# define SDADC1_JEXTSEL_TIM15_CH2 SDADC1_CR2_JEXTSEL_TIM15_CH2
# define SDADC1_JEXTSEL_TIM3_CH1 SDADC1_CR2_JEXTSEL_TIM3_CH1
# define SDADC1_JEXTSEL_TIM4_CH1 SDADC1_CR2_JEXTSEL_TIM4_CH1
# define SDADC1_JEXTSEL_TIM19_CH2 SDADC1_CR2_JEXTSEL_TIM19_CH2
# define SDADC1_JEXTSEL_EXTI15 SDADC1_CR2_JEXTSEL_EXTI15
# define SDADC1_JEXTSEL_EXTI11 SDADC1_CR2_JEXTSEL_EXTI11
# define SDADC2_JEXTSEL_TIM17_CH1 SDADC2_CR2_JEXTSEL_TIM17_CH1
# define SDADC2_JEXTSEL_TIM12_CH1 SDADC2_CR2_JEXTSEL_TIM12_CH1
# define SDADC2_JEXTSEL_TIM2_CH3 SDADC2_CR2_JEXTSEL_TIM2_CH3
# define SDADC2_JEXTSEL_TIM3_CH2 SDADC2_CR2_JEXTSEL_TIM3_CH2
# define SDADC2_JEXTSEL_TIM4_CH2 SDADC2_CR2_JEXTSEL_TIM4_CH2
# define SDADC2_JEXTSEL_TIM19_CH3 SDADC2_CR2_JEXTSEL_TIM19_CH3
# define SDADC2_JEXTSEL_EXTI15 SDADC2_CR2_JEXTSEL_EXTI15
# define SDADC2_JEXTSEL_EXTI11 SDADC2_CR2_JEXTSEL_EXTI11
# define SDADC3_JEXTSEL_TIM16_CH1 SDADC3_CR2_JEXTSEL_TIM16_CH1
# define SDADC3_JEXTSEL_TIM12_CH1 SDADC3_CR2_JEXTSEL_TIM12_CH1
# define SDADC3_JEXTSEL_TIM2_CH4 SDADC3_CR2_JEXTSEL_TIM2_CH4
# define SDADC3_JEXTSEL_TIM3_CH3 SDADC3_CR2_JEXTSEL_TIM3_CH3
# define SDADC3_JEXTSEL_TIM4_CH3 SDADC3_CR2_JEXTSEL_TIM4_CH3
# define SDADC3_JEXTSEL_TIM19_CH4 SDADC3_CR2_JEXTSEL_TIM19_CH4
# define SDADC3_JEXTSEL_EXTI15 SDADC3_CR2_JEXTSEL_EXTI15
# define SDADC3_JEXTSEL_EXTI11 SDADC3_CR2_JEXTSEL_EXTI11
#endif
#if defined(CONFIG_STM32_TIM3_SDADC1)
# define SDADC1_JEXTSEL_VALUE 3
#elif defined(CONFIG_STM32_TIM4_SDADC1)
# define SDADC1_JEXTSEL_VALUE 4
#elif defined(CONFIG_STM32_TIM13_SDADC1)
# define SDADC1_JEXTSEL_VALUE 0
#elif defined(CONFIG_STM32_TIM14_SDADC1)
# define SDADC1_JEXTSEL_VALUE 1
#elif defined(CONFIG_STM32_TIM15_SDADC1)
# define SDADC1_JEXTSEL_VALUE 2
#elif defined(CONFIG_STM32_TIM19_SDADC1)
# define SDADC1_JEXTSEL_VALUE 5
#else
# undef SDADC1_JEXTSEL_VALUE
#endif
#if defined(CONFIG_STM32_TIM2_SDADC2)
# define SDADC2_JEXTSEL_VALUE 2
#elif defined(CONFIG_STM32_TIM3_SDADC2)
# define SDADC2_JEXTSEL_VALUE 3
#elif defined(CONFIG_STM32_TIM4_SDADC2)
# define SDADC2_JEXTSEL_VALUE 4
#elif defined(CONFIG_STM32_TIM12_SDADC2)
# define SDADC2_JEXTSEL_VALUE 1
#elif defined(CONFIG_STM32_TIM17_SDADC2)
# define SDADC2_JEXTSEL_VALUE 0
#elif defined(CONFIG_STM32_TIM19_SDADC2)
# define SDADC2_JEXTSEL_VALUE 5
#else
# undef SDADC2_JEXTSEL_VALUE
#endif
#if defined(CONFIG_STM32_TIM2_SDADC3)
# define SDADC3_JEXTSEL_VALUE 2
#elif defined(CONFIG_STM32_TIM3_SDADC3)
# define SDADC3_JEXTSEL_VALUE 3
#elif defined(CONFIG_STM32_TIM4_SDADC3)
# define SDADC3_JEXTSEL_VALUE 4
#elif defined(CONFIG_STM32_TIM12_SDADC3)
# define SDADC3_JEXTSEL_VALUE 1
#elif defined(CONFIG_STM32_TIM16_SDADC3)
# define SDADC3_JEXTSEL_VALUE 0
#elif defined(CONFIG_STM32_TIM19_SDADC3)
# define SDADC3_JEXTSEL_VALUE 5
#else
# undef SDADC3_JEXTSEL_VALUE
#endif
/* SDADC Configurations ********************************************************
* Up to 3 configuration profiles may be defined in order to define:
* - calibration method
* - SE/differential mode
* - input gain
* Each of the 9 SDADC channels is assigned to a configuration profile
*/
#ifndef SDADC_CONF0R_DEFAULT
# define SDADC_CONF0R_DEFAULT (SDADC_CONFR_GAIN_1X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND)
#endif
#ifndef SDADC_CONF1R_DEFAULT
# define SDADC_CONF1R_DEFAULT (SDADC_CONFR_GAIN_2X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND)
#endif
#ifndef SDADC_CONF2R_DEFAULT
# define SDADC_CONF2R_DEFAULT (SDADC_CONFR_GAIN_4X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND)
#endif
#ifndef SDADC_CONFCHR1_DEFAULT
# define SDADC_CONFCHR1_DEFAULT ((SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(0)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(1)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(2)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(3)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(4)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(5)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(6)) | \
(SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(7)))
#endif
#ifndef SDADC_CONFCHR2_DEFAULT
# define SDADC_CONFCHR2_DEFAULT (SDADC_CONF0R << SDADC_CONFCHR2_CH8_SHIFT)
#endif
/* SDADC Reference voltage selection ************************************************/
#ifndef SDADC_REFV_DEFAULT
# define SDADC_REFV_DEFAULT SDADC_CR1_REFV_EXT
#endif
#ifndef SDADC1_REFV
# define SDADC1_REFV SDADC_REFV_DEFAULT
#endif
#ifndef SDADC2_REFV
# define SDADC2_REFV SDADC_REFV_DEFAULT
#endif
#ifndef SDADC3_REFV
# define SDADC3_REFV SDADC_REFV_DEFAULT
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_sdadcinitialize
*
****************************************************************************/
struct adc_dev_s *stm32_sdadcinitialize(int intf, FAR const uint8_t *chanlist,
int nchannels);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 ||
* CONFIG_STM32_SDADC3
*/
#endif /* __ARCH_ARM_SRC_STM32_STM32_SDADC_H */
arch/arm/src/stm32/stm32f30xxx_i2c.c
+2 -2
View File
@@ -101,7 +101,7 @@
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
/* This implementation is for the STM32 F1, F2, and F4 only */
#if defined(CONFIG_STM32_STM32F30XX)
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
/************************************************************************************
* Pre-processor Definitions
@@ -1949,7 +1949,7 @@ out:
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
{
struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
irqtate_t flags;
irqstate_t flags;
#if STM32_PCLK1_FREQUENCY < 4000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
arch/arm/src/stm32/stm32f37xxx_rcc.c
+52 -5
View File
@@ -80,7 +80,7 @@ static inline void rcc_reset(void)
regval |= RCC_CR_HSION;
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, USBPRE, and MCO bits */
regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE, USBPRE, MCO, SDADC bits */
regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
RCC_CFGR_PPRE2_MASK | RCC_CFGR_USBPRE | RCC_CFGR_MCO_MASK);
putreg32(regval, STM32_RCC_CFGR);
@@ -107,6 +107,7 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
}
/****************************************************************************
* Name: rcc_enableahb
*
@@ -169,7 +170,7 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32_USB
/* USB clock divider. This bit must be valid before enabling the USB
* clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
* clock in the RCC_APB1ENR register. This bit can't be reset if the USB
* clock is enabled.
*/
@@ -356,6 +357,28 @@ static inline void rcc_enableapb2(void)
{
uint32_t regval;
#if defined(CONFIG_STM32_SDADC) || defined(CONFIG_STM32_ADC)
/* Adjust clock of selected peripherals */
regval = getreg32(STM32_RCC_CFGR);
#ifdef CONFIG_STM32_ADC
/* ADC clock divider */
regval &= ~RCC_CFGR_ADCPRE_MASK;
regval |= STM32_RCC_ADCPRE;
#endif
#ifdef CONFIG_STM32_SDADC
/* SDADC clock divider */
regval &= ~RCC_CFGR_SDPRE_MASK;
regval |= STM32_RCC_SDPRE;
#endif
putreg32(regval, STM32_RCC_CFGR);
#endif
/* Set the appropriate bits in the APB2ENR register to enabled the
* selected APB2 peripherals.
*/
@@ -368,6 +391,12 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32_ADC1
/* ADC clock enable */
regval |= RCC_APB2ENR_ADC1EN;
#endif
#ifdef CONFIG_STM32_SPI1
/* SPI 1 clock enable */
@@ -412,6 +441,24 @@ static inline void rcc_enableapb2(void)
#endif
#endif
#ifdef CONFIG_STM32_SDADC1
/* SDCADC1 clock enable */
regval |= RCC_APB2ENR_SDADC1EN;
#endif
#ifdef CONFIG_STM32_SDADC2
/* SDCADC2 clock enable */
regval |= RCC_APB2ENR_SDADC2EN;
#endif
#ifdef CONFIG_STM32_SDADC3
/* SDCADC3 clock enable */
regval |= RCC_APB2ENR_SDADC3EN;
#endif
putreg32(regval, STM32_RCC_APB2ENR);
}
@@ -469,13 +516,13 @@ static void stm32_stdclockconfig(void)
/* If this is a value-line part and we are using the HSE as the PLL */
# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV & 1)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV
# endif
/* Set the HSE prescaler */
regval = STM32_CFGR2_PREDIV1;
regval = STM32_CFGR2_PREDIV;
putreg32(regval, STM32_RCC_CFGR2);
# endif
arch/xtensa/include/esp32/irq.h
+286 -96
View File
@@ -50,29 +50,6 @@
* Pre-processor Definitions
****************************************************************************/
/* Exceptions
*
* IRAM Offset Description
* 0x0000 Windows
* 0x0180 Level 2 interrupt
* 0x01c0 Level 3 interrupt
* 0x0200 Level 4 interrupt
* 0x0240 Level 5 interrupt
* 0x0280 Debug exception
* 0x02c0 NMI exception
* 0x0300 Kernel exception
* 0x0340 User exception
* 0x03c0 Double exception
*
* REVISIT: In more architectures supported by NuttX, exception errors
* tie into the normal interrupt handling via special IRQ numbers. I
* is still to be determined what will be done for the ESP32.
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
/* Interrupt Matrix
*
* The Interrupt Matrix embedded in the ESP32 independently allocates
@@ -102,94 +79,307 @@
/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */
#define XTENSA_IRQ_SREG0 3
#define XTENSA_IRQ_MAC 3 /* INTR_STATUS_REG_0, bit 0 */
#define XTENSA_IRQ_MAC_NMI 4 /* INTR_STATUS_REG_0, bit 1 */
#define XTENSA_IRQ_BB 5 /* INTR_STATUS_REG_0, bit 2 */
#define XTENSA_IRQ_BB_MAC 6 /* INTR_STATUS_REG_0, bit 3 */
#define XTENSA_IRQ_BT_BB 7 /* INTR_STATUS_REG_0, bit 4 */
#define XTENSA_IRQ_BT_BB_NMI 8 /* INTR_STATUS_REG_0, bit 5 */
#define XTENSA_IRQ_RWBT_IRQ 9 /* INTR_STATUS_REG_0, bit 6 */
#define XTENSA_IRQ_RWBLE_IRQ 10 /* INTR_STATUS_REG_0, bit 7 */
#define XTENSA_IRQ_RWBT_NMI 11 /* INTR_STATUS_REG_0, bit 8 */
#define XTENSA_IRQ_RWBLE_NMI 12 /* INTR_STATUS_REG_0, bit 9 */
#define ESP32_PERIPH_MAC 0 /* INTR_STATUS_REG_0, bit 0 */
#define ESP32_PERIPH_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */
#define ESP32_PERIPH_BB 2 /* INTR_STATUS_REG_0, bit 2 */
#define ESP32_PERIPH_BB_MAC 3 /* INTR_STATUS_REG_0, bit 3 */
#define ESP32_PERIPH_BT_BB 4 /* INTR_STATUS_REG_0, bit 4 */
#define ESP32_PERIPH_BT_BB_NMI 5 /* INTR_STATUS_REG_0, bit 5 */
#define ESP32_PERIPH_RWBT_IRQ 6 /* INTR_STATUS_REG_0, bit 6 */
#define ESP32_PERIPH_RWBLE_IRQ 7 /* INTR_STATUS_REG_0, bit 7 */
#define ESP32_PERIPH_RWBT_NMI 8 /* INTR_STATUS_REG_0, bit 8 */
#define ESP32_PERIPH_RWBLE_NMI 9 /* INTR_STATUS_REG_0, bit 9 */
#define XTENSA_IRQ_SLC0 13 /* INTR_STATUS_REG_0, bit 10 */
#define XTENSA_IRQ_SLC1 14 /* INTR_STATUS_REG_0, bit 11 */
#define XTENSA_IRQ_UHCI0 15 /* INTR_STATUS_REG_0, bit 12 */
#define XTENSA_IRQ_UHCI1 16 /* INTR_STATUS_REG_0, bit 13 */
#define XTENSA_IRQ_TG_T0_LEVEL 17 /* INTR_STATUS_REG_0, bit 14 */
#define XTENSA_IRQ_TG_T1_LEVEL 18 /* INTR_STATUS_REG_0, bit 15 */
#define XTENSA_IRQ_TG_WDT_LEVEL 19 /* INTR_STATUS_REG_0, bit 16 */
#define XTENSA_IRQ_TG_LACT_LEVEL 20 /* INTR_STATUS_REG_0, bit 17 */
#define XTENSA_IRQ_TG1_T0_LEVEL 21 /* INTR_STATUS_REG_0, bit 18 */
#define XTENSA_IRQ_TG1_T1_LEVEL 22 /* INTR_STATUS_REG_0, bit 19 */
#define ESP32_PERIPH_SLC0 10 /* INTR_STATUS_REG_0, bit 10 */
#define ESP32_PERIPH_SLC1 11 /* INTR_STATUS_REG_0, bit 11 */
#define ESP32_PERIPH_UHCI0 12 /* INTR_STATUS_REG_0, bit 12 */
#define ESP32_PERIPH_UHCI1 13 /* INTR_STATUS_REG_0, bit 13 */
#define ESP32_PERIPH_TG_T0_LEVEL 14 /* INTR_STATUS_REG_0, bit 14 */
#define ESP32_PERIPH_TG_T1_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */
#define ESP32_PERIPH_TG_WDT_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */
#define ESP32_PERIPH_TG_LACT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */
#define ESP32_PERIPH_TG1_T0_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */
#define ESP32_PERIPH_TG1_T1_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */
#define XTENSA_IRQ_TG1_WDT_LEVEL 23 /* INTR_STATUS_REG_0, bit 20 */
#define XTENSA_IRQ_G1_LACT_LEVEL 24 /* INTR_STATUS_REG_0, bit 21 */
#define XTENSA_IRQ_CPU_GPIO 25 /* INTR_STATUS_REG_0, bit 22 */
#define XTENSA_IRQ_CPU_NMI 26 /* INTR_STATUS_REG_0, bit 23 */
#define XTENSA_IRQ_CPU_CPU0 27 /* INTR_STATUS_REG_0, bit 24 */
#define XTENSA_IRQ_CPU_CPU1 28 /* INTR_STATUS_REG_0, bit 25 */
#define XTENSA_IRQ_CPU_CPU2 29 /* INTR_STATUS_REG_0, bit 26 */
#define XTENSA_IRQ_CPU_CPU3 30 /* INTR_STATUS_REG_0, bit 27 */
#define XTENSA_IRQ_SPI0 31 /* INTR_STATUS_REG_0, bit 28 */
#define XTENSA_IRQ_SPI1 32 /* INTR_STATUS_REG_0, bit 29 */
#define ESP32_PERIPH_TG1_WDT_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */
#define ESP32_PERIPH_G1_LACT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */
#define ESP32_PERIPH_CPU_GPIO 22 /* INTR_STATUS_REG_0, bit 22 */
#define ESP32_PERIPH_CPU_NMI 23 /* INTR_STATUS_REG_0, bit 23 */
#define ESP32_PERIPH_CPU_CPU0 24 /* INTR_STATUS_REG_0, bit 24 */
#define ESP32_PERIPH_CPU_CPU1 25 /* INTR_STATUS_REG_0, bit 25 */
#define ESP32_PERIPH_CPU_CPU2 26 /* INTR_STATUS_REG_0, bit 26 */
#define ESP32_PERIPH_CPU_CPU3 27 /* INTR_STATUS_REG_0, bit 27 */
#define ESP32_PERIPH_SPI0 28 /* INTR_STATUS_REG_0, bit 28 */
#define ESP32_PERIPH_SPI1 29 /* INTR_STATUS_REG_0, bit 29 */
#define XTENSA_IRQ_SPI2 33 /* INTR_STATUS_REG_0, bit 30 */
#define XTENSA_IRQ_SPI3 34 /* INTR_STATUS_REG_0, bit 31 */
#define ESP32_PERIPH_SPI2 30 /* INTR_STATUS_REG_0, bit 30 */
#define ESP32_PERIPH_SPI3 31 /* INTR_STATUS_REG_0, bit 31 */
/* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */
#define XTENSA_IRQ_SREG1 35
#define XTENSA_IRQ_I2S0 35 /* INTR_STATUS_REG_1, bit 0 */
#define XTENSA_IRQ_I2S1 36 /* INTR_STATUS_REG_1, bit 1 */
#define XTENSA_IRQ_UART 37 /* INTR_STATUS_REG_1, bit 2 */
#define XTENSA_IRQ_UART1 38 /* INTR_STATUS_REG_1, bit 3 */
#define XTENSA_IRQ_UART2 39 /* INTR_STATUS_REG_1, bit 4 */
#define XTENSA_IRQ_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 5 */
#define XTENSA_IRQ_EMAC 41 /* INTR_STATUS_REG_1, bit 6 */
#define XTENSA_IRQ_PWM0 42 /* INTR_STATUS_REG_1, bit 7 */
#define XTENSA_IRQ_PWM1 43 /* INTR_STATUS_REG_1, bit 8 */
#define XTENSA_IRQ_PWM2 44 /* INTR_STATUS_REG_1, bit 9 */
#define ESP32_PERIPH_I2S0 32 /* INTR_STATUS_REG_1, bit 0 */
#define ESP32_PERIPH_I2S1 33 /* INTR_STATUS_REG_1, bit 1 */
#define ESP32_PERIPH_UART 34 /* INTR_STATUS_REG_1, bit 2 */
#define ESP32_PERIPH_UART1 35 /* INTR_STATUS_REG_1, bit 3 */
#define ESP32_PERIPH_UART2 36 /* INTR_STATUS_REG_1, bit 4 */
#define ESP32_PERIPH_SDIO_HOST 37 /* INTR_STATUS_REG_1, bit 5 */
#define ESP32_PERIPH_EMAC 38 /* INTR_STATUS_REG_1, bit 6 */
#define ESP32_PERIPH_PWM0 39 /* INTR_STATUS_REG_1, bit 7 */
#define ESP32_PERIPH_PWM1 40 /* INTR_STATUS_REG_1, bit 8 */
#define ESP32_PERIPH_PWM2 41 /* INTR_STATUS_REG_1, bit 9 */
#define XTENSA_IRQ_PWM3 45 /* INTR_STATUS_REG_1, bit 10 */
#define XTENSA_IRQ_LEDC 46 /* INTR_STATUS_REG_1, bit 11 */
#define XTENSA_IRQ_EFUSE 47 /* INTR_STATUS_REG_1, bit 12 */
#define XTENSA_IRQ_CAN 48 /* INTR_STATUS_REG_1, bit 13 */
#define XTENSA_IRQ_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 14 */
#define XTENSA_IRQ_RMT 50 /* INTR_STATUS_REG_1, bit 15 */
#define XTENSA_IRQ_PCNT 51 /* INTR_STATUS_REG_1, bit 16 */
#define XTENSA_IRQ_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 17 */
#define XTENSA_IRQ_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 18 */
#define XTENSA_IRQ_RSA 54 /* INTR_STATUS_REG_1, bit 19 */
#define ESP32_PERIPH_PWM3 42 /* INTR_STATUS_REG_1, bit 10 */
#define ESP32_PERIPH_LEDC 43 /* INTR_STATUS_REG_1, bit 11 */
#define ESP32_PERIPH_EFUSE 44 /* INTR_STATUS_REG_1, bit 12 */
#define ESP32_PERIPH_CAN 45 /* INTR_STATUS_REG_1, bit 13 */
#define ESP32_PERIPH_RTC_CORE 46 /* INTR_STATUS_REG_1, bit 14 */
#define ESP32_PERIPH_RMT 47 /* INTR_STATUS_REG_1, bit 15 */
#define ESP32_PERIPH_PCNT 48 /* INTR_STATUS_REG_1, bit 16 */
#define ESP32_PERIPH_I2C_EXT0 49 /* INTR_STATUS_REG_1, bit 17 */
#define ESP32_PERIPH_I2C_EXT1 50 /* INTR_STATUS_REG_1, bit 18 */
#define ESP32_PERIPH_RSA 51 /* INTR_STATUS_REG_1, bit 19 */
#define XTENSA_IRQ_SPI1_DMA 55 /* INTR_STATUS_REG_1, bit 20 */
#define XTENSA_IRQ_SPI2_DMA 56 /* INTR_STATUS_REG_1, bit 21 */
#define XTENSA_IRQ_SPI3_DMA 57 /* INTR_STATUS_REG_1, bit 22 */
#define XTENSA_IRQ_WDG 58 /* INTR_STATUS_REG_1, bit 23 */
#define XTENSA_IRQ_TIMER1 59 /* INTR_STATUS_REG_1, bit 24 */
#define XTENSA_IRQ_TIMER2 60 /* INTR_STATUS_REG_1, bit 25 */
#define XTENSA_IRQ_TG_T0_EDGE 61 /* INTR_STATUS_REG_1, bit 26 */
#define XTENSA_IRQ_TG_T1_EDGE 62 /* INTR_STATUS_REG_1, bit 27 */
#define XTENSA_IRQ_TG_WDT_EDGE 63 /* INTR_STATUS_REG_1, bit 28 */
#define XTENSA_IRQ_TG_LACT_EDGE 64 /* INTR_STATUS_REG_1, bit 29 */
#define ESP32_PERIPH_SPI1_DMA 52 /* INTR_STATUS_REG_1, bit 20 */
#define ESP32_PERIPH_SPI2_DMA 53 /* INTR_STATUS_REG_1, bit 21 */
#define ESP32_PERIPH_SPI3_DMA 54 /* INTR_STATUS_REG_1, bit 22 */
#define ESP32_PERIPH_WDG 55 /* INTR_STATUS_REG_1, bit 23 */
#define ESP32_PERIPH_TIMER1 56 /* INTR_STATUS_REG_1, bit 24 */
#define ESP32_PERIPH_TIMER2 57 /* INTR_STATUS_REG_1, bit 25 */
#define ESP32_PERIPH_TG_T0_EDGE 58 /* INTR_STATUS_REG_1, bit 26 */
#define ESP32_PERIPH_TG_T1_EDGE 59 /* INTR_STATUS_REG_1, bit 27 */
#define ESP32_PERIPH_TG_WDT_EDGE 60 /* INTR_STATUS_REG_1, bit 28 */
#define ESP32_PERIPH_TG_LACT_EDGE 61 /* INTR_STATUS_REG_1, bit 29 */
#define XTENSA_IRQ_TG1_T0_EDGE 65 /* INTR_STATUS_REG_1, bit 30 */
#define XTENSA_IRQ_TG1_T1_EDGE 66 /* INTR_STATUS_REG_1, bit 31 */
#define ESP32_PERIPH_TG1_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */
#define ESP32_PERIPH_TG1_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */
/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */
#define XTENSA_IRQ_SREG2 67
#define XTENSA_IRQ_TG1_WDT_EDGE 67 /* INTR_STATUS_REG_2, bit 0 */
#define XTENSA_IRQ_TG1_LACT_EDGE 68 /* INTR_STATUS_REG_2, bit 1 */
#define XTENSA_IRQ_MMU_IA 69 /* INTR_STATUS_REG_2, bit 2 */
#define XTENSA_IRQ_MPU_IA 70 /* INTR_STATUS_REG_2, bit 3 */
#define XTENSA_IRQ_CACHE_IA 71 /* INTR_STATUS_REG_2, bit 4 */
#define ESP32_PERIPH_TG1_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */
#define ESP32_PERIPH_TG1_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */
#define ESP32_PERIPH_MMU_IA 66 /* INTR_STATUS_REG_2, bit 2 */
#define ESP32_PERIPH_MPU_IA 67 /* INTR_STATUS_REG_2, bit 3 */
#define ESP32_PERIPH_CACHE_IA 68 /* INTR_STATUS_REG_2, bit 4 */
/* Total number of peripherals */
#define NR_PERIPHERALS 69
/* Exceptions
*
* IRAM Offset Description
* 0x0000 Windows
* 0x0180 Level 2 interrupt
* 0x01c0 Level 3 interrupt
* 0x0200 Level 4 interrupt
* 0x0240 Level 5 interrupt
* 0x0280 Debug exception
* 0x02c0 NMI exception
* 0x0300 Kernel exception
* 0x0340 User exception
* 0x03c0 Double exception
*
* REVISIT: In more architectures supported by NuttX, exception errors
* tie into the normal interrupt handling via special IRQ numbers. I
* is still to be determined what will be done for the ESP32.
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_FIRSTPERIPH 3 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming throught the Interrupt
* Matrix.
*/
#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH)
/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */
#define ESP32_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MAC)
#define ESP32_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MAC_NMI)
#define ESP32_IRQ_BB (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BB)
#define ESP32_IRQ_BB_MAC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BB_MAC)
#define ESP32_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BT_BB)
#define ESP32_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BT_BB_NMI)
#define ESP32_IRQ_RWBT_IRQ (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBT_IRQ)
#define ESP32_IRQ_RWBLE_IRQ (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBLE_IRQ)
#define ESP32_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBT_NMI)
#define ESP32_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBLE_NMI)
#define ESP32_IRQ_SLC0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SLC0)
#define ESP32_IRQ_SLC1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SLC1)
#define ESP32_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UHCI0)
#define ESP32_IRQ_UHCI1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UHCI1)
#define ESP32_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T0_LEVEL)
#define ESP32_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T1_LEVEL)
#define ESP32_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_WDT_LEVEL)
#define ESP32_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_LACT_LEVEL)
#define ESP32_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T0_LEVEL)
#define ESP32_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T1_LEVEL)
#define ESP32_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_WDT_LEVEL)
#define ESP32_IRQ_G1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_G1_LACT_LEVEL)
#define ESP32_IRQ_CPU_GPIO (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_GPIO)
#define ESP32_IRQ_CPU_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_NMI)
#define ESP32_IRQ_CPU_CPU0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU0)
#define ESP32_IRQ_CPU_CPU1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU1)
#define ESP32_IRQ_CPU_CPU2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU2)
#define ESP32_IRQ_CPU_CPU3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU3)
#define ESP32_IRQ_SPI0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI0)
#define ESP32_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI1
#define ESP32_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI2)
#define ESP32_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI3
#define ESP32_IRQ_SREG0 ESP32_IRQ_MAC
#define ESP32_NIRQS_SREG0 32
/* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */
#define ESP32_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2S0)
#define ESP32_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2S1)
#define ESP32_IRQ_UART (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UART)
#define ESP32_IRQ_UART1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UART1)
#define ESP32_IRQ_UART2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UART2)
#define ESP32_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SDIO_HOST)
#define ESP32_IRQ_EMAC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_EMAC)
#define ESP32_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM0)
#define ESP32_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM1)
#define ESP32_IRQ_PWM2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM2)
#define ESP32_IRQ_PWM3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM3)
#define ESP32_IRQ_LEDC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_LEDC)
#define ESP32_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_EFUSE)
#define ESP32_IRQ_CAN (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CAN)
#define ESP32_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RTC_CORE)
#define ESP32_IRQ_RMT (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RMT)
#define ESP32_IRQ_PCNT (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PCNT)
#define ESP32_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2C_EXT0)
#define ESP32_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2C_EXT1)
#define ESP32_IRQ_RSA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RSA)
#define ESP32_IRQ_SPI1_DMA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI1_DMA)
#define ESP32_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI2_DMA)
#define ESP32_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI3_DMA)
#define ESP32_IRQ_WDG (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_WDG)
#define ESP32_IRQ_TIMER1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TIMER1)
#define ESP32_IRQ_TIMER2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TIMER2)
#define ESP32_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T0_EDGE)
#define ESP32_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T1_EDGE)
#define ESP32_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_WDT_EDGE)
#define ESP32_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_LACT_EDGE)
#define ESP32_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T0_EDGE)
#define ESP32_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T1_EDGE)
#define ESP32_IRQ_SREG1 ESP32_IRQ_I2S0
#define ESP32_NIRQS_SREG1 32
/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */
#define ESP32_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_WDT_EDGE)
#define ESP32_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_LACT_EDGE)
#define ESP32_IRQ_MMU_IA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MMU_IA)
#define ESP32_IRQ_MPU_IA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MPU_IA)
#define ESP32_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CACHE_IA)
#define ESP32_IRQ_SREG2 ESP32_IRQ_TG1_WDT_EDGE
#define ESP32_NIRQS_SREG2 5
/* Total number of interrupts */
#define NR_IRQS 72
#define NR_IRQS (ESP32_IRQ_CACHE_IA+1)
/* CPU Interrupts.
*
* Each of the two CPUs (PRO and APP) have 32 interrupts each, of which
* 26 can be mapped to peripheral interrupts:
*
* Level triggered peripherals (21 total):
* 0-5, 8-9, 12-13, 17-18 - Priority 1
* 19-21 - Priority 2
* 23, 27 - Priority 3
* 24-25 - Priority 4
* 26, 31 - Priority 5
* Edge triggered peripherals (4 total):
* 10 - Priority 1
* 22 - Priority 3
* 28, 30 - Priority 4
* NMI (1 total):
* 14 - NMI
*
* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
* PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
* each peripheral source. Multiple peripheral interrupt sources can be
* mapped to the same.
*
* The remaining, five, internal CPU interrupts are:
*
* 6 Timer0 - Priority 1
* 7 Software - Priority 1
* 11 Profiling - Priority 3
* 15 Timer1 - Priority 3
* 16 Timer2 - Priority 5
* 29 Software - Priority 3
*
* A peripheral interrupt can be disabled
*/
#define ESP32_CPUINT_LEVELPERIPH_0 0
#define ESP32_CPUINT_LEVELPERIPH_1 1
#define ESP32_CPUINT_LEVELPERIPH_2 2
#define ESP32_CPUINT_LEVELPERIPH_3 3
#define ESP32_CPUINT_LEVELPERIPH_4 4
#define ESP32_CPUINT_LEVELPERIPH_5 5
#define ESP32_CPUINT_LEVELPERIPH_6 8
#define ESP32_CPUINT_LEVELPERIPH_7 9
#define ESP32_CPUINT_LEVELPERIPH_8 12
#define ESP32_CPUINT_LEVELPERIPH_9 13
#define ESP32_CPUINT_LEVELPERIPH_10 17
#define ESP32_CPUINT_LEVELPERIPH_11 18
#define ESP32_CPUINT_LEVELPERIPH_12 19
#define ESP32_CPUINT_LEVELPERIPH_13 20
#define ESP32_CPUINT_LEVELPERIPH_14 21
#define ESP32_CPUINT_LEVELPERIPH_15 23
#define ESP32_CPUINT_LEVELPERIPH_16 24
#define ESP32_CPUINT_LEVELPERIPH_17 25
#define ESP32_CPUINT_LEVELPERIPH_18 26
#define ESP32_CPUINT_LEVELPERIPH_19 27
#define ESP32_CPUINT_LEVELPERIPH_20 31
#define ESP32_CPUINT_NLEVELPERIPHS 21
#define ESP32_CPUINT_EDGEPERIPH_0 10
#define ESP32_CPUINT_EDGEPERIPH_1 22
#define ESP32_CPUINT_EDGEPERIPH_2 28
#define ESP32_CPUINT_EDGEPERIPH_3 30
#define ESP32_CPUINT_NEDGEPERIPHS 4
#define ESP32_CPUINT_TIMER0 6
#define ESP32_CPUINT_SOFTWARE0 7
#define ESP32_CPUINT_TIMER1 15
#define ESP32_CPUINT_TIMER2 16
#define ESP32_CPUINT_SOFTWARE1 29
#define ESP32_CPUINT_NINTERNAL 5
#define ESP32_CPUINT_MAX 31
#define EPS32_CPUINT_PERIPHSET 0xdffe7f3f
#define EPS32_CPUINT_INTERNALSET 0x200180c0
/* Priority 1: 0-10, 12-13, 17-18 (15)
* Priority 2: 19-21 (3)
* Priority 3: 11, 15, 22-23, 27, 29 (6)
* Priority 4: 24-25, 28, 30 (4)
* Priority 5: 16, 26, 31 (3)
* Priority NMI: 14 (1)
*/
#define ESP32_INTPRI1_MASK 0x000637ff
#define ESP32_INTPRI2_MASK 0x00380000
#define ESP32_INTPRI3_MASK 0x28c08800
#define ESP32_INTPRI4_MASK 0x53000000
#define ESP32_INTPRI5_MASK 0x84010000
#define ESP32_INTNMI_MASK 0x00004000
/****************************************************************************
* Public Types
arch/xtensa/src/common/xtensa.h
+2 -7
View File
@@ -156,13 +156,6 @@ extern volatile uint32_t *g_current_regs[1];
#endif
/* This is the beginning of heap as provided from *_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The end
* of the heap is CONFIG_RAM_END
*/
extern uint32_t g_idle_topstack;
/* Address of the saved user stack pointer */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
@@ -243,6 +236,8 @@ void xtensa_dumpstate(void);
uint32_t *xtensa_int_decode(uint32_t *regs);
uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs);
uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask);
uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask);
/* Software interrupt handler */
arch/xtensa/src/common/xtensa_cpuint.S
+126
View File
@@ -0,0 +1,126 @@
/****************************************************************************
* arch/xtensa/src/common/xtensa_cpuint.S
*
* Adapted from use in NuttX by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives from logic originally provided by Cadence Design Systems Inc.
*
* Copyright (c) 2006-2015 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
.file "xtensa_cpuint.S"
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/core-isa.h>
#if XCHAL_HAVE_INTERRUPTS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_enable_cpuint
*
* C Prototype:
* uint32_t xtensa_enable_cpuint(uint32_t *shadow, unsigned int intmask)
*
* Description:
* Enables a set of interrupts. Does not simply set INTENABLE directly,
* but operates on a shadow copy of the CPU INTENABLE register then
* writes that value to the hardware INTENABLE register. Can be called
* from interrupt handlers.
*
* NOTE: It is possible only to enable interrupts on the current CPU
* because there is an INTENABLE register implemented in each CPU.
*
****************************************************************************/
.text
.global xtensa_enable_cpuint
.type xtensa_enable_cpuint, @function
.align 4
xtensa_enable_cpuint:
movi a4, 0
xsr a4, INTENABLE /* Disables all interrupts */
rsync
l32i a4, a2, 0 /* a4 = value of INTENABLE shadow */
or a5, a4, a3 /* a5 = shadow | mask */
s32i a5, a2, 0 /* shadow |= mask */
wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */
mov a3, a4 /* Return previous shadow content */
ret
.size xtensa_enable_cpuint, . - xtensa_enable_cpuint
/****************************************************************************
* Name: xtensa_disable_cpuint
*
* C Prototype:
* uint32_t xtensa_disable_cpuint(uint32_t *shadow, unsigned int intmask)
*
* Description:
* Disables a set of interrupts. Does not simply set INTENABLE directly,
* but operates on a shadow copy of the CPU INTENABLE register then
* writes that value to the hardware INTENABLE register. Can be called
* from interrupt handlers.
*
* NOTE: It is possible only to enable interrupts on the current CPU
* because there is an INTENABLE register implemented in each CPU.
*
****************************************************************************/
.text
.global xtensa_disable_cpuint
.type xtensa_disable_cpuint, @function
.align 4
xtensa_disable_cpuint:
movi a4, 0
xsr a4, INTENABLE /* Disables all interrupts */
rsync
l32i a4, a2, 0 /* a4 = value of INTENABLE shadow */
or a5, a4, a3 /* a5 = shadow | mask */
xor a5, a5, a3 /* a5 = shadow & ~mask */
s32i a5, a2, 0 /* shadow &= ~mask */
wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */
mov a3, a4 /* Return previous shadow content */
ret
.size xtensa_disable_cpuint, . - xtensa_disable_cpuint
#endif /* XCHAL_HAVE_INTERRUPTS */
arch/xtensa/src/common/xtensa_dumpstate.c
+12
View File
@@ -150,12 +150,24 @@ void xtensa_dumpstate(void)
uint32_t istacksize;
#endif
#ifdef CONFIG_SMP
/* Show the CPU number */
_alert("CPU%d:\n", up_cpu_index());
#endif
/* Get the limits on the user stack memory */
if (rtcb->pid == 0)
{
#warning REVISIT: Need top of IDLE stack
#if 0
ustackbase = g_idle_topstack - 4;
ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
#else
ustackbase = sp + 128;
ustacksize = 128;
#endif
}
else
{
arch/xtensa/src/common/xtensa_inthandlers.S
+1 -1
View File
@@ -62,9 +62,9 @@
#include <arch/irq.h>
#include <arch/chip/core-isa.h>
#include <arch/xtensa/xtensa_specregs.h>
#include <arch/chip/chip_macros.h>
#include "xtensa_macros.h"
#include "chip_macros.h"
#include "xtensa_timer.h"
/****************************************************************************
arch/xtensa/src/common/xtensa_nmihandler.S
+1 -1
View File
@@ -61,8 +61,8 @@
#include <arch/chip/core-isa.h>
#include <arch/xtensa/xtensa_specregs.h>
#include <arch/chip/chip_macros.h>
#include "chip_macros.h"
#include "xtensa_macros.h"
/****************************************************************************
arch/xtensa/src/esp32/Make.defs
+13 -12
View File
@@ -40,18 +40,18 @@ HEAD_CSRC = esp32_start.c
# Common XTENSA files (arch/xtensa/src/common)
CMN_ASRCS = xtensa_context.S xtensa_vectors.S xtensa_inthandlers.S
CMN_ASRCS += xtensa_nmihandler.S
CMN_ASRCS = xtensa_context.S xtensa_cpuint.S xtensa_vectors.S
CMN_ASRCS += xtensa_inthandlers.S xtensa_nmihandler.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c xtensa_lowputs.c
CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c
CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasepending.c
CMN_CSRCS += xtensa_releasestack.c xtensa_reprioritizertr.c
CMN_CSRCS += xtensa_schedsigaction.c xtensa_sigdeliver.c xtensa_stackframe.c
CMN_CSRCS += xtensa_udelay.c xtensa_unblocktask.c xtensa_usestack.c
CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
# Configuration-dependent common XTENSA files
@@ -77,8 +77,9 @@ endif
# Required ESP32 files (arch/xtensa/src/lx6)
CHIP_ASRCS =
CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_irq.c
CHIP_CSRCS += esp32_region.c esp32_start.c esp32_timerisr.c
CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c
CHIP_CSRCS += esp32_intdecode.c esp32_irq.c esp32_region.c esp32_start.c
CHIP_CSRCS += esp32_timerisr.c
# Configuration-dependent ESP32 files
arch/xtensa/src/esp32/chip/esp32_uart.h
+1668
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_clockconfig.c
+8 -4
View File
@@ -13,7 +13,7 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
@@ -26,21 +26,24 @@
/****************************************************************************
* Included Files
****************************************************************************
****************************************************************************/
#include <stdint.h>
#include "xtensa.h"
#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG
#warning REVISIT ... function prototypes
void phy_get_romfunc_addr(void);
void rtc_init_lite(void);
void rtc_set_cpu_freq(xtal_freq_t xtal_freq, enum xtal_freq_e cpu_freq);
#endif
/****************************************************************************
* Private Types
****************************************************************************
****************************************************************************/
#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG
enum xtal_freq_e
{
XTAL_40M = 40,
@@ -55,10 +58,11 @@ enum xtal_freq_e
CPU_160M = 2,
CPU_240M = 3,
};
#endif
/****************************************************************************
* Public Functions
****************************************************************************
****************************************************************************/
/****************************************************************************
* Name: esp32_clockconfig
arch/xtensa/src/esp32/esp32_cpuint.c
+510
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_cpuint.h
+154
View File
@@ -0,0 +1,154 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_cpuint.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H 1
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_alloc_levelint
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated level-sensitive, CPU interrupt numbr is
* returned. A negated errno is returned on failure. The only possible
* failure is that all level-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32_alloc_levelint(int priority);
/****************************************************************************
* Name: esp32_free_levelint
*
* Description:
* Free a previoulsy allocated level CPU interrupt
*
* Input Parameters:
* cpuint - The CPU interrupt number to be freed
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_free_levelint(int cpuint);
/****************************************************************************
* Name: esp32_alloc_edgeint
*
* Description:
* Allocate an edge CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated edge-sensitive, CPU interrupt numbr is
* returned. A negated errno is returned on failure. The only possible
* failure is that all edge-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32_alloc_edgeint(int priority);
/****************************************************************************
* Name: esp32_free_edgeint
*
* Description:
* Free a previoulsy allocated edge CPU interrupt
*
* Input Parameters:
* cpuint - The CPU interrupt number to be freed
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_free_edgeint(int cpuint, int priority);
/****************************************************************************
* Name: esp32_attach_peripheral
*
* Description:
* Attach a peripheral interupt to a CPU interrupt.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from ira.h to be attached.
* cpuint - The CPU interrupt to receive the peripheral interrupt
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_attach_peripheral(int cpu, int periphid, int cpuint);
/****************************************************************************
* Name: esp32_detach_peripheral
*
* Description:
* Detach a peripheral interupt from a CPU interrupt.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from ira.h to be detached.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_detach_peripheral(int cpu, int periphid);
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */
arch/xtensa/src/esp32/esp32_cpustart.c
+26
View File
@@ -83,6 +83,20 @@ static inline void xtensa_registerdump(FAR struct tcb_s *tcb)
# define xtensa_registerdump(tcb)
#endif
/****************************************************************************
* Name: xtensa_disable_all
****************************************************************************/
static inline void xtensa_disable_all(void)
{
__asm__ __volatile__
(
"movi a2, 0\n"
"xsr a2, INTENABLE\n"
: : : "a2"
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -106,6 +120,7 @@ static inline void xtensa_registerdump(FAR struct tcb_s *tcb)
int xtensa_start_handler(int irq, FAR void *context)
{
FAR struct tcb_s *tcb;
int i;
sinfo("CPU%d Started\n", up_cpu_index());
@@ -127,6 +142,17 @@ int xtensa_start_handler(int irq, FAR void *context)
esp32_region_protection();
/* Disable all PRO CPU interrupts */
xtensa_disable_all();
/* Detach all peripheral sources APP CPU interrupts */
for (i = 0; i < NR_PERIPHERALS)
{
esp32_detach_peripheral(1, i);;
}
/* Dump registers so that we can see what is going to happen on return */
xtensa_registerdump(tcb);
arch/xtensa/src/esp32/esp32_intdecode.c
+28 -5
View File
@@ -44,6 +44,24 @@
#include "chip/esp32_dport.h"
#include "xtensa.h"
/****************************************************************************
* Private Data
****************************************************************************/
static const uint8_t g_baseirq[3] =
{
ESP32_IRQ_SREG0,
ESP32_IRQ_SREG1,
ESP32_IRQ_SREG2
};
static const uint8_t g_nirqs[3] =
{
ESP32_NIRQS_SREG0,
ESP32_NIRQS_SREG1,
ESP32_NIRQS_SREG2
};
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -73,6 +91,7 @@ uint32_t *xtensa_int_decode(uint32_t *regs)
int regndx;
int bit;
int baseirq;
int nirqs;
#ifdef CONFIG_SMP
int cpu;
@@ -94,19 +113,23 @@ uint32_t *xtensa_int_decode(uint32_t *regs)
* registers.
*/
for (regndx = 0, baseirq = XTENSA_IRQ_SREG0;
regndx < 3;
regndx++, baseirq += 32, regaddr += sizeof(uint32_t))
for (regndx = 0; regndx < 3; regndx++)
{
/* Fetch the next register status register */
regval = getreg32(regaddr);
regval = getreg32(regaddr);
regaddr += sizeof(uint32_t);
/* Set up the search */
baseirq = g_baseirq[regndx];
nirqs = g_nirqs[regndx];
/* Decode and dispatch each pending bit in the interrupt status
* register.
*/
for (bit = 0; regval != 0 && bit < 32; bit++)
for (bit = 0; regval != 0 && bit < nirqs; bit++)
{
/* Check if this interrupt is pending */
arch/xtensa/src/esp32/esp32_irq.c
+38 -68
View File
@@ -48,10 +48,6 @@
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
@@ -62,8 +58,19 @@
* CURRENT_REGS for portability.
*/
#ifdef CONFIG_SMP
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#else
volatile uint32_t *g_current_regs[1];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -89,6 +96,20 @@ static void esp32_irq_dump(const char *msg, int irq)
# define esp32_irq_dump(msg, irq)
#endif
/****************************************************************************
* Name: xtensa_disable_all
****************************************************************************/
static inline void xtensa_disable_all(void)
{
__asm__ __volatile__
(
"movi a2, 0\n"
"xsr a2, INTENABLE\n"
: : : "a2"
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -99,8 +120,18 @@ static void esp32_irq_dump(const char *msg, int irq)
void xtensa_irq_initialize(void)
{
/* Disable all interrupts */
#warning Missing logic
int i;
/* Disable all PRO CPU interrupts */
xtensa_disable_all();
/* Detach all peripheral sources PRO CPU interrupts */
for (i = 0; i < NR_PERIPHERALS)
{
esp32_detach_peripheral(0, i);;
}
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
/* Colorize the interrupt stack for debug purposes */
@@ -108,75 +139,14 @@ void xtensa_irq_initialize(void)
#warning Missing logic
#endif
/* Set all interrupts (and exceptions) to the default priority */
#warning Missing logic
/* Attach all other processor exceptions (except reset and sys tick) */
/* Attach all processor exceptions */
#warning Missing logic
esp32_irq_dump("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
#warning Missing logic
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
#warning Missing logic
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void up_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
#warning Missing logic
return OK;
}
#endif
arch/xtensa/src/esp32/esp32_timerisr.c
+7 -22
View File
@@ -62,8 +62,7 @@ static uint32_t g_tick_divisor;
****************************************************************************/
/****************************************************************************
* Function: xtensa_getcount, xtensa_getcompare, xtensa_setcompare, and
* xtensa_enable_timer
* Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare
*
* Description:
* Lower level operations on Xtensa special registers.
@@ -108,22 +107,6 @@ static inline void xtensa_setcompare(uint32_t compare)
);
}
/* Enable the timer interrupt. NOTE: This is non-atomic but safe in this
* context because this occurs early in the initialization sequence.
*/
static inline void xtensa_enable_timer(void)
{
__asm__ __volatile__
(
"movi a3, %0\n"
"rsr a2, INTENABLE\n"
"or a2, a2, a3\n"
"wsr a2, INTENABLE\n"
: : "I"(XT_TIMER_INTEN) : "a2", "a3"
);
}
/****************************************************************************
* Function: esp32_timerisr
*
@@ -208,13 +191,15 @@ void xtensa_timer_initialize(void)
count = xtensa_getcount();
xtensa_setcompare(count + divisor);
/* NOTE: Timer 0 is an internal interrupt source so we do not need to
* attach any peripheral ID to the dedicated CPU interrupt.
*/
/* Attach the timer interrupt vector */
(void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr);
/* Enable the timer interrupt at the device level. NOTE: It is un-necessary
* to call up_enable_irq() for timers.
*/
/* Enable the timer 0 CPU interrupt. */
xtensa_enable_timer();
up_enable_irq(ESP32_CPUINT_TIMER0);
}
configs/nucleo-f303re/src/Makefile
+4
View File
@@ -62,6 +62,10 @@ ifeq ($(CONFIG_CAN),y)
CSRCS += stm32_can.c
endif
ifeq ($(CONFIG_DAC),y)
CSRCS += stm32_dac.c
endif
ifeq ($(CONFIG_PWM),y)
CSRCS += stm32_pwm.c
endif
configs/nucleo-f303re/src/nucleo-f303re.h
+14
View File
@@ -69,6 +69,8 @@
#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN5)
#define LED_DRIVER_PATH "/dev/userleds"
/* Button definitions *******************************************************/
/* The Nucleo F303RE supports two buttons; only one button is controllable
* by software:
@@ -153,4 +155,16 @@ void weak_function stm32_spidev_initialize(void);
int stm32_timer_driver_setup(FAR const char *devpath, int timer);
#endif
/****************************************************************************
* Name: stm32_dac_setup
*
* Description:
* Configure DAC peripheral for the board.
*
****************************************************************************/
#ifdef CONFIG_DAC
int stm32_dac_setup(void);
#endif
#endif /* __CONFIGS_NUCLEO_F303RE_SRC_NUCLEO_F303RE_H */
configs/nucleo-f303re/src/stm32_adc.c
+218 -60
View File
@@ -58,37 +58,66 @@
* Pre-processor Definitions
****************************************************************************/
#if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \
(defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4))
# error "will not work with this combination of ADCs"
#endif
/* Configuration ************************************************************/
#if defined(CONFIG_STM32_ADC1) && !defined(CONFIG_STM32_ADC2) && \
!defined(CONFIG_STM32_ADC3) && !defined(CONFIG_STM32_ADC4)
# define ADC_PORT 1
#elif defined(CONFIG_STM32_ADC2) && !defined(CONFIG_STM32_ADC1) && \
!defined(CONFIG_STM32_ADC3) && !defined(CONFIG_STM32_ADC4)
# define ADC_PORT 2
#elif defined(CONFIG_STM32_ADC3) && !defined(CONFIG_STM32_ADC1) && \
!defined(CONFIG_STM32_ADC2) && !defined(CONFIG_STM32_ADC4)
# define ADC_PORT 3
#elif defined(CONFIG_STM32_ADC4) && !defined(CONFIG_STM32_ADC1) && \
!defined(CONFIG_STM32_ADC2) && !defined(CONFIG_STM32_ADC3)
# define ADC_PORT 4
#else
# error "Choose only one of ADC1, ADC2, ADC3, ADC4"
/* 1 or 2 ADC devices (DEV1, DEV2) */
#if defined(CONFIG_STM32_ADC1)
# define DEV1_PORT 1
#endif
#if defined(CONFIG_STM32_ADC2)
# if defined(DEV1_PORT)
# define DEV2_PORT 2
# else
# define DEV1_PORT 2
# endif
#endif
#if defined(CONFIG_STM32_ADC3)
# if defined(DEV2_PORT)
# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4"
# else
# if defined(DEV1_PORT)
# define DEV2_PORT 3
# else
# define DEV1_PORT 3
# endif
# endif
#endif
#if defined(CONFIG_STM32_ADC4)
# if defined(DEV2_PORT)
# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4"
# else
# if defined(DEV1_PORT)
# define DEV2_PORT 4
# else
# define DEV1_PORT 4
# endif
# endif
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#if defined(CONFIG_STM32_ADC1) && defined(ADC1_HAVE_DMA)
# define ADC_NCHANNELS 4
#elif defined(CONFIG_STM32_ADC2) && defined(ADC2_HAVE_DMA)
# define ADC_NCHANNELS 3
#elif defined(CONFIG_STM32_ADC3) && defined(ADC3_HAVE_DMA)
# define ADC_NCHANNELS 1
#elif defined(CONFIG_STM32_ADC4) && defined(ADC4_HAVE_DMA)
# define ADC_NCHANNELS 1
#if defined(ADC1_HAVE_DMA)
# error "ADC1 with DMA support is not fully implemented"
#else
# define ADC_NCHANNELS 1
# define ADC1_NCHANNELS 4
#endif
#if defined(ADC2_HAVE_DMA)
# error "ADC2 with DMA support is not fully implemented"
#else
# define ADC2_NCHANNELS 3
#endif
#define ADC3_NCHANNELS 3
#define ADC4_NCHANNELS 1
/****************************************************************************
* Private Function Prototypes
@@ -98,88 +127,187 @@
* Private Data
****************************************************************************/
#if defined(CONFIG_STM32_ADC1)
/* DEV 1 */
/* Identifying number of each ADC channel */
#if DEV1_PORT == 1
static const uint8_t g_chanlist[ADC_NCHANNELS] =
#define DEV1_NCHANNELS ADC1_NCHANNELS
/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
static const uint8_t g_chanlist1[4] =
{
1,
#ifdef ADC1_HAVE_DMA
2,
6,
7,
#endif
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist[ADC_NCHANNELS] =
static const uint32_t g_pinlist1[4] =
{
GPIO_ADC1_IN1,
#ifdef ADC1_HAVE_DMA
GPIO_ADC1_IN2,
GPIO_ADC1_IN6,
GPIO_ADC1_IN7,
#endif
GPIO_ADC1_IN7
};
#elif defined(CONFIG_STM32_ADC2)
#elif DEV1_PORT == 2
#define DEV1_NCHANNELS ADC2_NCHANNELS
/* Identifying number of each ADC channel */
static const uint8_t g_chanlist[ADC_NCHANNELS] =
static const uint8_t g_chanlist1[3] =
{
1,
#ifdef ADC2_HAVE_DMA
6,
7,
#endif
3,
4
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist[ADC_NCHANNELS] =
static const uint32_t g_pinlist1[3] =
{
GPIO_ADC2_IN1,
#ifdef ADC2_HAVE_DMA
GPIO_ADC2_IN6,
GPIO_ADC2_IN7,
GPIO_ADC2_IN3,
GPIO_ADC2_IN4
};
#elif DEV1_PORT == 3
#define DEV1_NCHANNELS ADC3_NCHANNELS
/* Identifying number of each ADC channel */
static const uint8_t g_chanlist1[3] =
{
1,
5,
12
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist1[3] =
{
GPIO_ADC3_IN1,
GPIO_ADC3_IN5,
GPIO_ADC3_IN12
};
#elif DEV1_PORT == 4
#define DEV1_NCHANNELS ADC4_NCHANNELS
/* Identifying number of each ADC channel */
static const uint8_t g_chanlist1[1] =
{
3
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist1[1] =
{
GPIO_ADC4_IN3
};
#endif
};
#elif defined(CONFIG_STM32_ADC3)
#ifdef DEV2_PORT
/* Identifying number of each ADC channel */
/* DEV 2 */
static const uint8_t g_chanlist[ADC_NCHANNELS] =
#if DEV2_PORT == 1
#define DEV2_NCHANNELS ADC1_NCHANNELS
/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
static const uint8_t g_chanlist2[4] =
{
12,
1,
2,
6,
7
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist[ADC_NCHANNELS] =
static const uint32_t g_pinlist2[4] =
{
GPIO_ADC3_IN12,
GPIO_ADC1_IN1,
GPIO_ADC1_IN2,
GPIO_ADC1_IN6,
GPIO_ADC1_IN7
};
#elif defined(CONFIG_STM32_ADC4)
#elif DEV2_PORT == 2
#define DEV2_NCHANNELS ADC2_NCHANNELS
/* Identifying number of each ADC channel */
static const uint8_t g_chanlist[ADC_NCHANNELS] =
static const uint8_t g_chanlist2[3] =
{
1,
3,
4
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist[ADC_NCHANNELS] =
static const uint32_t g_pinlist2[3] =
{
GPIO_ADC4_IN3,
GPIO_ADC2_IN1,
GPIO_ADC2_IN3,
GPIO_ADC2_IN4
};
#elif DEV2_PORT == 3
#define DEV2_NCHANNELS ADC3_NCHANNELS
/* Identifying number of each ADC channel */
static const uint8_t g_chanlist2[3] =
{
1,
5,
12
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist2[3] =
{
GPIO_ADC3_IN1,
GPIO_ADC3_IN5,
GPIO_ADC3_IN12
};
#elif DEV2_PORT == 4
#define DEV2_NCHANNELS ADC4_NCHANNELS
/* Identifying number of each ADC channel */
static const uint8_t g_chanlist2[1] =
{
3
};
/* Configurations of pins used by each ADC channel */
static const uint32_t g_pinlist2[1] =
{
GPIO_ADC4_IN3
};
#endif
#endif
/****************************************************************************
@@ -208,21 +336,22 @@ int board_adc_setup(void)
/* Check if we have already initialized */
if (!initialized)
{
if (!initialized) {
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < ADC_NCHANNELS; i++)
for (i = 0; i < DEV1_NCHANNELS; i++)
{
stm32_configgpio(g_pinlist[i]);
stm32_configgpio(g_pinlist1[i]);
}
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
adc = stm32_adcinitialize(ADC_PORT, g_chanlist, ADC_NCHANNELS);
adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS);
if (adc == NULL)
{
aerr("ERROR: Failed to get ADC interface\n");
aerr("ERROR: Failed to get ADC interface 1\n");
return -ENODEV;
}
@@ -231,10 +360,39 @@ int board_adc_setup(void)
ret = adc_register("/dev/adc0", adc);
if (ret < 0)
{
aerr("ERROR: adc_register failed: %d\n", ret);
aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret);
return ret;
}
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)
{
stm32_configgpio(g_pinlist2[i]);
}
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS);
if (adc == NULL)
{
aerr("ERROR: Failed to get ADC interface 2\n");
return -ENODEV;
}
/* Register the ADC driver at "/dev/adc1" */
ret = adc_register("/dev/adc1", adc);
if (ret < 0)
{
aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret);
return ret;
}
#endif
/* Now we are initialized */
initialized = true;
configs/nucleo-f303re/src/stm32_appinitialize.c
+30
View File
@@ -42,8 +42,12 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <syslog.h>
#include <nuttx/board.h>
#include <nuttx/leds/userled.h>
#include "nucleo-f303re.h"
/****************************************************************************
* Pre-processor Definitions
@@ -80,5 +84,31 @@
int board_app_initialize(uintptr_t arg)
{
int ret;
#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
/* Register the LED driver */
ret = userled_lower_initialize(LED_DRIVER_PATH);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
return ret;
}
#endif
/* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. Il
* faut le faire ici
*/
#if defined(CONFIG_DAC)
ret = board_dac_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: board_dac_setup() failed: %d\n", ret);
return ret;
}
#endif
return OK;
}
configs/stm32f103-minimum/include/board.h
+6 -6
View File
@@ -114,12 +114,12 @@
* Note: TIM1,8 are on APB2, others on APB1 */
#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY
#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY
#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY
#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY
#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY
#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY
#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled