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arch/arm: add CONFIG_ARCH_TRUSTZONE_SECURE to some code

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Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
2023-08-16 19:01:19 +08:00
committed by Xiang Xiao
parent a96c6f1abf
commit f1b6cf78da
3 changed files with 12 additions and 0 deletions
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arch/arm/src/armv7-a/arm_gicv2.c
+4
View File
@@ -196,6 +196,7 @@ void arm_gic_initialize(void)
/* Registers with 1-bit per interrupt */
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
/* per-CPU inerrupts config:
* ID0-ID7(SGI) for Non-secure interrupts
* ID8-ID15(SGI) for Secure interrupts.
@@ -203,6 +204,9 @@ void arm_gic_initialize(void)
*/
putreg32(0x000000ff, GIC_ICDISR(0));
#else
putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
#endif
putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */
/* Registers with 8-bits per interrupt */
arch/arm/src/armv7-r/arm_gicv2.c
+4
View File
@@ -196,6 +196,7 @@ void arm_gic_initialize(void)
/* Registers with 1-bit per interrupt */
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
/* per-CPU inerrupts config:
* ID0-ID7(SGI) for Non-secure interrupts
* ID8-ID15(SGI) for Secure interrupts.
@@ -203,6 +204,9 @@ void arm_gic_initialize(void)
*/
putreg32(0x000000ff, GIC_ICDISR(0));
#else
putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
#endif
putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */
/* Registers with 8-bits per interrupt */
arch/arm64/src/common/arm64_gicv2.c
+4
View File
@@ -922,6 +922,7 @@ static void arm_gic_initialize(void)
/* Registers with 1-bit per interrupt */
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
/* per-CPU inerrupts config:
* ID0-ID7(SGI) for Non-secure interrupts
* ID8-ID15(SGI) for Secure interrupts.
@@ -929,6 +930,9 @@ static void arm_gic_initialize(void)
*/
putreg32(0x000000ff, GIC_ICDISR(0));
#else
putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
#endif
putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */
/* Registers with 8-bits per interrupt */