Add SAMA5 GPIO configuration support

ChangeLog

@@ -5159,4 +5159,6 @@
 	* arch/arm/src/sama5/sam_lowputc.c and sam_serial.c:  Add support
 	  for SAMA5 UARTs.  Does not even compile as of initial checkin.
 	  (2013-7-22).
+	* arch/arm/src/sama5/sam_gpio.c:  Add GPIO configuratino support
+	  for the SAMA5.  Still compilation issues.  (2013-7-22).
 

arch/arm/src/sam34/sam4s_gpio.h

@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
+#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
-#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
+#define __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -203,4 +203,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */
+#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H */

arch/arm/src/sama5/Make.defs

@@ -62,5 +62,5 @@ endif
 
 CHIP_ASRCS  =
 
-CHIP_CSRCS  = sam_boot.c sam_clockconfig.c sam_irq.c sam_lowputc.c
+CHIP_CSRCS  = sam_boot.c sam_clockconfig.c sam_gpio.c sam_irq.c
-CHIP_CSRCS += sam_serial.c sam_timerisr.c
+CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_timerisr.c

arch/arm/src/sama5/chip/sama5d3x_memorymap.h

@@ -144,6 +144,7 @@
 #define SAM_MATRIX_OFFSET        0x00ffec00 /* 0x0fffec00-0x0fffedff: MATRIX */
 #define SAM_DBGU_OFFSET          0x00ffee00 /* 0x0fffee00-0x0fffefff: DBGU */
 #define SAM_AIC_OFFSET           0x00fff000 /* 0x0ffff000-0x0ffff1ff: AIC */
+#define SAM_PION_OFFSET(n)       (0x00fff200+((n) << 9))
 #define SAM_PIOA_OFFSET          0x00fff200 /* 0x0ffff200-0x0ffff3ff: PIOA */
 #define SAM_PIOB_OFFSET          0x00fff400 /* 0x0ffff400-0x0ffff5ff: PIOB */
 #define SAM_PIOC_OFFSET          0x00fff600 /* 0x0ffff600-0x0ffff7ff: PIOC */
@@ -333,6 +334,7 @@
 #define SAM_MATRIX_VBASE         (SAM_SYSC_VSECTION+SAM_MATRIX_OFFSET)
 #define SAM_DBGU_VBASE           (SAM_SYSC_VSECTION+SAM_DBGU_OFFSET)
 #define SAM_AIC_VBASE            (SAM_SYSC_VSECTION+SAM_AIC_OFFSET)
+#define SAM_PION_VBASE(n)        (SAM_SYSC_VSECTION+SAM_PION_OFFSET(n))
 #define SAM_PIOA_VBASE           (SAM_SYSC_VSECTION+SAM_PIOA_OFFSET)
 #define SAM_PIOB_VBASE           (SAM_SYSC_VSECTION+SAM_PIOB_OFFSET)
 #define SAM_PIOC_VBASE           (SAM_SYSC_VSECTION+SAM_PIOC_OFFSET)

arch/arm/src/sama5/sam_gpio.h

@@ -0,0 +1,340 @@
+/************************************************************************************
+ * arch/arm/src/sama5/sam_gpio.h
+ * General Purpose Input/Output (GPIO) definitions for the SAM4S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H
+#define __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+#if defined(CONFIG_PIOA_IRQ) || defined(CONFIG_PIOB_IRQ) || \
+    defined(CONFIG_PIOC_IRQ) || defined(CONFIG_PIOD_IRQ) || \
+    defined(CONFIG_PIOD_IRQ)
+#  define CONFIG_PIO_IRQ 1
+#else
+#  undef CONFIG_PIO_IRQ
+#endif
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_DEBUG_GPIO
+#endif
+
+#define GPIO_HAVE_PULLDOWN         1
+#define GPIO_HAVE_PERIPHCD         1
+#define GPIO_HAVE_SCHMITT          1
+#define GPIO_HAVE_DRIVE            1
+
+/* Bit-encoded input to sam_configgpio() ********************************************/
+
+/* 32-bit Encoding:
+ *
+ *   ..MM MCCC CCDD IIIV PPPB BBBB
+ */
+
+/* Input/Output mode:
+ *
+ *   ..MM M... .... .... .... ....
+ */
+
+#define GPIO_MODE_SHIFT            (19)        /* Bits 19-21: GPIO mode */
+#define GPIO_MODE_MASK             (7 << GPIO_MODE_SHIFT)
+#  define GPIO_INPUT               (0 << GPIO_MODE_SHIFT) /* Input */
+#  define GPIO_OUTPUT              (1 << GPIO_MODE_SHIFT) /* Output */
+#  define GPIO_PERIPHA             (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
+#  define GPIO_PERIPHB             (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
+#  define GPIO_PERIPHC             (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */
+#  define GPIO_PERIPHD             (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */
+
+/* These bits set the configuration of the pin:
+ * NOTE: No definitions for parallel capture mode
+ *
+ *   .... .CCC CC.. .... .... ....
+ */
+
+#define GPIO_CFG_SHIFT             (14)        /* Bits 14-18: GPIO configuration bits */
+#define GPIO_CFG_MASK              (31 << GPIO_CFG_SHIFT)
+#  define GPIO_CFG_DEFAULT         (0  << GPIO_CFG_SHIFT) /* Default, no attribute */
+#  define GPIO_CFG_PULLUP          (1  << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
+#  define GPIO_CFG_PULLDOWN        (2  << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
+#  define GPIO_CFG_DEGLITCH        (4  << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
+#  define GPIO_CFG_OPENDRAIN       (8  << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
+#  define GPIO_CFG_SCHMITT         (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
+
+/* Drive Strength:
+ *
+ *   .... .... ..DD .... .... ....
+ */
+
+#define GPIO_DRIVE_SHIFT           (12)        /* Bits 12-13: Drive strength */
+#define GPIO_DRIVE_MASK            (7 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_LOW           (0 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_MEDIUM        (2 << GPIO_DRIVE_SHIFT)
+#  define GPIO_DRIVE_HIGH          (3 << GPIO_DRIVE_SHIFT)
+
+/* Additional interrupt modes:
+ *
+ *   .... .... .... III. .... ....
+ */
+
+#define GPIO_INT_SHIFT             (9)         /* Bits 9-11: GPIO interrupt bits */
+#define GPIO_INT_MASK              (7 << GPIO_INT_SHIFT)
+#  define _GIO_INT_AIM             (1 << 10)   /* Bit 10: Additional Interrupt modes */
+#  define _GPIO_INT_LEVEL          (1 << 9)    /* Bit 9: Level detection interrupt */
+#  define _GPIO_INT_EDGE           (0)         /*        (vs. Edge detection interrupt) */
+#  define _GPIO_INT_RH             (1 << 8)    /* Bit 9: Rising edge/High level detection interrupt */
+#  define _GPIO_INT_FL             (0)         /*        (vs. Falling edge/Low level detection interrupt) */
+
+#  define GPIO_INT_HIGHLEVEL       (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH)
+#  define GPIO_INT_LOWLEVEL        (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_FL)
+#  define GPIO_INT_RISING          (_GIO_INT_AIM | _GPIO_INT_EDGE  | _GPIO_INT_RH)
+#  define GPIO_INT_FALLING         (_GIO_INT_AIM | _GPIO_INT_EDGE  | _GPIO_INT_FL)
+#  define GPIO_INT_BOTHEDGES       (0)
+
+/* If the pin is an GPIO output, then this identifies the initial output value:
+ *
+ *   .... .... .... ...V .... ....
+ */
+
+#define GPIO_OUTPUT_SET            (1 << 8)    /* Bit 8: Inital value of output */
+#define GPIO_OUTPUT_CLEAR          (0)
+
+/* This identifies the GPIO port:
+ *
+ *   .... .... .... .... PPP. ....
+ */
+
+#define GPIO_PORT_SHIFT            (5)         /* Bit 5-7:  Port number */
+#define GPIO_PORT_MASK             (7 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOA           (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOB           (1 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOC           (2 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOD           (3 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOE           (4 << GPIO_PORT_SHIFT)
+
+/* This identifies the bit in the port:
+ *
+ *   .... .... .... .... ...B BBBB
+ */
+
+#define GPIO_PIN_SHIFT             (0)         /* Bits 0-4: GPIO number: 0-31 */
+#define GPIO_PIN_MASK              (31 << GPIO_PIN_SHIFT)
+#define GPIO_PIN0                  (0  << GPIO_PIN_SHIFT)
+#define GPIO_PIN1                  (1  << GPIO_PIN_SHIFT)
+#define GPIO_PIN2                  (2  << GPIO_PIN_SHIFT)
+#define GPIO_PIN3                  (3  << GPIO_PIN_SHIFT)
+#define GPIO_PIN4                  (4  << GPIO_PIN_SHIFT)
+#define GPIO_PIN5                  (5  << GPIO_PIN_SHIFT)
+#define GPIO_PIN6                  (6  << GPIO_PIN_SHIFT)
+#define GPIO_PIN7                  (7  << GPIO_PIN_SHIFT)
+#define GPIO_PIN8                  (8  << GPIO_PIN_SHIFT)
+#define GPIO_PIN9                  (9  << GPIO_PIN_SHIFT)
+#define GPIO_PIN10                 (10 << GPIO_PIN_SHIFT)
+#define GPIO_PIN11                 (11 << GPIO_PIN_SHIFT)
+#define GPIO_PIN12                 (12 << GPIO_PIN_SHIFT)
+#define GPIO_PIN13                 (13 << GPIO_PIN_SHIFT)
+#define GPIO_PIN14                 (14 << GPIO_PIN_SHIFT)
+#define GPIO_PIN15                 (15 << GPIO_PIN_SHIFT)
+#define GPIO_PIN16                 (16 << GPIO_PIN_SHIFT)
+#define GPIO_PIN17                 (17 << GPIO_PIN_SHIFT)
+#define GPIO_PIN18                 (18 << GPIO_PIN_SHIFT)
+#define GPIO_PIN19                 (19 << GPIO_PIN_SHIFT)
+#define GPIO_PIN20                 (20 << GPIO_PIN_SHIFT)
+#define GPIO_PIN21                 (21 << GPIO_PIN_SHIFT)
+#define GPIO_PIN22                 (22 << GPIO_PIN_SHIFT)
+#define GPIO_PIN23                 (23 << GPIO_PIN_SHIFT)
+#define GPIO_PIN24                 (24 << GPIO_PIN_SHIFT)
+#define GPIO_PIN25                 (25 << GPIO_PIN_SHIFT)
+#define GPIO_PIN26                 (26 << GPIO_PIN_SHIFT)
+#define GPIO_PIN27                 (27 << GPIO_PIN_SHIFT)
+#define GPIO_PIN28                 (28 << GPIO_PIN_SHIFT)
+#define GPIO_PIN29                 (29 << GPIO_PIN_SHIFT)
+#define GPIO_PIN30                 (30 << GPIO_PIN_SHIFT)
+#define GPIO_PIN31                 (31 << GPIO_PIN_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* Must be big enough to hold the 32-bit encoding */
+
+typedef uint32_t gpio_pinset_t;
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_gpioirqinitialize
+ *
+ * Description:
+ *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PIO_IRQ
+void sam_gpioirqinitialize(void);
+#else
+#  define sam_gpioirqinitialize()
+#endif
+
+/************************************************************************************
+ * Name: sam_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ************************************************************************************/
+
+int sam_configgpio(gpio_pinset_t cfgset);
+
+/************************************************************************************
+ * Name: sam_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ************************************************************************************/
+
+void sam_gpiowrite(gpio_pinset_t pinset, bool value);
+
+/************************************************************************************
+ * Name: sam_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ************************************************************************************/
+
+bool sam_gpioread(gpio_pinset_t pinset);
+
+/************************************************************************************
+ * Name: sam_gpioirq
+ *
+ * Description:
+ *   Configure an interrupt for the specified GPIO pin.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PIO_IRQ
+void sam_gpioirq(gpio_pinset_t pinset);
+#else
+#  define sam_gpioirq(pinset)
+#endif
+
+/************************************************************************************
+ * Name: sam_gpioirqenable
+ *
+ * Description:
+ *   Enable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PIO_IRQ
+void sam_gpioirqenable(int irq);
+#else
+#  define sam_gpioirqenable(irq)
+#endif
+
+/************************************************************************************
+ * Name: sam_gpioirqdisable
+ *
+ * Description:
+ *   Disable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PIO_IRQ
+void sam_gpioirqdisable(int irq);
+#else
+#  define sam_gpioirqdisable(irq)
+#endif
+
+/************************************************************************************
+ * Function:  sam_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO
+int sam_dumpgpio(uint32_t pinset, const char *msg);
+#else
+#  define sam_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H */

arch/arm/src/sama5/sam_lowputc.c

@@ -140,37 +140,37 @@
 /* Select USART parameters for the selected console */
 
 #if defined(CONFIG_UART0_SERIAL_CONSOLE)
-#  define SAM_CONSOLE_BASE     SAM_UART0_BASE
+#  define SAM_CONSOLE_VBASE    SAM_UART0_VBASE
 #  define SAM_CONSOLE_BAUD     CONFIG_UART0_BAUD
 #  define SAM_CONSOLE_BITS     CONFIG_UART0_BITS
 #  define SAM_CONSOLE_PARITY   CONFIG_UART0_PARITY
 #  define SAM_CONSOLE_2STOP    CONFIG_UART0_2STOP
 #elif defined(CONFIG_UART1_SERIAL_CONSOLE)
-#  define SAM_CONSOLE_BASE     SAM_UART1_BASE
+#  define SAM_CONSOLE_VBASE    SAM_UART1_VBASE
 #  define SAM_CONSOLE_BAUD     CONFIG_UART1_BAUD
 #  define SAM_CONSOLE_BITS     CONFIG_UART1_BITS
 #  define SAM_CONSOLE_PARITY   CONFIG_UART1_PARITY
 #  define SAM_CONSOLE_2STOP    CONFIG_UART1_2STOP
 #elif defined(CONFIG_USART0_SERIAL_CONSOLE)
-#  define SAM_CONSOLE_BASE     SAM_USART0_BASE
+#  define SAM_CONSOLE_VBASE    SAM_USART0_VBASE
 #  define SAM_CONSOLE_BAUD     CONFIG_USART0_BAUD
 #  define SAM_CONSOLE_BITS     CONFIG_USART0_BITS
 #  define SAM_CONSOLE_PARITY   CONFIG_USART0_PARITY
 #  define SAM_CONSOLE_2STOP    CONFIG_USART0_2STOP
 #elif defined(CONFIG_USART1_SERIAL_CONSOLE)
-#  define SAM_CONSOLE_BASE     SAM_USART1_BASE
+#  define SAM_CONSOLE_VBASE    SAM_USART1_VBASE
 #  define SAM_CONSOLE_BAUD     CONFIG_USART1_BAUD
 #  define SAM_CONSOLE_BITS     CONFIG_USART1_BITS
 #  define SAM_CONSOLE_PARITY   CONFIG_USART1_PARITY
 #  define SAM_CONSOLE_2STOP    CONFIG_USART1_2STOP
 #elif defined(CONFIG_USART2_SERIAL_CONSOLE)
-#  define SAM_CONSOLE_BASE     SAM_USART2_BASE
+#  define SAM_CONSOLE_VBASE    SAM_USART2_VBASE
 #  define SAM_CONSOLE_BAUD     CONFIG_USART2_BAUD
 #  define SAM_CONSOLE_BITS     CONFIG_USART2_BITS
 #  define SAM_CONSOLE_PARITY   CONFIG_USART2_PARITY
 #  define SAM_CONSOLE_2STOP    CONFIG_USART2_2STOP
 #elif defined(CONFIG_USART3_SERIAL_CONSOLE)
-#  define SAM_CONSOLE_BASE     SAM_USART3_BASE
+#  define SAM_CONSOLE_VBASE    SAM_USART3_VBASE
 #  define SAM_CONSOLE_BAUD     CONFIG_USART3_BAUD
 #  define SAM_CONSOLE_BITS     CONFIG_USART3_BITS
 #  define SAM_CONSOLE_PARITY   CONFIG_USART3_PARITY
@@ -249,11 +249,11 @@ void up_lowputc(char ch)
 {
   /* Wait for the transmitter to be available */
 
-  while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
+  while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
 
   /* Send the character */
 
-  putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
+  putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET);
 }
 
 /**************************************************************************
@@ -350,27 +350,27 @@ void sam_lowsetup(void)
   /* Reset and disable receiver and transmitter */
 
   putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS),
-           SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
+           SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
 
   /* Disable all interrupts */
 
-  putreg32(0xffffffff, SAM_CONSOLE_BASE + SAM_UART_IDR_OFFSET);
+  putreg32(0xffffffff, SAM_CONSOLE_VBASE + SAM_UART_IDR_OFFSET);
 
   /* Set up the mode register */
 
-  putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET);
+  putreg32(MR_VALUE, SAM_CONSOLE_VBASE + SAM_UART_MR_OFFSET);
 
   /* Configure the console baud.  NOTE: Oversampling by 8 is not supported.
    * This may limit BAUD rates for lower USART clocks.
    */
 
   putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
-           SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET);
+           SAM_CONSOLE_VBASE + SAM_UART_BRGR_OFFSET);
 
   /* Enable receiver & transmitter */
 
   putreg32((UART_CR_RXEN | UART_CR_TXEN),
-           SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
+           SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
 #endif
 }
 

arch/arm/src/sama5/sam_periphclks.h

@@ -43,7 +43,7 @@
 #include <nuttx/config.h>
 #include <stdint.h>
 #include <arch/irq.h>
-#include "chip/sam3u_pmc.h"
+#include "chip/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions

arch/arm/src/sama5/sam_serial.c

@@ -391,7 +391,7 @@ static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
 #ifdef CONFIG_SAM34_UART0
 static struct up_dev_s g_uart0priv =
 {
-  .usartbase      = SAM_UART0_BASE,
+  .usartbase      = SAM_UART0_VBASE,
   .baud           = CONFIG_UART0_BAUD,
   .irq            = SAM_IRQ_UART0,
   .parity         = CONFIG_UART0_PARITY,
@@ -421,7 +421,7 @@ static uart_dev_t g_uart0port =
 #ifdef CONFIG_SAM34_UART1
 static struct up_dev_s g_uart1priv =
 {
-  .usartbase      = SAM_UART1_BASE,
+  .usartbase      = SAM_UART1_VBASE,
   .baud           = CONFIG_UART1_BAUD,
   .irq            = SAM_IRQ_UART1,
   .parity         = CONFIG_UART1_PARITY,
@@ -451,7 +451,7 @@ static uart_dev_t g_uart1port =
 #ifdef CONFIG_SAM34_USART0
 static struct up_dev_s g_usart0priv =
 {
-  .usartbase      = SAM_USART0_BASE,
+  .usartbase      = SAM_USART0_VBASE,
   .baud           = CONFIG_USART0_BAUD,
   .irq            = SAM_IRQ_USART0,
   .parity         = CONFIG_USART0_PARITY,
@@ -481,7 +481,7 @@ static uart_dev_t g_usart0port =
 #ifdef CONFIG_SAM34_USART1
 static struct up_dev_s g_usart1priv =
 {
-  .usartbase      = SAM_USART1_BASE,
+  .usartbase      = SAM_USART1_VBASE,
   .baud           = CONFIG_USART1_BAUD,
   .irq            = SAM_IRQ_USART1,
   .parity         = CONFIG_USART1_PARITY,
@@ -511,7 +511,7 @@ static uart_dev_t g_usart1port =
 #ifdef CONFIG_SAM34_USART2
 static struct up_dev_s g_usart2priv =
 {
-  .usartbase      = SAM_USART2_BASE,
+  .usartbase      = SAM_USART2_VBASE,
   .baud           = CONFIG_USART2_BAUD,
   .irq            = SAM_IRQ_USART2,
   .parity         = CONFIG_USART2_PARITY,
@@ -541,7 +541,7 @@ static uart_dev_t g_usart2port =
 #ifdef CONFIG_SAM34_USART3
 static struct up_dev_s g_usart3priv =
 {
-  .usartbase      = SAM_USART3_BASE,
+  .usartbase      = SAM_USART3_VBASE,
   .baud           = CONFIG_USART3_BAUD,
   .irq            = SAM_IRQ_USART3,
   .parity         = CONFIG_USART3_PARITY,
@@ -669,10 +669,10 @@ static int up_setup(struct uart_dev_s *dev)
 #ifdef HAVE_USART
   else if (priv->bits == 9
 #if defined(CONFIG_SAM34_UART0)
-           && priv->usartbase != SAM_UART0_BASE
+           && priv->usartbase != SAM_UART0_VBASE
 #endif
 #if defined(CONFIG_SAM34_UART1)
-           && priv->usartbase != SAM_UART1_BASE
+           && priv->usartbase != SAM_UART1_VBASE
 #endif
           )
     {