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Add SAMA5 GPIO configuration support
This commit is contained in:
Gregory Nutt
@@ -5159,4 +5159,6 @@
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* arch/arm/src/sama5/sam_lowputc.c and sam_serial.c: Add support
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for SAMA5 UARTs. Does not even compile as of initial checkin.
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(2013-7-22).
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* arch/arm/src/sama5/sam_gpio.c: Add GPIO configuratino support
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for the SAMA5. Still compilation issues. (2013-7-22).
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@@ -34,8 +34,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
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#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
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#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
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#define __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
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/************************************************************************************
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* Included Files
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@@ -203,4 +203,4 @@ extern "C"
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */
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#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H */
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@@ -62,5 +62,5 @@ endif
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CHIP_ASRCS =
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CHIP_CSRCS = sam_boot.c sam_clockconfig.c sam_irq.c sam_lowputc.c
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CHIP_CSRCS += sam_serial.c sam_timerisr.c
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CHIP_CSRCS = sam_boot.c sam_clockconfig.c sam_gpio.c sam_irq.c
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CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_timerisr.c
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File diff suppressed because it is too large
Load Diff
@@ -65,102 +65,103 @@
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/* SAMA5 Physical (unmapped) Memory Map */
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#define SAM_INTMEM_PSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
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#define SAM_EBICS0_PSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
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#define SAM_DDRCS_PSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
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#define SAM_EBICS1_PSECTION 0x40000000 /* 0x40000000-0x4fffffff: EBI Chip select 1 */
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#define SAM_EBICS2_PSECTION 0x50000000 /* 0x50000000-0x5fffffff: EBI Chip select 2 */
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#define SAM_EBICS3_PSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 2 */
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#define SAM_NFCCR_PSECTION 0x70000000 /* 0x70000000-0x7fffffff: NFC Command Registers */
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/* 0x80000000-0xefffffff: Undefined */
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#define SAM_PERIPH_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
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#define SAM_INTMEM_PSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
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#define SAM_EBICS0_PSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
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#define SAM_DDRCS_PSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
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#define SAM_EBICS1_PSECTION 0x40000000 /* 0x40000000-0x4fffffff: EBI Chip select 1 */
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#define SAM_EBICS2_PSECTION 0x50000000 /* 0x50000000-0x5fffffff: EBI Chip select 2 */
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#define SAM_EBICS3_PSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 2 */
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#define SAM_NFCCR_PSECTION 0x70000000 /* 0x70000000-0x7fffffff: NFC Command Registers */
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/* 0x80000000-0xefffffff: Undefined */
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#define SAM_PERIPH_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
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/* SAMA5 Internal Memories */
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#define SAM_BOOTMEM_PSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
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#define SAM_ROM_PSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
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#define SAM_NFCSRAM_PSECTION 0x00200000 /* 0x00200000-0x002fffff: NFC SRAM */
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#define SAM_ISRAM_PSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM */
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# define SAM_ISRAM0_PADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
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# define SAM_ISRAM1_PADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
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#define SAM_SMD_PSECTION 0x00400000 /* 0x00400000-0x004fffff: SMD */
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#define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
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#define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
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#define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */
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#define SAM_AXIMATRIX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */
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#define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
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/* 0x000a0000-0x0fffffff: Undefined */
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#define SAM_BOOTMEM_PSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
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#define SAM_ROM_PSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
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#define SAM_NFCSRAM_PSECTION 0x00200000 /* 0x00200000-0x002fffff: NFC SRAM */
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#define SAM_ISRAM_PSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM */
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# define SAM_ISRAM0_PADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
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# define SAM_ISRAM1_PADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
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#define SAM_SMD_PSECTION 0x00400000 /* 0x00400000-0x004fffff: SMD */
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#define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
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#define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
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#define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */
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#define SAM_AXIMATRIX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */
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#define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
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/* 0x000a0000-0x0fffffff: Undefined */
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/* SAMA5 Internal Peripheral Offsets */
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#define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
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# define SAM_HSMCI0_OFFSET 0x00000000 /* 0x00000000-0x00003fff: HSMCI0 */
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# define SAM_SPI0_OFFSET 0x00004000 /* 0x00004000-0x00007fff: SPI0 */
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# define SAM_SSC0_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SSC0 */
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# define SAM_CAN0_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: CAN0 */
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# define SAM_TC012_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC0, TC1, TC2 */
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# define SAM_TWI0_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TWI0 */
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# define SAM_TWI1_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TWI1 */
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# define SAM_USART0_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: USART0 */
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# define SAM_USART1_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART1 */
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# define SAM_UART0_OFFSET 0x00024000 /* 0x00024000-0x00027fff: UART0 */
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# define SAM_GMAC_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: GMAC */
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# define SAM_PWMC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: PWMC */
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# define SAM_LCDC_OFFSET 0x00030000 /* 0x00030000-0x00033fff: LCDC */
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# define SAM_ISI_OFFSET 0x00034000 /* 0x00034000-0x00037fff: ISI */
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# define SAM_SFR_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: SFR */
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/* 0x0003c000-0x07ffffff: Reserved */
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#define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
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# define SAM_HSMCI0_OFFSET 0x00000000 /* 0x00000000-0x00003fff: HSMCI0 */
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# define SAM_SPI0_OFFSET 0x00004000 /* 0x00004000-0x00007fff: SPI0 */
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# define SAM_SSC0_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SSC0 */
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# define SAM_CAN0_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: CAN0 */
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# define SAM_TC012_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC0, TC1, TC2 */
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# define SAM_TWI0_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TWI0 */
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# define SAM_TWI1_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TWI1 */
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# define SAM_USART0_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: USART0 */
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# define SAM_USART1_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART1 */
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# define SAM_UART0_OFFSET 0x00024000 /* 0x00024000-0x00027fff: UART0 */
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# define SAM_GMAC_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: GMAC */
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# define SAM_PWMC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: PWMC */
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# define SAM_LCDC_OFFSET 0x00030000 /* 0x00030000-0x00033fff: LCDC */
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# define SAM_ISI_OFFSET 0x00034000 /* 0x00034000-0x00037fff: ISI */
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# define SAM_SFR_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: SFR */
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/* 0x0003c000-0x07ffffff: Reserved */
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#define SAM_PERIPHB_PSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
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# define SAM_HSMCI1_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMCI1 */
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# define SAM_HSMCI2_OFFSET 0x00004000 /* 0x00004000-0x00007fff: HSMCI2 */
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# define SAM_SPI1_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SPI1 */
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# define SAM_SSC1_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: SSC1 */
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# define SAM_CAN1_OFFSET 0x00010000 /* 0x00010000-0x00013fff: CAN1 */
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# define SAM_TC345_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TC3, TC4, TC5 */
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# define SAM_TSADC_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TSADC */
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# define SAM_TWI2_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: TWI2 */
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# define SAM_USART2_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART2 */
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# define SAM_USART3_OFFSET 0x00024000 /* 0x00024000-0x00027fff: USART3 */
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# define SAM_UART1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: UART1 */
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# define SAM_EMAC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
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# define SAM_UDPHS_OFFSET 0x00030000 /* 0x00030000-0x00033fff: UDPHS */
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# define SAM_SHA_OFFSET 0x00034000 /* 0x00034000-0x00037fff: SHA */
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# define SAM_AES_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: AES */
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# define SAM_TDES_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: TDES */
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# define SAM_TRNG_OFFSET 0x00040000 /* 0x00040000-0x00043fff: TRNG */
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/* 0x00044000-0x00ffbfff: Reserved */
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#define SAM_SYSC_PSECTION 0xff000000 /* 0xff000000-0xffffffff: System Controller */
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#define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
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# define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */
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#define SAM_PERIPHB_PSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
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# define SAM_HSMCI1_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMCI1 */
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# define SAM_HSMCI2_OFFSET 0x00004000 /* 0x00004000-0x00007fff: HSMCI2 */
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# define SAM_SPI1_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SPI1 */
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# define SAM_SSC1_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: SSC1 */
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# define SAM_CAN1_OFFSET 0x00010000 /* 0x00010000-0x00013fff: CAN1 */
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# define SAM_TC345_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TC3, TC4, TC5 */
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# define SAM_TSADC_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TSADC */
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# define SAM_TWI2_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: TWI2 */
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# define SAM_USART2_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART2 */
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# define SAM_USART3_OFFSET 0x00024000 /* 0x00024000-0x00027fff: USART3 */
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# define SAM_UART1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: UART1 */
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# define SAM_EMAC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
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# define SAM_UDPHS_OFFSET 0x00030000 /* 0x00030000-0x00033fff: UDPHS */
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# define SAM_SHA_OFFSET 0x00034000 /* 0x00034000-0x00037fff: SHA */
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# define SAM_AES_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: AES */
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# define SAM_TDES_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: TDES */
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# define SAM_TRNG_OFFSET 0x00040000 /* 0x00040000-0x00043fff: TRNG */
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/* 0x00044000-0x00ffbfff: Reserved */
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#define SAM_SYSC_PSECTION 0xff000000 /* 0xff000000-0xffffffff: System Controller */
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#define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
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# define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */
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/* System Controller Peripheral Offsets */
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#define SAM_HSMC_OFFSET 0x00ffc000 /* 0x0fffc000-0x0fffcfff: HSMC */
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/* 0x0fffd000-0x0fffe3ff: Reserved */
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#define SAM_FUSE_OFFSET 0x00ffe400 /* 0x0fffe400-0x0fffe5ff: FUSE */
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#define SAM_DMAC0_OFFSET 0x00ffe600 /* 0x0fffe600-0x0fffe7ff: DMAC0 */
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#define SAM_DMAC1_OFFSET 0x00ffe800 /* 0x0fffe800-0x0fffe9ff: DMAC1 */
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#define SAM_MPDDRC_OFFSET 0x00ffea00 /* 0x0fffea00-0x0fffebff: MPDDRC */
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#define SAM_MATRIX_OFFSET 0x00ffec00 /* 0x0fffec00-0x0fffedff: MATRIX */
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#define SAM_DBGU_OFFSET 0x00ffee00 /* 0x0fffee00-0x0fffefff: DBGU */
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#define SAM_AIC_OFFSET 0x00fff000 /* 0x0ffff000-0x0ffff1ff: AIC */
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#define SAM_PIOA_OFFSET 0x00fff200 /* 0x0ffff200-0x0ffff3ff: PIOA */
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#define SAM_PIOB_OFFSET 0x00fff400 /* 0x0ffff400-0x0ffff5ff: PIOB */
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#define SAM_PIOC_OFFSET 0x00fff600 /* 0x0ffff600-0x0ffff7ff: PIOC */
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#define SAM_PIOD_OFFSET 0x00fff800 /* 0x0ffff800-0x0ffff9ff: PIOD */
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#define SAM_PIOE_OFFSET 0x00fffa00 /* 0x0ffffa00-0x0ffffbff: PIOE */
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#define SAM_PMC_OFFSET 0x00fffc00 /* 0x0ffffc00-0x0ffffdff: PMC */
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#define SAM_RSTC_OFFSET 0x00fffe00 /* 0x0ffffe00-0x0ffffe0f: RSTC */
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#define SAM_SHDC_OFFSET 0x00fffe10 /* 0x0ffffe10-0x0ffffe1f: SHDC */
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/* 0x0ffffe20-0x0ffffe2f: Reserved */
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#define SAM_PITC_OFFSET 0x00fffe30 /* 0x0ffffe30-0x0ffffe3f: PITC */
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#define SAM_WDT_OFFSET 0x00fffe40 /* 0x0ffffe40-0x0ffffe4f: WDT */
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#define SAM_SCKCR_OFFSET 0x00fffe50 /* 0x0ffffe50-0x0ffffe53: SCKCR */
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#define SAM_BSC_OFFSET 0x00fffe54 /* 0x0ffffe54-0x0ffffe5f: BSC */
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#define SAM_GPBR_OFFSET 0x00fffe60 /* 0x0ffffe60-0x0ffffe6f: GPBR */
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/* 0x0ffffe70-0x0ffffeaf: Reserved */
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#define SAM_RTCC_OFFSET 0x00fffeb0 /* 0x0ffffeb0-0x0ffffedf: RTCC */
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/* 0x0ffffee0-0x0fffffff: Reserved */
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#define SAM_HSMC_OFFSET 0x00ffc000 /* 0x0fffc000-0x0fffcfff: HSMC */
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/* 0x0fffd000-0x0fffe3ff: Reserved */
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#define SAM_FUSE_OFFSET 0x00ffe400 /* 0x0fffe400-0x0fffe5ff: FUSE */
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#define SAM_DMAC0_OFFSET 0x00ffe600 /* 0x0fffe600-0x0fffe7ff: DMAC0 */
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#define SAM_DMAC1_OFFSET 0x00ffe800 /* 0x0fffe800-0x0fffe9ff: DMAC1 */
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#define SAM_MPDDRC_OFFSET 0x00ffea00 /* 0x0fffea00-0x0fffebff: MPDDRC */
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#define SAM_MATRIX_OFFSET 0x00ffec00 /* 0x0fffec00-0x0fffedff: MATRIX */
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#define SAM_DBGU_OFFSET 0x00ffee00 /* 0x0fffee00-0x0fffefff: DBGU */
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#define SAM_AIC_OFFSET 0x00fff000 /* 0x0ffff000-0x0ffff1ff: AIC */
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#define SAM_PION_OFFSET(n) (0x00fff200+((n) << 9))
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#define SAM_PIOA_OFFSET 0x00fff200 /* 0x0ffff200-0x0ffff3ff: PIOA */
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#define SAM_PIOB_OFFSET 0x00fff400 /* 0x0ffff400-0x0ffff5ff: PIOB */
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#define SAM_PIOC_OFFSET 0x00fff600 /* 0x0ffff600-0x0ffff7ff: PIOC */
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#define SAM_PIOD_OFFSET 0x00fff800 /* 0x0ffff800-0x0ffff9ff: PIOD */
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#define SAM_PIOE_OFFSET 0x00fffa00 /* 0x0ffffa00-0x0ffffbff: PIOE */
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#define SAM_PMC_OFFSET 0x00fffc00 /* 0x0ffffc00-0x0ffffdff: PMC */
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#define SAM_RSTC_OFFSET 0x00fffe00 /* 0x0ffffe00-0x0ffffe0f: RSTC */
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#define SAM_SHDC_OFFSET 0x00fffe10 /* 0x0ffffe10-0x0ffffe1f: SHDC */
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/* 0x0ffffe20-0x0ffffe2f: Reserved */
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#define SAM_PITC_OFFSET 0x00fffe30 /* 0x0ffffe30-0x0ffffe3f: PITC */
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#define SAM_WDT_OFFSET 0x00fffe40 /* 0x0ffffe40-0x0ffffe4f: WDT */
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#define SAM_SCKCR_OFFSET 0x00fffe50 /* 0x0ffffe50-0x0ffffe53: SCKCR */
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#define SAM_BSC_OFFSET 0x00fffe54 /* 0x0ffffe54-0x0ffffe5f: BSC */
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#define SAM_GPBR_OFFSET 0x00fffe60 /* 0x0ffffe60-0x0ffffe6f: GPBR */
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/* 0x0ffffe70-0x0ffffeaf: Reserved */
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#define SAM_RTCC_OFFSET 0x00fffeb0 /* 0x0ffffeb0-0x0ffffedf: RTCC */
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/* 0x0ffffee0-0x0fffffff: Reserved */
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/* Sizes of memory regions in bytes.
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*
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@@ -168,27 +169,27 @@
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* region. The implemented sizes of the EBI CS0-3 and DDRCS regions
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* are not known apriori and must be specified with configuration settings.
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*/
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/* 0x00000000-0x0fffffff: Internal Memories */
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#define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */
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#define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */
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#define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */
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/* 0x00300000-0x003fffff: SRAM0 and SRAM1 */
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#define SAM_ISRAM_SIZE (64*1024 + SAM_ISRAM1_SIZE)
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#define SAM_SMD_SIZE (1*1024*1024) /* 0x00400000-0x004fffff: SMD */
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#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
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#define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */
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#define SAM_UHPEHCI_SIZE (1*1024*1024) /* 0x00700000-0x007fffff: UHP EHCI */
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#define SAM_AXIMATRIX_SIZE (1*1024*1024) /* 0x00800000-0x008fffff: AXI Matr */
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#define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */
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#define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */
|
||||
/* 0xf0000000-0xffffffff: Internal Peripherals */
|
||||
#define SAM_PERIPHA_SIZE (15*1024) /* 0xf0000000-0xf003bfff: Internal Peripherals */
|
||||
#define SAM_PERIPHB_SIZE (272*1024) /* 0xf8000000-0xf8043fff: Internal Peripherals */
|
||||
#define SAM_SYSC_SIZE (1*1024*1024) /* 0xff000000-0x0ffffedf: Internal Peripherals */
|
||||
/* 0x00000000-0x0fffffff: Internal Memories */
|
||||
#define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */
|
||||
#define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */
|
||||
#define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */
|
||||
/* 0x00300000-0x003fffff: SRAM0 and SRAM1 */
|
||||
#define SAM_ISRAM_SIZE (64*1024 + SAM_ISRAM1_SIZE)
|
||||
#define SAM_SMD_SIZE (1*1024*1024) /* 0x00400000-0x004fffff: SMD */
|
||||
#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
|
||||
#define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */
|
||||
#define SAM_UHPEHCI_SIZE (1*1024*1024) /* 0x00700000-0x007fffff: UHP EHCI */
|
||||
#define SAM_AXIMATRIX_SIZE (1*1024*1024) /* 0x00800000-0x008fffff: AXI Matr */
|
||||
#define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */
|
||||
#define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */
|
||||
/* 0xf0000000-0xffffffff: Internal Peripherals */
|
||||
#define SAM_PERIPHA_SIZE (15*1024) /* 0xf0000000-0xf003bfff: Internal Peripherals */
|
||||
#define SAM_PERIPHB_SIZE (272*1024) /* 0xf8000000-0xf8043fff: Internal Peripherals */
|
||||
#define SAM_SYSC_SIZE (1*1024*1024) /* 0xff000000-0x0ffffedf: Internal Peripherals */
|
||||
|
||||
/* Convert size in bytes to number of sections (in Mb). */
|
||||
|
||||
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
|
||||
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
|
||||
|
||||
/* Sizes of memory regions in sections.
|
||||
*
|
||||
@@ -198,51 +199,51 @@
|
||||
* region.
|
||||
*/
|
||||
|
||||
#define SAM_BOOTMEM_NSECTIONS _NSECTIONS(SAM_BOOTMEM_SIZE)
|
||||
#define SAM_ROM_NSECTIONS _NSECTIONS(SAM_ROM_SIZE)
|
||||
#define SAM_NFCSRAM_NSECTIONS _NSECTIONS(SAM_NFCSRAM_SIZE)
|
||||
#define SAM_ISRAM_NSECTIONS _NSECTIONS(SAM_ISRAM_SIZE)
|
||||
#define SAM_SMD_NSECTIONS _NSECTIONS(SAM_SMD_SIZE)
|
||||
#define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE)
|
||||
#define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE)
|
||||
#define SAM_UHPEHCI_NSECTIONS _NSECTIONS(SAM_UHPEHCI_SIZE)
|
||||
#define SAM_AXIMATRIX_NSECTIONS _NSECTIONS(SAM_AXIMATRIX_SIZE)
|
||||
#define SAM_DAP_NSECTIONS _NSECTIONS(SAM_DAP_SIZE)
|
||||
#define SAM_BOOTMEM_NSECTIONS _NSECTIONS(SAM_BOOTMEM_SIZE)
|
||||
#define SAM_ROM_NSECTIONS _NSECTIONS(SAM_ROM_SIZE)
|
||||
#define SAM_NFCSRAM_NSECTIONS _NSECTIONS(SAM_NFCSRAM_SIZE)
|
||||
#define SAM_ISRAM_NSECTIONS _NSECTIONS(SAM_ISRAM_SIZE)
|
||||
#define SAM_SMD_NSECTIONS _NSECTIONS(SAM_SMD_SIZE)
|
||||
#define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE)
|
||||
#define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE)
|
||||
#define SAM_UHPEHCI_NSECTIONS _NSECTIONS(SAM_UHPEHCI_SIZE)
|
||||
#define SAM_AXIMATRIX_NSECTIONS _NSECTIONS(SAM_AXIMATRIX_SIZE)
|
||||
#define SAM_DAP_NSECTIONS _NSECTIONS(SAM_DAP_SIZE)
|
||||
|
||||
#define SAM_EBICS0_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE)
|
||||
#define SAM_DDRCS_NSECTIONS _NSECTIONS(CONFIG_SAMA5_DDRCS_SIZE)
|
||||
#define SAM_EBICS1_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC1_SIZE)
|
||||
#define SAM_EBICS2_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC2_SIZE)
|
||||
#define SAM_EBICS3_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC3_SIZE)
|
||||
#define SAM_NFCCR_NSECTIONS _NSECTIONS(SAM_NFCCR_SIZE)
|
||||
#define SAM_EBICS0_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE)
|
||||
#define SAM_DDRCS_NSECTIONS _NSECTIONS(CONFIG_SAMA5_DDRCS_SIZE)
|
||||
#define SAM_EBICS1_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC1_SIZE)
|
||||
#define SAM_EBICS2_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC2_SIZE)
|
||||
#define SAM_EBICS3_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC3_SIZE)
|
||||
#define SAM_NFCCR_NSECTIONS _NSECTIONS(SAM_NFCCR_SIZE)
|
||||
|
||||
#define SAM_PERIPHA_NSECTIONS _NSECTIONS(SAM_PERIPHA_SIZE)
|
||||
#define SAM_PERIPHB_NSECTIONS _NSECTIONS(SAM_PERIPHB_SIZE)
|
||||
#define SAM_SYSC_NSECTIONS _NSECTIONS(SAM_SYSC_SIZE)
|
||||
#define SAM_PERIPHA_NSECTIONS _NSECTIONS(SAM_PERIPHA_SIZE)
|
||||
#define SAM_PERIPHB_NSECTIONS _NSECTIONS(SAM_PERIPHB_SIZE)
|
||||
#define SAM_SYSC_NSECTIONS _NSECTIONS(SAM_SYSC_SIZE)
|
||||
|
||||
/* Section MMU Flags */
|
||||
|
||||
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
|
||||
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
|
||||
#define SAM_NFCSRAM_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_AXIMATRIX_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
|
||||
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
|
||||
#define SAM_NFCSRAM_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_AXIMATRIX_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
|
||||
|
||||
#define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_DDRCS_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_EBICS1_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_EBICS2_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_EBICS3_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_DDRCS_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_EBICS1_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_EBICS2_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_EBICS3_MMUFLAGS MMU_MEMFLAGS
|
||||
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
|
||||
|
||||
#define SAM_PERIPHA_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_SYSC_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_PERIPHA_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS
|
||||
#define SAM_SYSC_MMUFLAGS MMU_IOFLAGS
|
||||
|
||||
/* SAMA5 Virtual (mapped) Memory Map
|
||||
*
|
||||
@@ -333,6 +334,7 @@
|
||||
#define SAM_MATRIX_VBASE (SAM_SYSC_VSECTION+SAM_MATRIX_OFFSET)
|
||||
#define SAM_DBGU_VBASE (SAM_SYSC_VSECTION+SAM_DBGU_OFFSET)
|
||||
#define SAM_AIC_VBASE (SAM_SYSC_VSECTION+SAM_AIC_OFFSET)
|
||||
#define SAM_PION_VBASE(n) (SAM_SYSC_VSECTION+SAM_PION_OFFSET(n))
|
||||
#define SAM_PIOA_VBASE (SAM_SYSC_VSECTION+SAM_PIOA_OFFSET)
|
||||
#define SAM_PIOB_VBASE (SAM_SYSC_VSECTION+SAM_PIOB_OFFSET)
|
||||
#define SAM_PIOC_VBASE (SAM_SYSC_VSECTION+SAM_PIOC_OFFSET)
|
||||
@@ -356,13 +358,13 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_BOOT_RUNFROMFLASH)
|
||||
# define NUTTX_START_VADDR CONFIG_SAMA5_NORFLASH_VBASE
|
||||
# define NUTTX_START_VADDR CONFIG_SAMA5_NORFLASH_VBASE
|
||||
#elif defined(CONFIG_BOOT_RUNFROMSDRAM)
|
||||
# define NUTTX_START_VADDR SAM_DDRCS_VSECTION
|
||||
# define NUTTX_START_VADDR SAM_DDRCS_VSECTION
|
||||
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
|
||||
# define NUTTX_START_VADDR CONFIG_SAMA5_SRAM_VBASE
|
||||
# define NUTTX_START_VADDR CONFIG_SAMA5_SRAM_VBASE
|
||||
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
|
||||
# define NUTTX_START_VADDR SAM_ISRAM_VSECTION
|
||||
# define NUTTX_START_VADDR SAM_ISRAM_VSECTION
|
||||
#endif
|
||||
|
||||
/* MMU Page Table Location
|
||||
@@ -427,7 +429,7 @@
|
||||
# define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
|
||||
# endif
|
||||
# endif
|
||||
# define PGTABLE_IN_HIGHSRAM 1
|
||||
# define PGTABLE_IN_HIGHSRAM 1
|
||||
# else
|
||||
|
||||
/* Otherwise, ISRAM1 (or ISRAM0 if ISRAM1 is not available in this
|
||||
@@ -436,11 +438,11 @@
|
||||
* the first 16Kb of ISRAM0.
|
||||
*/
|
||||
|
||||
# define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR
|
||||
# define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR
|
||||
# ifndef CONFIG_PAGING
|
||||
# define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR
|
||||
# define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR
|
||||
# endif
|
||||
# define PGTABLE_IN_LOWSRAM 1
|
||||
# define PGTABLE_IN_LOWSRAM 1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
@@ -454,19 +456,19 @@
|
||||
* of the page table.
|
||||
*/
|
||||
|
||||
#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+0x00000800)
|
||||
#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+0x00000800)
|
||||
#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+0x00000800)
|
||||
#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+0x00000800)
|
||||
|
||||
/* Page table end addresses: */
|
||||
|
||||
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
||||
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
||||
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
||||
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
||||
|
||||
/* Page table sizes */
|
||||
|
||||
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_VBASE)
|
||||
#define PGTABLE_L2_SIZE (4*256)
|
||||
#define PGTABLE_L2_NENTRIES (PGTABLE_L2_ALLOC / PGTABLE_L2_SIZE)
|
||||
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_VBASE)
|
||||
#define PGTABLE_L2_SIZE (4*256)
|
||||
#define PGTABLE_L2_NENTRIES (PGTABLE_L2_ALLOC / PGTABLE_L2_SIZE)
|
||||
|
||||
/* Base address of the interrupt vector table.
|
||||
*
|
||||
@@ -475,22 +477,22 @@
|
||||
* SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
|
||||
*/
|
||||
|
||||
#define VECTOR_TABLE_SIZE 0x00010000
|
||||
#define VECTOR_TABLE_SIZE 0x00010000
|
||||
#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
|
||||
# define SAM_VECTOR_PADDR SAM_ISRAM0_PADDR
|
||||
# define SAM_VECTOR_VSRAM SAM_ISRAM0_VADDR
|
||||
# define SAM_VECTOR_VADDR 0x00000000
|
||||
# define SAM_VECTOR_VCOARSE 0x00000000
|
||||
# define SAM_VECTOR_PADDR SAM_ISRAM0_PADDR
|
||||
# define SAM_VECTOR_VSRAM SAM_ISRAM0_VADDR
|
||||
# define SAM_VECTOR_VADDR 0x00000000
|
||||
# define SAM_VECTOR_VCOARSE 0x00000000
|
||||
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
|
||||
# ifdef HAVE_ISRAM1
|
||||
# define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
|
||||
# define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
|
||||
# define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
|
||||
# define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
|
||||
# else
|
||||
# define SAM_VECTOR_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
|
||||
# define SAM_VECTOR_VSRAM (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
|
||||
# define SAM_VECTOR_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
|
||||
# define SAM_VECTOR_VSRAM (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
|
||||
# endif
|
||||
# define SAM_VECTOR_VADDR 0xffff0000
|
||||
# define SAM_VECTOR_VCOARSE 0xfff00000
|
||||
# define SAM_VECTOR_VADDR 0xffff0000
|
||||
# define SAM_VECTOR_VCOARSE 0xfff00000
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,340 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sama5/sam_gpio.h
|
||||
* General Purpose Input/Output (GPIO) definitions for the SAM4S
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_PIOA_IRQ) || defined(CONFIG_PIOB_IRQ) || \
|
||||
defined(CONFIG_PIOC_IRQ) || defined(CONFIG_PIOD_IRQ) || \
|
||||
defined(CONFIG_PIOD_IRQ)
|
||||
# define CONFIG_PIO_IRQ 1
|
||||
#else
|
||||
# undef CONFIG_PIO_IRQ
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DEBUG
|
||||
# undef CONFIG_DEBUG_GPIO
|
||||
#endif
|
||||
|
||||
#define GPIO_HAVE_PULLDOWN 1
|
||||
#define GPIO_HAVE_PERIPHCD 1
|
||||
#define GPIO_HAVE_SCHMITT 1
|
||||
#define GPIO_HAVE_DRIVE 1
|
||||
|
||||
/* Bit-encoded input to sam_configgpio() ********************************************/
|
||||
|
||||
/* 32-bit Encoding:
|
||||
*
|
||||
* ..MM MCCC CCDD IIIV PPPB BBBB
|
||||
*/
|
||||
|
||||
/* Input/Output mode:
|
||||
*
|
||||
* ..MM M... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (19) /* Bits 19-21: GPIO mode */
|
||||
#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */
|
||||
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */
|
||||
# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
|
||||
# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
|
||||
# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */
|
||||
# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */
|
||||
|
||||
/* These bits set the configuration of the pin:
|
||||
* NOTE: No definitions for parallel capture mode
|
||||
*
|
||||
* .... .CCC CC.. .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_CFG_SHIFT (14) /* Bits 14-18: GPIO configuration bits */
|
||||
#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT)
|
||||
# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
|
||||
# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
|
||||
# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
|
||||
# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
|
||||
# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
|
||||
# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
|
||||
|
||||
/* Drive Strength:
|
||||
*
|
||||
* .... .... ..DD .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_DRIVE_SHIFT (12) /* Bits 12-13: Drive strength */
|
||||
#define GPIO_DRIVE_MASK (7 << GPIO_DRIVE_SHIFT)
|
||||
# define GPIO_DRIVE_LOW (0 << GPIO_DRIVE_SHIFT)
|
||||
# define GPIO_DRIVE_MEDIUM (2 << GPIO_DRIVE_SHIFT)
|
||||
# define GPIO_DRIVE_HIGH (3 << GPIO_DRIVE_SHIFT)
|
||||
|
||||
/* Additional interrupt modes:
|
||||
*
|
||||
* .... .... .... III. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_INT_SHIFT (9) /* Bits 9-11: GPIO interrupt bits */
|
||||
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
|
||||
# define _GIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
|
||||
# define _GPIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
|
||||
# define _GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
|
||||
# define _GPIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
|
||||
# define _GPIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
|
||||
|
||||
# define GPIO_INT_HIGHLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH)
|
||||
# define GPIO_INT_LOWLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_FL)
|
||||
# define GPIO_INT_RISING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_RH)
|
||||
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
|
||||
# define GPIO_INT_BOTHEDGES (0)
|
||||
|
||||
/* If the pin is an GPIO output, then this identifies the initial output value:
|
||||
*
|
||||
* .... .... .... ...V .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: Inital value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
*
|
||||
* .... .... .... .... PPP. ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOD (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_PIOE (4 << GPIO_PORT_SHIFT)
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
*
|
||||
* .... .... .... .... ...B BBBB
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/* Must be big enough to hold the 32-bit encoding */
|
||||
|
||||
typedef uint32_t gpio_pinset_t;
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PIO_IRQ
|
||||
void sam_gpioirqinitialize(void);
|
||||
#else
|
||||
# define sam_gpioirqinitialize()
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int sam_configgpio(gpio_pinset_t cfgset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_gpiowrite(gpio_pinset_t pinset, bool value);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool sam_gpioread(gpio_pinset_t pinset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirq
|
||||
*
|
||||
* Description:
|
||||
* Configure an interrupt for the specified GPIO pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PIO_IRQ
|
||||
void sam_gpioirq(gpio_pinset_t pinset);
|
||||
#else
|
||||
# define sam_gpioirq(pinset)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PIO_IRQ
|
||||
void sam_gpioirqenable(int irq);
|
||||
#else
|
||||
# define sam_gpioirqenable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PIO_IRQ
|
||||
void sam_gpioirqdisable(int irq);
|
||||
#else
|
||||
# define sam_gpioirqdisable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: sam_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the base address of the provided pinset.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
int sam_dumpgpio(uint32_t pinset, const char *msg);
|
||||
#else
|
||||
# define sam_dumpgpio(p,m)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H */
|
||||
@@ -140,37 +140,37 @@
|
||||
/* Select USART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_BASE SAM_UART0_BASE
|
||||
# define SAM_CONSOLE_VBASE SAM_UART0_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_BASE SAM_UART1_BASE
|
||||
# define SAM_CONSOLE_VBASE SAM_UART1_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_BASE SAM_USART0_BASE
|
||||
# define SAM_CONSOLE_VBASE SAM_USART0_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_USART0_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_USART0_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_USART0_2STOP
|
||||
#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_BASE SAM_USART1_BASE
|
||||
# define SAM_CONSOLE_VBASE SAM_USART1_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_BASE SAM_USART2_BASE
|
||||
# define SAM_CONSOLE_VBASE SAM_USART2_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define SAM_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
|
||||
# define SAM_CONSOLE_BASE SAM_USART3_BASE
|
||||
# define SAM_CONSOLE_VBASE SAM_USART3_VBASE
|
||||
# define SAM_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define SAM_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define SAM_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
@@ -249,11 +249,11 @@ void up_lowputc(char ch)
|
||||
{
|
||||
/* Wait for the transmitter to be available */
|
||||
|
||||
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
|
||||
while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
|
||||
|
||||
/* Send the character */
|
||||
|
||||
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
|
||||
putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
@@ -350,27 +350,27 @@ void sam_lowsetup(void)
|
||||
/* Reset and disable receiver and transmitter */
|
||||
|
||||
putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS),
|
||||
SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
|
||||
SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0xffffffff, SAM_CONSOLE_BASE + SAM_UART_IDR_OFFSET);
|
||||
putreg32(0xffffffff, SAM_CONSOLE_VBASE + SAM_UART_IDR_OFFSET);
|
||||
|
||||
/* Set up the mode register */
|
||||
|
||||
putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET);
|
||||
putreg32(MR_VALUE, SAM_CONSOLE_VBASE + SAM_UART_MR_OFFSET);
|
||||
|
||||
/* Configure the console baud. NOTE: Oversampling by 8 is not supported.
|
||||
* This may limit BAUD rates for lower USART clocks.
|
||||
*/
|
||||
|
||||
putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
|
||||
SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET);
|
||||
SAM_CONSOLE_VBASE + SAM_UART_BRGR_OFFSET);
|
||||
|
||||
/* Enable receiver & transmitter */
|
||||
|
||||
putreg32((UART_CR_RXEN | UART_CR_TXEN),
|
||||
SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
|
||||
SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/irq.h>
|
||||
#include "chip/sam3u_pmc.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@@ -391,7 +391,7 @@ static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
|
||||
#ifdef CONFIG_SAM34_UART0
|
||||
static struct up_dev_s g_uart0priv =
|
||||
{
|
||||
.usartbase = SAM_UART0_BASE,
|
||||
.usartbase = SAM_UART0_VBASE,
|
||||
.baud = CONFIG_UART0_BAUD,
|
||||
.irq = SAM_IRQ_UART0,
|
||||
.parity = CONFIG_UART0_PARITY,
|
||||
@@ -421,7 +421,7 @@ static uart_dev_t g_uart0port =
|
||||
#ifdef CONFIG_SAM34_UART1
|
||||
static struct up_dev_s g_uart1priv =
|
||||
{
|
||||
.usartbase = SAM_UART1_BASE,
|
||||
.usartbase = SAM_UART1_VBASE,
|
||||
.baud = CONFIG_UART1_BAUD,
|
||||
.irq = SAM_IRQ_UART1,
|
||||
.parity = CONFIG_UART1_PARITY,
|
||||
@@ -451,7 +451,7 @@ static uart_dev_t g_uart1port =
|
||||
#ifdef CONFIG_SAM34_USART0
|
||||
static struct up_dev_s g_usart0priv =
|
||||
{
|
||||
.usartbase = SAM_USART0_BASE,
|
||||
.usartbase = SAM_USART0_VBASE,
|
||||
.baud = CONFIG_USART0_BAUD,
|
||||
.irq = SAM_IRQ_USART0,
|
||||
.parity = CONFIG_USART0_PARITY,
|
||||
@@ -481,7 +481,7 @@ static uart_dev_t g_usart0port =
|
||||
#ifdef CONFIG_SAM34_USART1
|
||||
static struct up_dev_s g_usart1priv =
|
||||
{
|
||||
.usartbase = SAM_USART1_BASE,
|
||||
.usartbase = SAM_USART1_VBASE,
|
||||
.baud = CONFIG_USART1_BAUD,
|
||||
.irq = SAM_IRQ_USART1,
|
||||
.parity = CONFIG_USART1_PARITY,
|
||||
@@ -511,7 +511,7 @@ static uart_dev_t g_usart1port =
|
||||
#ifdef CONFIG_SAM34_USART2
|
||||
static struct up_dev_s g_usart2priv =
|
||||
{
|
||||
.usartbase = SAM_USART2_BASE,
|
||||
.usartbase = SAM_USART2_VBASE,
|
||||
.baud = CONFIG_USART2_BAUD,
|
||||
.irq = SAM_IRQ_USART2,
|
||||
.parity = CONFIG_USART2_PARITY,
|
||||
@@ -541,7 +541,7 @@ static uart_dev_t g_usart2port =
|
||||
#ifdef CONFIG_SAM34_USART3
|
||||
static struct up_dev_s g_usart3priv =
|
||||
{
|
||||
.usartbase = SAM_USART3_BASE,
|
||||
.usartbase = SAM_USART3_VBASE,
|
||||
.baud = CONFIG_USART3_BAUD,
|
||||
.irq = SAM_IRQ_USART3,
|
||||
.parity = CONFIG_USART3_PARITY,
|
||||
@@ -669,10 +669,10 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
#ifdef HAVE_USART
|
||||
else if (priv->bits == 9
|
||||
#if defined(CONFIG_SAM34_UART0)
|
||||
&& priv->usartbase != SAM_UART0_BASE
|
||||
&& priv->usartbase != SAM_UART0_VBASE
|
||||
#endif
|
||||
#if defined(CONFIG_SAM34_UART1)
|
||||
&& priv->usartbase != SAM_UART1_BASE
|
||||
&& priv->usartbase != SAM_UART1_VBASE
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user