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arch/arm64: use up_prioritize_irq and up_set_type_irq instead

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arm64_gic_irq_set_priority

use use up_prioritize_irq and up_set_type_irq as std api

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
This commit is contained in:
lipengfei28
2024-12-25 16:30:39 +08:00
committed by Xiang Xiao
parent e70c31162a
commit efedf48cde
13 changed files with 20 additions and 115 deletions
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arch/arm64/src/a64/a64_serial.c
+2 -1
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@@ -648,7 +648,8 @@ static int a64_uart_attach(struct uart_dev_s *dev)
/* Set Interrupt Priority in Generic Interrupt Controller v2 */
arm64_gic_irq_set_priority(port->irq_num, 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(port->irq_num, 0);
up_set_irq_type(port->irq_num, IRQ_HIGH_LEVEL);
/* Enable UART Interrupt */
arch/arm64/src/a64/a64_twi.c
+2 -1
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@@ -1845,7 +1845,8 @@ static void twi_hw_initialize(struct a64_twi_priv_s *priv)
/* Set Interrupt Priority in Generic Interrupt Controller v2 */
arm64_gic_irq_set_priority(priv->config->irq, IRQ_TYPE_LEVEL, 0);
up_prioritize_irq(priv->config->irq, 0);
up_set_irq_type(priv->config->irq, IRQ_HIGH_LEVEL);
/* Enable TWI Interrupt */
arch/arm64/src/bcm2711/bcm2711_gpio.c
+2 -1
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@@ -272,7 +272,8 @@ static int bcm2711_gpio_irqs_init(void)
for (int i = 0; i < NUM_GPIO_IRQS; i++)
{
up_enable_irq(g_gpio_irqs[i]);
arm64_gic_irq_set_priority(g_gpio_irqs[i], 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(g_gpio_irqs[i], 0);
up_set_irq_type(g_gpio_irqs[i], IRQ_HIGH_LEVEL);
}
/* Mark as initialized. */
arch/arm64/src/bcm2711/bcm2711_i2c.c
+2 -1
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@@ -1106,7 +1106,8 @@ struct i2c_master_s *bcm2711_i2cbus_initialize(int port)
/* Enable interrupt handler */
arm64_gic_irq_set_priority(BCM_IRQ_VC_I2C, 0, IRQ_TYPE_EDGE);
up_prioritize_irq(BCM_IRQ_VC_I2C, 0);
up_set_irq_type(BCM_IRQ_VC_I2C, IRQ_RISING_EDGE);
up_enable_irq(BCM_IRQ_VC_I2C);
g_i2c_irqinit = true; /* Mark IRQ handler as initialized */
i2cinfo("I2C IRQ enabled\n");
arch/arm64/src/bcm2711/bcm2711_sdio.c
+2 -1
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@@ -1068,7 +1068,8 @@ static int bcm2711_attach(FAR struct sdio_dev_s *dev)
/* Enable the interrupt handler */
arm64_gic_irq_set_priority(BCM_IRQ_VC_EMMC, 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(BCM_IRQ_VC_EMMC, 0);
up_set_irq_type(BCM_IRQ_VC_EMMC, IRQ_HIGH_LEVEL);
up_enable_irq(BCM_IRQ_VC_EMMC);
g_emmc_irqinit = true;
mcinfo("EMMC IRQ enabled.");
arch/arm64/src/bcm2711/bcm2711_serial.c
+2 -1
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@@ -568,7 +568,8 @@ static int bcm2711_miniuart_attach(struct uart_dev_s *dev)
/* Set interrupt priority in GICv2 */
arm64_gic_irq_set_priority(BCM_IRQ_VC_AUX, 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(BCM_IRQ_VC_AUX, 0);
up_set_irq_type(BCM_IRQ_VC_AUX, IRQ_HIGH_LEVEL);
/* Enable UART interrupt */
arch/arm64/src/bcm2711/bcm2711_spi.c
+2 -1
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@@ -1020,7 +1020,8 @@ struct spi_dev_s *bcm2711_spibus_initialize(int port)
return NULL;
}
arm64_gic_irq_set_priority(BCM_IRQ_VC_SPI, 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(BCM_IRQ_VC_SPI, 0);
up_set_irq_type(BCM_IRQ_VC_SPI, IRQ_HIGH_LEVEL);
up_enable_irq(BCM_IRQ_VC_SPI);
g_interrupts = true;
arch/arm64/src/common/arm64_gic.h
-10
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@@ -248,10 +248,6 @@
#define GICD_ICFGR_MASK BIT_MASK(2)
#define GICD_ICFGR_TYPE BIT(1)
/* BIT(0) reserved for IRQ_ZERO_LATENCY */
#define IRQ_TYPE_LEVEL BIT(1)
#define IRQ_TYPE_EDGE BIT(2)
#define GIC_SPI_INT_BASE 32
#define GIC_SPI_MAX_INTID 1019
#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
@@ -261,10 +257,6 @@
#define GIC_DIST_IROUTER 0x6000
#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
/* BIT(0) reserved for IRQ_ZERO_LATENCY */
#define IRQ_TYPE_LEVEL BIT(1)
#define IRQ_TYPE_EDGE BIT(2)
#define IRQ_DEFAULT_PRIORITY 0xa0
#define GIC_IRQ_SGI0 0
@@ -300,8 +292,6 @@
bool arm64_gic_irq_is_enabled(unsigned int intid);
int arm64_gic_initialize(void);
void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
uint32_t flags);
/****************************************************************************
* Name: arm64_decodeirq
arch/arm64/src/common/arm64_gicv2.c
-50
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@@ -1373,56 +1373,6 @@ int up_set_irq_type(int irq, int mode)
return -EINVAL;
}
/****************************************************************************
* Name: arm64_gic_irq_set_priority
*
* Description:
* Set the interrupt priority and type.
*
* If CONFIG_SMP is not selected, the cpuset is ignored and SGI is sent
* only to the current CPU.
*
* Input Parameters
* intid - The SGI interrupt ID (0-15)
* prio - The interrupt priority
* flags - Bit IRQ_TYPE_EDGE is 1 if interrupt should be edge-triggered
*
* Returned Value:
* None
*
****************************************************************************/
void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
uint32_t flags)
{
int ret;
/* Disable the interrupt */
up_disable_irq(intid);
/* Set the interrupt priority */
ret = up_prioritize_irq(intid, prio);
DEBUGASSERT(ret == OK);
/* Configure interrupt type */
if (!GIC_IS_SGI(intid))
{
if (flags & IRQ_TYPE_EDGE)
{
ret = up_set_irq_type(intid, IRQ_RISING_EDGE);
DEBUGASSERT(ret == OK);
}
else
{
ret = up_set_irq_type(intid, IRQ_HIGH_LEVEL);
DEBUGASSERT(ret == OK);
}
}
}
/****************************************************************************
* Name: arm64_gic_initialize
*
arch/arm64/src/common/arm64_gicv3.c
-45
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@@ -156,51 +156,6 @@ static inline void arm64_gic_write_irouter(uint64_t val, unsigned int intid)
putreg64(val, addr);
}
void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
uint32_t flags)
{
uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
uint32_t shift;
uint32_t val;
unsigned long base = GET_DIST_BASE(intid);
irqstate_t irq_flags;
/* Disable the interrupt */
putreg32(mask, ICENABLER(base, idx));
gic_wait_rwp(intid);
/* PRIORITYR registers provide byte access */
putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
/* Interrupt type config */
if (!GIC_IS_SGI(intid))
{
idx = intid / GIC_NUM_CFG_PER_REG;
shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
/* GICD_ICFGR requires full 32-bit RMW operations.
* Each interrupt uses 2 bits; thus updates must be synchronized
* to avoid losing configuration in concurrent environments.
*/
irq_flags = spin_lock_irqsave(&g_gic_lock);
val = getreg32(ICFGR(base, idx));
val &= ~(GICD_ICFGR_MASK << shift);
if (flags & IRQ_TYPE_EDGE)
{
val |= (GICD_ICFGR_TYPE << shift);
}
putreg32(val, ICFGR(base, idx));
spin_unlock_irqrestore(&g_gic_lock, irq_flags);
}
}
/***************************************************************************
* Name: up_set_irq_type
*
arch/arm64/src/rk3399/rk3399_serial.c
+2 -1
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@@ -641,7 +641,8 @@ static int a64_uart_attach(struct uart_dev_s *dev)
/* Set Interrupt Priority in Generic Interrupt Controller v2 */
arm64_gic_irq_set_priority(port->irq_num, 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(port->irq_num, 0);
up_set_irq_type(port->irq_num, IRQ_RISING_EDGE);
/* Enable UART Interrupt */
arch/arm64/src/zynq-mpsoc/zynq_serial.c
+2 -1
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@@ -775,7 +775,8 @@ static int zynq_uart_attach(struct uart_dev_s *dev)
/* Set Interrupt Priority in Generic Interrupt Controller v2 */
arm64_gic_irq_set_priority(port->irq_num, 0, IRQ_TYPE_LEVEL);
up_prioritize_irq(port->irq_num, 0);
up_set_irq_type(port->irq_num, IRQ_HIGH_LEVEL);
/* Enable UART Interrupt */
boards/arm64/a64/pinephone/src/pinephone_touch.c
+2 -1
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@@ -117,7 +117,8 @@ static int pinephone_gt9xx_irq_attach(const struct gt9xx_board_s *state,
/* Set Interrupt Priority in Generic Interrupt Controller v2 */
arm64_gic_irq_set_priority(A64_IRQ_PH_EINT, 0, IRQ_TYPE_EDGE);
up_prioritize_irq(A64_IRQ_PH_EINT, 0);
up_set_irq_type(A64_IRQ_PH_EINT, IRQ_RISING_EDGE);
/* Enable Interrupts for Port PH */